1 /* $FreeBSD: src/sys/dev/isp/ispmbox.h,v 1.20.2.13 2002/10/11 18:51:13 mjacob Exp $ */
2 /* $DragonFly: src/sys/dev/disk/isp/ispmbox.h,v 1.2 2003/06/17 04:28:27 dillon Exp $ */
4 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
6 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice immediately at the beginning of the file, without modification,
14 * this list of conditions, and the following disclaimer.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * Mailbox Command Opcodes
37 #define MBOX_NO_OP 0x0000
38 #define MBOX_LOAD_RAM 0x0001
39 #define MBOX_EXEC_FIRMWARE 0x0002
40 #define MBOX_DUMP_RAM 0x0003
41 #define MBOX_WRITE_RAM_WORD 0x0004
42 #define MBOX_READ_RAM_WORD 0x0005
43 #define MBOX_MAILBOX_REG_TEST 0x0006
44 #define MBOX_VERIFY_CHECKSUM 0x0007
45 #define MBOX_ABOUT_FIRMWARE 0x0008
51 #define MBOX_CHECK_FIRMWARE 0x000e
52 #define MBOX_READ_RAM_WORD_EXTENDED 0x000f
53 #define MBOX_INIT_REQ_QUEUE 0x0010
54 #define MBOX_INIT_RES_QUEUE 0x0011
55 #define MBOX_EXECUTE_IOCB 0x0012
56 #define MBOX_WAKE_UP 0x0013
57 #define MBOX_STOP_FIRMWARE 0x0014
58 #define MBOX_ABORT 0x0015
59 #define MBOX_ABORT_DEVICE 0x0016
60 #define MBOX_ABORT_TARGET 0x0017
61 #define MBOX_BUS_RESET 0x0018
62 #define MBOX_STOP_QUEUE 0x0019
63 #define MBOX_START_QUEUE 0x001a
64 #define MBOX_SINGLE_STEP_QUEUE 0x001b
65 #define MBOX_ABORT_QUEUE 0x001c
66 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
68 #define MBOX_GET_FIRMWARE_STATUS 0x001f
69 #define MBOX_GET_INIT_SCSI_ID 0x0020
70 #define MBOX_GET_SELECT_TIMEOUT 0x0021
71 #define MBOX_GET_RETRY_COUNT 0x0022
72 #define MBOX_GET_TAG_AGE_LIMIT 0x0023
73 #define MBOX_GET_CLOCK_RATE 0x0024
74 #define MBOX_GET_ACT_NEG_STATE 0x0025
75 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
76 #define MBOX_GET_SBUS_PARAMS 0x0027
77 #define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS
78 #define MBOX_GET_TARGET_PARAMS 0x0028
79 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
80 #define MBOX_GET_RESET_DELAY_PARAMS 0x002a
86 #define MBOX_SET_INIT_SCSI_ID 0x0030
87 #define MBOX_SET_SELECT_TIMEOUT 0x0031
88 #define MBOX_SET_RETRY_COUNT 0x0032
89 #define MBOX_SET_TAG_AGE_LIMIT 0x0033
90 #define MBOX_SET_CLOCK_RATE 0x0034
91 #define MBOX_SET_ACT_NEG_STATE 0x0035
92 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
93 #define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
94 #define MBOX_SET_PCI_PARAMETERS 0x0037
95 #define MBOX_SET_TARGET_PARAMS 0x0038
96 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
97 #define MBOX_SET_RESET_DELAY_PARAMS 0x003a
103 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
104 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
105 #define MBOX_EXEC_BIOS_IOCB 0x0042
106 #define MBOX_SET_FW_FEATURES 0x004a
107 #define MBOX_GET_FW_FEATURES 0x004b
108 #define FW_FEATURE_FAST_POST 0x1
109 #define FW_FEATURE_LVD_NOTIFY 0x2
110 #define FW_FEATURE_RIO_32BIT 0x4
111 #define FW_FEATURE_RIO_16BIT 0x8
113 #define MBOX_INIT_REQ_QUEUE_A64 0x0052
114 #define MBOX_INIT_RES_QUEUE_A64 0x0053
116 #define MBOX_ENABLE_TARGET_MODE 0x0055
117 #define ENABLE_TARGET_FLAG 0x8000
118 #define ENABLE_TQING_FLAG 0x0004
119 #define ENABLE_MANDATORY_DISC 0x0002
120 #define MBOX_GET_TARGET_STATUS 0x0056
122 /* These are for the ISP2X00 FC cards */
123 #define MBOX_GET_LOOP_ID 0x0020
124 #define MBOX_GET_FIRMWARE_OPTIONS 0x0028
125 #define MBOX_SET_FIRMWARE_OPTIONS 0x0038
126 #define MBOX_GET_RESOURCE_COUNT 0x0042
127 #define MBOX_ENHANCED_GET_PDB 0x0047
128 #define MBOX_EXEC_COMMAND_IOCB_A64 0x0054
129 #define MBOX_INIT_FIRMWARE 0x0060
130 #define MBOX_GET_INIT_CONTROL_BLOCK 0x0061
131 #define MBOX_INIT_LIP 0x0062
132 #define MBOX_GET_FC_AL_POSITION_MAP 0x0063
133 #define MBOX_GET_PORT_DB 0x0064
134 #define MBOX_CLEAR_ACA 0x0065
135 #define MBOX_TARGET_RESET 0x0066
136 #define MBOX_CLEAR_TASK_SET 0x0067
137 #define MBOX_ABORT_TASK_SET 0x0068
138 #define MBOX_GET_FW_STATE 0x0069
139 #define MBOX_GET_PORT_NAME 0x006A
140 #define MBOX_GET_LINK_STATUS 0x006B
141 #define MBOX_INIT_LIP_RESET 0x006C
142 #define MBOX_SEND_SNS 0x006E
143 #define MBOX_FABRIC_LOGIN 0x006F
144 #define MBOX_SEND_CHANGE_REQUEST 0x0070
145 #define MBOX_FABRIC_LOGOUT 0x0071
146 #define MBOX_INIT_LIP_LOGIN 0x0072
148 #define MBOX_DRIVER_HEARTBEAT 0x005B
149 #define MBOX_FW_HEARTBEAT 0x005C
151 #define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */
152 #define MBGSD_GET_RATE 0
153 #define MBGSD_SET_RATE 1
154 #define MBGSD_ONEGB 0
155 #define MBGSD_TWOGB 1
159 #define ISP2100_SET_PCI_PARAM 0x00ff
161 #define MBOX_BUSY 0x04
168 * Mailbox Command Complete Status Codes
170 #define MBOX_COMMAND_COMPLETE 0x4000
171 #define MBOX_INVALID_COMMAND 0x4001
172 #define MBOX_HOST_INTERFACE_ERROR 0x4002
173 #define MBOX_TEST_FAILED 0x4003
174 #define MBOX_COMMAND_ERROR 0x4005
175 #define MBOX_COMMAND_PARAM_ERROR 0x4006
176 #define MBOX_PORT_ID_USED 0x4007
177 #define MBOX_LOOP_ID_USED 0x4008
178 #define MBOX_ALL_IDS_USED 0x4009
179 #define MBOX_NOT_LOGGED_IN 0x400A
180 #define MBLOGALL 0x000f
181 #define MBLOGNONE 0x0000
182 #define MBLOGMASK(x) ((x) & 0xf)
185 * Asynchronous event status codes
187 #define ASYNC_BUS_RESET 0x8001
188 #define ASYNC_SYSTEM_ERROR 0x8002
189 #define ASYNC_RQS_XFER_ERR 0x8003
190 #define ASYNC_RSP_XFER_ERR 0x8004
191 #define ASYNC_QWAKEUP 0x8005
192 #define ASYNC_TIMEOUT_RESET 0x8006
193 #define ASYNC_DEVICE_RESET 0x8007
194 #define ASYNC_EXTMSG_UNDERRUN 0x800A
195 #define ASYNC_SCAM_INT 0x800B
196 #define ASYNC_HUNG_SCSI 0x800C
197 #define ASYNC_KILLED_BUS 0x800D
198 #define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */
199 #define ASYNC_LIP_OCCURRED 0x8010
200 #define ASYNC_LOOP_UP 0x8011
201 #define ASYNC_LOOP_DOWN 0x8012
202 #define ASYNC_LOOP_RESET 0x8013
203 #define ASYNC_PDB_CHANGED 0x8014
204 #define ASYNC_CHANGE_NOTIFY 0x8015
205 #define ASYNC_LIP_F8 0x8016
206 #define ASYNC_CMD_CMPLT 0x8020
207 #define ASYNC_CTIO_DONE 0x8021
208 #define ASYNC_IP_XMIT_DONE 0x8022
209 #define ASYNC_IP_RECV_DONE 0x8023
210 #define ASYNC_IP_BROADCAST 0x8024
211 #define ASYNC_IP_RCVQ_LOW 0x8025
212 #define ASYNC_IP_RCVQ_EMPTY 0x8026
213 #define ASYNC_IP_RECV_DONE_ALIGNED 0x8027
214 #define ASYNC_PTPMODE 0x8030
215 #define ASYNC_RIO1 0x8031
216 #define ASYNC_RIO2 0x8032
217 #define ASYNC_RIO3 0x8033
218 #define ASYNC_RIO4 0x8034
219 #define ASYNC_RIO5 0x8035
220 #define ASYNC_CONNMODE 0x8036
221 #define ISP_CONN_LOOP 1
222 #define ISP_CONN_PTP 2
223 #define ISP_CONN_BADLIP 3
224 #define ISP_CONN_FATAL 4
225 #define ISP_CONN_LOOPBACK 5
226 #define ASYNC_RIO_RESP 0x8040
227 #define ASYNC_RIO_COMP 0x8042
229 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options
230 * mailbox command to enable this.
232 #define ASYNC_QFULL_SENT 0x8049
238 #define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \
239 ISP_WRITE(isp, isp->isp_rqstinrp, value)
241 #define READ_REQUEST_QUEUE_OUT_POINTER(isp) \
242 ISP_READ(isp, isp->isp_rqstoutrp)
244 #define READ_RESPONSE_QUEUE_IN_POINTER(isp) \
245 ISP_READ(isp, isp->isp_respinrp)
247 #define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \
248 ISP_WRITE(isp, isp->isp_respoutrp, value)
251 * Command Structure Definitions
265 #define DSTYPE_32BIT 0
266 #define DSTYPE_64BIT 1
268 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */
269 u_int32_t ds_segment; /* unused */
270 u_int32_t ds_base; /* 32 bit address of DSD list */
275 * These elements get swizzled around for SBus instances.
277 #define ISP_SWAP8(a, b) { \
284 u_int8_t rqs_entry_type;
285 u_int8_t rqs_entry_count;
290 /* RQS Flag definitions */
291 #define RQSFLAG_CONTINUATION 0x01
292 #define RQSFLAG_FULL 0x02
293 #define RQSFLAG_BADHEADER 0x04
294 #define RQSFLAG_BADPACKET 0x08
296 /* RQS entry_type definitions */
297 #define RQSTYPE_REQUEST 0x01
298 #define RQSTYPE_DATASEG 0x02
299 #define RQSTYPE_RESPONSE 0x03
300 #define RQSTYPE_MARKER 0x04
301 #define RQSTYPE_CMDONLY 0x05
302 #define RQSTYPE_ATIO 0x06 /* Target Mode */
303 #define RQSTYPE_CTIO 0x07 /* Target Mode */
304 #define RQSTYPE_SCAM 0x08
305 #define RQSTYPE_A64 0x09
306 #define RQSTYPE_A64_CONT 0x0a
307 #define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */
308 #define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */
309 #define RQSTYPE_NOTIFY 0x0d /* Target Mode */
310 #define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */
311 #define RQSTYPE_CTIO1 0x0f /* Target Mode */
312 #define RQSTYPE_STATUS_CONT 0x10
313 #define RQSTYPE_T2RQS 0x11
314 #define RQSTYPE_IP_XMIT 0x13
315 #define RQSTYPE_T4RQS 0x15
316 #define RQSTYPE_ATIO2 0x16 /* Target Mode */
317 #define RQSTYPE_CTIO2 0x17 /* Target Mode */
318 #define RQSTYPE_CSET0 0x18
319 #define RQSTYPE_T3RQS 0x19
320 #define RQSTYPE_IP_XMIT_64 0x1b
321 #define RQSTYPE_CTIO4 0x1e /* Target Mode */
322 #define RQSTYPE_CTIO3 0x1f /* Target Mode */
323 #define RQSTYPE_RIO1 0x21
324 #define RQSTYPE_RIO2 0x22
325 #define RQSTYPE_IP_RECV 0x23
326 #define RQSTYPE_IP_RECV_CONT 0x24
332 u_int32_t req_handle;
333 u_int8_t req_lun_trn;
335 u_int16_t req_cdblen;
336 #define req_modifier req_cdblen /* marker packet */
338 u_int16_t req_reserved;
340 u_int16_t req_seg_count;
341 u_int8_t req_cdb[12];
342 ispds_t req_dataseg[ISP_RQDSEG];
345 #define ispreq64_t ispreqt3_t /* same as.... */
346 #define ISP_RQDSEG_A64 2
349 * A request packet can also be a marker packet.
351 #define SYNC_DEVICE 0
352 #define SYNC_TARGET 1
355 #define ISP_RQDSEG_T2 3
358 u_int32_t req_handle;
359 u_int8_t req_lun_trn;
361 u_int16_t req_scclun;
365 u_int16_t req_seg_count;
366 u_int8_t req_cdb[16];
367 u_int32_t req_totalcnt;
368 ispds_t req_dataseg[ISP_RQDSEG_T2];
371 #define ISP_RQDSEG_T3 2
374 u_int32_t req_handle;
375 u_int8_t req_lun_trn;
377 u_int16_t req_scclun;
381 u_int16_t req_seg_count;
382 u_int8_t req_cdb[16];
383 u_int32_t req_totalcnt;
384 ispds64_t req_dataseg[ISP_RQDSEG_T3];
387 /* req_flag values */
388 #define REQFLAG_NODISCON 0x0001
389 #define REQFLAG_HTAG 0x0002
390 #define REQFLAG_OTAG 0x0004
391 #define REQFLAG_STAG 0x0008
392 #define REQFLAG_TARGET_RTN 0x0010
394 #define REQFLAG_NODATA 0x0000
395 #define REQFLAG_DATA_IN 0x0020
396 #define REQFLAG_DATA_OUT 0x0040
397 #define REQFLAG_DATA_UNKNOWN 0x0060
399 #define REQFLAG_DISARQ 0x0100
400 #define REQFLAG_FRC_ASYNC 0x0200
401 #define REQFLAG_FRC_SYNC 0x0400
402 #define REQFLAG_FRC_WIDE 0x0800
403 #define REQFLAG_NOPARITY 0x1000
404 #define REQFLAG_STOPQ 0x2000
405 #define REQFLAG_XTRASNS 0x4000
406 #define REQFLAG_PRIORITY 0x8000
410 u_int32_t req_handle;
411 u_int8_t req_lun_trn;
413 u_int16_t req_cdblen;
417 u_int16_t req_seg_count;
418 u_int8_t req_cdb[44];
425 ispds_t req_dataseg[ISP_CDSEG];
428 #define ISP_CDSEG64 5
431 ispds64_t req_dataseg[ISP_CDSEG64];
436 u_int32_t req_handle;
437 u_int16_t req_scsi_status;
438 u_int16_t req_completion_status;
439 u_int16_t req_state_flags;
440 u_int16_t req_status_flags;
442 #define req_response_len req_time /* FC only */
443 u_int16_t req_sense_len;
445 u_int8_t req_response[8]; /* FC only */
446 u_int8_t req_sense_data[32];
451 u_int8_t req_sense_data[60];
455 * For Qlogic 2X00, the high order byte of SCSI status has
456 * additional meaning.
458 #define RQCS_RU 0x800 /* Residual Under */
459 #define RQCS_RO 0x400 /* Residual Over */
460 #define RQCS_RESID (RQCS_RU|RQCS_RO)
461 #define RQCS_SV 0x200 /* Sense Length Valid */
462 #define RQCS_RV 0x100 /* FCP Response Length Valid */
465 * Completion Status Codes.
467 #define RQCS_COMPLETE 0x0000
468 #define RQCS_DMA_ERROR 0x0002
469 #define RQCS_RESET_OCCURRED 0x0004
470 #define RQCS_ABORTED 0x0005
471 #define RQCS_TIMEOUT 0x0006
472 #define RQCS_DATA_OVERRUN 0x0007
473 #define RQCS_DATA_UNDERRUN 0x0015
474 #define RQCS_QUEUE_FULL 0x001C
476 /* 1X00 Only Completion Codes */
477 #define RQCS_INCOMPLETE 0x0001
478 #define RQCS_TRANSPORT_ERROR 0x0003
479 #define RQCS_COMMAND_OVERRUN 0x0008
480 #define RQCS_STATUS_OVERRUN 0x0009
481 #define RQCS_BAD_MESSAGE 0x000a
482 #define RQCS_NO_MESSAGE_OUT 0x000b
483 #define RQCS_EXT_ID_FAILED 0x000c
484 #define RQCS_IDE_MSG_FAILED 0x000d
485 #define RQCS_ABORT_MSG_FAILED 0x000e
486 #define RQCS_REJECT_MSG_FAILED 0x000f
487 #define RQCS_NOP_MSG_FAILED 0x0010
488 #define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
489 #define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
490 #define RQCS_ID_MSG_FAILED 0x0013
491 #define RQCS_UNEXP_BUS_FREE 0x0014
492 #define RQCS_XACT_ERR1 0x0018
493 #define RQCS_XACT_ERR2 0x0019
494 #define RQCS_XACT_ERR3 0x001A
495 #define RQCS_BAD_ENTRY 0x001B
496 #define RQCS_PHASE_SKIPPED 0x001D
497 #define RQCS_ARQS_FAILED 0x001E
498 #define RQCS_WIDE_FAILED 0x001F
499 #define RQCS_SYNCXFER_FAILED 0x0020
500 #define RQCS_LVD_BUSERR 0x0021
502 /* 2X00 Only Completion Codes */
503 #define RQCS_PORT_UNAVAILABLE 0x0028
504 #define RQCS_PORT_LOGGED_OUT 0x0029
505 #define RQCS_PORT_CHANGED 0x002A
506 #define RQCS_PORT_BUSY 0x002B
509 * 1X00 specific State Flags
511 #define RQSF_GOT_BUS 0x0100
512 #define RQSF_GOT_TARGET 0x0200
513 #define RQSF_SENT_CDB 0x0400
514 #define RQSF_XFRD_DATA 0x0800
515 #define RQSF_GOT_STATUS 0x1000
516 #define RQSF_GOT_SENSE 0x2000
517 #define RQSF_XFER_COMPLETE 0x4000
520 * 2X00 specific State Flags
521 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available)
523 #define RQSF_DATA_IN 0x0020
524 #define RQSF_DATA_OUT 0x0040
525 #define RQSF_STAG 0x0008
526 #define RQSF_OTAG 0x0004
527 #define RQSF_HTAG 0x0002
531 #define RQSTF_DISCONNECT 0x0001
532 #define RQSTF_SYNCHRONOUS 0x0002
533 #define RQSTF_PARITY_ERROR 0x0004
534 #define RQSTF_BUS_RESET 0x0008
535 #define RQSTF_DEVICE_RESET 0x0010
536 #define RQSTF_ABORTED 0x0020
537 #define RQSTF_TIMEOUT 0x0040
538 #define RQSTF_NEGOTIATION 0x0080
541 * 2X00 specific state flags
545 /* RQSF_GOT_STATUS */
546 /* RQSF_XFER_COMPLETE */
549 * 2X00 specific status flags
553 #define RQSTF_DMA_ERROR 0x0080
554 #define RQSTF_LOGOUT 0x2000
559 #ifndef ISP_EXEC_THROTTLE
560 #define ISP_EXEC_THROTTLE 16
564 * About Firmware returns an 'attribute' word in mailbox 6.
566 #define ISP_FW_ATTR_TMODE 0x01
567 #define ISP_FW_ATTR_SCCLUN 0x02
568 #define ISP_FW_ATTR_FABRIC 0x04
569 #define ISP_FW_ATTR_CLASS2 0x08
570 #define ISP_FW_ATTR_FCTAPE 0x10
571 #define ISP_FW_ATTR_IP 0x20
574 * Reduced Interrupt Operation Response Queue Entreis
579 u_int32_t req_handles[15];
584 u_int16_t req_handles[30];
588 * FC (ISP2100) specific data structures
592 * Initialization Control Block
594 * Version One (prime) format.
596 typedef struct isp_icb {
597 u_int8_t icb_version;
599 u_int16_t icb_fwoptions;
600 u_int16_t icb_maxfrmlen;
601 u_int16_t icb_maxalloc;
602 u_int16_t icb_execthrottle;
603 u_int8_t icb_retry_count;
604 u_int8_t icb_retry_delay;
605 u_int8_t icb_portname[8];
606 u_int16_t icb_hardaddr;
607 u_int8_t icb_iqdevtype;
608 u_int8_t icb_logintime;
609 u_int8_t icb_nodename[8];
610 u_int16_t icb_rqstout;
611 u_int16_t icb_rspnsin;
612 u_int16_t icb_rqstqlen;
613 u_int16_t icb_rsltqlen;
614 u_int16_t icb_rqstaddr[4];
615 u_int16_t icb_respaddr[4];
616 u_int16_t icb_lunenables;
619 u_int16_t icb_lunetimeout;
620 u_int16_t _reserved1;
621 u_int16_t icb_xfwoptions;
622 u_int8_t icb_racctimer;
623 u_int8_t icb_idelaytimer;
624 u_int16_t icb_zfwoptions;
625 u_int16_t _reserved2[13];
627 #define ICB_VERSION1 1
629 #define ICBOPT_HARD_ADDRESS 0x0001
630 #define ICBOPT_FAIRNESS 0x0002
631 #define ICBOPT_FULL_DUPLEX 0x0004
632 #define ICBOPT_FAST_POST 0x0008
633 #define ICBOPT_TGT_ENABLE 0x0010
634 #define ICBOPT_INI_DISABLE 0x0020
635 #define ICBOPT_INI_ADISC 0x0040
636 #define ICBOPT_INI_TGTTYPE 0x0080
637 #define ICBOPT_PDBCHANGE_AE 0x0100
638 #define ICBOPT_NOLIP 0x0200
639 #define ICBOPT_SRCHDOWN 0x0400
640 #define ICBOPT_PREVLOOP 0x0800
641 #define ICBOPT_STOP_ON_QFULL 0x1000
642 #define ICBOPT_FULL_LOGIN 0x2000
643 #define ICBOPT_BOTH_WWNS 0x4000
644 #define ICBOPT_EXTENDED 0x8000
646 #define ICBXOPT_CLASS2_ACK0 0x0200
647 #define ICBXOPT_CLASS2 0x0100
648 #define ICBXOPT_LOOP_ONLY (0 << 4)
649 #define ICBXOPT_PTP_ONLY (1 << 4)
650 #define ICBXOPT_LOOP_2_PTP (2 << 4)
651 #define ICBXOPT_PTP_2_LOOP (3 << 4)
653 #define ICBXOPT_RIO_OFF 0
654 #define ICBXOPT_RIO_16BIT 1
655 #define ICBXOPT_RIO_32BIT 2
656 #define ICBXOPT_RIO_16BIT_IOCB 3
657 #define ICBXOPT_RIO_32BIT_IOCB 4
658 #define ICBXOPT_ZIO 5
660 #define ICBZOPT_ENA_RDXFR_RDY 0x01
661 #define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */
662 /* These 3 only apply to the 2300 */
663 #define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14)
664 #define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14)
665 #define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14)
668 #define ICB_MIN_FRMLEN 256
669 #define ICB_MAX_FRMLEN 2112
670 #define ICB_DFLT_FRMLEN 1024
671 #define ICB_DFLT_ALLOC 256
672 #define ICB_DFLT_THROTTLE 16
673 #define ICB_DFLT_RDELAY 5
674 #define ICB_DFLT_RCOUNT 3
677 #define RQRSP_ADDR0015 0
678 #define RQRSP_ADDR1631 1
679 #define RQRSP_ADDR3247 2
680 #define RQRSP_ADDR4863 3
692 #define MAKE_NODE_NAME_FROM_WWN(array, wwn) \
693 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \
694 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \
695 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \
696 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \
697 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \
698 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \
699 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \
700 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff)
705 * This is an at most 128 byte map that returns either
706 * the LILP or Firmware generated list of ports.
708 * We deviate a bit from the returned qlogic format to
709 * use an extra bit to say whether this was a LILP or
719 * Port Data Base Element
723 u_int16_t pdb_options;
726 #define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2])
727 u_int8_t pdb_hardaddr_bits[4];
728 u_int8_t pdb_portid_bits[4];
729 u_int8_t pdb_nodename[8];
730 u_int8_t pdb_portname[8];
731 u_int16_t pdb_execthrottle;
732 u_int16_t pdb_exec_count;
733 u_int8_t pdb_retry_count;
734 u_int8_t pdb_retry_delay;
735 u_int16_t pdb_resalloc;
736 u_int16_t pdb_curalloc;
739 u_int16_t pdb_tl_next;
740 u_int16_t pdb_tl_last;
741 u_int16_t pdb_features; /* PLOGI, Common Service */
742 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */
743 u_int16_t pdb_roi; /* PLOGI, Common Service */
745 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */
746 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */
747 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */
748 u_int16_t pdb_noseq; /* PLOGI, Class 3 */
749 u_int16_t pdb_labrtflg;
750 u_int16_t pdb_lstopflg;
751 u_int16_t pdb_sqhead;
752 u_int16_t pdb_sqtail;
753 u_int16_t pdb_ptimer;
754 u_int16_t pdb_nxt_seqid;
755 u_int16_t pdb_fcount;
756 u_int16_t pdb_prli_len;
757 u_int16_t pdb_prli_svc0;
758 u_int16_t pdb_prli_svc3;
759 u_int16_t pdb_loopid;
760 u_int16_t pdb_il_ptr;
761 u_int16_t pdb_sl_ptr;
764 #define PDB_OPTIONS_XMITTING (1<<11)
765 #define PDB_OPTIONS_LNKXMIT (1<<10)
766 #define PDB_OPTIONS_ABORTED (1<<9)
767 #define PDB_OPTIONS_ADISC (1<<1)
769 #define PDB_STATE_DISCOVERY 0
770 #define PDB_STATE_WDISC_ACK 1
771 #define PDB_STATE_PLOGI 2
772 #define PDB_STATE_PLOGI_ACK 3
773 #define PDB_STATE_PRLI 4
774 #define PDB_STATE_PRLI_ACK 5
775 #define PDB_STATE_LOGGED_IN 6
776 #define PDB_STATE_PORT_UNAVAIL 7
777 #define PDB_STATE_PRLO 8
778 #define PDB_STATE_PRLO_ACK 9
779 #define PDB_STATE_PLOGO 10
780 #define PDB_STATE_PLOG_ACK 11
782 #define SVC3_TGT_ROLE 0x10
783 #define SVC3_INI_ROLE 0x20
784 #define SVC3_ROLE_MASK 0x30
785 #define SVC3_ROLE_SHIFT 4
790 * This is as the QLogic f/w documentations defines it- which is just opposite,
791 * bit wise, from what the specification defines it as. Additionally, the
792 * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped.
796 u_int8_t ct_revision;
797 u_int8_t ct_portid[3];
798 u_int8_t ct_fcs_type;
799 u_int8_t ct_fcs_subtype;
802 u_int16_t ct_response;
806 u_int8_t ct_explanation;
809 #define FS_ACC 0x8002
810 #define FS_RJT 0x8001
812 #define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */
813 #define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */
814 #define FC4_FC_SVC 0x20 /* Fibre Channel Services */
816 #define SNS_GA_NXT 0x100
817 #define SNS_GPN_ID 0x112
818 #define SNS_GNN_ID 0x113
819 #define SNS_GFF_ID 0x11F
820 #define SNS_GID_FT 0x171
821 #define SNS_RFT_ID 0x217
823 u_int16_t snscb_rblen; /* response buffer length (words) */
824 u_int16_t snscb_res0;
825 u_int16_t snscb_addr[4]; /* response buffer address */
826 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
827 u_int16_t snscb_res1;
828 u_int16_t snscb_data[1]; /* variable data */
829 } sns_screq_t; /* Subcommand Request Structure */
832 u_int16_t snscb_rblen; /* response buffer length (words) */
833 u_int16_t snscb_res0;
834 u_int16_t snscb_addr[4]; /* response buffer address */
835 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
836 u_int16_t snscb_res1;
838 u_int16_t snscb_res2;
839 u_int32_t snscb_res3;
840 u_int32_t snscb_port;
842 #define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t))
845 u_int16_t snscb_rblen; /* response buffer length (words) */
846 u_int16_t snscb_res0;
847 u_int16_t snscb_addr[4]; /* response buffer address */
848 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
849 u_int16_t snscb_res1;
851 u_int16_t snscb_res2;
852 u_int32_t snscb_res3;
853 u_int32_t snscb_portid;
855 #define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t))
858 u_int16_t snscb_rblen; /* response buffer length (words) */
859 u_int16_t snscb_res0;
860 u_int16_t snscb_addr[4]; /* response buffer address */
861 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
862 u_int16_t snscb_res1;
864 u_int16_t snscb_mword_div_2;
865 u_int32_t snscb_res3;
866 u_int32_t snscb_fc4_type;
868 #define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t))
871 u_int16_t snscb_rblen; /* response buffer length (words) */
872 u_int16_t snscb_res0;
873 u_int16_t snscb_addr[4]; /* response buffer address */
874 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
875 u_int16_t snscb_res1;
877 u_int16_t snscb_res2;
878 u_int32_t snscb_res3;
879 u_int32_t snscb_port;
880 u_int32_t snscb_fc4_types[8];
882 #define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t))
885 ct_hdr_t snscb_cthdr;
886 u_int8_t snscb_port_type;
887 u_int8_t snscb_port_id[3];
888 u_int8_t snscb_portname[8];
889 u_int16_t snscb_data[1]; /* variable data */
890 } sns_scrsp_t; /* Subcommand Response Structure */
893 ct_hdr_t snscb_cthdr;
894 u_int8_t snscb_port_type;
895 u_int8_t snscb_port_id[3];
896 u_int8_t snscb_portname[8];
897 u_int8_t snscb_pnlen; /* symbolic port name length */
898 u_int8_t snscb_pname[255]; /* symbolic port name */
899 u_int8_t snscb_nodename[8];
900 u_int8_t snscb_nnlen; /* symbolic node name length */
901 u_int8_t snscb_nname[255]; /* symbolic node name */
902 u_int8_t snscb_ipassoc[8];
903 u_int8_t snscb_ipaddr[16];
904 u_int8_t snscb_svc_class[4];
905 u_int8_t snscb_fc4_types[32];
906 u_int8_t snscb_fpname[8];
907 u_int8_t snscb_reserved;
908 u_int8_t snscb_hardaddr[3];
909 } sns_ga_nxt_rsp_t; /* Subcommand Response Structure */
910 #define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t))
913 ct_hdr_t snscb_cthdr;
914 u_int8_t snscb_wwn[8];
916 #define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t))
919 ct_hdr_t snscb_cthdr;
920 u_int32_t snscb_fc4_features[32];
922 #define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t))
925 ct_hdr_t snscb_cthdr;
931 #define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2))
933 #define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t))
935 #endif /* _ISPMBOX_H */