sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_ringbuffer.h"
  34 #include <linux/workqueue.h>
  35
  36 extern struct drm_i915_private *i915_mch_dev;
  37
  38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  39
  40 #define BEGIN_LP_RING(n) \
  41         intel_ring_begin(LP_RING(dev_priv), (n))
  42
  43 #define OUT_RING(x) \
  44         intel_ring_emit(LP_RING(dev_priv), x)
  45
  46 #define ADVANCE_LP_RING() \
  47         intel_ring_advance(LP_RING(dev_priv))
  48
  49 /**
  50  * Lock test for when it's just for synchronization of ring access.
  51  *
  52  * In that case, we don't need to do it when GEM is initialized as nobody else
  53  * has access to the ring.
  54  */
  55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  56         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  58 } while (0)
  59
  60 static inline u32
  61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  62 {
  63         if (I915_NEED_GFX_HWS(dev_priv->dev))
  64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  65         else
  66                 return intel_read_status_page(LP_RING(dev_priv), reg);
  67 }
  68
  69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71 #define I915_BREADCRUMB_INDEX           0x21
  72
  73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  74 {
  75         /* XXX: We don't care about dri1 */
  76         return;
  77 }
  78
  79 static void i915_write_hws_pga(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         u32 addr;
  83
  84         addr = dev_priv->status_page_dmah->busaddr;
  85         if (INTEL_INFO(dev)->gen >= 4)
  86                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  87         I915_WRITE(HWS_PGA, addr);
  88 }
  89
  90 /**
  91  * Frees the hardware status page, whether it's a physical address or a virtual
  92  * address set up by the X Server.
  93  */
  94 static void i915_free_hws(struct drm_device *dev)
  95 {
  96         drm_i915_private_t *dev_priv = dev->dev_private;
  97         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  98
  99         if (dev_priv->status_page_dmah) {
 100                 drm_pci_free(dev, dev_priv->status_page_dmah);
 101                 dev_priv->status_page_dmah = NULL;
 102         }
 103
 104         if (ring->status_page.gfx_addr) {
 105                 ring->status_page.gfx_addr = 0;
 106 #if 0   /* We don't care about dri1 */
 107                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 108 #endif
 109         }
 110
 111         /* Need to rewrite hardware status page */
 112         I915_WRITE(HWS_PGA, 0x1ffff000);
 113 }
 114
 115 void i915_kernel_lost_context(struct drm_device * dev)
 116 {
 117         drm_i915_private_t *dev_priv = dev->dev_private;
 118         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 119
 120         /*
 121          * We should never lose context on the ring with modesetting
 122          * as we don't expose it to userspace
 123          */
 124         if (drm_core_check_feature(dev, DRIVER_MODESET))
 125                 return;
 126
 127         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 128         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 129         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 130         if (ring->space < 0)
 131                 ring->space += ring->size;
 132
 133 #if 0
 134         if (!dev->primary->master)
 135                 return;
 136 #endif
 137
 138         if (ring->head == ring->tail && dev_priv->sarea_priv)
 139                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 140 }
 141
 142 static int i915_dma_cleanup(struct drm_device * dev)
 143 {
 144         drm_i915_private_t *dev_priv = dev->dev_private;
 145         int i;
 146
 147         /* Make sure interrupts are disabled here because the uninstall ioctl
 148          * may not have been called from userspace and after dev_private
 149          * is freed, it's too late.
 150          */
 151         if (dev->irq_enabled)
 152                 drm_irq_uninstall(dev);
 153
 154         mutex_lock(&dev->struct_mutex);
 155         for (i = 0; i < I915_NUM_RINGS; i++)
 156                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 157         mutex_unlock(&dev->struct_mutex);
 158
 159         /* Clear the HWS virtual address at teardown */
 160         if (I915_NEED_GFX_HWS(dev))
 161                 i915_free_hws(dev);
 162
 163         return 0;
 164 }
 165
 166 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 167 {
 168         drm_i915_private_t *dev_priv = dev->dev_private;
 169         int ret;
 170
 171         dev_priv->sarea = drm_getsarea(dev);
 172         if (!dev_priv->sarea) {
 173                 DRM_ERROR("can not find sarea!\n");
 174                 i915_dma_cleanup(dev);
 175                 return -EINVAL;
 176         }
 177
 178         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 179             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
 180
 181         if (init->ring_size != 0) {
 182                 if (LP_RING(dev_priv)->obj != NULL) {
 183                         i915_dma_cleanup(dev);
 184                         DRM_ERROR("Client tried to initialize ringbuffer in "
 185                                   "GEM mode\n");
 186                         return -EINVAL;
 187                 }
 188
 189                 ret = intel_render_ring_init_dri(dev,
 190                                                  init->ring_start,
 191                                                  init->ring_size);
 192                 if (ret) {
 193                         i915_dma_cleanup(dev);
 194                         return ret;
 195                 }
 196         }
 197
 198         dev_priv->dri1.cpp = init->cpp;
 199         dev_priv->dri1.back_offset = init->back_offset;
 200         dev_priv->dri1.front_offset = init->front_offset;
 201         dev_priv->dri1.current_page = 0;
 202         dev_priv->sarea_priv->pf_current_page = 0;
 203
 204
 205         /* Allow hardware batchbuffers unless told otherwise.
 206          */
 207         dev_priv->dri1.allow_batchbuffer = 1;
 208
 209         return 0;
 210 }
 211
 212 static int i915_dma_resume(struct drm_device * dev)
 213 {
 214         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 215         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 216
 217         DRM_DEBUG_DRIVER("%s\n", __func__);
 218
 219         if (ring->virtual_start == NULL) {
 220                 DRM_ERROR("can not ioremap virtual address for"
 221                           " ring buffer\n");
 222                 return -ENOMEM;
 223         }
 224
 225         /* Program Hardware Status Page */
 226         if (!ring->status_page.page_addr) {
 227                 DRM_ERROR("Can not find hardware status page\n");
 228                 return -EINVAL;
 229         }
 230         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 231                                 ring->status_page.page_addr);
 232         if (ring->status_page.gfx_addr != 0)
 233                 intel_ring_setup_status_page(ring);
 234         else
 235                 i915_write_hws_pga(dev);
 236
 237         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 238
 239         return 0;
 240 }
 241
 242 static int i915_dma_init(struct drm_device *dev, void *data,
 243                          struct drm_file *file_priv)
 244 {
 245         drm_i915_init_t *init = data;
 246         int retcode = 0;
 247
 248         if (drm_core_check_feature(dev, DRIVER_MODESET))
 249                 return -ENODEV;
 250
 251         switch (init->func) {
 252         case I915_INIT_DMA:
 253                 retcode = i915_initialize(dev, init);
 254                 break;
 255         case I915_CLEANUP_DMA:
 256                 retcode = i915_dma_cleanup(dev);
 257                 break;
 258         case I915_RESUME_DMA:
 259                 retcode = i915_dma_resume(dev);
 260                 break;
 261         default:
 262                 retcode = -EINVAL;
 263                 break;
 264         }
 265
 266         return retcode;
 267 }
 268
 269 /* Implement basically the same security restrictions as hardware does
 270  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 271  *
 272  * Most of the calculations below involve calculating the size of a
 273  * particular instruction.  It's important to get the size right as
 274  * that tells us where the next instruction to check is.  Any illegal
 275  * instruction detected will be given a size of zero, which is a
 276  * signal to abort the rest of the buffer.
 277  */
 278 static int validate_cmd(int cmd)
 279 {
 280         switch (((cmd >> 29) & 0x7)) {
 281         case 0x0:
 282                 switch ((cmd >> 23) & 0x3f) {
 283                 case 0x0:
 284                         return 1;       /* MI_NOOP */
 285                 case 0x4:
 286                         return 1;       /* MI_FLUSH */
 287                 default:
 288                         return 0;       /* disallow everything else */
 289                 }
 290                 break;
 291         case 0x1:
 292                 return 0;       /* reserved */
 293         case 0x2:
 294                 return (cmd & 0xff) + 2;        /* 2d commands */
 295         case 0x3:
 296                 if (((cmd >> 24) & 0x1f) <= 0x18)
 297                         return 1;
 298
 299                 switch ((cmd >> 24) & 0x1f) {
 300                 case 0x1c:
 301                         return 1;
 302                 case 0x1d:
 303                         switch ((cmd >> 16) & 0xff) {
 304                         case 0x3:
 305                                 return (cmd & 0x1f) + 2;
 306                         case 0x4:
 307                                 return (cmd & 0xf) + 2;
 308                         default:
 309                                 return (cmd & 0xffff) + 2;
 310                         }
 311                 case 0x1e:
 312                         if (cmd & (1 << 23))
 313                                 return (cmd & 0xffff) + 1;
 314                         else
 315                                 return 1;
 316                 case 0x1f:
 317                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 318                                 return (cmd & 0x1ffff) + 2;
 319                         else if (cmd & (1 << 17))       /* indirect random */
 320                                 if ((cmd & 0xffff) == 0)
 321                                         return 0;       /* unknown length, too hard */
 322                                 else
 323                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 324                         else
 325                                 return 2;       /* indirect sequential */
 326                 default:
 327                         return 0;
 328                 }
 329         default:
 330                 return 0;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 337 {
 338         drm_i915_private_t *dev_priv = dev->dev_private;
 339         int i, ret;
 340
 341         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 342                 return -EINVAL;
 343
 344         for (i = 0; i < dwords;) {
 345                 int sz = validate_cmd(buffer[i]);
 346                 if (sz == 0 || i + sz > dwords)
 347                         return -EINVAL;
 348                 i += sz;
 349         }
 350
 351         ret = BEGIN_LP_RING((dwords+1)&~1);
 352         if (ret)
 353                 return ret;
 354
 355         for (i = 0; i < dwords; i++)
 356                 OUT_RING(buffer[i]);
 357         if (dwords & 1)
 358                 OUT_RING(0);
 359
 360         ADVANCE_LP_RING();
 361
 362         return 0;
 363 }
 364
 365 int
 366 i915_emit_box(struct drm_device *dev,
 367               struct drm_clip_rect *box,
 368               int DR1, int DR4)
 369 {
 370         struct drm_i915_private *dev_priv = dev->dev_private;
 371         int ret;
 372
 373         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 374             box->y2 <= 0 || box->x2 <= 0) {
 375                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 376                           box->x1, box->y1, box->x2, box->y2);
 377                 return -EINVAL;
 378         }
 379
 380         if (INTEL_INFO(dev)->gen >= 4) {
 381                 ret = BEGIN_LP_RING(4);
 382                 if (ret)
 383                         return ret;
 384
 385                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 386                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 387                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 388                 OUT_RING(DR4);
 389         } else {
 390                 ret = BEGIN_LP_RING(6);
 391                 if (ret)
 392                         return ret;
 393
 394                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 395                 OUT_RING(DR1);
 396                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 397                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 398                 OUT_RING(DR4);
 399                 OUT_RING(0);
 400         }
 401         ADVANCE_LP_RING();
 402
 403         return 0;
 404 }
 405
 406 /* XXX: Emitting the counter should really be moved to part of the IRQ
 407  * emit. For now, do it in both places:
 408  */
 409
 410 static void i915_emit_breadcrumb(struct drm_device *dev)
 411 {
 412         drm_i915_private_t *dev_priv = dev->dev_private;
 413
 414         dev_priv->dri1.counter++;
 415         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 416                 dev_priv->dri1.counter = 0;
 417         if (dev_priv->sarea_priv)
 418                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 419
 420         if (BEGIN_LP_RING(4) == 0) {
 421                 OUT_RING(MI_STORE_DWORD_INDEX);
 422                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 423                 OUT_RING(dev_priv->dri1.counter);
 424                 OUT_RING(0);
 425                 ADVANCE_LP_RING();
 426         }
 427 }
 428
 429 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 430                                    drm_i915_cmdbuffer_t *cmd,
 431                                    struct drm_clip_rect *cliprects,
 432                                    void *cmdbuf)
 433 {
 434         int nbox = cmd->num_cliprects;
 435         int i = 0, count, ret;
 436
 437         if (cmd->sz & 0x3) {
 438                 DRM_ERROR("alignment");
 439                 return -EINVAL;
 440         }
 441
 442         i915_kernel_lost_context(dev);
 443
 444         count = nbox ? nbox : 1;
 445
 446         for (i = 0; i < count; i++) {
 447                 if (i < nbox) {
 448                         ret = i915_emit_box(dev, &cliprects[i],
 449                                             cmd->DR1, cmd->DR4);
 450                         if (ret)
 451                                 return ret;
 452                 }
 453
 454                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 455                 if (ret)
 456                         return ret;
 457         }
 458
 459         i915_emit_breadcrumb(dev);
 460         return 0;
 461 }
 462
 463 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 464                                      drm_i915_batchbuffer_t * batch,
 465                                      struct drm_clip_rect *cliprects)
 466 {
 467         struct drm_i915_private *dev_priv = dev->dev_private;
 468         int nbox = batch->num_cliprects;
 469         int i, count, ret;
 470
 471         if ((batch->start | batch->used) & 0x7) {
 472                 DRM_ERROR("alignment");
 473                 return -EINVAL;
 474         }
 475
 476         i915_kernel_lost_context(dev);
 477
 478         count = nbox ? nbox : 1;
 479         for (i = 0; i < count; i++) {
 480                 if (i < nbox) {
 481                         ret = i915_emit_box(dev, &cliprects[i],
 482                                             batch->DR1, batch->DR4);
 483                         if (ret)
 484                                 return ret;
 485                 }
 486
 487                 if (!IS_I830(dev) && !IS_845G(dev)) {
 488                         ret = BEGIN_LP_RING(2);
 489                         if (ret)
 490                                 return ret;
 491
 492                         if (INTEL_INFO(dev)->gen >= 4) {
 493                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 494                                 OUT_RING(batch->start);
 495                         } else {
 496                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 497                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 498                         }
 499                 } else {
 500                         ret = BEGIN_LP_RING(4);
 501                         if (ret)
 502                                 return ret;
 503
 504                         OUT_RING(MI_BATCH_BUFFER);
 505                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 506                         OUT_RING(batch->start + batch->used - 4);
 507                         OUT_RING(0);
 508                 }
 509                 ADVANCE_LP_RING();
 510         }
 511
 512
 513         if (IS_G4X(dev) || IS_GEN5(dev)) {
 514                 if (BEGIN_LP_RING(2) == 0) {
 515                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 516                         OUT_RING(MI_NOOP);
 517                         ADVANCE_LP_RING();
 518                 }
 519         }
 520
 521         i915_emit_breadcrumb(dev);
 522         return 0;
 523 }
 524
 525 static int i915_dispatch_flip(struct drm_device * dev)
 526 {
 527         drm_i915_private_t *dev_priv = dev->dev_private;
 528         int ret;
 529
 530         if (!dev_priv->sarea_priv)
 531                 return -EINVAL;
 532
 533         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 534                           __func__,
 535                          dev_priv->dri1.current_page,
 536                          dev_priv->sarea_priv->pf_current_page);
 537
 538         i915_kernel_lost_context(dev);
 539
 540         ret = BEGIN_LP_RING(10);
 541         if (ret)
 542                 return ret;
 543
 544         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 545         OUT_RING(0);
 546
 547         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 548         OUT_RING(0);
 549         if (dev_priv->dri1.current_page == 0) {
 550                 OUT_RING(dev_priv->dri1.back_offset);
 551                 dev_priv->dri1.current_page = 1;
 552         } else {
 553                 OUT_RING(dev_priv->dri1.front_offset);
 554                 dev_priv->dri1.current_page = 0;
 555         }
 556         OUT_RING(0);
 557
 558         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 559         OUT_RING(0);
 560
 561         ADVANCE_LP_RING();
 562
 563         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 564
 565         if (BEGIN_LP_RING(4) == 0) {
 566                 OUT_RING(MI_STORE_DWORD_INDEX);
 567                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 568                 OUT_RING(dev_priv->dri1.counter);
 569                 OUT_RING(0);
 570                 ADVANCE_LP_RING();
 571         }
 572
 573         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 574         return 0;
 575 }
 576
 577 static int i915_quiescent(struct drm_device *dev)
 578 {
 579         i915_kernel_lost_context(dev);
 580         return intel_ring_idle(LP_RING(dev->dev_private));
 581 }
 582
 583 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 584                             struct drm_file *file_priv)
 585 {
 586         int ret;
 587
 588         if (drm_core_check_feature(dev, DRIVER_MODESET))
 589                 return -ENODEV;
 590
 591         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 592
 593         mutex_lock(&dev->struct_mutex);
 594         ret = i915_quiescent(dev);
 595         mutex_unlock(&dev->struct_mutex);
 596
 597         return ret;
 598 }
 599
 600 static int i915_batchbuffer(struct drm_device *dev, void *data,
 601                             struct drm_file *file_priv)
 602 {
 603         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 604         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 605         drm_i915_batchbuffer_t *batch = data;
 606         int ret;
 607         struct drm_clip_rect *cliprects = NULL;
 608
 609         if (drm_core_check_feature(dev, DRIVER_MODESET))
 610                 return -ENODEV;
 611
 612         if (!dev_priv->dri1.allow_batchbuffer) {
 613                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 614                 return -EINVAL;
 615         }
 616
 617         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 618                         batch->start, batch->used, batch->num_cliprects);
 619
 620         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 621
 622         if (batch->num_cliprects < 0)
 623                 return -EINVAL;
 624
 625         if (batch->num_cliprects) {
 626                 cliprects = kmalloc(batch->num_cliprects *
 627                                     sizeof(struct drm_clip_rect), M_DRM,
 628                                     M_WAITOK | M_ZERO);
 629                 if (cliprects == NULL)
 630                         return -ENOMEM;
 631
 632                 ret = copy_from_user(cliprects, batch->cliprects,
 633                                      batch->num_cliprects *
 634                                      sizeof(struct drm_clip_rect));
 635                 if (ret != 0) {
 636                         ret = -EFAULT;
 637                         goto fail_free;
 638                 }
 639         }
 640
 641         mutex_lock(&dev->struct_mutex);
 642         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 643         mutex_unlock(&dev->struct_mutex);
 644
 645         if (sarea_priv)
 646                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 647
 648 fail_free:
 649         kfree(cliprects);
 650
 651         return ret;
 652 }
 653
 654 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 655                           struct drm_file *file_priv)
 656 {
 657         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 658         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 659         drm_i915_cmdbuffer_t *cmdbuf = data;
 660         struct drm_clip_rect *cliprects = NULL;
 661         void *batch_data;
 662         int ret;
 663
 664         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 665                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 666
 667         if (drm_core_check_feature(dev, DRIVER_MODESET))
 668                 return -ENODEV;
 669
 670         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 671
 672         if (cmdbuf->num_cliprects < 0)
 673                 return -EINVAL;
 674
 675         batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
 676         if (batch_data == NULL)
 677                 return -ENOMEM;
 678
 679         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 680         if (ret != 0) {
 681                 ret = -EFAULT;
 682                 goto fail_batch_free;
 683         }
 684
 685         if (cmdbuf->num_cliprects) {
 686                 cliprects = kmalloc(cmdbuf->num_cliprects *
 687                                     sizeof(struct drm_clip_rect), M_DRM,
 688                                     M_WAITOK | M_ZERO);
 689                 if (cliprects == NULL) {
 690                         ret = -ENOMEM;
 691                         goto fail_batch_free;
 692                 }
 693
 694                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 695                                      cmdbuf->num_cliprects *
 696                                      sizeof(struct drm_clip_rect));
 697                 if (ret != 0) {
 698                         ret = -EFAULT;
 699                         goto fail_clip_free;
 700                 }
 701         }
 702
 703         mutex_lock(&dev->struct_mutex);
 704         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 705         mutex_unlock(&dev->struct_mutex);
 706         if (ret) {
 707                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 708                 goto fail_clip_free;
 709         }
 710
 711         if (sarea_priv)
 712                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 713
 714 fail_clip_free:
 715         kfree(cliprects);
 716 fail_batch_free:
 717         kfree(batch_data);
 718         return ret;
 719 }
 720
 721 static int i915_emit_irq(struct drm_device * dev)
 722 {
 723         drm_i915_private_t *dev_priv = dev->dev_private;
 724 #if 0
 725         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 726 #endif
 727
 728         i915_kernel_lost_context(dev);
 729
 730         DRM_DEBUG_DRIVER("\n");
 731
 732         dev_priv->dri1.counter++;
 733         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 734                 dev_priv->dri1.counter = 1;
 735         if (dev_priv->sarea_priv)
 736                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 737
 738         if (BEGIN_LP_RING(4) == 0) {
 739                 OUT_RING(MI_STORE_DWORD_INDEX);
 740                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 741                 OUT_RING(dev_priv->dri1.counter);
 742                 OUT_RING(MI_USER_INTERRUPT);
 743                 ADVANCE_LP_RING();
 744         }
 745
 746         return dev_priv->dri1.counter;
 747 }
 748
 749 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 750 {
 751         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 752 #if 0
 753         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 754 #endif
 755         int ret = 0;
 756         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 757
 758         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 759                   READ_BREADCRUMB(dev_priv));
 760
 761 #if 0
 762         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 763                 if (master_priv->sarea_priv)
 764                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 765                 return 0;
 766         }
 767
 768         if (master_priv->sarea_priv)
 769                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 770 #else
 771         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 772                 if (dev_priv->sarea_priv) {
 773                         dev_priv->sarea_priv->last_dispatch =
 774                                 READ_BREADCRUMB(dev_priv);
 775                 }
 776                 return 0;
 777         }
 778
 779         if (dev_priv->sarea_priv)
 780                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 781 #endif
 782
 783         if (ring->irq_get(ring)) {
 784                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 785                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 786                 ring->irq_put(ring);
 787         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 788                 ret = -EBUSY;
 789
 790         if (ret == -EBUSY) {
 791                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 792                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 793         }
 794
 795         return ret;
 796 }
 797
 798 /* Needs the lock as it touches the ring.
 799  */
 800 static int i915_irq_emit(struct drm_device *dev, void *data,
 801                          struct drm_file *file_priv)
 802 {
 803         drm_i915_private_t *dev_priv = dev->dev_private;
 804         drm_i915_irq_emit_t *emit = data;
 805         int result;
 806
 807         if (drm_core_check_feature(dev, DRIVER_MODESET))
 808                 return -ENODEV;
 809
 810         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 811                 DRM_ERROR("called with no initialization\n");
 812                 return -EINVAL;
 813         }
 814
 815         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 816
 817         mutex_lock(&dev->struct_mutex);
 818         result = i915_emit_irq(dev);
 819         mutex_unlock(&dev->struct_mutex);
 820
 821         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 822                 DRM_ERROR("copy_to_user\n");
 823                 return -EFAULT;
 824         }
 825
 826         return 0;
 827 }
 828
 829 /* Doesn't need the hardware lock.
 830  */
 831 static int i915_irq_wait(struct drm_device *dev, void *data,
 832                          struct drm_file *file_priv)
 833 {
 834         drm_i915_private_t *dev_priv = dev->dev_private;
 835         drm_i915_irq_wait_t *irqwait = data;
 836
 837         if (drm_core_check_feature(dev, DRIVER_MODESET))
 838                 return -ENODEV;
 839
 840         if (!dev_priv) {
 841                 DRM_ERROR("called with no initialization\n");
 842                 return -EINVAL;
 843         }
 844
 845         return i915_wait_irq(dev, irqwait->irq_seq);
 846 }
 847
 848 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 849                          struct drm_file *file_priv)
 850 {
 851         drm_i915_private_t *dev_priv = dev->dev_private;
 852         drm_i915_vblank_pipe_t *pipe = data;
 853
 854         if (drm_core_check_feature(dev, DRIVER_MODESET))
 855                 return -ENODEV;
 856
 857         if (!dev_priv) {
 858                 DRM_ERROR("called with no initialization\n");
 859                 return -EINVAL;
 860         }
 861
 862         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 863
 864         return 0;
 865 }
 866
 867 /**
 868  * Schedule buffer swap at given vertical blank.
 869  */
 870 static int i915_vblank_swap(struct drm_device *dev, void *data,
 871                      struct drm_file *file_priv)
 872 {
 873         /* The delayed swap mechanism was fundamentally racy, and has been
 874          * removed.  The model was that the client requested a delayed flip/swap
 875          * from the kernel, then waited for vblank before continuing to perform
 876          * rendering.  The problem was that the kernel might wake the client
 877          * up before it dispatched the vblank swap (since the lock has to be
 878          * held while touching the ringbuffer), in which case the client would
 879          * clear and start the next frame before the swap occurred, and
 880          * flicker would occur in addition to likely missing the vblank.
 881          *
 882          * In the absence of this ioctl, userland falls back to a correct path
 883          * of waiting for a vblank, then dispatching the swap on its own.
 884          * Context switching to userland and back is plenty fast enough for
 885          * meeting the requirements of vblank swapping.
 886          */
 887         return -EINVAL;
 888 }
 889
 890 static int i915_flip_bufs(struct drm_device *dev, void *data,
 891                           struct drm_file *file_priv)
 892 {
 893         int ret;
 894
 895         if (drm_core_check_feature(dev, DRIVER_MODESET))
 896                 return -ENODEV;
 897
 898         DRM_DEBUG_DRIVER("%s\n", __func__);
 899
 900         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 901
 902         mutex_lock(&dev->struct_mutex);
 903         ret = i915_dispatch_flip(dev);
 904         mutex_unlock(&dev->struct_mutex);
 905
 906         return ret;
 907 }
 908
 909 static int i915_getparam(struct drm_device *dev, void *data,
 910                          struct drm_file *file_priv)
 911 {
 912         drm_i915_private_t *dev_priv = dev->dev_private;
 913         drm_i915_getparam_t *param = data;
 914         int value;
 915
 916         if (!dev_priv) {
 917                 DRM_ERROR("called with no initialization\n");
 918                 return -EINVAL;
 919         }
 920
 921         switch (param->param) {
 922         case I915_PARAM_IRQ_ACTIVE:
 923                 value = dev->irq_enabled ? 1 : 0;
 924                 break;
 925         case I915_PARAM_ALLOW_BATCHBUFFER:
 926                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 927                 break;
 928         case I915_PARAM_LAST_DISPATCH:
 929                 value = READ_BREADCRUMB(dev_priv);
 930                 break;
 931         case I915_PARAM_CHIPSET_ID:
 932                 value = dev->pci_device;
 933                 break;
 934         case I915_PARAM_HAS_GEM:
 935                 value = 1;
 936                 break;
 937         case I915_PARAM_NUM_FENCES_AVAIL:
 938                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 939                 break;
 940         case I915_PARAM_HAS_OVERLAY:
 941                 value = dev_priv->overlay ? 1 : 0;
 942                 break;
 943         case I915_PARAM_HAS_PAGEFLIPPING:
 944                 value = 1;
 945                 break;
 946         case I915_PARAM_HAS_EXECBUF2:
 947                 /* depends on GEM */
 948                 value = 1;
 949                 break;
 950         case I915_PARAM_HAS_BSD:
 951                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 952                 break;
 953         case I915_PARAM_HAS_BLT:
 954                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 955                 break;
 956         case I915_PARAM_HAS_RELAXED_FENCING:
 957                 value = 1;
 958                 break;
 959         case I915_PARAM_HAS_COHERENT_RINGS:
 960                 value = 1;
 961                 break;
 962         case I915_PARAM_HAS_EXEC_CONSTANTS:
 963                 value = INTEL_INFO(dev)->gen >= 4;
 964                 break;
 965         case I915_PARAM_HAS_RELAXED_DELTA:
 966                 value = 1;
 967                 break;
 968         case I915_PARAM_HAS_GEN7_SOL_RESET:
 969                 value = 1;
 970                 break;
 971         case I915_PARAM_HAS_LLC:
 972                 value = HAS_LLC(dev);
 973                 break;
 974         case I915_PARAM_HAS_ALIASING_PPGTT:
 975                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
 976                 break;
 977         case I915_PARAM_HAS_WAIT_TIMEOUT:
 978                 value = 1;
 979                 break;
 980         case I915_PARAM_HAS_SEMAPHORES:
 981                 value = i915_semaphore_is_enabled(dev);
 982                 break;
 983         case I915_PARAM_HAS_PINNED_BATCHES:
 984                 value = 1;
 985                 break;
 986         case I915_PARAM_HAS_EXEC_NO_RELOC:
 987                 value = 1;
 988                 break;
 989         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 990                 value = 1;
 991                 break;
 992         default:
 993                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 994                                  param->param);
 995                 return -EINVAL;
 996         }
 997
 998         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 999                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1000                 return -EFAULT;
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int i915_setparam(struct drm_device *dev, void *data,
1007                          struct drm_file *file_priv)
1008 {
1009         drm_i915_private_t *dev_priv = dev->dev_private;
1010         drm_i915_setparam_t *param = data;
1011
1012         if (!dev_priv) {
1013                 DRM_ERROR("called with no initialization\n");
1014                 return -EINVAL;
1015         }
1016
1017         switch (param->param) {
1018         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1019                 break;
1020         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1021                 break;
1022         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1023                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1024                 break;
1025         case I915_SETPARAM_NUM_USED_FENCES:
1026                 if (param->value > dev_priv->num_fence_regs ||
1027                     param->value < 0)
1028                         return -EINVAL;
1029                 /* Userspace can use first N regs */
1030                 dev_priv->fence_reg_start = param->value;
1031                 break;
1032         default:
1033                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1034                                         param->param);
1035                 return -EINVAL;
1036         }
1037
1038         return 0;
1039 }
1040
1041 static int i915_set_status_page(struct drm_device *dev, void *data,
1042                                 struct drm_file *file_priv)
1043 {
1044 #if 0   /* We don't care about dri1 */
1045         drm_i915_private_t *dev_priv = dev->dev_private;
1046         drm_i915_hws_addr_t *hws = data;
1047         struct intel_ring_buffer *ring;
1048
1049         if (drm_core_check_feature(dev, DRIVER_MODESET))
1050                 return -ENODEV;
1051
1052         if (!I915_NEED_GFX_HWS(dev))
1053                 return -EINVAL;
1054
1055         if (!dev_priv) {
1056                 DRM_ERROR("called with no initialization\n");
1057                 return -EINVAL;
1058         }
1059
1060         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1061                 WARN(1, "tried to set status page when mode setting active\n");
1062                 return 0;
1063         }
1064
1065         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1066
1067         ring = LP_RING(dev_priv);
1068         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1069
1070         dev_priv->dri1.gfx_hws_cpu_addr =
1071                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1072         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1073                 i915_dma_cleanup(dev);
1074                 ring->status_page.gfx_addr = 0;
1075                 DRM_ERROR("can not ioremap virtual address for"
1076                                 " G33 hw status page\n");
1077                 return -ENOMEM;
1078         }
1079
1080         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1081         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1082
1083         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1084                          ring->status_page.gfx_addr);
1085         DRM_DEBUG_DRIVER("load hws at %p\n",
1086                          ring->status_page.page_addr);
1087         return 0;
1088 #endif
1089         return -EINVAL;
1090 }
1091
1092 static int i915_get_bridge_dev(struct drm_device *dev)
1093 {
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         static struct pci_dev i915_bridge_dev;
1096
1097         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1098         if (!i915_bridge_dev.dev) {
1099                 DRM_ERROR("bridge device not found\n");
1100                 return -1;
1101         }
1102
1103         dev_priv->bridge_dev = &i915_bridge_dev;
1104         return 0;
1105 }
1106
1107 #define MCHBAR_I915 0x44
1108 #define MCHBAR_I965 0x48
1109 #define MCHBAR_SIZE (4*4096)
1110
1111 #define DEVEN_REG 0x54
1112 #define   DEVEN_MCHBAR_EN (1 << 28)
1113
1114 /* Allocate space for the MCH regs if needed, return nonzero on error */
1115 static int
1116 intel_alloc_mchbar_resource(struct drm_device *dev)
1117 {
1118         drm_i915_private_t *dev_priv = dev->dev_private;
1119         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1120         device_t vga;
1121         u32 temp_lo, temp_hi = 0;
1122         u64 mchbar_addr;
1123
1124         if (INTEL_INFO(dev)->gen >= 4)
1125                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1126         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1127         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1128
1129         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1130 #ifdef CONFIG_PNP
1131         if (mchbar_addr &&
1132             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1133                 return 0;
1134 #endif
1135
1136         /* Get some space for it */
1137         vga = device_get_parent(dev->dev);
1138         dev_priv->mch_res_rid = 0x100;
1139         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1140             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1141             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1142         if (dev_priv->mch_res == NULL) {
1143                 DRM_ERROR("failed mchbar resource alloc\n");
1144                 return (-ENOMEM);
1145         }
1146
1147         if (INTEL_INFO(dev)->gen >= 4)
1148                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1149                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
1150
1151         pci_write_config_dword(dev_priv->bridge_dev, reg,
1152                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
1153         return 0;
1154 }
1155
1156 /* Setup MCHBAR if possible, return true if we should disable it again */
1157 static void
1158 intel_setup_mchbar(struct drm_device *dev)
1159 {
1160         drm_i915_private_t *dev_priv = dev->dev_private;
1161         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1162         u32 temp;
1163         bool enabled;
1164
1165         dev_priv->mchbar_need_disable = false;
1166
1167         if (IS_I915G(dev) || IS_I915GM(dev)) {
1168                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1169                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1170         } else {
1171                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1172                 enabled = temp & 1;
1173         }
1174
1175         /* If it's already enabled, don't have to do anything */
1176         if (enabled)
1177                 return;
1178
1179         if (intel_alloc_mchbar_resource(dev))
1180                 return;
1181
1182         dev_priv->mchbar_need_disable = true;
1183
1184         /* Space is allocated or reserved, so enable it. */
1185         if (IS_I915G(dev) || IS_I915GM(dev)) {
1186                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1187                                        temp | DEVEN_MCHBAR_EN);
1188         } else {
1189                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1190                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1191         }
1192 }
1193
1194 static void
1195 intel_teardown_mchbar(struct drm_device *dev)
1196 {
1197         drm_i915_private_t *dev_priv = dev->dev_private;
1198         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1199         device_t vga;
1200         u32 temp;
1201
1202         if (dev_priv->mchbar_need_disable) {
1203                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1204                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1205                         temp &= ~DEVEN_MCHBAR_EN;
1206                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1207                 } else {
1208                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1209                         temp &= ~1;
1210                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1211                 }
1212         }
1213
1214         if (dev_priv->mch_res != NULL) {
1215                 vga = device_get_parent(dev->dev);
1216                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1217                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1218                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1219                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1220                 dev_priv->mch_res = NULL;
1221         }
1222 }
1223
1224 static int i915_load_modeset_init(struct drm_device *dev)
1225 {
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         int ret;
1228
1229         ret = intel_parse_bios(dev);
1230         if (ret)
1231                 DRM_INFO("failed to find VBIOS tables\n");
1232
1233 #if 0
1234         /* If we have > 1 VGA cards, then we need to arbitrate access
1235          * to the common VGA resources.
1236          *
1237          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1238          * then we do not take part in VGA arbitration and the
1239          * vga_client_register() fails with -ENODEV.
1240          */
1241         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1242         if (ret && ret != -ENODEV)
1243                 goto out;
1244
1245         intel_register_dsm_handler();
1246
1247         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1248         if (ret)
1249                 goto cleanup_vga_client;
1250
1251         /* Initialise stolen first so that we may reserve preallocated
1252          * objects for the BIOS to KMS transition.
1253          */
1254         ret = i915_gem_init_stolen(dev);
1255         if (ret)
1256                 goto cleanup_vga_switcheroo;
1257 #endif
1258
1259         ret = drm_irq_install(dev);
1260         if (ret)
1261                 goto cleanup_gem_stolen;
1262
1263         /* Important: The output setup functions called by modeset_init need
1264          * working irqs for e.g. gmbus and dp aux transfers. */
1265         intel_modeset_init(dev);
1266
1267         ret = i915_gem_init(dev);
1268         if (ret)
1269                 goto cleanup_irq;
1270
1271 #if 0
1272         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1273 #endif
1274
1275         intel_modeset_gem_init(dev);
1276
1277         /* Always safe in the mode setting case. */
1278         /* FIXME: do pre/post-mode set stuff in core KMS code */
1279         dev->vblank_disable_allowed = 1;
1280         if (INTEL_INFO(dev)->num_pipes == 0) {
1281                 dev_priv->mm.suspended = 0;
1282                 return 0;
1283         }
1284
1285         ret = intel_fbdev_init(dev);
1286         if (ret)
1287                 goto cleanup_gem;
1288
1289         /* Only enable hotplug handling once the fbdev is fully set up. */
1290         intel_hpd_init(dev);
1291
1292         /*
1293          * Some ports require correctly set-up hpd registers for detection to
1294          * work properly (leading to ghost connected connector status), e.g. VGA
1295          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1296          * irqs are fully enabled. Now we should scan for the initial config
1297          * only once hotplug handling is enabled, but due to screwed-up locking
1298          * around kms/fbdev init we can't protect the fdbev initial config
1299          * scanning against hotplug events. Hence do this first and ignore the
1300          * tiny window where we will loose hotplug notifactions.
1301          */
1302         intel_fbdev_initial_config(dev);
1303
1304         /* Only enable hotplug handling once the fbdev is fully set up. */
1305         dev_priv->enable_hotplug_processing = true;
1306
1307         drm_kms_helper_poll_init(dev);
1308
1309         /* We're off and running w/KMS */
1310         dev_priv->mm.suspended = 0;
1311
1312         return 0;
1313
1314 cleanup_gem:
1315         mutex_lock(&dev->struct_mutex);
1316         i915_gem_cleanup_ringbuffer(dev);
1317         mutex_unlock(&dev->struct_mutex);
1318         i915_gem_cleanup_aliasing_ppgtt(dev);
1319 cleanup_irq:
1320         drm_irq_uninstall(dev);
1321 cleanup_gem_stolen:
1322 #if 0
1323         i915_gem_cleanup_stolen(dev);
1324 cleanup_vga_switcheroo:
1325         vga_switcheroo_unregister_client(dev->pdev);
1326 cleanup_vga_client:
1327         vga_client_register(dev->pdev, NULL, NULL, NULL);
1328 out:
1329 #endif
1330         return ret;
1331 }
1332
1333 #if 0
1334 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1335 {
1336         struct apertures_struct *ap;
1337         struct pci_dev *pdev = dev_priv->dev->pdev;
1338         bool primary;
1339
1340         ap = alloc_apertures(1);
1341         if (!ap)
1342                 return;
1343
1344         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1345         ap->ranges[0].size = dev_priv->gtt.mappable_end - dev_priv->gtt.start;
1346
1347         primary =
1348                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1349
1350         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1351
1352         kfree(ap);
1353 }
1354
1355 /**
1356  * intel_early_sanitize_regs - clean up BIOS state
1357  * @dev: DRM device
1358  *
1359  * This function must be called before we do any I915_READ or I915_WRITE. Its
1360  * purpose is to clean up any state left by the BIOS that may affect us when
1361  * reading and/or writing registers.
1362  */
1363 static void intel_early_sanitize_regs(struct drm_device *dev)
1364 {
1365         struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367         if (IS_HASWELL(dev))
1368                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1369 }
1370 #endif
1371
1372 /**
1373  * i915_driver_load - setup chip and create an initial config
1374  * @dev: DRM device
1375  * @flags: startup flags
1376  *
1377  * The driver load routine has to do several things:
1378  *   - drive output discovery via intel_modeset_init()
1379  *   - initialize the memory manager
1380  *   - allocate initial config memory
1381  *   - setup the DRM framebuffer with the allocated memory
1382  */
1383 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1384 {
1385         struct drm_i915_private *dev_priv = dev->dev_private;
1386         const struct intel_device_info *info;
1387         unsigned long base, size;
1388         int ret = 0, mmio_bar, mmio_size;
1389         uint32_t aperture_size;
1390         static struct pci_dev i915_pdev;
1391
1392         /* XXX: struct pci_dev */
1393         i915_pdev.dev = dev->dev;
1394         dev->pdev = &i915_pdev;
1395
1396         info = i915_get_device_id(dev->pci_device);
1397
1398         /* Refuse to load on gen6+ without kms enabled. */
1399         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET))
1400                 return -ENODEV;
1401
1402         /* i915 has 4 more counters */
1403         dev->counters += 4;
1404         dev->types[6] = _DRM_STAT_IRQ;
1405         dev->types[7] = _DRM_STAT_PRIMARY;
1406         dev->types[8] = _DRM_STAT_SECONDARY;
1407         dev->types[9] = _DRM_STAT_DMA;
1408
1409         dev_priv = kmalloc(sizeof(drm_i915_private_t), M_DRM,
1410             M_ZERO | M_WAITOK);
1411         if (dev_priv == NULL)
1412                 return -ENOMEM;
1413
1414         dev->dev_private = (void *)dev_priv;
1415         dev_priv->dev = dev;
1416         dev_priv->info = info;
1417
1418         if (i915_get_bridge_dev(dev)) {
1419                 ret = -EIO;
1420                 goto free_priv;
1421         }
1422
1423         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1424         /* Before gen4, the registers and the GTT are behind different BARs.
1425          * However, from gen4 onwards, the registers and the GTT are shared
1426          * in the same BAR, so we want to restrict this ioremap from
1427          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1428          * the register BAR remains the same size for all the earlier
1429          * generations up to Ironlake.
1430          */
1431         if (info->gen < 5)
1432                 mmio_size = 512*1024;
1433         else
1434                 mmio_size = 2*1024*1024;
1435
1436 #if 0
1437         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1438         if (!dev_priv->regs) {
1439                 DRM_ERROR("failed to map registers\n");
1440                 ret = -EIO;
1441                 goto put_bridge;
1442         }
1443
1444         intel_early_sanitize_regs(dev);
1445 #endif
1446
1447         ret = i915_gem_gtt_init(dev);
1448         if (ret)
1449                 goto put_bridge;
1450
1451 #if 0
1452         if (drm_core_check_feature(dev, DRIVER_MODESET))
1453                 i915_kick_out_firmware_fb(dev_priv);
1454
1455         pci_set_master(dev->pdev);
1456
1457         /* overlay on gen2 is broken and can't address above 1G */
1458         if (IS_GEN2(dev))
1459                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1460
1461         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1462          * using 32bit addressing, overwriting memory if HWS is located
1463          * above 4GB.
1464          *
1465          * The documentation also mentions an issue with undefined
1466          * behaviour if any general state is accessed within a page above 4GB,
1467          * which also needs to be handled carefully.
1468          */
1469         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1470                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1471 #endif
1472
1473         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1474
1475 #if 0
1476         dev_priv->gtt.mappable =
1477                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1478                                      aperture_size);
1479         if (dev_priv->gtt.mappable == NULL) {
1480                 ret = -EIO;
1481                 goto out_rmmap;
1482         }
1483
1484         i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
1485                         aperture_size);
1486 #endif
1487
1488         base = drm_get_resource_start(dev, mmio_bar);
1489         size = drm_get_resource_len(dev, mmio_bar);
1490
1491         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1492             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1493
1494         /* The i915 workqueue is primarily used for batched retirement of
1495          * requests (and thus managing bo) once the task has been completed
1496          * by the GPU. i915_gem_retire_requests() is called directly when we
1497          * need high-priority retirement, such as waiting for an explicit
1498          * bo.
1499          *
1500          * It is also used for periodic low-priority events, such as
1501          * idle-timers and recording error state.
1502          *
1503          * All tasks on the workqueue are expected to acquire the dev mutex
1504          * so there is no point in running more than one instance of the
1505          * workqueue at any time.  Use an ordered one.
1506          */
1507         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1508         if (dev_priv->wq == NULL) {
1509                 DRM_ERROR("Failed to create our workqueue.\n");
1510                 ret = -ENOMEM;
1511                 goto out_mtrrfree;
1512         }
1513
1514         /* This must be called before any calls to HAS_PCH_* */
1515         intel_detect_pch(dev);
1516
1517         intel_irq_init(dev);
1518         intel_gt_init(dev);
1519
1520         /* Try to make sure MCHBAR is enabled before poking at it */
1521         intel_setup_mchbar(dev);
1522         intel_setup_gmbus(dev);
1523         intel_opregion_setup(dev);
1524
1525         intel_setup_bios(dev);
1526
1527         i915_gem_load(dev);
1528
1529         /* On the 945G/GM, the chipset reports the MSI capability on the
1530          * integrated graphics even though the support isn't actually there
1531          * according to the published specs.  It doesn't appear to function
1532          * correctly in testing on 945G.
1533          * This may be a side effect of MSI having been made available for PEG
1534          * and the registers being closely associated.
1535          *
1536          * According to chipset errata, on the 965GM, MSI interrupts may
1537          * be lost or delayed, but we use them anyways to avoid
1538          * stuck interrupts on some machines.
1539          */
1540 #if 0
1541         if (!IS_I945G(dev) && !IS_I945GM(dev))
1542                 pci_enable_msi(dev->pdev);
1543 #endif
1544
1545         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1546         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1547         spin_init(&dev_priv->rps.lock, "i915initrps");
1548         lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1549
1550         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1551         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1552
1553         dev_priv->num_plane = 1;
1554         if (IS_VALLEYVIEW(dev))
1555                 dev_priv->num_plane = 2;
1556
1557         if (INTEL_INFO(dev)->num_pipes) {
1558                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1559                 if (ret)
1560                         goto out_gem_unload;
1561         }
1562
1563         /* Start out suspended */
1564         dev_priv->mm.suspended = 1;
1565
1566         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1567                 ret = i915_load_modeset_init(dev);
1568                 if (ret < 0) {
1569                         DRM_ERROR("failed to init modeset\n");
1570                         goto out_gem_unload;
1571                 }
1572         }
1573
1574 #if 0
1575         i915_setup_sysfs(dev);
1576 #endif
1577
1578         if (INTEL_INFO(dev)->num_pipes) {
1579                 /* Must be done after probing outputs */
1580                 intel_opregion_init(dev);
1581 #if 0
1582                 acpi_video_register();
1583 #endif
1584         }
1585
1586         if (IS_GEN5(dev))
1587                 intel_gpu_ips_init(dev_priv);
1588
1589         return 0;
1590
1591 out_gem_unload:
1592
1593         intel_teardown_gmbus(dev);
1594         intel_teardown_mchbar(dev);
1595         destroy_workqueue(dev_priv->wq);
1596 out_mtrrfree:
1597 put_bridge:
1598 free_priv:
1599         kfree(dev_priv);
1600         return ret;
1601 }
1602
1603 int i915_driver_unload(struct drm_device *dev)
1604 {
1605         struct drm_i915_private *dev_priv = dev->dev_private;
1606         int ret;
1607
1608         intel_gpu_ips_teardown();
1609
1610 #if 0
1611         i915_teardown_sysfs(dev);
1612
1613         if (dev_priv->mm.inactive_shrinker.shrink)
1614                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1615 #endif
1616
1617         mutex_lock(&dev->struct_mutex);
1618         ret = i915_gpu_idle(dev);
1619         if (ret)
1620                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1621         i915_gem_retire_requests(dev);
1622         mutex_unlock(&dev->struct_mutex);
1623
1624         /* Cancel the retire work handler, which should be idle now. */
1625         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1626
1627 #if 0
1628         io_mapping_free(dev_priv->gtt.mappable);
1629         if (dev_priv->mm.gtt_mtrr >= 0) {
1630                 mtrr_del(dev_priv->mm.gtt_mtrr,
1631                          dev_priv->gtt.mappable_base,
1632                          dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1633                 dev_priv->mm.gtt_mtrr = -1;
1634         }
1635
1636         acpi_video_unregister();
1637 #endif
1638
1639         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1640                 intel_fbdev_fini(dev);
1641                 intel_modeset_cleanup(dev);
1642 #if 0
1643                 cancel_work_sync(&dev_priv->console_resume_work);
1644 #endif
1645
1646                 /*
1647                  * free the memory space allocated for the child device
1648                  * config parsed from VBT
1649                  */
1650                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1651                         kfree(dev_priv->child_dev);
1652                         dev_priv->child_dev = NULL;
1653                         dev_priv->child_dev_num = 0;
1654                 }
1655
1656         }
1657
1658         /* Free error state after interrupts are fully disabled. */
1659         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1660         cancel_work_sync(&dev_priv->gpu_error.work);
1661         i915_destroy_error_state(dev);
1662
1663         intel_opregion_fini(dev);
1664
1665         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1666                 /* Flush any outstanding unpin_work. */
1667                 flush_workqueue(dev_priv->wq);
1668
1669                 mutex_lock(&dev->struct_mutex);
1670                 i915_gem_free_all_phys_object(dev);
1671                 i915_gem_cleanup_ringbuffer(dev);
1672                 i915_gem_context_fini(dev);
1673                 mutex_unlock(&dev->struct_mutex);
1674                 i915_gem_cleanup_aliasing_ppgtt(dev);
1675 #if 0
1676                 i915_gem_cleanup_stolen(dev);
1677 #endif
1678
1679                 if (!I915_NEED_GFX_HWS(dev))
1680                         i915_free_hws(dev);
1681         }
1682
1683 #if 0
1684         if (dev_priv->regs != NULL)
1685                 pci_iounmap(dev->pdev, dev_priv->regs);
1686 #endif
1687
1688         intel_teardown_gmbus(dev);
1689         intel_teardown_mchbar(dev);
1690
1691         bus_generic_detach(dev->dev);
1692         drm_rmmap(dev, dev_priv->mmio_map);
1693         intel_teardown_gmbus(dev);
1694
1695         destroy_workqueue(dev_priv->wq);
1696         pm_qos_remove_request(&dev_priv->pm_qos);
1697
1698         pci_dev_put(dev_priv->bridge_dev);
1699         drm_free(dev->dev_private, M_DRM);
1700
1701         return 0;
1702 }
1703
1704 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1705 {
1706         struct drm_i915_file_private *file_priv;
1707
1708         DRM_DEBUG_DRIVER("\n");
1709         file_priv = kmalloc(sizeof(*file_priv), M_DRM, M_WAITOK | M_ZERO);
1710         if (!file_priv)
1711                 return -ENOMEM;
1712
1713         file->driver_priv = file_priv;
1714
1715         spin_init(&file_priv->mm.lock, "i915_priv");
1716         INIT_LIST_HEAD(&file_priv->mm.request_list);
1717
1718         idr_init(&file_priv->context_idr);
1719
1720         return 0;
1721 }
1722
1723 /**
1724  * i915_driver_lastclose - clean up after all DRM clients have exited
1725  * @dev: DRM device
1726  *
1727  * Take care of cleaning up after all DRM clients have exited.  In the
1728  * mode setting case, we want to restore the kernel's initial mode (just
1729  * in case the last client left us in a bad state).
1730  *
1731  * Additionally, in the non-mode setting case, we'll tear down the GTT
1732  * and DMA structures, since the kernel won't be using them, and clea
1733  * up any GEM state.
1734  */
1735 void i915_driver_lastclose(struct drm_device * dev)
1736 {
1737         drm_i915_private_t *dev_priv = dev->dev_private;
1738
1739         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1740          * goes right around and calls lastclose. Check for this and don't clean
1741          * up anything. */
1742         if (!dev_priv)
1743                 return;
1744
1745         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1746 #if 0
1747                 intel_fb_restore_mode(dev);
1748                 vga_switcheroo_process_delayed_switch();
1749 #endif
1750                 return;
1751         }
1752
1753         i915_gem_lastclose(dev);
1754
1755         i915_dma_cleanup(dev);
1756 }
1757
1758 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1759 {
1760         i915_gem_context_close(dev, file_priv);
1761         i915_gem_release(dev, file_priv);
1762 }
1763
1764 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1765 {
1766         struct drm_i915_file_private *file_priv = file->driver_priv;
1767
1768         kfree(file_priv);
1769 }
1770
1771 struct drm_ioctl_desc i915_ioctls[] = {
1772         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1773         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1774         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1775         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1776         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1777         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1778         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1779         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1780         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1781         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1782         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1783         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1784         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1785         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1786         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1787         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1788         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1789         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1790         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1791         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1792         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1793         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1794         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1795         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1796         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1797         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1798         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1799         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1800         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1801         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1802         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1803         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1804         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1805         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1806         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1807         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1808         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1809         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1810         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1811         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1812         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1813         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1814         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1815         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1816         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1817         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1818         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1819         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1820 };
1821
1822 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1823
1824 /*
1825  * This is really ugly: Because old userspace abused the linux agp interface to
1826  * manage the gtt, we need to claim that all intel devices are agp.  For
1827  * otherwise the drm core refuses to initialize the agp support code.
1828  */
1829 int i915_driver_device_is_agp(struct drm_device * dev)
1830 {
1831         return 1;
1832 }