sys/dev/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include <drm/drm_pciids.h>
  34 #include "intel_drv.h"
  35
  36 /*               "Specify LVDS channel mode "
  37                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)" */
  38 int i915_lvds_channel_mode __read_mostly = 0;
  39 TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
  40
  41 int i915_disable_power_well __read_mostly = 0;
  42 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
  43 MODULE_PARM_DESC(disable_power_well,
  44                  "Disable the power well when possible (default: false)");
  45
  46 bool i915_enable_hangcheck __read_mostly = true;
  47 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
  48 MODULE_PARM_DESC(enable_hangcheck,
  49                 "Periodically check GPU activity for detecting hangs. "
  50                 "WARNING: Disabling this can cause system wide hangs. "
  51                 "(default: true)");
  52
  53 static struct drm_driver driver;
  54
  55 #define INTEL_VGA_DEVICE(id, info) {            \
  56         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
  57         .class_mask = 0xff0000,                 \
  58         .vendor = 0x8086,                       \
  59         .device = id,                           \
  60         .subvendor = PCI_ANY_ID,                \
  61         .subdevice = PCI_ANY_ID,                \
  62         .driver_data = (unsigned long) info }
  63
  64 #define INTEL_QUANTA_VGA_DEVICE(info) {         \
  65         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
  66         .class_mask = 0xff0000,                 \
  67         .vendor = 0x8086,                       \
  68         .device = 0x16a,                        \
  69         .subvendor = 0x152d,                    \
  70         .subdevice = 0x8990,                    \
  71         .driver_data = (unsigned long) info }
  72
  73
  74 static const struct intel_device_info intel_i830_info = {
  75         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77 };
  78
  79 static const struct intel_device_info intel_845g_info = {
  80         .gen = 2, .num_pipes = 1,
  81         .has_overlay = 1, .overlay_needs_physical = 1,
  82 };
  83
  84 static const struct intel_device_info intel_i85x_info = {
  85         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  86         .cursor_needs_physical = 1,
  87         .has_overlay = 1, .overlay_needs_physical = 1,
  88 };
  89
  90 static const struct intel_device_info intel_i865g_info = {
  91         .gen = 2, .num_pipes = 1,
  92         .has_overlay = 1, .overlay_needs_physical = 1,
  93 };
  94
  95 static const struct intel_device_info intel_i915g_info = {
  96         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  97         .has_overlay = 1, .overlay_needs_physical = 1,
  98 };
  99 static const struct intel_device_info intel_i915gm_info = {
 100         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 101         .cursor_needs_physical = 1,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .supports_tv = 1,
 104 };
 105 static const struct intel_device_info intel_i945g_info = {
 106         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 107         .has_overlay = 1, .overlay_needs_physical = 1,
 108 };
 109 static const struct intel_device_info intel_i945gm_info = {
 110         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 111         .has_hotplug = 1, .cursor_needs_physical = 1,
 112         .has_overlay = 1, .overlay_needs_physical = 1,
 113         .supports_tv = 1,
 114 };
 115
 116 static const struct intel_device_info intel_i965g_info = {
 117         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 118         .has_hotplug = 1,
 119         .has_overlay = 1,
 120 };
 121
 122 static const struct intel_device_info intel_i965gm_info = {
 123         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 124         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 125         .has_overlay = 1,
 126         .supports_tv = 1,
 127 };
 128
 129 static const struct intel_device_info intel_g33_info = {
 130         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 131         .need_gfx_hws = 1, .has_hotplug = 1,
 132         .has_overlay = 1,
 133 };
 134
 135 static const struct intel_device_info intel_g45_info = {
 136         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 137         .has_pipe_cxsr = 1, .has_hotplug = 1,
 138         .has_bsd_ring = 1,
 139 };
 140
 141 static const struct intel_device_info intel_gm45_info = {
 142         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 143         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 144         .has_pipe_cxsr = 1, .has_hotplug = 1,
 145         .supports_tv = 1,
 146         .has_bsd_ring = 1,
 147 };
 148
 149 static const struct intel_device_info intel_pineview_info = {
 150         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 151         .need_gfx_hws = 1, .has_hotplug = 1,
 152         .has_overlay = 1,
 153 };
 154
 155 static const struct intel_device_info intel_ironlake_d_info = {
 156         .gen = 5, .num_pipes = 2,
 157         .need_gfx_hws = 1, .has_hotplug = 1,
 158         .has_bsd_ring = 1,
 159 };
 160
 161 static const struct intel_device_info intel_ironlake_m_info = {
 162         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 163         .need_gfx_hws = 1, .has_hotplug = 1,
 164         .has_fbc = 1,
 165         .has_bsd_ring = 1,
 166 };
 167
 168 static const struct intel_device_info intel_sandybridge_d_info = {
 169         .gen = 6, .num_pipes = 2,
 170         .need_gfx_hws = 1, .has_hotplug = 1,
 171         .has_bsd_ring = 1,
 172         .has_blt_ring = 1,
 173         .has_llc = 1,
 174         .has_force_wake = 1,
 175 };
 176
 177 static const struct intel_device_info intel_sandybridge_m_info = {
 178         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 179         .need_gfx_hws = 1, .has_hotplug = 1,
 180         .has_fbc = 1,
 181         .has_bsd_ring = 1,
 182         .has_blt_ring = 1,
 183         .has_llc = 1,
 184         .has_force_wake = 1,
 185 };
 186
 187 #define GEN7_FEATURES  \
 188         .gen = 7, .num_pipes = 3, \
 189         .need_gfx_hws = 1, .has_hotplug = 1, \
 190         .has_bsd_ring = 1, \
 191         .has_blt_ring = 1, \
 192         .has_llc = 1, \
 193         .has_force_wake = 1
 194
 195 static const struct intel_device_info intel_ivybridge_d_info = {
 196         GEN7_FEATURES,
 197         .is_ivybridge = 1,
 198 };
 199
 200 static const struct intel_device_info intel_ivybridge_m_info = {
 201         GEN7_FEATURES,
 202         .is_ivybridge = 1,
 203         .is_mobile = 1,
 204 };
 205
 206 static const struct intel_device_info intel_ivybridge_q_info = {
 207         GEN7_FEATURES,
 208         .is_ivybridge = 1,
 209         .num_pipes = 0, /* legal, last one wins */
 210 };
 211
 212 static const struct intel_device_info intel_valleyview_m_info = {
 213         GEN7_FEATURES,
 214         .is_mobile = 1,
 215         .num_pipes = 2,
 216         .is_valleyview = 1,
 217         .display_mmio_offset = VLV_DISPLAY_BASE,
 218         .has_llc = 0, /* legal, last one wins */
 219 };
 220
 221 static const struct intel_device_info intel_valleyview_d_info = {
 222         GEN7_FEATURES,
 223         .num_pipes = 2,
 224         .is_valleyview = 1,
 225         .display_mmio_offset = VLV_DISPLAY_BASE,
 226         .has_llc = 0, /* legal, last one wins */
 227 };
 228
 229 static const struct intel_device_info intel_haswell_d_info = {
 230         GEN7_FEATURES,
 231         .is_haswell = 1,
 232 };
 233
 234 static const struct intel_device_info intel_haswell_m_info = {
 235         GEN7_FEATURES,
 236         .is_haswell = 1,
 237         .is_mobile = 1,
 238 };
 239
 240 static const struct pci_device_id pciidlist[] = {               /* aka */
 241         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 242         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 243         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 244         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 245         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 246         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 247         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 248         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 249         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 250         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 251         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 252         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 253         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 254         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 255         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 256         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 257         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 258         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 259         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 260         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 261         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 262         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 263         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 264         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 265         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 266         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 267         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 268         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 269         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 270         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 271         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 272         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 273         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 274         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 275         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 276         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 277         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 278         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 279         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 280         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 281         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 282         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 283         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 284         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 285         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 286         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 287         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
 288         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 289         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 290         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
 291         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 292         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 293         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 294         INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
 295         INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
 296         INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
 297         INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
 298         INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
 299         INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
 300         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 301         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 302         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
 303         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 304         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 305         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
 306         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 307         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 308         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
 309         INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
 310         INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
 311         INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
 312         INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
 313         INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
 314         INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
 315         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 316         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 317         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
 318         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 319         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 320         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
 321         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 322         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 323         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
 324         INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
 325         INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
 326         INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
 327         INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
 328         INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
 329         INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
 330         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 331         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 332         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
 333         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 334         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 335         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
 336         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 337         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 338         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
 339         INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
 340         INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
 341         INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
 342         INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
 343         INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
 344         INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
 345         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 346         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
 347         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
 348         INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
 349         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 350         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 351         {0, 0}
 352 };
 353
 354 #define PCI_VENDOR_INTEL        0x8086
 355
 356 void intel_detect_pch(struct drm_device *dev)
 357 {
 358         struct drm_i915_private *dev_priv = dev->dev_private;
 359         device_t pch;
 360
 361         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 362          * (which really amounts to a PCH but no South Display).
 363          */
 364         if (INTEL_INFO(dev)->num_pipes == 0) {
 365                 dev_priv->pch_type = PCH_NOP;
 366                 dev_priv->num_pch_pll = 0;
 367                 return;
 368         }
 369
 370         /*
 371          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 372          * make graphics device passthrough work easy for VMM, that only
 373          * need to expose ISA bridge to let driver know the real hardware
 374          * underneath. This is a requirement from virtualization team.
 375          */
 376         pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
 377         if (pch) {
 378                 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
 379                         unsigned short id;
 380                         id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
 381                         dev_priv->pch_id = id;
 382
 383                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 384                                 dev_priv->pch_type = PCH_IBX;
 385                                 dev_priv->num_pch_pll = 2;
 386                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 387                                 WARN_ON(!IS_GEN5(dev));
 388                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 389                                 dev_priv->pch_type = PCH_CPT;
 390                                 dev_priv->num_pch_pll = 2;
 391                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 392                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 393                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 394                                 /* PantherPoint is CPT compatible */
 395                                 dev_priv->pch_type = PCH_CPT;
 396                                 dev_priv->num_pch_pll = 2;
 397                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 398                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 399                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 400                                 dev_priv->pch_type = PCH_LPT;
 401                                 dev_priv->num_pch_pll = 0;
 402                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 403                                 WARN_ON(!IS_HASWELL(dev));
 404                                 WARN_ON(IS_ULT(dev));
 405                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 406                                 dev_priv->pch_type = PCH_LPT;
 407                                 dev_priv->num_pch_pll = 0;
 408                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 409                                 WARN_ON(!IS_HASWELL(dev));
 410                                 WARN_ON(!IS_ULT(dev));
 411                         }
 412                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 413                 }
 414 #if 0
 415                 pci_dev_put(pch);
 416 #endif
 417         }
 418 }
 419
 420 bool i915_semaphore_is_enabled(struct drm_device *dev)
 421 {
 422         if (INTEL_INFO(dev)->gen < 6)
 423                 return 0;
 424
 425         if (i915_semaphores >= 0)
 426                 return i915_semaphores;
 427
 428 #ifdef CONFIG_INTEL_IOMMU
 429         /* Enable semaphores on SNB when IO remapping is off */
 430         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 431                 return false;
 432 #endif
 433
 434         return 1;
 435 }
 436
 437 static int i915_drm_freeze(struct drm_device *dev)
 438 {
 439         struct drm_i915_private *dev_priv = dev->dev_private;
 440         struct drm_crtc *crtc;
 441
 442         /* ignore lid events during suspend */
 443         mutex_lock(&dev_priv->modeset_restore_lock);
 444         dev_priv->modeset_restore = MODESET_SUSPENDED;
 445         mutex_unlock(&dev_priv->modeset_restore_lock);
 446
 447         intel_set_power_well(dev, true);
 448
 449         drm_kms_helper_poll_disable(dev);
 450
 451 #if 0
 452         pci_save_state(dev->pdev);
 453 #endif
 454
 455         /* If KMS is active, we do the leavevt stuff here */
 456         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 457                 int error = i915_gem_idle(dev);
 458                 if (error) {
 459                         dev_err(dev->pdev->dev,
 460                                 "GEM idle failed, resume might fail\n");
 461                         return error;
 462                 }
 463
 464                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 465
 466                 drm_irq_uninstall(dev);
 467                 dev_priv->enable_hotplug_processing = false;
 468                 /*
 469                  * Disable CRTCs directly since we want to preserve sw state
 470                  * for _thaw.
 471                  */
 472                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 473                         dev_priv->display.crtc_disable(crtc);
 474         }
 475
 476         i915_save_state(dev);
 477
 478         intel_opregion_fini(dev);
 479
 480         return 0;
 481 }
 482
 483 static int
 484 i915_suspend(device_t kdev)
 485 {
 486         struct drm_device *dev;
 487         int error;
 488
 489         dev = device_get_softc(kdev);
 490         if (dev == NULL || dev->dev_private == NULL) {
 491                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 492                 return -ENODEV;
 493         }
 494
 495         DRM_DEBUG_KMS("starting suspend\n");
 496         error = i915_drm_freeze(dev);
 497         if (error)
 498                 return (error);
 499
 500         error = bus_generic_suspend(kdev);
 501         DRM_DEBUG_KMS("finished suspend %d\n", error);
 502         return (error);
 503 }
 504
 505 static void intel_resume_hotplug(struct drm_device *dev)
 506 {
 507         struct drm_mode_config *mode_config = &dev->mode_config;
 508         struct intel_encoder *encoder;
 509
 510         mutex_lock(&mode_config->mutex);
 511         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 512
 513         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 514                 if (encoder->hot_plug)
 515                         encoder->hot_plug(encoder);
 516
 517         mutex_unlock(&mode_config->mutex);
 518
 519         /* Just fire off a uevent and let userspace tell us what to do */
 520         drm_helper_hpd_irq_event(dev);
 521 }
 522
 523 static int __i915_drm_thaw(struct drm_device *dev)
 524 {
 525         struct drm_i915_private *dev_priv = dev->dev_private;
 526         int error = 0;
 527
 528         i915_restore_state(dev);
 529         intel_opregion_setup(dev);
 530
 531         /* KMS EnterVT equivalent */
 532         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 533                 intel_init_pch_refclk(dev);
 534
 535                 mutex_lock(&dev->struct_mutex);
 536                 dev_priv->mm.suspended = 0;
 537
 538                 error = i915_gem_init_hw(dev);
 539                 mutex_unlock(&dev->struct_mutex);
 540
 541                 /* We need working interrupts for modeset enabling ... */
 542                 drm_irq_install(dev);
 543
 544                 intel_modeset_init_hw(dev);
 545
 546                 drm_modeset_lock_all(dev);
 547                 intel_modeset_setup_hw_state(dev, true);
 548                 drm_modeset_unlock_all(dev);
 549
 550                 /*
 551                  * ... but also need to make sure that hotplug processing
 552                  * doesn't cause havoc. Like in the driver load code we don't
 553                  * bother with the tiny race here where we might loose hotplug
 554                  * notifications.
 555                  * */
 556                 intel_hpd_init(dev);
 557                 dev_priv->enable_hotplug_processing = true;
 558                 /* Config may have changed between suspend and resume */
 559                 intel_resume_hotplug(dev);
 560         }
 561
 562         intel_opregion_init(dev);
 563
 564         /*
 565          * The console lock can be pretty contented on resume due
 566          * to all the printk activity.  Try to keep it out of the hot
 567          * path of resume if possible.
 568          */
 569 #if 0
 570         if (console_trylock()) {
 571                 intel_fbdev_set_suspend(dev, 0);
 572                 console_unlock();
 573         } else {
 574                 schedule_work(&dev_priv->console_resume_work);
 575         }
 576 #endif
 577
 578         mutex_lock(&dev_priv->modeset_restore_lock);
 579         dev_priv->modeset_restore = MODESET_DONE;
 580         mutex_unlock(&dev_priv->modeset_restore_lock);
 581         return error;
 582 }
 583
 584 static int i915_drm_thaw(struct drm_device *dev)
 585 {
 586         int error = 0;
 587
 588         intel_gt_reset(dev);
 589
 590         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 591                 mutex_lock(&dev->struct_mutex);
 592                 i915_gem_restore_gtt_mappings(dev);
 593                 mutex_unlock(&dev->struct_mutex);
 594         }
 595
 596         __i915_drm_thaw(dev);
 597
 598         return error;
 599 }
 600
 601 static int
 602 i915_resume(device_t kdev)
 603 {
 604         struct drm_device *dev;
 605         int ret;
 606
 607         dev = device_get_softc(kdev);
 608         DRM_DEBUG_KMS("starting resume\n");
 609 #if 0
 610         if (pci_enable_device(dev->pdev))
 611                 return -EIO;
 612
 613         pci_set_master(dev->pdev);
 614 #endif
 615
 616         ret = -i915_drm_thaw(dev);
 617         if (ret != 0)
 618                 return (ret);
 619
 620         drm_kms_helper_poll_enable(dev);
 621         ret = bus_generic_resume(kdev);
 622         DRM_DEBUG_KMS("finished resume %d\n", ret);
 623         return (ret);
 624 }
 625
 626 /* XXX Hack for the old *BSD drm code base
 627  * The device id field is set at probe time */
 628 static drm_pci_id_list_t i915_attach_list[] = {
 629         {0x8086, 0, 0, "Intel i915 GPU"},
 630         {0, 0, 0, NULL}
 631 };
 632
 633 int i915_modeset;
 634
 635 /* static int __init i915_init(void) */
 636 static int
 637 i915_attach(device_t kdev)
 638 {
 639         struct drm_device *dev;
 640
 641         dev = device_get_softc(kdev);
 642
 643         driver.num_ioctls = i915_max_ioctl;
 644
 645         if (i915_modeset == 1)
 646                 driver.driver_features |= DRIVER_MODESET;
 647
 648         dev->driver = &driver;
 649         return (drm_attach(kdev, i915_attach_list));
 650 }
 651
 652 const struct intel_device_info *
 653 i915_get_device_id(int device)
 654 {
 655         const struct pci_device_id *did;
 656
 657         for (did = &pciidlist[0]; did->device != 0; did++) {
 658                 if (did->device != device)
 659                         continue;
 660                 return (struct intel_device_info *)did->driver_data;
 661         }
 662         return (NULL);
 663 }
 664
 665 extern devclass_t drm_devclass;
 666
 667 int intel_iommu_enabled = 0;
 668 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
 669
 670 int i915_semaphores = -1;
 671 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
 672 static int i915_try_reset = 1;
 673 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
 674 unsigned int i915_lvds_downclock = 0;
 675 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
 676 int i915_vbt_sdvo_panel_type = -1;
 677 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
 678 unsigned int i915_powersave = 1;
 679 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
 680 int i915_enable_fbc = 0;
 681 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
 682 int i915_enable_rc6 = 0;
 683 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
 684 int i915_panel_use_ssc = -1;
 685 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
 686 int i915_panel_ignore_lid = 0;
 687 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
 688 int i915_modeset = 1;
 689 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
 690 int i915_enable_ppgtt = -1;
 691 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
 692
 693 static int i8xx_do_reset(struct drm_device *dev)
 694 {
 695         struct drm_i915_private *dev_priv = dev->dev_private;
 696
 697         if (IS_I85X(dev))
 698                 return -ENODEV;
 699
 700         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 701         POSTING_READ(D_STATE);
 702
 703         if (IS_I830(dev) || IS_845G(dev)) {
 704                 I915_WRITE(DEBUG_RESET_I830,
 705                            DEBUG_RESET_DISPLAY |
 706                            DEBUG_RESET_RENDER |
 707                            DEBUG_RESET_FULL);
 708                 POSTING_READ(DEBUG_RESET_I830);
 709                 msleep(1);
 710
 711                 I915_WRITE(DEBUG_RESET_I830, 0);
 712                 POSTING_READ(DEBUG_RESET_I830);
 713         }
 714
 715         msleep(1);
 716
 717         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 718         POSTING_READ(D_STATE);
 719
 720         return 0;
 721 }
 722
 723 static int i965_reset_complete(struct drm_device *dev)
 724 {
 725         u8 gdrst;
 726         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 727         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 728 }
 729
 730 static int i965_do_reset(struct drm_device *dev)
 731 {
 732         int ret;
 733         u8 gdrst;
 734
 735         /*
 736          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 737          * well as the reset bit (GR/bit 0).  Setting the GR bit
 738          * triggers the reset; when done, the hardware will clear it.
 739          */
 740         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 741         pci_write_config_byte(dev->pdev, I965_GDRST,
 742                               gdrst | GRDOM_RENDER |
 743                               GRDOM_RESET_ENABLE);
 744         ret =  wait_for(i965_reset_complete(dev), 500);
 745         if (ret)
 746                 return ret;
 747
 748         /* We can't reset render&media without also resetting display ... */
 749         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 750         pci_write_config_byte(dev->pdev, I965_GDRST,
 751                               gdrst | GRDOM_MEDIA |
 752                               GRDOM_RESET_ENABLE);
 753
 754         return wait_for(i965_reset_complete(dev), 500);
 755 }
 756
 757 static int ironlake_do_reset(struct drm_device *dev)
 758 {
 759         struct drm_i915_private *dev_priv = dev->dev_private;
 760         u32 gdrst;
 761         int ret;
 762
 763         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 764         gdrst &= ~GRDOM_MASK;
 765         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 766                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 767         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 768         if (ret)
 769                 return ret;
 770
 771         /* We can't reset render&media without also resetting display ... */
 772         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 773         gdrst &= ~GRDOM_MASK;
 774         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 775                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 776         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 777 }
 778
 779 static int gen6_do_reset(struct drm_device *dev)
 780 {
 781         struct drm_i915_private *dev_priv = dev->dev_private;
 782         int ret;
 783
 784         dev_priv = dev->dev_private;
 785
 786         /* Hold gt_lock across reset to prevent any register access
 787          * with forcewake not set correctly
 788          */
 789         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
 790
 791         /* Reset the chip */
 792
 793         /* GEN6_GDRST is not in the gt power well, no need to check
 794          * for fifo space for the write or forcewake the chip for
 795          * the read
 796          */
 797         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 798
 799         /* Spin waiting for the device to ack the reset request */
 800         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 801
 802         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 803         if (dev_priv->forcewake_count)
 804                 dev_priv->gt.force_wake_get(dev_priv);
 805         else
 806                 dev_priv->gt.force_wake_put(dev_priv);
 807
 808         /* Restore fifo count */
 809         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 810
 811         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
 812         return ret;
 813 }
 814
 815 int intel_gpu_reset(struct drm_device *dev)
 816 {
 817         struct drm_i915_private *dev_priv = dev->dev_private;
 818         int ret = -ENODEV;
 819
 820         switch (INTEL_INFO(dev)->gen) {
 821         case 7:
 822         case 6:
 823                 ret = gen6_do_reset(dev);
 824                 break;
 825         case 5:
 826                 ret = ironlake_do_reset(dev);
 827                 break;
 828         case 4:
 829                 ret = i965_do_reset(dev);
 830                 break;
 831         case 2:
 832                 ret = i8xx_do_reset(dev);
 833                 break;
 834         }
 835
 836         /* Also reset the gpu hangman. */
 837         if (dev_priv->gpu_error.stop_rings) {
 838                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 839                 dev_priv->gpu_error.stop_rings = 0;
 840                 if (ret == -ENODEV) {
 841                         DRM_ERROR("Reset not implemented, but ignoring "
 842                                   "error for simulated gpu hangs\n");
 843                         ret = 0;
 844                 }
 845         }
 846
 847         return ret;
 848 }
 849
 850 /**
 851  * i915_reset - reset chip after a hang
 852  * @dev: drm device to reset
 853  *
 854  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 855  * reset or otherwise an error code.
 856  *
 857  * Procedure is fairly simple:
 858  *   - reset the chip using the reset reg
 859  *   - re-init context state
 860  *   - re-init hardware status page
 861  *   - re-init ring buffer
 862  *   - re-init interrupt state
 863  *   - re-init display
 864  */
 865 int i915_reset(struct drm_device *dev)
 866 {
 867         drm_i915_private_t *dev_priv = dev->dev_private;
 868         int ret;
 869
 870         if (!i915_try_reset)
 871                 return 0;
 872
 873         mutex_lock(&dev->struct_mutex);
 874
 875         i915_gem_reset(dev);
 876
 877         ret = -ENODEV;
 878         if (time_uptime - dev_priv->gpu_error.last_reset < 5)
 879                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 880         else
 881                 ret = intel_gpu_reset(dev);
 882
 883         dev_priv->gpu_error.last_reset = time_uptime;
 884         if (ret) {
 885                 DRM_ERROR("Failed to reset chip.\n");
 886                 mutex_unlock(&dev->struct_mutex);
 887                 return ret;
 888         }
 889
 890         /* Ok, now get things going again... */
 891
 892         /*
 893          * Everything depends on having the GTT running, so we need to start
 894          * there.  Fortunately we don't need to do this unless we reset the
 895          * chip at a PCI level.
 896          *
 897          * Next we need to restore the context, but we don't use those
 898          * yet either...
 899          *
 900          * Ring buffer needs to be re-initialized in the KMS case, or if X
 901          * was running at the time of the reset (i.e. we weren't VT
 902          * switched away).
 903          */
 904         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 905                         !dev_priv->mm.suspended) {
 906                 struct intel_ring_buffer *ring;
 907                 int i;
 908
 909                 dev_priv->mm.suspended = 0;
 910
 911                 i915_gem_init_swizzling(dev);
 912
 913                 for_each_ring(ring, dev_priv, i)
 914                         ring->init(ring);
 915
 916                 i915_gem_context_init(dev);
 917                 if (dev_priv->mm.aliasing_ppgtt) {
 918                         ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
 919                         if (ret)
 920                                 i915_gem_cleanup_aliasing_ppgtt(dev);
 921                 }
 922
 923                 /*
 924                  * It would make sense to re-init all the other hw state, at
 925                  * least the rps/rc6/emon init done within modeset_init_hw. For
 926                  * some unknown reason, this blows up my ilk, so don't.
 927                  */
 928
 929                 mutex_unlock(&dev->struct_mutex);
 930
 931                 drm_irq_uninstall(dev);
 932                 drm_irq_install(dev);
 933                 intel_hpd_init(dev);
 934         } else {
 935                 mutex_unlock(&dev->struct_mutex);
 936         }
 937
 938         return 0;
 939 }
 940
 941 static int
 942 i915_pci_probe(device_t kdev)
 943 {
 944         int device, i = 0;
 945
 946         if (pci_get_class(kdev) != PCIC_DISPLAY)
 947                 return ENXIO;
 948
 949         if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL)
 950                 return ENXIO;
 951
 952         device = pci_get_device(kdev);
 953
 954         for (i = 0; pciidlist[i].device != 0; i++) {
 955                 if (pciidlist[i].device == device) {
 956                         i915_attach_list[0].device = device;
 957                         return 0;
 958                 }
 959         }
 960
 961         return ENXIO;
 962 }
 963
 964 static struct drm_driver driver = {
 965         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 966             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
 967             DRIVER_GEM /*| DRIVER_MODESET*/,
 968
 969         .buf_priv_size  = sizeof(drm_i915_private_t),
 970         .load           = i915_driver_load,
 971         .open           = i915_driver_open,
 972         .unload         = i915_driver_unload,
 973         .preclose       = i915_driver_preclose,
 974         .lastclose      = i915_driver_lastclose,
 975         .postclose      = i915_driver_postclose,
 976         .device_is_agp  = i915_driver_device_is_agp,
 977         .gem_init_object = i915_gem_init_object,
 978         .gem_free_object = i915_gem_free_object,
 979         .gem_pager_ops  = &i915_gem_pager_ops,
 980         .dumb_create    = i915_gem_dumb_create,
 981         .dumb_map_offset = i915_gem_mmap_gtt,
 982         .dumb_destroy   = i915_gem_dumb_destroy,
 983
 984         .ioctls         = i915_ioctls,
 985
 986         .name           = DRIVER_NAME,
 987         .desc           = DRIVER_DESC,
 988         .date           = DRIVER_DATE,
 989         .major          = DRIVER_MAJOR,
 990         .minor          = DRIVER_MINOR,
 991         .patchlevel     = DRIVER_PATCHLEVEL,
 992 };
 993
 994 static device_method_t i915_methods[] = {
 995         /* Device interface */
 996         DEVMETHOD(device_probe,         i915_pci_probe),
 997         DEVMETHOD(device_attach,        i915_attach),
 998         DEVMETHOD(device_suspend,       i915_suspend),
 999         DEVMETHOD(device_resume,        i915_resume),
1000         DEVMETHOD(device_detach,        drm_release),
1001         DEVMETHOD_END
1002 };
1003
1004 static driver_t i915_driver = {
1005         "drm",
1006         i915_methods,
1007         sizeof(struct drm_device)
1008 };
1009
1010 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
1011     SI_ORDER_ANY);
1012 MODULE_DEPEND(i915kms, drm, 1, 1, 1);
1013 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
1014 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
1015 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
1016 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
1017
1018 /* We give fast paths for the really cool registers */
1019 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1020         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1021          ((reg) < 0x40000) &&            \
1022          ((reg) != FORCEWAKE))
1023 static void
1024 ilk_dummy_write(struct drm_i915_private *dev_priv)
1025 {
1026         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1027          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1028          * harmless to write 0 into. */
1029         I915_WRITE_NOTRACE(MI_MODE, 0);
1030 }
1031
1032 static void
1033 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1034 {
1035         if (IS_HASWELL(dev_priv->dev) &&
1036             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1037                 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1038                           reg);
1039                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1040         }
1041 }
1042
1043 static void
1044 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1045 {
1046         if (IS_HASWELL(dev_priv->dev) &&
1047             (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1048                 DRM_ERROR("Unclaimed write to %x\n", reg);
1049                 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1050         }
1051 }
1052
1053 #define __i915_read(x, y) \
1054 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1055         u##x val = 0; \
1056         if (IS_GEN5(dev_priv->dev)) \
1057                 ilk_dummy_write(dev_priv); \
1058         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1059                 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
1060                 if (dev_priv->forcewake_count == 0) \
1061                         dev_priv->gt.force_wake_get(dev_priv); \
1062                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
1063                 if (dev_priv->forcewake_count == 0) \
1064                         dev_priv->gt.force_wake_put(dev_priv); \
1065                 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
1066         } else { \
1067                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
1068         } \
1069         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1070         return val; \
1071 }
1072
1073 __i915_read(8, 8)
1074 __i915_read(16, 16)
1075 __i915_read(32, 32)
1076 __i915_read(64, 64)
1077 #undef __i915_read
1078
1079 #define __i915_write(x, y) \
1080 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1081         u32 __fifo_ret = 0; \
1082         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1083         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1084                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1085         } \
1086         if (IS_GEN5(dev_priv->dev)) \
1087                 ilk_dummy_write(dev_priv); \
1088         hsw_unclaimed_reg_clear(dev_priv, reg); \
1089         DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
1090         if (unlikely(__fifo_ret)) { \
1091                 gen6_gt_check_fifodbg(dev_priv); \
1092         } \
1093         hsw_unclaimed_reg_check(dev_priv, reg); \
1094 }
1095
1096 __i915_write(8, 8)
1097 __i915_write(16, 16)
1098 __i915_write(32, 32)
1099 __i915_write(64, 64)
1100 #undef __i915_write
1101
1102 static const struct register_whitelist {
1103         uint64_t offset;
1104         uint32_t size;
1105         uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1106 } whitelist[] = {
1107         { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1108 };
1109
1110 int i915_reg_read_ioctl(struct drm_device *dev,
1111                         void *data, struct drm_file *file)
1112 {
1113         struct drm_i915_private *dev_priv = dev->dev_private;
1114         struct drm_i915_reg_read *reg = data;
1115         struct register_whitelist const *entry = whitelist;
1116         int i;
1117
1118         for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1119                 if (entry->offset == reg->offset &&
1120                     (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1121                         break;
1122         }
1123
1124         if (i == ARRAY_SIZE(whitelist))
1125                 return -EINVAL;
1126
1127         switch (entry->size) {
1128         case 8:
1129                 reg->val = I915_READ64(reg->offset);
1130                 break;
1131         case 4:
1132                 reg->val = I915_READ(reg->offset);
1133                 break;
1134         case 2:
1135                 reg->val = I915_READ16(reg->offset);
1136                 break;
1137         case 1:
1138                 reg->val = I915_READ8(reg->offset);
1139                 break;
1140         default:
1141                 WARN_ON(1);
1142                 return -EINVAL;
1143         }
1144
1145         return 0;
1146 }