sys/dev/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33
  34 static const u32 hpd_ibx[] = {
  35         [HPD_CRT] = SDE_CRT_HOTPLUG,
  36         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  37         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  38         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  39         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  40 };
  41
  42 static const u32 hpd_cpt[] = {
  43         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  44         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  45         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  46         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  47         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  48 };
  49
  50 static const u32 hpd_mask_i915[] = {
  51         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  52         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  53         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  54         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  55         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  56         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  57 };
  58
  59 static const u32 hpd_status_gen4[] = {
  60         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  61         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  62         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  63         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  64         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  65         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  66 };
  67
  68 static const u32 hpd_status_i965[] = {
  69          [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  70          [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  71          [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  72          [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  73          [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  74          [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  75 };
  76
  77 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  78         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  79         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  80         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  81         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  82         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  83         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  84 };
  85
  86 static void ibx_hpd_irq_setup(struct drm_device *dev);
  87 static void i915_hpd_irq_setup(struct drm_device *dev);
  88
  89 /* For display hotplug interrupt */
  90 static void
  91 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  92 {
  93         if ((dev_priv->irq_mask & mask) != 0) {
  94                 dev_priv->irq_mask &= ~mask;
  95                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  96                 POSTING_READ(DEIMR);
  97         }
  98 }
  99
 100 static void
 101 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 102 {
 103         if ((dev_priv->irq_mask & mask) != mask) {
 104                 dev_priv->irq_mask |= mask;
 105                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 106                 POSTING_READ(DEIMR);
 107         }
 108 }
 109
 110 void
 111 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 112 {
 113         u32 reg = PIPESTAT(pipe);
 114         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 115
 116         if ((pipestat & mask) == mask)
 117                 return;
 118
 119         /* Enable the interrupt, clear any pending status */
 120         pipestat |= mask | (mask >> 16);
 121         I915_WRITE(reg, pipestat);
 122         POSTING_READ(reg);
 123 }
 124
 125 void
 126 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 127 {
 128         u32 reg = PIPESTAT(pipe);
 129         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 130
 131         if ((pipestat & mask) == 0)
 132                 return;
 133
 134         pipestat &= ~mask;
 135         I915_WRITE(reg, pipestat);
 136         POSTING_READ(reg);
 137 }
 138
 139 /**
 140  * intel_enable_asle - enable ASLE interrupt for OpRegion
 141  */
 142 void intel_enable_asle(struct drm_device *dev)
 143 {
 144         drm_i915_private_t *dev_priv = dev->dev_private;
 145
 146         /* FIXME: opregion/asle for VLV */
 147         if (IS_VALLEYVIEW(dev))
 148                 return;
 149
 150         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 151
 152         if (HAS_PCH_SPLIT(dev))
 153                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 154         else {
 155                 i915_enable_pipestat(dev_priv, 1,
 156                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 157                 if (INTEL_INFO(dev)->gen >= 4)
 158                         i915_enable_pipestat(dev_priv, 0,
 159                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 160         }
 161
 162         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 163 }
 164
 165 /**
 166  * i915_pipe_enabled - check if a pipe is enabled
 167  * @dev: DRM device
 168  * @pipe: pipe to check
 169  *
 170  * Reading certain registers when the pipe is disabled can hang the chip.
 171  * Use this routine to make sure the PLL is running and the pipe is active
 172  * before reading such registers if unsure.
 173  */
 174 static int
 175 i915_pipe_enabled(struct drm_device *dev, int pipe)
 176 {
 177         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 178         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 179                                                                       pipe);
 180
 181         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 182 }
 183
 184 /* Called from drm generic code, passed a 'crtc', which
 185  * we use as a pipe index
 186  */
 187 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 188 {
 189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 190         unsigned long high_frame;
 191         unsigned long low_frame;
 192         u32 high1, high2, low;
 193
 194         if (!i915_pipe_enabled(dev, pipe)) {
 195                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 196                                 "pipe %c\n", pipe_name(pipe));
 197                 return 0;
 198         }
 199
 200         high_frame = PIPEFRAME(pipe);
 201         low_frame = PIPEFRAMEPIXEL(pipe);
 202
 203         /*
 204          * High & low register fields aren't synchronized, so make sure
 205          * we get a low value that's stable across two reads of the high
 206          * register.
 207          */
 208         do {
 209                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 210                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 211                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 212         } while (high1 != high2);
 213
 214         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 215         low >>= PIPE_FRAME_LOW_SHIFT;
 216         return (high1 << 8) | low;
 217 }
 218
 219 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 220 {
 221         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 222         int reg = PIPE_FRMCOUNT_GM45(pipe);
 223
 224         if (!i915_pipe_enabled(dev, pipe)) {
 225                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 226                                  "pipe %c\n", pipe_name(pipe));
 227                 return 0;
 228         }
 229
 230         return I915_READ(reg);
 231 }
 232
 233 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 234                              int *vpos, int *hpos)
 235 {
 236         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 237         u32 vbl = 0, position = 0;
 238         int vbl_start, vbl_end, htotal, vtotal;
 239         bool in_vbl = true;
 240         int ret = 0;
 241         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 242                                                                       pipe);
 243
 244         if (!i915_pipe_enabled(dev, pipe)) {
 245                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 246                                  "pipe %c\n", pipe_name(pipe));
 247                 return 0;
 248         }
 249
 250         /* Get vtotal. */
 251         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 252
 253         if (INTEL_INFO(dev)->gen >= 4) {
 254                 /* No obvious pixelcount register. Only query vertical
 255                  * scanout position from Display scan line register.
 256                  */
 257                 position = I915_READ(PIPEDSL(pipe));
 258
 259                 /* Decode into vertical scanout position. Don't have
 260                  * horizontal scanout position.
 261                  */
 262                 *vpos = position & 0x1fff;
 263                 *hpos = 0;
 264         } else {
 265                 /* Have access to pixelcount since start of frame.
 266                  * We can split this into vertical and horizontal
 267                  * scanout position.
 268                  */
 269                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 270
 271                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 272                 *vpos = position / htotal;
 273                 *hpos = position - (*vpos * htotal);
 274         }
 275
 276         /* Query vblank area. */
 277         vbl = I915_READ(VBLANK(cpu_transcoder));
 278
 279         /* Test position against vblank region. */
 280         vbl_start = vbl & 0x1fff;
 281         vbl_end = (vbl >> 16) & 0x1fff;
 282
 283         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 284                 in_vbl = false;
 285
 286         /* Inside "upper part" of vblank area? Apply corrective offset: */
 287         if (in_vbl && (*vpos >= vbl_start))
 288                 *vpos = *vpos - vtotal;
 289
 290         /* Readouts valid? */
 291         if (vbl > 0)
 292                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 293
 294         /* In vblank? */
 295         if (in_vbl)
 296                 ret |= DRM_SCANOUTPOS_INVBL;
 297
 298         return ret;
 299 }
 300
 301 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 302                               int *max_error,
 303                               struct timeval *vblank_time,
 304                               unsigned flags)
 305 {
 306         struct drm_crtc *crtc;
 307
 308         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 309                 DRM_ERROR("Invalid crtc %d\n", pipe);
 310                 return -EINVAL;
 311         }
 312
 313         /* Get drm_crtc to timestamp: */
 314         crtc = intel_get_crtc_for_pipe(dev, pipe);
 315         if (crtc == NULL) {
 316                 DRM_ERROR("Invalid crtc %d\n", pipe);
 317                 return -EINVAL;
 318         }
 319
 320         if (!crtc->enabled) {
 321                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 322                 return -EBUSY;
 323         }
 324
 325         /* Helper routine in DRM core does all the work: */
 326         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 327                                                      vblank_time, flags,
 328                                                      crtc);
 329 }
 330
 331 /*
 332  * Handle hotplug events outside the interrupt handler proper.
 333  */
 334 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 335
 336 static void i915_hotplug_work_func(struct work_struct *work)
 337 {
 338         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 339                                                     hotplug_work);
 340         struct drm_device *dev = dev_priv->dev;
 341         struct drm_mode_config *mode_config = &dev->mode_config;
 342         struct intel_connector *intel_connector;
 343         struct intel_encoder *intel_encoder;
 344         struct drm_connector *connector;
 345         bool hpd_disabled = false;
 346
 347         /* HPD irq before everything is fully set up. */
 348         if (!dev_priv->enable_hotplug_processing)
 349                 return;
 350
 351         mutex_lock(&mode_config->mutex);
 352         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 353
 354         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 355         list_for_each_entry(connector, &mode_config->connector_list, head) {
 356                 intel_connector = to_intel_connector(connector);
 357                 intel_encoder = intel_connector->encoder;
 358                 if (intel_encoder->hpd_pin > HPD_NONE &&
 359                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 360                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 361                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 362                                  "switching from hotplug detection to polling\n",
 363                                 drm_get_connector_name(connector));
 364                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 365                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 366                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 367                         hpd_disabled = true;
 368                 }
 369         }
 370          /* if there were no outputs to poll, poll was disabled,
 371           * therefore make sure it's enabled when disabling HPD on
 372           * some connectors */
 373         if (hpd_disabled) {
 374                 drm_kms_helper_poll_enable(dev);
 375                 mod_timer(&dev_priv->hotplug_reenable_timer,
 376                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 377         }
 378
 379         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 380
 381         list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
 382                 if (intel_encoder->hot_plug)
 383                         intel_encoder->hot_plug(intel_encoder);
 384
 385         mutex_unlock(&mode_config->mutex);
 386
 387         /* Just fire off a uevent and let userspace tell us what to do */
 388         drm_helper_hpd_irq_event(dev);
 389 }
 390
 391 static void ironlake_handle_rps_change(struct drm_device *dev)
 392 {
 393         drm_i915_private_t *dev_priv = dev->dev_private;
 394         u32 busy_up, busy_down, max_avg, min_avg;
 395         u8 new_delay;
 396
 397         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
 398
 399         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 400
 401         new_delay = dev_priv->ips.cur_delay;
 402
 403         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 404         busy_up = I915_READ(RCPREVBSYTUPAVG);
 405         busy_down = I915_READ(RCPREVBSYTDNAVG);
 406         max_avg = I915_READ(RCBMAXAVG);
 407         min_avg = I915_READ(RCBMINAVG);
 408
 409         /* Handle RCS change request from hw */
 410         if (busy_up > max_avg) {
 411                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 412                         new_delay = dev_priv->ips.cur_delay - 1;
 413                 if (new_delay < dev_priv->ips.max_delay)
 414                         new_delay = dev_priv->ips.max_delay;
 415         } else if (busy_down < min_avg) {
 416                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 417                         new_delay = dev_priv->ips.cur_delay + 1;
 418                 if (new_delay > dev_priv->ips.min_delay)
 419                         new_delay = dev_priv->ips.min_delay;
 420         }
 421
 422         if (ironlake_set_drps(dev, new_delay))
 423                 dev_priv->ips.cur_delay = new_delay;
 424
 425         lockmgr(&mchdev_lock, LK_RELEASE);
 426
 427         return;
 428 }
 429
 430 static void notify_ring(struct drm_device *dev,
 431                         struct intel_ring_buffer *ring)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434
 435         if (ring->obj == NULL)
 436                 return;
 437
 438         wake_up_all(&ring->irq_queue);
 439         if (i915_enable_hangcheck) {
 440                 dev_priv->gpu_error.hangcheck_count = 0;
 441                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 442                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 443         }
 444 }
 445
 446 static void gen6_pm_rps_work(struct work_struct *work)
 447 {
 448         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 449                                                     rps.work);
 450         u32 pm_iir, pm_imr;
 451         u8 new_delay;
 452
 453         spin_lock(&dev_priv->rps.lock);
 454         pm_iir = dev_priv->rps.pm_iir;
 455         dev_priv->rps.pm_iir = 0;
 456         pm_imr = I915_READ(GEN6_PMIMR);
 457         I915_WRITE(GEN6_PMIMR, 0);
 458         spin_unlock(&dev_priv->rps.lock);
 459
 460         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 461                 return;
 462
 463         mutex_lock(&dev_priv->rps.hw_lock);
 464
 465         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 466                 new_delay = dev_priv->rps.cur_delay + 1;
 467         else
 468                 new_delay = dev_priv->rps.cur_delay - 1;
 469
 470         /* sysfs frequency interfaces may have snuck in while servicing the
 471          * interrupt
 472          */
 473         if (!(new_delay > dev_priv->rps.max_delay ||
 474               new_delay < dev_priv->rps.min_delay)) {
 475                 gen6_set_rps(dev_priv->dev, new_delay);
 476         }
 477
 478         mutex_unlock(&dev_priv->rps.hw_lock);
 479 }
 480
 481
 482 /**
 483  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 484  * occurred.
 485  * @work: workqueue struct
 486  *
 487  * Doesn't actually do anything except notify userspace. As a consequence of
 488  * this event, userspace should try to remap the bad rows since statistically
 489  * it is likely the same row is more likely to go bad again.
 490  */
 491 static void ivybridge_parity_work(struct work_struct *work)
 492 {
 493         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 494                                                     l3_parity.error_work);
 495         u32 error_status, row, bank, subbank;
 496         char *parity_event[5];
 497         uint32_t misccpctl;
 498
 499         /* We must turn off DOP level clock gating to access the L3 registers.
 500          * In order to prevent a get/put style interface, acquire struct mutex
 501          * any time we access those registers.
 502          */
 503         mutex_lock(&dev_priv->dev->struct_mutex);
 504
 505         misccpctl = I915_READ(GEN7_MISCCPCTL);
 506         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 507         POSTING_READ(GEN7_MISCCPCTL);
 508
 509         error_status = I915_READ(GEN7_L3CDERRST1);
 510         row = GEN7_PARITY_ERROR_ROW(error_status);
 511         bank = GEN7_PARITY_ERROR_BANK(error_status);
 512         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 513
 514         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 515                                     GEN7_L3CDERRST1_ENABLE);
 516         POSTING_READ(GEN7_L3CDERRST1);
 517
 518         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 519
 520         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 521         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 522         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 523         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 524
 525         mutex_unlock(&dev_priv->dev->struct_mutex);
 526
 527         parity_event[0] = "L3_PARITY_ERROR=1";
 528         parity_event[4] = NULL;
 529
 530         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 531                   row, bank, subbank);
 532 }
 533
 534 static void ivybridge_handle_parity_error(struct drm_device *dev)
 535 {
 536         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 537
 538         if (!HAS_L3_GPU_CACHE(dev))
 539                 return;
 540
 541         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 542         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 543         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 544         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 545
 546         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 547 }
 548
 549 static void snb_gt_irq_handler(struct drm_device *dev,
 550                                struct drm_i915_private *dev_priv,
 551                                u32 gt_iir)
 552 {
 553
 554         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 555                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 556                 notify_ring(dev, &dev_priv->ring[RCS]);
 557         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 558                 notify_ring(dev, &dev_priv->ring[VCS]);
 559         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 560                 notify_ring(dev, &dev_priv->ring[BCS]);
 561
 562         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 563                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 564                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 565                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 566                 i915_handle_error(dev, false);
 567         }
 568
 569         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 570                 ivybridge_handle_parity_error(dev);
 571 }
 572
 573 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 574                                 u32 pm_iir)
 575 {
 576
 577         /*
 578          * IIR bits should never already be set because IMR should
 579          * prevent an interrupt from being shown in IIR. The warning
 580          * displays a case where we've unsafely cleared
 581          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 582          * type is not a problem, it displays a problem in the logic.
 583          *
 584          * The mask bit in IMR is cleared by dev_priv->rps.work.
 585          */
 586
 587         spin_lock(&dev_priv->rps.lock);
 588         dev_priv->rps.pm_iir |= pm_iir;
 589         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 590         POSTING_READ(GEN6_PMIMR);
 591         spin_unlock(&dev_priv->rps.lock);
 592
 593         queue_work(dev_priv->wq, &dev_priv->rps.work);
 594 }
 595
 596 #define HPD_STORM_DETECT_PERIOD 1000
 597 #define HPD_STORM_THRESHOLD 5
 598
 599 static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
 600                                             u32 hotplug_trigger,
 601                                             const u32 *hpd)
 602 {
 603         drm_i915_private_t *dev_priv = dev->dev_private;
 604         int i;
 605         bool ret = false;
 606
 607         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 608
 609         for (i = 1; i < HPD_NUM_PINS; i++) {
 610
 611                 if (!(hpd[i] & hotplug_trigger) ||
 612                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
 613                         continue;
 614
 615                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
 616                                    dev_priv->hpd_stats[i].hpd_last_jiffies
 617                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
 618                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
 619                         dev_priv->hpd_stats[i].hpd_cnt = 0;
 620                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
 621                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
 622                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
 623                         ret = true;
 624                 } else {
 625                         dev_priv->hpd_stats[i].hpd_cnt++;
 626                 }
 627         }
 628
 629         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 630
 631         return ret;
 632 }
 633
 634 static void gmbus_irq_handler(struct drm_device *dev)
 635 {
 636         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 637
 638         wake_up_all(&dev_priv->gmbus_wait_queue);
 639 }
 640
 641 static void dp_aux_irq_handler(struct drm_device *dev)
 642 {
 643         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 644
 645         wake_up_all(&dev_priv->gmbus_wait_queue);
 646 }
 647
 648 static irqreturn_t valleyview_irq_handler(void *arg)
 649 {
 650         struct drm_device *dev = (struct drm_device *) arg;
 651         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 652         u32 iir, gt_iir, pm_iir;
 653         int pipe;
 654         u32 pipe_stats[I915_MAX_PIPES];
 655
 656         atomic_inc(&dev_priv->irq_received);
 657
 658         while (true) {
 659                 iir = I915_READ(VLV_IIR);
 660                 gt_iir = I915_READ(GTIIR);
 661                 pm_iir = I915_READ(GEN6_PMIIR);
 662
 663                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 664                         goto out;
 665
 666                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 667
 668                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
 669                 for_each_pipe(pipe) {
 670                         int reg = PIPESTAT(pipe);
 671                         pipe_stats[pipe] = I915_READ(reg);
 672
 673                         /*
 674                          * Clear the PIPE*STAT regs before the IIR
 675                          */
 676                         if (pipe_stats[pipe] & 0x8000ffff) {
 677                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 678                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 679                                                          pipe_name(pipe));
 680                                 I915_WRITE(reg, pipe_stats[pipe]);
 681                         }
 682                 }
 683                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
 684
 685                 for_each_pipe(pipe) {
 686                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 687                                 drm_handle_vblank(dev, pipe);
 688
 689                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 690                                 intel_prepare_page_flip(dev, pipe);
 691                                 intel_finish_page_flip(dev, pipe);
 692                         }
 693                 }
 694
 695                 /* Consume port.  Then clear IIR or we'll miss events */
 696                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 697                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 698                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
 699
 700                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 701                                          hotplug_status);
 702                         if (hotplug_trigger) {
 703                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
 704                                         i915_hpd_irq_setup(dev);
 705                                 queue_work(dev_priv->wq,
 706                                            &dev_priv->hotplug_work);
 707                         }
 708                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 709                         I915_READ(PORT_HOTPLUG_STAT);
 710                 }
 711
 712                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 713                         gmbus_irq_handler(dev);
 714
 715                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 716                         gen6_queue_rps_work(dev_priv, pm_iir);
 717
 718                 I915_WRITE(GTIIR, gt_iir);
 719                 I915_WRITE(GEN6_PMIIR, pm_iir);
 720                 I915_WRITE(VLV_IIR, iir);
 721         }
 722
 723 out:
 724         return;
 725 }
 726
 727 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 728 {
 729         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 730         int pipe;
 731         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
 732
 733         if (hotplug_trigger) {
 734                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
 735                         ibx_hpd_irq_setup(dev);
 736                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 737         }
 738         if (pch_iir & SDE_AUDIO_POWER_MASK)
 739                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 740                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 741                                  SDE_AUDIO_POWER_SHIFT);
 742
 743         if (pch_iir & SDE_AUX_MASK)
 744                 dp_aux_irq_handler(dev);
 745
 746         if (pch_iir & SDE_GMBUS)
 747                 gmbus_irq_handler(dev);
 748
 749         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 750                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 751
 752         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 753                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 754
 755         if (pch_iir & SDE_POISON)
 756                 DRM_ERROR("PCH poison interrupt\n");
 757
 758         if (pch_iir & SDE_FDI_MASK)
 759                 for_each_pipe(pipe)
 760                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 761                                          pipe_name(pipe),
 762                                          I915_READ(FDI_RX_IIR(pipe)));
 763
 764         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 765                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 766
 767         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 768                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 769
 770         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 771                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 772         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 773                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 774 }
 775
 776 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 777 {
 778         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 779         int pipe;
 780         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
 781
 782         if (hotplug_trigger) {
 783                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
 784                         ibx_hpd_irq_setup(dev);
 785                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 786         }
 787         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 788                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 789                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 790                                  SDE_AUDIO_POWER_SHIFT_CPT);
 791
 792         if (pch_iir & SDE_AUX_MASK_CPT)
 793                 dp_aux_irq_handler(dev);
 794
 795         if (pch_iir & SDE_GMBUS_CPT)
 796                 gmbus_irq_handler(dev);
 797
 798         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 799                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 800
 801         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 802                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 803
 804         if (pch_iir & SDE_FDI_MASK_CPT)
 805                 for_each_pipe(pipe)
 806                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 807                                          pipe_name(pipe),
 808                                          I915_READ(FDI_RX_IIR(pipe)));
 809 }
 810
 811 static irqreturn_t ivybridge_irq_handler(void *arg)
 812 {
 813         struct drm_device *dev = (struct drm_device *) arg;
 814         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 815         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
 816         int i;
 817
 818         atomic_inc(&dev_priv->irq_received);
 819
 820         /* disable master interrupt before clearing iir  */
 821         de_ier = I915_READ(DEIER);
 822         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 823
 824         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 825          * interrupts will will be stored on its back queue, and then we'll be
 826          * able to process them after we restore SDEIER (as soon as we restore
 827          * it, we'll get an interrupt if SDEIIR still has something to process
 828          * due to its back queue). */
 829         if (!HAS_PCH_NOP(dev)) {
 830                 sde_ier = I915_READ(SDEIER);
 831                 I915_WRITE(SDEIER, 0);
 832                 POSTING_READ(SDEIER);
 833         }
 834
 835         gt_iir = I915_READ(GTIIR);
 836         if (gt_iir) {
 837                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 838                 I915_WRITE(GTIIR, gt_iir);
 839         }
 840
 841         de_iir = I915_READ(DEIIR);
 842         if (de_iir) {
 843                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
 844                         dp_aux_irq_handler(dev);
 845
 846                 if (de_iir & DE_GSE_IVB)
 847                         intel_opregion_gse_intr(dev);
 848
 849                 for (i = 0; i < 3; i++) {
 850                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 851                                 drm_handle_vblank(dev, i);
 852                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 853                                 intel_prepare_page_flip(dev, i);
 854                                 intel_finish_page_flip_plane(dev, i);
 855                         }
 856                 }
 857
 858                 /* check event from PCH */
 859                 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
 860                         u32 pch_iir = I915_READ(SDEIIR);
 861
 862                         cpt_irq_handler(dev, pch_iir);
 863
 864                         /* clear PCH hotplug event before clear CPU irq */
 865                         I915_WRITE(SDEIIR, pch_iir);
 866                 }
 867
 868                 I915_WRITE(DEIIR, de_iir);
 869         }
 870
 871         pm_iir = I915_READ(GEN6_PMIIR);
 872         if (pm_iir) {
 873                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 874                         gen6_queue_rps_work(dev_priv, pm_iir);
 875                 I915_WRITE(GEN6_PMIIR, pm_iir);
 876         }
 877
 878         I915_WRITE(DEIER, de_ier);
 879         POSTING_READ(DEIER);
 880         if (!HAS_PCH_NOP(dev)) {
 881                 I915_WRITE(SDEIER, sde_ier);
 882                 POSTING_READ(SDEIER);
 883         }
 884 }
 885
 886 static void ilk_gt_irq_handler(struct drm_device *dev,
 887                                struct drm_i915_private *dev_priv,
 888                                u32 gt_iir)
 889 {
 890         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 891                 notify_ring(dev, &dev_priv->ring[RCS]);
 892         if (gt_iir & GT_BSD_USER_INTERRUPT)
 893                 notify_ring(dev, &dev_priv->ring[VCS]);
 894 }
 895
 896 static irqreturn_t ironlake_irq_handler(void *arg)
 897 {
 898         struct drm_device *dev = (struct drm_device *) arg;
 899         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 900         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 901
 902         atomic_inc(&dev_priv->irq_received);
 903
 904         /* disable master interrupt before clearing iir  */
 905         de_ier = I915_READ(DEIER);
 906         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 907         POSTING_READ(DEIER);
 908
 909         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 910          * interrupts will will be stored on its back queue, and then we'll be
 911          * able to process them after we restore SDEIER (as soon as we restore
 912          * it, we'll get an interrupt if SDEIIR still has something to process
 913          * due to its back queue). */
 914         sde_ier = I915_READ(SDEIER);
 915         I915_WRITE(SDEIER, 0);
 916         POSTING_READ(SDEIER);
 917
 918         de_iir = I915_READ(DEIIR);
 919         gt_iir = I915_READ(GTIIR);
 920         pm_iir = I915_READ(GEN6_PMIIR);
 921
 922         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
 923                 goto done;
 924
 925         if (IS_GEN5(dev))
 926                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 927         else
 928                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 929
 930         if (de_iir & DE_AUX_CHANNEL_A)
 931                 dp_aux_irq_handler(dev);
 932
 933         if (de_iir & DE_GSE)
 934                 intel_opregion_gse_intr(dev);
 935
 936         if (de_iir & DE_PIPEA_VBLANK)
 937                 drm_handle_vblank(dev, 0);
 938
 939         if (de_iir & DE_PIPEB_VBLANK)
 940                 drm_handle_vblank(dev, 1);
 941
 942         if (de_iir & DE_PLANEA_FLIP_DONE) {
 943                 intel_prepare_page_flip(dev, 0);
 944                 intel_finish_page_flip_plane(dev, 0);
 945         }
 946
 947         if (de_iir & DE_PLANEB_FLIP_DONE) {
 948                 intel_prepare_page_flip(dev, 1);
 949                 intel_finish_page_flip_plane(dev, 1);
 950         }
 951
 952         /* check event from PCH */
 953         if (de_iir & DE_PCH_EVENT) {
 954                 u32 pch_iir = I915_READ(SDEIIR);
 955
 956                 if (HAS_PCH_CPT(dev))
 957                         cpt_irq_handler(dev, pch_iir);
 958                 else
 959                         ibx_irq_handler(dev, pch_iir);
 960
 961                 /* should clear PCH hotplug event before clear CPU irq */
 962                 I915_WRITE(SDEIIR, pch_iir);
 963         }
 964
 965         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 966                 ironlake_handle_rps_change(dev);
 967
 968         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 969                 gen6_queue_rps_work(dev_priv, pm_iir);
 970
 971         I915_WRITE(GTIIR, gt_iir);
 972         I915_WRITE(DEIIR, de_iir);
 973         I915_WRITE(GEN6_PMIIR, pm_iir);
 974
 975 done:
 976         I915_WRITE(DEIER, de_ier);
 977         POSTING_READ(DEIER);
 978         I915_WRITE(SDEIER, sde_ier);
 979         POSTING_READ(SDEIER);
 980 }
 981
 982 /**
 983  * i915_error_work_func - do process context error handling work
 984  * @work: work struct
 985  *
 986  * Fire an error uevent so userspace can see that a hang or error
 987  * was detected.
 988  */
 989 static void i915_error_work_func(struct work_struct *work)
 990 {
 991         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
 992                                                     work);
 993         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
 994                                                     gpu_error);
 995         struct drm_device *dev = dev_priv->dev;
 996         struct intel_ring_buffer *ring;
 997 #if 0
 998         char *error_event[] = { "ERROR=1", NULL };
 999         char *reset_event[] = { "RESET=1", NULL };
1000         char *reset_done_event[] = { "ERROR=0", NULL };
1001 #endif
1002         int i, ret;
1003
1004         /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */
1005
1006         /*
1007          * Note that there's only one work item which does gpu resets, so we
1008          * need not worry about concurrent gpu resets potentially incrementing
1009          * error->reset_counter twice. We only need to take care of another
1010          * racing irq/hangcheck declaring the gpu dead for a second time. A
1011          * quick check for that is good enough: schedule_work ensures the
1012          * correct ordering between hang detection and this work item, and since
1013          * the reset in-progress bit is only ever set by code outside of this
1014          * work we don't need to worry about any other races.
1015          */
1016         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1017                 DRM_DEBUG_DRIVER("resetting chip\n");
1018 #if 0
1019                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1020                                    reset_event);
1021 #endif
1022
1023                 ret = i915_reset(dev);
1024
1025                 if (ret == 0) {
1026                         /*
1027                          * After all the gem state is reset, increment the reset
1028                          * counter and wake up everyone waiting for the reset to
1029                          * complete.
1030                          *
1031                          * Since unlock operations are a one-sided barrier only,
1032                          * we need to insert a barrier here to order any seqno
1033                          * updates before
1034                          * the counter increment.
1035                          */
1036                         cpu_sfence();
1037                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1038
1039 #if 0
1040                         kobject_uevent_env(&dev->primary->kdev.kobj,
1041                                            KOBJ_CHANGE, reset_done_event);
1042 #endif
1043                 } else {
1044                         atomic_set(&error->reset_counter, I915_WEDGED);
1045                 }
1046
1047                 for_each_ring(ring, dev_priv, i)
1048                         wake_up_all(&ring->irq_queue);
1049
1050                 intel_display_handle_reset(dev);
1051
1052                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1053         }
1054 }
1055
1056 /* NB: please notice the memset */
1057 static void i915_get_extra_instdone(struct drm_device *dev,
1058                                     uint32_t *instdone)
1059 {
1060         struct drm_i915_private *dev_priv = dev->dev_private;
1061         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1062
1063         switch(INTEL_INFO(dev)->gen) {
1064         case 2:
1065         case 3:
1066                 instdone[0] = I915_READ(INSTDONE);
1067                 break;
1068         case 4:
1069         case 5:
1070         case 6:
1071                 instdone[0] = I915_READ(INSTDONE_I965);
1072                 instdone[1] = I915_READ(INSTDONE1);
1073                 break;
1074         default:
1075 #if 0
1076                 WARN_ONCE(1, "Unsupported platform\n");
1077 #endif
1078         case 7:
1079                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1080                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1081                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1082                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1083                 break;
1084         }
1085 }
1086
1087 #if 0 /* CONFIG_DEBUG_FS */
1088 static struct drm_i915_error_object *
1089 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1090                                struct drm_i915_gem_object *src,
1091                                const int num_pages)
1092 {
1093         struct drm_i915_error_object *dst;
1094         int i;
1095         u32 reloc_offset;
1096
1097         if (src == NULL || src->pages == NULL)
1098                 return NULL;
1099
1100         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1101         if (dst == NULL)
1102                 return NULL;
1103
1104         reloc_offset = src->gtt_offset;
1105         for (i = 0; i < num_pages; i++) {
1106                 unsigned long flags;
1107                 void *d;
1108
1109                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1110                 if (d == NULL)
1111                         goto unwind;
1112
1113                 local_irq_save(flags);
1114                 if (reloc_offset < dev_priv->gtt.mappable_end &&
1115                     src->has_global_gtt_mapping) {
1116                         void __iomem *s;
1117
1118                         /* Simply ignore tiling or any overlapping fence.
1119                          * It's part of the error state, and this hopefully
1120                          * captures what the GPU read.
1121                          */
1122
1123                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1124                                                      reloc_offset);
1125                         memcpy_fromio(d, s, PAGE_SIZE);
1126                         io_mapping_unmap_atomic(s);
1127                 } else if (src->stolen) {
1128                         unsigned long offset;
1129
1130                         offset = dev_priv->mm.stolen_base;
1131                         offset += src->stolen->start;
1132                         offset += i << PAGE_SHIFT;
1133
1134                         memcpy_fromio(d, (void *)offset, PAGE_SIZE);
1135                 } else {
1136                         struct page *page;
1137                         void *s;
1138
1139                         page = i915_gem_object_get_page(src, i);
1140
1141                         drm_clflush_pages(&page, 1);
1142
1143                         s = kmap_atomic(page);
1144                         memcpy(d, s, PAGE_SIZE);
1145                         kunmap_atomic(s);
1146
1147                         drm_clflush_pages(&page, 1);
1148                 }
1149                 local_irq_restore(flags);
1150
1151                 dst->pages[i] = d;
1152
1153                 reloc_offset += PAGE_SIZE;
1154         }
1155         dst->page_count = num_pages;
1156         dst->gtt_offset = src->gtt_offset;
1157
1158         return dst;
1159
1160 unwind:
1161         while (i--)
1162                 kfree(dst->pages[i]);
1163         kfree(dst);
1164         return NULL;
1165 }
1166 #define i915_error_object_create(dev_priv, src) \
1167         i915_error_object_create_sized((dev_priv), (src), \
1168                                        (src)->base.size>>PAGE_SHIFT)
1169
1170 static void
1171 i915_error_object_free(struct drm_i915_error_object *obj)
1172 {
1173         int page;
1174
1175         if (obj == NULL)
1176                 return;
1177
1178         for (page = 0; page < obj->page_count; page++)
1179                 kfree(obj->pages[page]);
1180
1181         kfree(obj);
1182 }
1183
1184 void
1185 i915_error_state_free(struct drm_device *dev,
1186                       struct drm_i915_error_state *error)
1187 {
1188         struct drm_i915_error_state *error = container_of(error_ref,
1189                                                           typeof(*error), ref);
1190         int i;
1191
1192         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1193                 i915_error_object_free(error->ring[i].batchbuffer);
1194                 i915_error_object_free(error->ring[i].ringbuffer);
1195                 kfree(error->ring[i].requests);
1196         }
1197
1198         kfree(error->active_bo);
1199         kfree(error->overlay);
1200         kfree(error);
1201 }
1202 static void capture_bo(struct drm_i915_error_buffer *err,
1203                        struct drm_i915_gem_object *obj)
1204 {
1205         err->size = obj->base.size;
1206         err->name = obj->base.name;
1207         err->rseqno = obj->last_read_seqno;
1208         err->wseqno = obj->last_write_seqno;
1209         err->gtt_offset = obj->gtt_offset;
1210         err->read_domains = obj->base.read_domains;
1211         err->write_domain = obj->base.write_domain;
1212         err->fence_reg = obj->fence_reg;
1213         err->pinned = 0;
1214         if (obj->pin_count > 0)
1215                 err->pinned = 1;
1216         if (obj->user_pin_count > 0)
1217                 err->pinned = -1;
1218         err->tiling = obj->tiling_mode;
1219         err->dirty = obj->dirty;
1220         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1221         err->ring = obj->ring ? obj->ring->id : -1;
1222         err->cache_level = obj->cache_level;
1223 }
1224
1225 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1226                              int count, struct list_head *head)
1227 {
1228         struct drm_i915_gem_object *obj;
1229         int i = 0;
1230
1231         list_for_each_entry(obj, head, mm_list) {
1232                 capture_bo(err++, obj);
1233                 if (++i == count)
1234                         break;
1235         }
1236
1237         return i;
1238 }
1239
1240 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1241                              int count, struct list_head *head)
1242 {
1243         struct drm_i915_gem_object *obj;
1244         int i = 0;
1245
1246         list_for_each_entry(obj, head, gtt_list) {
1247                 if (obj->pin_count == 0)
1248                         continue;
1249
1250                 capture_bo(err++, obj);
1251                 if (++i == count)
1252                         break;
1253         }
1254
1255         return i;
1256 }
1257
1258 static void i915_gem_record_fences(struct drm_device *dev,
1259                                    struct drm_i915_error_state *error)
1260 {
1261         struct drm_i915_private *dev_priv = dev->dev_private;
1262         int i;
1263
1264         /* Fences */
1265         switch (INTEL_INFO(dev)->gen) {
1266         case 7:
1267         case 6:
1268                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1269                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1270                 break;
1271         case 5:
1272         case 4:
1273                 for (i = 0; i < 16; i++)
1274                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1275                 break;
1276         case 3:
1277                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1278                         for (i = 0; i < 8; i++)
1279                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1280         case 2:
1281                 for (i = 0; i < 8; i++)
1282                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1283                 break;
1284
1285         default:
1286                 BUG();
1287         }
1288 }
1289
1290 static struct drm_i915_error_object *
1291 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1292                              struct intel_ring_buffer *ring)
1293 {
1294         struct drm_i915_gem_object *obj;
1295         u32 seqno;
1296
1297         if (!ring->get_seqno)
1298                 return NULL;
1299
1300         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1301                 u32 acthd = I915_READ(ACTHD);
1302
1303                 if (WARN_ON(ring->id != RCS))
1304                         return NULL;
1305
1306                 obj = ring->private;
1307                 if (acthd >= obj->gtt_offset &&
1308                     acthd < obj->gtt_offset + obj->base.size)
1309                         return i915_error_object_create(dev_priv, obj);
1310         }
1311
1312         seqno = ring->get_seqno(ring, false);
1313         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1314                 if (obj->ring != ring)
1315                         continue;
1316
1317                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1318                         continue;
1319
1320                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1321                         continue;
1322
1323                 /* We need to copy these to an anonymous buffer as the simplest
1324                  * method to avoid being overwritten by userspace.
1325                  */
1326                 return i915_error_object_create(dev_priv, obj);
1327         }
1328
1329         return NULL;
1330 }
1331
1332 static void i915_record_ring_state(struct drm_device *dev,
1333                                    struct drm_i915_error_state *error,
1334                                    struct intel_ring_buffer *ring)
1335 {
1336         struct drm_i915_private *dev_priv = dev->dev_private;
1337
1338         if (INTEL_INFO(dev)->gen >= 6) {
1339                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1340                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1341                 error->semaphore_mboxes[ring->id][0]
1342                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1343                 error->semaphore_mboxes[ring->id][1]
1344                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1345                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1346                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1347         }
1348
1349         if (INTEL_INFO(dev)->gen >= 4) {
1350                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1351                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1352                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1353                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1354                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1355                 if (ring->id == RCS)
1356                         error->bbaddr = I915_READ64(BB_ADDR);
1357         } else {
1358                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1359                 error->ipeir[ring->id] = I915_READ(IPEIR);
1360                 error->ipehr[ring->id] = I915_READ(IPEHR);
1361                 error->instdone[ring->id] = I915_READ(INSTDONE);
1362         }
1363
1364         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1365         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1366         error->seqno[ring->id] = ring->get_seqno(ring, false);
1367         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1368         error->head[ring->id] = I915_READ_HEAD(ring);
1369         error->tail[ring->id] = I915_READ_TAIL(ring);
1370         error->ctl[ring->id] = I915_READ_CTL(ring);
1371
1372         error->cpu_ring_head[ring->id] = ring->head;
1373         error->cpu_ring_tail[ring->id] = ring->tail;
1374 }
1375
1376
1377 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1378                                            struct drm_i915_error_state *error,
1379                                            struct drm_i915_error_ring *ering)
1380 {
1381         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1382         struct drm_i915_gem_object *obj;
1383
1384         /* Currently render ring is the only HW context user */
1385         if (ring->id != RCS || !error->ccid)
1386                 return;
1387
1388         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1389                 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1390                         ering->ctx = i915_error_object_create_sized(dev_priv,
1391                                                                     obj, 1);
1392                 }
1393         }
1394 }
1395
1396 static void i915_gem_record_rings(struct drm_device *dev,
1397                                   struct drm_i915_error_state *error)
1398 {
1399         struct drm_i915_private *dev_priv = dev->dev_private;
1400         struct intel_ring_buffer *ring;
1401         struct drm_i915_gem_request *request;
1402         int i, count;
1403
1404         for_each_ring(ring, dev_priv, i) {
1405                 i915_record_ring_state(dev, error, ring);
1406
1407                 error->ring[i].batchbuffer =
1408                         i915_error_first_batchbuffer(dev_priv, ring);
1409
1410                 error->ring[i].ringbuffer =
1411                         i915_error_object_create(dev_priv, ring->obj);
1412
1413
1414                 i915_gem_record_active_context(ring, error, &error->ring[i]);
1415
1416                 count = 0;
1417                 list_for_each_entry(request, &ring->request_list, list)
1418                         count++;
1419
1420                 error->ring[i].num_requests = count;
1421                 error->ring[i].requests =
1422                         kmalloc(count*sizeof(struct drm_i915_error_request),
1423                                 GFP_ATOMIC);
1424                 if (error->ring[i].requests == NULL) {
1425                         error->ring[i].num_requests = 0;
1426                         continue;
1427                 }
1428
1429                 count = 0;
1430                 list_for_each_entry(request, &ring->request_list, list) {
1431                         struct drm_i915_error_request *erq;
1432
1433                         erq = &error->ring[i].requests[count++];
1434                         erq->seqno = request->seqno;
1435                         erq->jiffies = request->emitted_jiffies;
1436                         erq->tail = request->tail;
1437                 }
1438         }
1439 }
1440
1441 /**
1442  * i915_capture_error_state - capture an error record for later analysis
1443  * @dev: drm device
1444  *
1445  * Should be called when an error is detected (either a hang or an error
1446  * interrupt) to capture error state from the time of the error.  Fills
1447  * out a structure which becomes available in debugfs for user level tools
1448  * to pick up.
1449  */
1450 static void i915_capture_error_state(struct drm_device *dev)
1451 {
1452         struct drm_i915_private *dev_priv = dev->dev_private;
1453         struct drm_i915_gem_object *obj;
1454         struct drm_i915_error_state *error;
1455         unsigned long flags;
1456         int i, pipe;
1457
1458         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1459         error = dev_priv->gpu_error.first_error;
1460         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1461         if (error)
1462                 return;
1463
1464         /* Account for pipe specific data like PIPE*STAT */
1465         error = kmalloc(sizeof(*error), M_DRM, M_WAITOK | M_NULLOK | M_ZERO);
1466         if (!error) {
1467                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1468                 return;
1469         }
1470
1471         DRM_INFO("capturing error event; look for more information in "
1472                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1473                  dev->primary->index);
1474
1475         kref_init(&error->ref);
1476         error->eir = I915_READ(EIR);
1477         error->pgtbl_er = I915_READ(PGTBL_ER);
1478         if (HAS_HW_CONTEXTS(dev))
1479                 error->ccid = I915_READ(CCID);
1480
1481         if (HAS_PCH_SPLIT(dev))
1482                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1483         else if (IS_VALLEYVIEW(dev))
1484                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1485         else if (IS_GEN2(dev))
1486                 error->ier = I915_READ16(IER);
1487         else
1488                 error->ier = I915_READ(IER);
1489
1490         if (INTEL_INFO(dev)->gen >= 6)
1491                 error->derrmr = I915_READ(DERRMR);
1492
1493         if (IS_VALLEYVIEW(dev))
1494                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1495         else if (INTEL_INFO(dev)->gen >= 7)
1496                 error->forcewake = I915_READ(FORCEWAKE_MT);
1497         else if (INTEL_INFO(dev)->gen == 6)
1498                 error->forcewake = I915_READ(FORCEWAKE);
1499
1500         if (!HAS_PCH_SPLIT(dev))
1501                 for_each_pipe(pipe)
1502                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1503
1504         if (INTEL_INFO(dev)->gen >= 6) {
1505                 error->error = I915_READ(ERROR_GEN6);
1506                 error->done_reg = I915_READ(DONE_REG);
1507         }
1508
1509         if (INTEL_INFO(dev)->gen == 7)
1510                 error->err_int = I915_READ(GEN7_ERR_INT);
1511
1512         i915_get_extra_instdone(dev, error->extra_instdone);
1513
1514         i915_gem_record_fences(dev, error);
1515         i915_gem_record_rings(dev, error);
1516
1517         /* Record buffers on the active and pinned lists. */
1518         error->active_bo = NULL;
1519         error->pinned_bo = NULL;
1520
1521         i = 0;
1522         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1523                 i++;
1524         error->active_bo_count = i;
1525         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1526                 if (obj->pin_count)
1527                         i++;
1528         error->pinned_bo_count = i - error->active_bo_count;
1529
1530         error->active_bo = NULL;
1531         error->pinned_bo = NULL;
1532         if (i) {
1533                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1534                                            GFP_ATOMIC);
1535                 if (error->active_bo)
1536                         error->pinned_bo =
1537                                 error->active_bo + error->active_bo_count;
1538         }
1539
1540         if (error->active_bo)
1541                 error->active_bo_count =
1542                         capture_active_bo(error->active_bo,
1543                                           error->active_bo_count,
1544                                           &dev_priv->mm.active_list);
1545
1546         if (error->pinned_bo)
1547                 error->pinned_bo_count =
1548                         capture_pinned_bo(error->pinned_bo,
1549                                           error->pinned_bo_count,
1550                                           &dev_priv->mm.bound_list);
1551
1552         do_gettimeofday(&error->time);
1553
1554         error->overlay = intel_overlay_capture_error_state(dev);
1555         error->display = intel_display_capture_error_state(dev);
1556
1557         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1558         if (dev_priv->gpu_error.first_error == NULL) {
1559                 dev_priv->gpu_error.first_error = error;
1560                 error = NULL;
1561         }
1562         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1563
1564         if (error)
1565                 i915_error_state_free(&error->ref);
1566 }
1567
1568 void i915_destroy_error_state(struct drm_device *dev)
1569 {
1570         struct drm_i915_private *dev_priv = dev->dev_private;
1571         struct drm_i915_error_state *error;
1572
1573         lockmgr(&dev_priv->gpu_error.lock, LK_EXCLUSIVE);
1574         error = dev_priv->gpu_error.first_error;
1575         dev_priv->gpu_error.first_error = NULL;
1576         lockmgr(&dev_priv->gpu_error.lock, LK_RELEASE);
1577
1578         if (error)
1579                 i915_error_state_free(dev, error);
1580 }
1581 #else
1582 #define i915_capture_error_state(x)
1583 #endif
1584
1585 static void i915_report_and_clear_eir(struct drm_device *dev)
1586 {
1587         struct drm_i915_private *dev_priv = dev->dev_private;
1588         uint32_t instdone[I915_NUM_INSTDONE_REG];
1589         u32 eir = I915_READ(EIR);
1590         int pipe, i;
1591
1592         if (!eir)
1593                 return;
1594
1595         pr_err("render error detected, EIR: 0x%08x\n", eir);
1596
1597         i915_get_extra_instdone(dev, instdone);
1598
1599         if (IS_G4X(dev)) {
1600                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1601                         u32 ipeir = I915_READ(IPEIR_I965);
1602
1603                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1604                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1605                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1606                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1607                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1608                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1609                         I915_WRITE(IPEIR_I965, ipeir);
1610                         POSTING_READ(IPEIR_I965);
1611                 }
1612                 if (eir & GM45_ERROR_PAGE_TABLE) {
1613                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1614                         pr_err("page table error\n");
1615                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1616                         I915_WRITE(PGTBL_ER, pgtbl_err);
1617                         POSTING_READ(PGTBL_ER);
1618                 }
1619         }
1620
1621         if (!IS_GEN2(dev)) {
1622                 if (eir & I915_ERROR_PAGE_TABLE) {
1623                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1624                         pr_err("page table error\n");
1625                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1626                         I915_WRITE(PGTBL_ER, pgtbl_err);
1627                         POSTING_READ(PGTBL_ER);
1628                 }
1629         }
1630
1631         if (eir & I915_ERROR_MEMORY_REFRESH) {
1632                 pr_err("memory refresh error:\n");
1633                 for_each_pipe(pipe)
1634                         pr_err("pipe %c stat: 0x%08x\n",
1635                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1636                 /* pipestat has already been acked */
1637         }
1638         if (eir & I915_ERROR_INSTRUCTION) {
1639                 pr_err("instruction error\n");
1640                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1641                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1642                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1643                 if (INTEL_INFO(dev)->gen < 4) {
1644                         u32 ipeir = I915_READ(IPEIR);
1645
1646                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1647                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1648                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1649                         I915_WRITE(IPEIR, ipeir);
1650                         POSTING_READ(IPEIR);
1651                 } else {
1652                         u32 ipeir = I915_READ(IPEIR_I965);
1653
1654                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1655                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1656                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1657                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1658                         I915_WRITE(IPEIR_I965, ipeir);
1659                         POSTING_READ(IPEIR_I965);
1660                 }
1661         }
1662
1663         I915_WRITE(EIR, eir);
1664         POSTING_READ(EIR);
1665         eir = I915_READ(EIR);
1666         if (eir) {
1667                 /*
1668                  * some errors might have become stuck,
1669                  * mask them.
1670                  */
1671                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1672                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1673                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1674         }
1675 }
1676
1677 /**
1678  * i915_handle_error - handle an error interrupt
1679  * @dev: drm device
1680  *
1681  * Do some basic checking of regsiter state at error interrupt time and
1682  * dump it to the syslog.  Also call i915_capture_error_state() to make
1683  * sure we get a record and make it available in debugfs.  Fire a uevent
1684  * so userspace knows something bad happened (should trigger collection
1685  * of a ring dump etc.).
1686  */
1687 void i915_handle_error(struct drm_device *dev, bool wedged)
1688 {
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         struct intel_ring_buffer *ring;
1691         int i;
1692
1693         i915_capture_error_state(dev);
1694         i915_report_and_clear_eir(dev);
1695
1696         if (wedged) {
1697                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1698                                 &dev_priv->gpu_error.reset_counter);
1699
1700                 /*
1701                  * Wakeup waiting processes so that the reset work item
1702                  * doesn't deadlock trying to grab various locks.
1703                  */
1704                 for_each_ring(ring, dev_priv, i)
1705                         wake_up_all(&ring->irq_queue);
1706         }
1707
1708         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1709 }
1710
1711 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1712 {
1713         drm_i915_private_t *dev_priv = dev->dev_private;
1714         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1715         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1716         struct drm_i915_gem_object *obj;
1717         struct intel_unpin_work *work;
1718         bool stall_detected;
1719
1720         /* Ignore early vblank irqs */
1721         if (intel_crtc == NULL)
1722                 return;
1723
1724         lockmgr(&dev->event_lock, LK_EXCLUSIVE);
1725         work = intel_crtc->unpin_work;
1726
1727         if (work == NULL ||
1728             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1729             !work->enable_stall_check) {
1730                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1731                 lockmgr(&dev->event_lock, LK_RELEASE);
1732                 return;
1733         }
1734
1735         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1736         obj = work->pending_flip_obj;
1737         if (INTEL_INFO(dev)->gen >= 4) {
1738                 int dspsurf = DSPSURF(intel_crtc->plane);
1739                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1740                                         obj->gtt_offset;
1741         } else {
1742                 int dspaddr = DSPADDR(intel_crtc->plane);
1743                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1744                                                         crtc->y * crtc->fb->pitches[0] +
1745                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1746         }
1747
1748         lockmgr(&dev->event_lock, LK_RELEASE);
1749
1750         if (stall_detected) {
1751                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1752                 intel_prepare_page_flip(dev, intel_crtc->plane);
1753         }
1754 }
1755
1756 /* Called from drm generic code, passed 'crtc' which
1757  * we use as a pipe index
1758  */
1759 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1760 {
1761         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1762
1763         if (!i915_pipe_enabled(dev, pipe))
1764                 return -EINVAL;
1765
1766         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1767         if (INTEL_INFO(dev)->gen >= 4)
1768                 i915_enable_pipestat(dev_priv, pipe,
1769                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1770         else
1771                 i915_enable_pipestat(dev_priv, pipe,
1772                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1773
1774         /* maintain vblank delivery even in deep C-states */
1775         if (dev_priv->info->gen == 3)
1776                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1777         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1778
1779         return 0;
1780 }
1781
1782 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1783 {
1784         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1785
1786         if (!i915_pipe_enabled(dev, pipe))
1787                 return -EINVAL;
1788
1789         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1790         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1791                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1792         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1793
1794         return 0;
1795 }
1796
1797 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1798 {
1799         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1800
1801         if (!i915_pipe_enabled(dev, pipe))
1802                 return -EINVAL;
1803
1804         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1805         ironlake_enable_display_irq(dev_priv,
1806                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1807         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1808
1809         return 0;
1810 }
1811
1812 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1813 {
1814         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1815         u32 imr;
1816
1817         if (!i915_pipe_enabled(dev, pipe))
1818                 return -EINVAL;
1819
1820         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1821         imr = I915_READ(VLV_IMR);
1822         if (pipe == 0)
1823                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1824         else
1825                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1826         I915_WRITE(VLV_IMR, imr);
1827         i915_enable_pipestat(dev_priv, pipe,
1828                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1829         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1830
1831         return 0;
1832 }
1833
1834 /* Called from drm generic code, passed 'crtc' which
1835  * we use as a pipe index
1836  */
1837 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1838 {
1839         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1840
1841         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1842         if (dev_priv->info->gen == 3)
1843                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1844
1845         i915_disable_pipestat(dev_priv, pipe,
1846                               PIPE_VBLANK_INTERRUPT_ENABLE |
1847                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1848         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1849 }
1850
1851 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1852 {
1853         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1854
1855         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1856         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1857                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1858         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1859 }
1860
1861 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1862 {
1863         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1864
1865         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1866         ironlake_disable_display_irq(dev_priv,
1867                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1868         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1869 }
1870
1871 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1872 {
1873         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1874         u32 imr;
1875
1876         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
1877         i915_disable_pipestat(dev_priv, pipe,
1878                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1879         imr = I915_READ(VLV_IMR);
1880         if (pipe == 0)
1881                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1882         else
1883                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1884         I915_WRITE(VLV_IMR, imr);
1885         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
1886 }
1887
1888 static u32
1889 ring_last_seqno(struct intel_ring_buffer *ring)
1890 {
1891         return list_entry(ring->request_list.prev,
1892                           struct drm_i915_gem_request, list)->seqno;
1893 }
1894
1895 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1896 {
1897         if (list_empty(&ring->request_list) ||
1898             i915_seqno_passed(ring->get_seqno(ring, false),
1899                               ring_last_seqno(ring))) {
1900                 /* Issue a wake-up to catch stuck h/w. */
1901 #if 0 /* XXX From OpenBSD */
1902                 if (waitqueue_active(&ring->irq_queue)) {
1903                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1904                                   ring->name);
1905                         wake_up_all(&ring->irq_queue);
1906                         *err = true;
1907                 }
1908 #else
1909                 wake_up_all(&ring->irq_queue);
1910 #endif
1911                 return true;
1912         }
1913         return false;
1914 }
1915
1916 static bool semaphore_passed(struct intel_ring_buffer *ring)
1917 {
1918         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1919         u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1920         struct intel_ring_buffer *signaller;
1921         u32 cmd, ipehr, acthd_min;
1922
1923         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1924         if ((ipehr & ~(0x3 << 16)) !=
1925             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1926                 return false;
1927
1928         /* ACTHD is likely pointing to the dword after the actual command,
1929          * so scan backwards until we find the MBOX.
1930          */
1931         acthd_min = max((int)acthd - 3 * 4, 0);
1932         do {
1933                 cmd = ioread32(ring->virtual_start + acthd);
1934                 if (cmd == ipehr)
1935                         break;
1936
1937                 acthd -= 4;
1938                 if (acthd < acthd_min)
1939                         return false;
1940         } while (1);
1941
1942         signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1943         return i915_seqno_passed(signaller->get_seqno(signaller, false),
1944                                  ioread32(ring->virtual_start+acthd+4)+1);
1945 }
1946
1947 static bool kick_ring(struct intel_ring_buffer *ring)
1948 {
1949         struct drm_device *dev = ring->dev;
1950         struct drm_i915_private *dev_priv = dev->dev_private;
1951         u32 tmp = I915_READ_CTL(ring);
1952         if (tmp & RING_WAIT) {
1953                 DRM_ERROR("Kicking stuck wait on %s\n",
1954                           ring->name);
1955                 I915_WRITE_CTL(ring, tmp);
1956                 return true;
1957         }
1958
1959         if (INTEL_INFO(dev)->gen >= 6 &&
1960             tmp & RING_WAIT_SEMAPHORE &&
1961             semaphore_passed(ring)) {
1962                 DRM_ERROR("Kicking stuck semaphore on %s\n",
1963                           ring->name);
1964                 I915_WRITE_CTL(ring, tmp);
1965                 return true;
1966         }
1967         return false;
1968 }
1969
1970 static bool i915_hangcheck_hung(struct drm_device *dev)
1971 {
1972         drm_i915_private_t *dev_priv = dev->dev_private;
1973
1974         if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1975                 bool hung = true;
1976
1977                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1978                 i915_handle_error(dev, true);
1979
1980                 if (!IS_GEN2(dev)) {
1981                         struct intel_ring_buffer *ring;
1982                         int i;
1983
1984                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1985                          * If so we can simply poke the RB_WAIT bit
1986                          * and break the hang. This should work on
1987                          * all but the second generation chipsets.
1988                          */
1989                         for_each_ring(ring, dev_priv, i)
1990                                 hung &= !kick_ring(ring);
1991                 }
1992
1993                 return hung;
1994         }
1995
1996         return false;
1997 }
1998
1999 /**
2000  * This is called when the chip hasn't reported back with completed
2001  * batchbuffers in a long time. The first time this is called we simply record
2002  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
2003  * again, we assume the chip is wedged and try to fix it.
2004  */
2005 void i915_hangcheck_elapsed(unsigned long data)
2006 {
2007         struct drm_device *dev = (struct drm_device *)data;
2008         drm_i915_private_t *dev_priv = dev->dev_private;
2009         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
2010         struct intel_ring_buffer *ring;
2011         bool err = false, idle;
2012         int i;
2013
2014         if (!i915_enable_hangcheck)
2015                 return;
2016
2017         memset(acthd, 0, sizeof(acthd));
2018         idle = true;
2019         for_each_ring(ring, dev_priv, i) {
2020             idle &= i915_hangcheck_ring_idle(ring, &err);
2021             acthd[i] = intel_ring_get_active_head(ring);
2022         }
2023
2024         /* If all work is done then ACTHD clearly hasn't advanced. */
2025         if (idle) {
2026                 if (err) {
2027                         if (i915_hangcheck_hung(dev))
2028                                 return;
2029
2030                         goto repeat;
2031                 }
2032
2033                 dev_priv->gpu_error.hangcheck_count = 0;
2034                 return;
2035         }
2036
2037         i915_get_extra_instdone(dev, instdone);
2038         if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
2039                    sizeof(acthd)) == 0 &&
2040             memcmp(dev_priv->gpu_error.prev_instdone, instdone,
2041                    sizeof(instdone)) == 0) {
2042                 if (i915_hangcheck_hung(dev))
2043                         return;
2044         } else {
2045                 dev_priv->gpu_error.hangcheck_count = 0;
2046
2047                 memcpy(dev_priv->gpu_error.last_acthd, acthd,
2048                        sizeof(acthd));
2049                 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
2050                        sizeof(instdone));
2051         }
2052
2053 repeat:
2054         /* Reset timer case chip hangs without another request being added */
2055         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2056                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2057 }
2058
2059 /* drm_dma.h hooks
2060 */
2061 static void ironlake_irq_preinstall(struct drm_device *dev)
2062 {
2063         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2064
2065         atomic_set(&dev_priv->irq_received, 0);
2066
2067         I915_WRITE(HWSTAM, 0xeffe);
2068
2069         /* XXX hotplug from PCH */
2070
2071         I915_WRITE(DEIMR, 0xffffffff);
2072         I915_WRITE(DEIER, 0x0);
2073         POSTING_READ(DEIER);
2074
2075         /* and GT */
2076         I915_WRITE(GTIMR, 0xffffffff);
2077         I915_WRITE(GTIER, 0x0);
2078         POSTING_READ(GTIER);
2079
2080         if (HAS_PCH_NOP(dev))
2081                 return;
2082
2083         /* south display irq */
2084         I915_WRITE(SDEIMR, 0xffffffff);
2085         /*
2086          * SDEIER is also touched by the interrupt handler to work around missed
2087          * PCH interrupts. Hence we can't update it after the interrupt handler
2088          * is enabled - instead we unconditionally enable all PCH interrupt
2089          * sources here, but then only unmask them as needed with SDEIMR.
2090          */
2091         I915_WRITE(SDEIER, 0xffffffff);
2092         POSTING_READ(SDEIER);
2093 }
2094
2095 static void valleyview_irq_preinstall(struct drm_device *dev)
2096 {
2097         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2098         int pipe;
2099
2100         atomic_set(&dev_priv->irq_received, 0);
2101
2102         /* VLV magic */
2103         I915_WRITE(VLV_IMR, 0);
2104         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2105         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2106         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2107
2108         /* and GT */
2109         I915_WRITE(GTIIR, I915_READ(GTIIR));
2110         I915_WRITE(GTIIR, I915_READ(GTIIR));
2111         I915_WRITE(GTIMR, 0xffffffff);
2112         I915_WRITE(GTIER, 0x0);
2113         POSTING_READ(GTIER);
2114
2115         I915_WRITE(DPINVGTT, 0xff);
2116
2117         I915_WRITE(PORT_HOTPLUG_EN, 0);
2118         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2119         for_each_pipe(pipe)
2120                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2121         I915_WRITE(VLV_IIR, 0xffffffff);
2122         I915_WRITE(VLV_IMR, 0xffffffff);
2123         I915_WRITE(VLV_IER, 0x0);
2124         POSTING_READ(VLV_IER);
2125 }
2126
2127 static void ibx_hpd_irq_setup(struct drm_device *dev)
2128 {
2129         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2130         struct drm_mode_config *mode_config = &dev->mode_config;
2131         struct intel_encoder *intel_encoder;
2132         u32 mask = ~I915_READ(SDEIMR);
2133         u32 hotplug;
2134
2135         if (HAS_PCH_IBX(dev)) {
2136                 mask &= ~SDE_HOTPLUG_MASK;
2137                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2138                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2139                                 mask |= hpd_ibx[intel_encoder->hpd_pin];
2140         } else {
2141                 mask &= ~SDE_HOTPLUG_MASK_CPT;
2142                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2143                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2144                                 mask |= hpd_cpt[intel_encoder->hpd_pin];
2145         }
2146
2147         I915_WRITE(SDEIMR, ~mask);
2148
2149         /*
2150          * Enable digital hotplug on the PCH, and configure the DP short pulse
2151          * duration to 2ms (which is the minimum in the Display Port spec)
2152          *
2153          * This register is the same on all known PCH chips.
2154          */
2155         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2156         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2157         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2158         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2159         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2160         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2161 }
2162
2163 static void ibx_irq_postinstall(struct drm_device *dev)
2164 {
2165         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2166         u32 mask;
2167
2168         if (HAS_PCH_IBX(dev))
2169                 mask = SDE_GMBUS | SDE_AUX_MASK;
2170         else
2171                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2172
2173         if (HAS_PCH_NOP(dev))
2174                 return;
2175
2176         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2177         I915_WRITE(SDEIMR, ~mask);
2178 }
2179
2180 static int ironlake_irq_postinstall(struct drm_device *dev)
2181 {
2182         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2183         /* enable kind of interrupts always enabled */
2184         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2185                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2186                            DE_AUX_CHANNEL_A;
2187         u32 render_irqs;
2188
2189         dev_priv->irq_mask = ~display_mask;
2190
2191         /* should always can generate irq */
2192         I915_WRITE(DEIIR, I915_READ(DEIIR));
2193         I915_WRITE(DEIMR, dev_priv->irq_mask);
2194         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2195         POSTING_READ(DEIER);
2196
2197         dev_priv->gt_irq_mask = ~0;
2198
2199         I915_WRITE(GTIIR, I915_READ(GTIIR));
2200         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2201
2202         if (IS_GEN6(dev))
2203                 render_irqs =
2204                         GT_USER_INTERRUPT |
2205                         GEN6_BSD_USER_INTERRUPT |
2206                         GEN6_BLITTER_USER_INTERRUPT;
2207         else
2208                 render_irqs =
2209                         GT_USER_INTERRUPT |
2210                         GT_PIPE_NOTIFY |
2211                         GT_BSD_USER_INTERRUPT;
2212         I915_WRITE(GTIER, render_irqs);
2213         POSTING_READ(GTIER);
2214
2215         ibx_irq_postinstall(dev);
2216
2217         if (IS_IRONLAKE_M(dev)) {
2218                 /* Clear & enable PCU event interrupts */
2219                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2220                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2221                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2222         }
2223
2224         return 0;
2225 }
2226
2227 static int ivybridge_irq_postinstall(struct drm_device *dev)
2228 {
2229         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2230         /* enable kind of interrupts always enabled */
2231         u32 display_mask =
2232                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2233                 DE_PLANEC_FLIP_DONE_IVB |
2234                 DE_PLANEB_FLIP_DONE_IVB |
2235                 DE_PLANEA_FLIP_DONE_IVB |
2236                 DE_AUX_CHANNEL_A_IVB;
2237         u32 render_irqs;
2238
2239         dev_priv->irq_mask = ~display_mask;
2240
2241         /* should always can generate irq */
2242         I915_WRITE(DEIIR, I915_READ(DEIIR));
2243         I915_WRITE(DEIMR, dev_priv->irq_mask);
2244         I915_WRITE(DEIER,
2245                    display_mask |
2246                    DE_PIPEC_VBLANK_IVB |
2247                    DE_PIPEB_VBLANK_IVB |
2248                    DE_PIPEA_VBLANK_IVB);
2249         POSTING_READ(DEIER);
2250
2251         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2252
2253         I915_WRITE(GTIIR, I915_READ(GTIIR));
2254         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2255
2256         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2257                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2258         I915_WRITE(GTIER, render_irqs);
2259         POSTING_READ(GTIER);
2260
2261         ibx_irq_postinstall(dev);
2262
2263         return 0;
2264 }
2265
2266 static int valleyview_irq_postinstall(struct drm_device *dev)
2267 {
2268         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2269         u32 enable_mask;
2270         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2271         u32 render_irqs;
2272         u16 msid;
2273
2274         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2275         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2276                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2277                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2278                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2279
2280         /*
2281          *Leave vblank interrupts masked initially.  enable/disable will
2282          * toggle them based on usage.
2283          */
2284         dev_priv->irq_mask = (~enable_mask) |
2285                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2286                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2287
2288         /* Hack for broken MSIs on VLV */
2289         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2290         pci_read_config_word(dev->pdev, 0x98, &msid);
2291         msid &= 0xff; /* mask out delivery bits */
2292         msid |= (1<<14);
2293         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2294
2295         I915_WRITE(PORT_HOTPLUG_EN, 0);
2296         POSTING_READ(PORT_HOTPLUG_EN);
2297
2298         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2299         I915_WRITE(VLV_IER, enable_mask);
2300         I915_WRITE(VLV_IIR, 0xffffffff);
2301         I915_WRITE(PIPESTAT(0), 0xffff);
2302         I915_WRITE(PIPESTAT(1), 0xffff);
2303         POSTING_READ(VLV_IER);
2304
2305         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2306         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2307         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2308
2309         I915_WRITE(VLV_IIR, 0xffffffff);
2310         I915_WRITE(VLV_IIR, 0xffffffff);
2311
2312         I915_WRITE(GTIIR, I915_READ(GTIIR));
2313         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2314
2315         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2316                 GEN6_BLITTER_USER_INTERRUPT;
2317         I915_WRITE(GTIER, render_irqs);
2318         POSTING_READ(GTIER);
2319
2320         /* ack & enable invalid PTE error interrupts */
2321 #if 0 /* FIXME: add support to irq handler for checking these bits */
2322         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2323         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2324 #endif
2325
2326         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2327
2328         return 0;
2329 }
2330
2331 static void valleyview_irq_uninstall(struct drm_device *dev)
2332 {
2333         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2334         int pipe;
2335
2336         if (!dev_priv)
2337                 return;
2338
2339         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2340
2341         for_each_pipe(pipe)
2342                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2343
2344         I915_WRITE(HWSTAM, 0xffffffff);
2345         I915_WRITE(PORT_HOTPLUG_EN, 0);
2346         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2347         for_each_pipe(pipe)
2348                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2349         I915_WRITE(VLV_IIR, 0xffffffff);
2350         I915_WRITE(VLV_IMR, 0xffffffff);
2351         I915_WRITE(VLV_IER, 0x0);
2352         POSTING_READ(VLV_IER);
2353 }
2354
2355 static void ironlake_irq_uninstall(struct drm_device *dev)
2356 {
2357         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2358
2359         if (!dev_priv)
2360                 return;
2361
2362         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2363
2364         I915_WRITE(HWSTAM, 0xffffffff);
2365
2366         I915_WRITE(DEIMR, 0xffffffff);
2367         I915_WRITE(DEIER, 0x0);
2368         I915_WRITE(DEIIR, I915_READ(DEIIR));
2369
2370         I915_WRITE(GTIMR, 0xffffffff);
2371         I915_WRITE(GTIER, 0x0);
2372         I915_WRITE(GTIIR, I915_READ(GTIIR));
2373
2374         if (HAS_PCH_NOP(dev))
2375                 return;
2376
2377         I915_WRITE(SDEIMR, 0xffffffff);
2378         I915_WRITE(SDEIER, 0x0);
2379         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2380 }
2381
2382 static void i8xx_irq_preinstall(struct drm_device * dev)
2383 {
2384         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2385         int pipe;
2386
2387         atomic_set(&dev_priv->irq_received, 0);
2388
2389         for_each_pipe(pipe)
2390                 I915_WRITE(PIPESTAT(pipe), 0);
2391         I915_WRITE16(IMR, 0xffff);
2392         I915_WRITE16(IER, 0x0);
2393         POSTING_READ16(IER);
2394 }
2395
2396 static int i8xx_irq_postinstall(struct drm_device *dev)
2397 {
2398         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2399
2400         I915_WRITE16(EMR,
2401                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2402
2403         /* Unmask the interrupts that we always want on. */
2404         dev_priv->irq_mask =
2405                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2406                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2407                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2408                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2409                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2410         I915_WRITE16(IMR, dev_priv->irq_mask);
2411
2412         I915_WRITE16(IER,
2413                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2414                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2415                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2416                      I915_USER_INTERRUPT);
2417         POSTING_READ16(IER);
2418
2419         return 0;
2420 }
2421
2422 /*
2423  * Returns true when a page flip has completed.
2424  */
2425 static bool i8xx_handle_vblank(struct drm_device *dev,
2426                                int pipe, u16 iir)
2427 {
2428         drm_i915_private_t *dev_priv = dev->dev_private;
2429         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2430
2431         if (!drm_handle_vblank(dev, pipe))
2432                 return false;
2433
2434         if ((iir & flip_pending) == 0)
2435                 return false;
2436
2437         intel_prepare_page_flip(dev, pipe);
2438
2439         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2440          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2441          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2442          * the flip is completed (no longer pending). Since this doesn't raise
2443          * an interrupt per se, we watch for the change at vblank.
2444          */
2445         if (I915_READ16(ISR) & flip_pending)
2446                 return false;
2447
2448         intel_finish_page_flip(dev, pipe);
2449
2450         return true;
2451 }
2452
2453 static irqreturn_t i8xx_irq_handler(void *arg)
2454 {
2455         struct drm_device *dev = (struct drm_device *) arg;
2456         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2457         u16 iir, new_iir;
2458         u32 pipe_stats[2];
2459         int irq_received;
2460         int pipe;
2461         u16 flip_mask =
2462                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2463                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2464
2465         atomic_inc(&dev_priv->irq_received);
2466
2467         iir = I915_READ16(IIR);
2468         if (iir == 0)
2469                 return;
2470
2471         while (iir & ~flip_mask) {
2472                 /* Can't rely on pipestat interrupt bit in iir as it might
2473                  * have been cleared after the pipestat interrupt was received.
2474                  * It doesn't set the bit in iir again, but it still produces
2475                  * interrupts (for non-MSI).
2476                  */
2477                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
2478                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2479                         i915_handle_error(dev, false);
2480
2481                 for_each_pipe(pipe) {
2482                         int reg = PIPESTAT(pipe);
2483                         pipe_stats[pipe] = I915_READ(reg);
2484
2485                         /*
2486                          * Clear the PIPE*STAT regs before the IIR
2487                          */
2488                         if (pipe_stats[pipe] & 0x8000ffff) {
2489                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2490                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2491                                                          pipe_name(pipe));
2492                                 I915_WRITE(reg, pipe_stats[pipe]);
2493                                 irq_received = 1;
2494                         }
2495                 }
2496                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
2497
2498                 I915_WRITE16(IIR, iir & ~flip_mask);
2499                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2500
2501                 i915_update_dri1_breadcrumb(dev);
2502
2503                 if (iir & I915_USER_INTERRUPT)
2504                         notify_ring(dev, &dev_priv->ring[RCS]);
2505
2506                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2507                     i8xx_handle_vblank(dev, 0, iir))
2508                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2509
2510                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2511                     i8xx_handle_vblank(dev, 1, iir))
2512                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2513
2514                 iir = new_iir;
2515         }
2516
2517         return;
2518 }
2519
2520 static void i8xx_irq_uninstall(struct drm_device * dev)
2521 {
2522         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2523         int pipe;
2524
2525         for_each_pipe(pipe) {
2526                 /* Clear enable bits; then clear status bits */
2527                 I915_WRITE(PIPESTAT(pipe), 0);
2528                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2529         }
2530         I915_WRITE16(IMR, 0xffff);
2531         I915_WRITE16(IER, 0x0);
2532         I915_WRITE16(IIR, I915_READ16(IIR));
2533 }
2534
2535 static void i915_irq_preinstall(struct drm_device * dev)
2536 {
2537         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2538         int pipe;
2539
2540         atomic_set(&dev_priv->irq_received, 0);
2541
2542         if (I915_HAS_HOTPLUG(dev)) {
2543                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2544                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2545         }
2546
2547         I915_WRITE16(HWSTAM, 0xeffe);
2548         for_each_pipe(pipe)
2549                 I915_WRITE(PIPESTAT(pipe), 0);
2550         I915_WRITE(IMR, 0xffffffff);
2551         I915_WRITE(IER, 0x0);
2552         POSTING_READ(IER);
2553 }
2554
2555 static int i915_irq_postinstall(struct drm_device *dev)
2556 {
2557         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2558         u32 enable_mask;
2559
2560         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2561
2562         /* Unmask the interrupts that we always want on. */
2563         dev_priv->irq_mask =
2564                 ~(I915_ASLE_INTERRUPT |
2565                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2566                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2567                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2568                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2569                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2570
2571         enable_mask =
2572                 I915_ASLE_INTERRUPT |
2573                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2574                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2575                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2576                 I915_USER_INTERRUPT;
2577
2578         if (I915_HAS_HOTPLUG(dev)) {
2579                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2580                 POSTING_READ(PORT_HOTPLUG_EN);
2581
2582                 /* Enable in IER... */
2583                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2584                 /* and unmask in IMR */
2585                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2586         }
2587
2588         I915_WRITE(IMR, dev_priv->irq_mask);
2589         I915_WRITE(IER, enable_mask);
2590         POSTING_READ(IER);
2591
2592         intel_opregion_enable_asle(dev);
2593
2594         return 0;
2595 }
2596
2597 /*
2598  * Returns true when a page flip has completed.
2599  */
2600 static bool i915_handle_vblank(struct drm_device *dev,
2601                                int plane, int pipe, u32 iir)
2602 {
2603         drm_i915_private_t *dev_priv = dev->dev_private;
2604         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2605
2606         if (!drm_handle_vblank(dev, pipe))
2607                 return false;
2608
2609         if ((iir & flip_pending) == 0)
2610                 return false;
2611
2612         intel_prepare_page_flip(dev, plane);
2613
2614         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2615          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2616          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2617          * the flip is completed (no longer pending). Since this doesn't raise
2618          * an interrupt per se, we watch for the change at vblank.
2619          */
2620         if (I915_READ(ISR) & flip_pending)
2621                 return false;
2622
2623         intel_finish_page_flip(dev, pipe);
2624
2625         return true;
2626 }
2627
2628 static irqreturn_t i915_irq_handler(void *arg)
2629 {
2630         struct drm_device *dev = (struct drm_device *) arg;
2631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2632         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2633         u32 flip_mask =
2634                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2635                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2636         int pipe;
2637
2638         atomic_inc(&dev_priv->irq_received);
2639
2640         iir = I915_READ(IIR);
2641         do {
2642                 bool irq_received = (iir & ~flip_mask) != 0;
2643                 bool blc_event = false;
2644
2645                 /* Can't rely on pipestat interrupt bit in iir as it might
2646                  * have been cleared after the pipestat interrupt was received.
2647                  * It doesn't set the bit in iir again, but it still produces
2648                  * interrupts (for non-MSI).
2649                  */
2650                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
2651                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2652                         i915_handle_error(dev, false);
2653
2654                 for_each_pipe(pipe) {
2655                         int reg = PIPESTAT(pipe);
2656                         pipe_stats[pipe] = I915_READ(reg);
2657
2658                         /* Clear the PIPE*STAT regs before the IIR */
2659                         if (pipe_stats[pipe] & 0x8000ffff) {
2660                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2661                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2662                                                          pipe_name(pipe));
2663                                 I915_WRITE(reg, pipe_stats[pipe]);
2664                                 irq_received = true;
2665                         }
2666                 }
2667                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
2668
2669                 if (!irq_received)
2670                         break;
2671
2672                 /* Consume port.  Then clear IIR or we'll miss events */
2673                 if ((I915_HAS_HOTPLUG(dev)) &&
2674                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2675                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2676                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2677
2678                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2679                                   hotplug_status);
2680                         if (hotplug_trigger) {
2681                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
2682                                         i915_hpd_irq_setup(dev);
2683                                 queue_work(dev_priv->wq,
2684                                            &dev_priv->hotplug_work);
2685                         }
2686                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2687                         POSTING_READ(PORT_HOTPLUG_STAT);
2688                 }
2689
2690                 I915_WRITE(IIR, iir & ~flip_mask);
2691                 new_iir = I915_READ(IIR); /* Flush posted writes */
2692
2693                 if (iir & I915_USER_INTERRUPT)
2694                         notify_ring(dev, &dev_priv->ring[RCS]);
2695
2696                 for_each_pipe(pipe) {
2697                         int plane = pipe;
2698                         if (IS_MOBILE(dev))
2699                                 plane = !plane;
2700
2701                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2702                             i915_handle_vblank(dev, plane, pipe, iir))
2703                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2704
2705                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2706                                 blc_event = true;
2707                 }
2708
2709                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2710                         intel_opregion_asle_intr(dev);
2711
2712                 /* With MSI, interrupts are only generated when iir
2713                  * transitions from zero to nonzero.  If another bit got
2714                  * set while we were handling the existing iir bits, then
2715                  * we would never get another interrupt.
2716                  *
2717                  * This is fine on non-MSI as well, as if we hit this path
2718                  * we avoid exiting the interrupt handler only to generate
2719                  * another one.
2720                  *
2721                  * Note that for MSI this could cause a stray interrupt report
2722                  * if an interrupt landed in the time between writing IIR and
2723                  * the posting read.  This should be rare enough to never
2724                  * trigger the 99% of 100,000 interrupts test for disabling
2725                  * stray interrupts.
2726                  */
2727                 iir = new_iir;
2728         } while (iir & ~flip_mask);
2729
2730         i915_update_dri1_breadcrumb(dev);
2731 }
2732
2733 static void i915_irq_uninstall(struct drm_device * dev)
2734 {
2735         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2736         int pipe;
2737
2738         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2739
2740         if (I915_HAS_HOTPLUG(dev)) {
2741                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2742                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2743         }
2744
2745         I915_WRITE16(HWSTAM, 0xffff);
2746         for_each_pipe(pipe) {
2747                 /* Clear enable bits; then clear status bits */
2748                 I915_WRITE(PIPESTAT(pipe), 0);
2749                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2750         }
2751         I915_WRITE(IMR, 0xffffffff);
2752         I915_WRITE(IER, 0x0);
2753
2754         I915_WRITE(IIR, I915_READ(IIR));
2755 }
2756
2757 static void i965_irq_preinstall(struct drm_device * dev)
2758 {
2759         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2760         int pipe;
2761
2762         atomic_set(&dev_priv->irq_received, 0);
2763
2764         I915_WRITE(PORT_HOTPLUG_EN, 0);
2765         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2766
2767         I915_WRITE(HWSTAM, 0xeffe);
2768         for_each_pipe(pipe)
2769                 I915_WRITE(PIPESTAT(pipe), 0);
2770         I915_WRITE(IMR, 0xffffffff);
2771         I915_WRITE(IER, 0x0);
2772         POSTING_READ(IER);
2773 }
2774
2775 static int i965_irq_postinstall(struct drm_device *dev)
2776 {
2777         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2778         u32 enable_mask;
2779         u32 error_mask;
2780
2781         /* Unmask the interrupts that we always want on. */
2782         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2783                                I915_DISPLAY_PORT_INTERRUPT |
2784                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2785                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2786                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2787                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2788                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2789
2790         enable_mask = ~dev_priv->irq_mask;
2791         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2792                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2793         enable_mask |= I915_USER_INTERRUPT;
2794
2795         if (IS_G4X(dev))
2796                 enable_mask |= I915_BSD_USER_INTERRUPT;
2797
2798         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2799
2800         /*
2801          * Enable some error detection, note the instruction error mask
2802          * bit is reserved, so we leave it masked.
2803          */
2804         if (IS_G4X(dev)) {
2805                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2806                                GM45_ERROR_MEM_PRIV |
2807                                GM45_ERROR_CP_PRIV |
2808                                I915_ERROR_MEMORY_REFRESH);
2809         } else {
2810                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2811                                I915_ERROR_MEMORY_REFRESH);
2812         }
2813         I915_WRITE(EMR, error_mask);
2814
2815         I915_WRITE(IMR, dev_priv->irq_mask);
2816         I915_WRITE(IER, enable_mask);
2817         POSTING_READ(IER);
2818
2819         I915_WRITE(PORT_HOTPLUG_EN, 0);
2820         POSTING_READ(PORT_HOTPLUG_EN);
2821
2822         intel_opregion_enable_asle(dev);
2823
2824         return 0;
2825 }
2826
2827 static void i915_hpd_irq_setup(struct drm_device *dev)
2828 {
2829         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2830         struct drm_mode_config *mode_config = &dev->mode_config;
2831         struct intel_encoder *intel_encoder;
2832         u32 hotplug_en;
2833
2834         if (I915_HAS_HOTPLUG(dev)) {
2835                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2836                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2837                 /* Note HDMI and DP share hotplug bits */
2838                 /* enable bits are the same for all generations */
2839                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2840                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2841                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
2842                 /* Programming the CRT detection parameters tends
2843                    to generate a spurious hotplug event about three
2844                    seconds later.  So just do it once.
2845                 */
2846                 if (IS_G4X(dev))
2847                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2848                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2849                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2850
2851                 /* Ignore TV since it's buggy */
2852                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2853         }
2854 }
2855
2856 static irqreturn_t i965_irq_handler(void *arg)
2857 {
2858         struct drm_device *dev = (struct drm_device *) arg;
2859         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2860         u32 iir, new_iir;
2861         u32 pipe_stats[I915_MAX_PIPES];
2862         int irq_received;
2863         int pipe;
2864         u32 flip_mask =
2865                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2866                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2867
2868         atomic_inc(&dev_priv->irq_received);
2869
2870         iir = I915_READ(IIR);
2871
2872         for (;;) {
2873                 bool blc_event = false;
2874
2875                 irq_received = (iir & ~flip_mask) != 0;
2876
2877                 /* Can't rely on pipestat interrupt bit in iir as it might
2878                  * have been cleared after the pipestat interrupt was received.
2879                  * It doesn't set the bit in iir again, but it still produces
2880                  * interrupts (for non-MSI).
2881                  */
2882                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
2883                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2884                         i915_handle_error(dev, false);
2885
2886                 for_each_pipe(pipe) {
2887                         int reg = PIPESTAT(pipe);
2888                         pipe_stats[pipe] = I915_READ(reg);
2889
2890                         /*
2891                          * Clear the PIPE*STAT regs before the IIR
2892                          */
2893                         if (pipe_stats[pipe] & 0x8000ffff) {
2894                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2895                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2896                                                          pipe_name(pipe));
2897                                 I915_WRITE(reg, pipe_stats[pipe]);
2898                                 irq_received = 1;
2899                         }
2900                 }
2901                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
2902
2903                 if (!irq_received)
2904                         break;
2905
2906                 /* Consume port.  Then clear IIR or we'll miss events */
2907                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2908                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2909                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2910                                                                   HOTPLUG_INT_STATUS_G4X :
2911                                                                   HOTPLUG_INT_STATUS_I965);
2912
2913                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2914                                   hotplug_status);
2915                         if (hotplug_trigger) {
2916                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
2917                                                             IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
2918                                         i915_hpd_irq_setup(dev);
2919                                 queue_work(dev_priv->wq,
2920                                            &dev_priv->hotplug_work);
2921                         }
2922                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2923                         I915_READ(PORT_HOTPLUG_STAT);
2924                 }
2925
2926                 I915_WRITE(IIR, iir & ~flip_mask);
2927                 new_iir = I915_READ(IIR); /* Flush posted writes */
2928
2929                 if (iir & I915_USER_INTERRUPT)
2930                         notify_ring(dev, &dev_priv->ring[RCS]);
2931                 if (iir & I915_BSD_USER_INTERRUPT)
2932                         notify_ring(dev, &dev_priv->ring[VCS]);
2933
2934                 for_each_pipe(pipe) {
2935                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2936                             i915_handle_vblank(dev, pipe, pipe, iir))
2937                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2938
2939                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2940                                 blc_event = true;
2941                 }
2942
2943                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2944                         intel_opregion_asle_intr(dev);
2945
2946                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2947                         gmbus_irq_handler(dev);
2948
2949                 /* With MSI, interrupts are only generated when iir
2950                  * transitions from zero to nonzero.  If another bit got
2951                  * set while we were handling the existing iir bits, then
2952                  * we would never get another interrupt.
2953                  *
2954                  * This is fine on non-MSI as well, as if we hit this path
2955                  * we avoid exiting the interrupt handler only to generate
2956                  * another one.
2957                  *
2958                  * Note that for MSI this could cause a stray interrupt report
2959                  * if an interrupt landed in the time between writing IIR and
2960                  * the posting read.  This should be rare enough to never
2961                  * trigger the 99% of 100,000 interrupts test for disabling
2962                  * stray interrupts.
2963                  */
2964                 iir = new_iir;
2965         }
2966
2967         i915_update_dri1_breadcrumb(dev);
2968 }
2969
2970 static void i965_irq_uninstall(struct drm_device * dev)
2971 {
2972         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2973         int pipe;
2974
2975         if (!dev_priv)
2976                 return;
2977
2978         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2979
2980         I915_WRITE(PORT_HOTPLUG_EN, 0);
2981         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2982
2983         I915_WRITE(HWSTAM, 0xffffffff);
2984         for_each_pipe(pipe)
2985                 I915_WRITE(PIPESTAT(pipe), 0);
2986         I915_WRITE(IMR, 0xffffffff);
2987         I915_WRITE(IER, 0x0);
2988
2989         for_each_pipe(pipe)
2990                 I915_WRITE(PIPESTAT(pipe),
2991                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2992         I915_WRITE(IIR, I915_READ(IIR));
2993 }
2994
2995 static void i915_reenable_hotplug_timer_func(unsigned long data)
2996 {
2997         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
2998         struct drm_device *dev = dev_priv->dev;
2999         struct drm_mode_config *mode_config = &dev->mode_config;
3000         int i;
3001
3002         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
3003         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3004                 struct drm_connector *connector;
3005
3006                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3007                         continue;
3008
3009                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3010
3011                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3012                         struct intel_connector *intel_connector = to_intel_connector(connector);
3013
3014                         if (intel_connector->encoder->hpd_pin == i) {
3015                                 if (connector->polled != intel_connector->polled)
3016                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3017                                                          drm_get_connector_name(connector));
3018                                 connector->polled = intel_connector->polled;
3019                                 if (!connector->polled)
3020                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3021                         }
3022                 }
3023         }
3024         if (dev_priv->display.hpd_irq_setup)
3025                 dev_priv->display.hpd_irq_setup(dev);
3026         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
3027 }
3028
3029 void intel_irq_init(struct drm_device *dev)
3030 {
3031         struct drm_i915_private *dev_priv = dev->dev_private;
3032
3033         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3034         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3035         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3036         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3037
3038         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3039                     i915_hangcheck_elapsed,
3040                     (unsigned long) dev);
3041         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3042                     (unsigned long) dev_priv);
3043
3044         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3045
3046         dev->driver->get_vblank_counter = i915_get_vblank_counter;
3047         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3048         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3049                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3050                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3051         }
3052
3053         if (drm_core_check_feature(dev, DRIVER_MODESET))
3054                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3055         else
3056                 dev->driver->get_vblank_timestamp = NULL;
3057         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3058
3059         if (IS_VALLEYVIEW(dev)) {
3060                 dev->driver->irq_handler = valleyview_irq_handler;
3061                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3062                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3063                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3064                 dev->driver->enable_vblank = valleyview_enable_vblank;
3065                 dev->driver->disable_vblank = valleyview_disable_vblank;
3066                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3067         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3068                 /* Share pre & uninstall handlers with ILK/SNB */
3069                 dev->driver->irq_handler = ivybridge_irq_handler;
3070                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3071                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3072                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3073                 dev->driver->enable_vblank = ivybridge_enable_vblank;
3074                 dev->driver->disable_vblank = ivybridge_disable_vblank;
3075                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3076         } else if (HAS_PCH_SPLIT(dev)) {
3077                 dev->driver->irq_handler = ironlake_irq_handler;
3078                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3079                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3080                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3081                 dev->driver->enable_vblank = ironlake_enable_vblank;
3082                 dev->driver->disable_vblank = ironlake_disable_vblank;
3083                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3084         } else {
3085                 if (INTEL_INFO(dev)->gen == 2) {
3086                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3087                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3088                         dev->driver->irq_handler = i8xx_irq_handler;
3089                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3090                 } else if (INTEL_INFO(dev)->gen == 3) {
3091                         dev->driver->irq_preinstall = i915_irq_preinstall;
3092                         dev->driver->irq_postinstall = i915_irq_postinstall;
3093                         dev->driver->irq_uninstall = i915_irq_uninstall;
3094                         dev->driver->irq_handler = i915_irq_handler;
3095                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3096                 } else {
3097                         dev->driver->irq_preinstall = i965_irq_preinstall;
3098                         dev->driver->irq_postinstall = i965_irq_postinstall;
3099                         dev->driver->irq_uninstall = i965_irq_uninstall;
3100                         dev->driver->irq_handler = i965_irq_handler;
3101                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3102                 }
3103                 dev->driver->enable_vblank = i915_enable_vblank;
3104                 dev->driver->disable_vblank = i915_disable_vblank;
3105         }
3106 }
3107
3108 void intel_hpd_init(struct drm_device *dev)
3109 {
3110         struct drm_i915_private *dev_priv = dev->dev_private;
3111         struct drm_mode_config *mode_config = &dev->mode_config;
3112         struct drm_connector *connector;
3113         int i;
3114
3115         for (i = 1; i < HPD_NUM_PINS; i++) {
3116                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3117                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3118         }
3119         list_for_each_entry(connector, &mode_config->connector_list, head) {
3120                 struct intel_connector *intel_connector = to_intel_connector(connector);
3121                 connector->polled = intel_connector->polled;
3122                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3123                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3124         }
3125         if (dev_priv->display.hpd_irq_setup)
3126                 dev_priv->display.hpd_irq_setup(dev);
3127 }