2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/rv515d.h 254885 2013-08-25 19:37:15Z dumbbell $
36 #define PCIE_INDEX 0x0030
37 #define PCIE_DATA 0x0034
38 #define MC_IND_INDEX 0x0070
39 #define MC_IND_WR_EN (1 << 24)
40 #define MC_IND_DATA 0x0074
41 #define RBBM_SOFT_RESET 0x00F0
42 #define CONFIG_MEMSIZE 0x00F8
43 #define HDP_FB_LOCATION 0x0134
44 #define CP_CSQ_CNTL 0x0740
45 #define CP_CSQ_MODE 0x0744
46 #define CP_CSQ_ADDR 0x07F0
47 #define CP_CSQ_DATA 0x07F4
48 #define CP_CSQ_STAT 0x07F8
49 #define CP_CSQ2_STAT 0x07FC
50 #define RBBM_STATUS 0x0E40
51 #define DST_PIPE_CONFIG 0x170C
52 #define WAIT_UNTIL 0x1720
53 #define WAIT_2D_IDLE (1 << 14)
54 #define WAIT_3D_IDLE (1 << 15)
55 #define WAIT_2D_IDLECLEAN (1 << 16)
56 #define WAIT_3D_IDLECLEAN (1 << 17)
57 #define ISYNC_CNTL 0x1724
58 #define ISYNC_ANY2D_IDLE3D (1 << 0)
59 #define ISYNC_ANY3D_IDLE2D (1 << 1)
60 #define ISYNC_TRIG2D_IDLE3D (1 << 2)
61 #define ISYNC_TRIG3D_IDLE2D (1 << 3)
62 #define ISYNC_WAIT_IDLEGUI (1 << 4)
63 #define ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
64 #define VAP_INDEX_OFFSET 0x208C
65 #define VAP_PVS_STATE_FLUSH_REG 0x2284
66 #define GB_ENABLE 0x4008
67 #define GB_MSPOS0 0x4010
71 #define MS_Y1_SHIFT 12
72 #define MS_X2_SHIFT 16
73 #define MS_Y2_SHIFT 20
74 #define MSBD0_Y_SHIFT 24
75 #define MSBD0_X_SHIFT 28
76 #define GB_MSPOS1 0x4014
80 #define MS_Y4_SHIFT 12
81 #define MS_X5_SHIFT 16
82 #define MS_Y5_SHIFT 20
83 #define MSBD1_SHIFT 24
84 #define GB_TILE_CONFIG 0x4018
85 #define ENABLE_TILING (1 << 0)
86 #define PIPE_COUNT_MASK 0x0000000E
87 #define PIPE_COUNT_SHIFT 1
88 #define TILE_SIZE_8 (0 << 4)
89 #define TILE_SIZE_16 (1 << 4)
90 #define TILE_SIZE_32 (2 << 4)
91 #define SUBPIXEL_1_12 (0 << 16)
92 #define SUBPIXEL_1_16 (1 << 16)
93 #define GB_SELECT 0x401C
94 #define GB_AA_CONFIG 0x4020
95 #define GB_PIPE_SELECT 0x402C
96 #define GA_ENHANCE 0x4274
97 #define GA_DEADLOCK_CNTL (1 << 0)
98 #define GA_FASTSYNC_CNTL (1 << 1)
99 #define GA_POLY_MODE 0x4288
100 #define FRONT_PTYPE_POINT (0 << 4)
101 #define FRONT_PTYPE_LINE (1 << 4)
102 #define FRONT_PTYPE_TRIANGE (2 << 4)
103 #define BACK_PTYPE_POINT (0 << 7)
104 #define BACK_PTYPE_LINE (1 << 7)
105 #define BACK_PTYPE_TRIANGE (2 << 7)
106 #define GA_ROUND_MODE 0x428C
107 #define GEOMETRY_ROUND_TRUNC (0 << 0)
108 #define GEOMETRY_ROUND_NEAREST (1 << 0)
109 #define COLOR_ROUND_TRUNC (0 << 2)
110 #define COLOR_ROUND_NEAREST (1 << 2)
111 #define SU_REG_DEST 0x42C8
112 #define RB3D_DSTCACHE_CTLSTAT 0x4E4C
113 #define RB3D_DC_FLUSH (2 << 0)
114 #define RB3D_DC_FREE (2 << 2)
115 #define RB3D_DC_FINISH (1 << 4)
116 #define ZB_ZCACHE_CTLSTAT 0x4F18
117 #define ZC_FLUSH (1 << 0)
118 #define ZC_FREE (1 << 1)
119 #define DC_LB_MEMORY_SPLIT 0x6520
120 #define DC_LB_MEMORY_SPLIT_MASK 0x00000003
121 #define DC_LB_MEMORY_SPLIT_SHIFT 0
122 #define DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
123 #define DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
124 #define DC_LB_MEMORY_SPLIT_D1_ONLY 2
125 #define DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
126 #define DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
127 #define DC_LB_DISP1_END_ADR_SHIFT 4
128 #define DC_LB_DISP1_END_ADR_MASK 0x00007FF0
129 #define D1MODE_PRIORITY_A_CNT 0x6548
130 #define MODE_PRIORITY_MARK_MASK 0x00007FFF
131 #define MODE_PRIORITY_OFF (1 << 16)
132 #define MODE_PRIORITY_ALWAYS_ON (1 << 20)
133 #define MODE_PRIORITY_FORCE_MASK (1 << 24)
134 #define D1MODE_PRIORITY_B_CNT 0x654C
135 #define LB_MAX_REQ_OUTSTANDING 0x6D58
136 #define LB_D1_MAX_REQ_OUTSTANDING_MASK 0x0000000F
137 #define LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0
138 #define LB_D2_MAX_REQ_OUTSTANDING_MASK 0x000F0000
139 #define LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16
140 #define D2MODE_PRIORITY_A_CNT 0x6D48
141 #define D2MODE_PRIORITY_B_CNT 0x6D4C
143 /* ix[MC] registers */
144 #define MC_FB_LOCATION 0x01
145 #define MC_FB_START_MASK 0x0000FFFF
146 #define MC_FB_START_SHIFT 0
147 #define MC_FB_TOP_MASK 0xFFFF0000
148 #define MC_FB_TOP_SHIFT 16
149 #define MC_AGP_LOCATION 0x02
150 #define MC_AGP_START_MASK 0x0000FFFF
151 #define MC_AGP_START_SHIFT 0
152 #define MC_AGP_TOP_MASK 0xFFFF0000
153 #define MC_AGP_TOP_SHIFT 16
154 #define MC_AGP_BASE 0x03
155 #define MC_AGP_BASE_2 0x04
157 #define MEM_NUM_CHANNELS_MASK 0x00000003
158 #define MC_STATUS 0x08
159 #define MC_STATUS_IDLE (1 << 4)
160 #define MC_MISC_LAT_TIMER 0x09
161 #define MC_CPR_INIT_LAT_MASK 0x0000000F
162 #define MC_VF_INIT_LAT_MASK 0x000000F0
163 #define MC_DISP0R_INIT_LAT_MASK 0x00000F00
164 #define MC_DISP0R_INIT_LAT_SHIFT 8
165 #define MC_DISP1R_INIT_LAT_MASK 0x0000F000
166 #define MC_DISP1R_INIT_LAT_SHIFT 12
167 #define MC_FIXED_INIT_LAT_MASK 0x000F0000
168 #define MC_E2R_INIT_LAT_MASK 0x00F00000
169 #define SAME_PAGE_PRIO_MASK 0x0F000000
170 #define MC_GLOBW_INIT_LAT_MASK 0xF0000000
176 #define CP_PACKET0 0x00000000
177 #define PACKET0_BASE_INDEX_SHIFT 0
178 #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)
179 #define PACKET0_COUNT_SHIFT 16
180 #define PACKET0_COUNT_MASK (0x3fff << 16)
181 #define CP_PACKET1 0x40000000
182 #define CP_PACKET2 0x80000000
183 #define PACKET2_PAD_SHIFT 0
184 #define PACKET2_PAD_MASK (0x3fffffff << 0)
185 #define CP_PACKET3 0xC0000000
186 #define PACKET3_IT_OPCODE_SHIFT 8
187 #define PACKET3_IT_OPCODE_MASK (0xff << 8)
188 #define PACKET3_COUNT_SHIFT 16
189 #define PACKET3_COUNT_MASK (0x3fff << 16)
190 /* PACKET3 op code */
191 #define PACKET3_NOP 0x10
192 #define PACKET3_3D_DRAW_VBUF 0x28
193 #define PACKET3_3D_DRAW_IMMD 0x29
194 #define PACKET3_3D_DRAW_INDX 0x2A
195 #define PACKET3_3D_LOAD_VBPNTR 0x2F
196 #define PACKET3_INDX_BUFFER 0x33
197 #define PACKET3_3D_DRAW_VBUF_2 0x34
198 #define PACKET3_3D_DRAW_IMMD_2 0x35
199 #define PACKET3_3D_DRAW_INDX_2 0x36
200 #define PACKET3_BITBLT_MULTI 0x9B
202 #define PACKET0(reg, n) (CP_PACKET0 | \
203 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
204 REG_SET(PACKET0_COUNT, (n)))
205 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
206 #define PACKET3(op, n) (CP_PACKET3 | \
207 REG_SET(PACKET3_IT_OPCODE, (op)) | \
208 REG_SET(PACKET3_COUNT, (n)))
210 #define PACKET_TYPE0 0
211 #define PACKET_TYPE1 1
212 #define PACKET_TYPE2 2
213 #define PACKET_TYPE3 3
215 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
216 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
217 #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
218 #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
219 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
222 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0
223 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
224 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)
225 #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE
226 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)
227 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)
228 #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD
229 #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2)
230 #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1)
231 #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB
232 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)
233 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)
234 #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7
235 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)
236 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)
237 #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF
238 #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5)
239 #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1)
240 #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF
241 #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6)
242 #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1)
243 #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF
244 #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7)
245 #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1)
246 #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F
247 #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8)
248 #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1)
249 #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF
250 #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9)
251 #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1)
252 #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF
253 #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10)
254 #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1)
255 #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF
256 #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11)
257 #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1)
258 #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF
259 #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12)
260 #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1)
261 #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF
262 #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13)
263 #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1)
264 #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF
265 #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14)
266 #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1)
267 #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF
268 #define R_0000F8_CONFIG_MEMSIZE 0x0000F8
269 #define S_0000F8_CONFIG_MEMSIZE(x) (((x) & 0xFFFFFFFF) << 0)
270 #define G_0000F8_CONFIG_MEMSIZE(x) (((x) >> 0) & 0xFFFFFFFF)
271 #define C_0000F8_CONFIG_MEMSIZE 0x00000000
272 #define R_000134_HDP_FB_LOCATION 0x000134
273 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0)
274 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF)
275 #define C_000134_HDP_FB_START 0xFFFF0000
276 #define R_000300_VGA_RENDER_CONTROL 0x000300
277 #define S_000300_VGA_BLINK_RATE(x) (((x) & 0x1F) << 0)
278 #define G_000300_VGA_BLINK_RATE(x) (((x) >> 0) & 0x1F)
279 #define C_000300_VGA_BLINK_RATE 0xFFFFFFE0
280 #define S_000300_VGA_BLINK_MODE(x) (((x) & 0x3) << 5)
281 #define G_000300_VGA_BLINK_MODE(x) (((x) >> 5) & 0x3)
282 #define C_000300_VGA_BLINK_MODE 0xFFFFFF9F
283 #define S_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) & 0x1) << 7)
284 #define G_000300_VGA_CURSOR_BLINK_INVERT(x) (((x) >> 7) & 0x1)
285 #define C_000300_VGA_CURSOR_BLINK_INVERT 0xFFFFFF7F
286 #define S_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) & 0x1) << 8)
287 #define G_000300_VGA_EXTD_ADDR_COUNT_ENABLE(x) (((x) >> 8) & 0x1)
288 #define C_000300_VGA_EXTD_ADDR_COUNT_ENABLE 0xFFFFFEFF
289 #define S_000300_VGA_VSTATUS_CNTL(x) (((x) & 0x3) << 16)
290 #define G_000300_VGA_VSTATUS_CNTL(x) (((x) >> 16) & 0x3)
291 #define C_000300_VGA_VSTATUS_CNTL 0xFFFCFFFF
292 #define S_000300_VGA_LOCK_8DOT(x) (((x) & 0x1) << 24)
293 #define G_000300_VGA_LOCK_8DOT(x) (((x) >> 24) & 0x1)
294 #define C_000300_VGA_LOCK_8DOT 0xFEFFFFFF
295 #define S_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) & 0x1) << 25)
296 #define G_000300_VGAREG_LINECMP_COMPATIBILITY_SEL(x) (((x) >> 25) & 0x1)
297 #define C_000300_VGAREG_LINECMP_COMPATIBILITY_SEL 0xFDFFFFFF
298 #define R_000310_VGA_MEMORY_BASE_ADDRESS 0x000310
299 #define S_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
300 #define G_000310_VGA_MEMORY_BASE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
301 #define C_000310_VGA_MEMORY_BASE_ADDRESS 0x00000000
302 #define R_000328_VGA_HDP_CONTROL 0x000328
303 #define S_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) & 0x1) << 0)
304 #define G_000328_VGA_MEM_PAGE_SELECT_EN(x) (((x) >> 0) & 0x1)
305 #define C_000328_VGA_MEM_PAGE_SELECT_EN 0xFFFFFFFE
306 #define S_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) & 0x1) << 8)
307 #define G_000328_VGA_RBBM_LOCK_DISABLE(x) (((x) >> 8) & 0x1)
308 #define C_000328_VGA_RBBM_LOCK_DISABLE 0xFFFFFEFF
309 #define S_000328_VGA_SOFT_RESET(x) (((x) & 0x1) << 16)
310 #define G_000328_VGA_SOFT_RESET(x) (((x) >> 16) & 0x1)
311 #define C_000328_VGA_SOFT_RESET 0xFFFEFFFF
312 #define S_000328_VGA_TEST_RESET_CONTROL(x) (((x) & 0x1) << 24)
313 #define G_000328_VGA_TEST_RESET_CONTROL(x) (((x) >> 24) & 0x1)
314 #define C_000328_VGA_TEST_RESET_CONTROL 0xFEFFFFFF
315 #define R_000330_D1VGA_CONTROL 0x000330
316 #define S_000330_D1VGA_MODE_ENABLE(x) (((x) & 0x1) << 0)
317 #define G_000330_D1VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1)
318 #define C_000330_D1VGA_MODE_ENABLE 0xFFFFFFFE
319 #define S_000330_D1VGA_TIMING_SELECT(x) (((x) & 0x1) << 8)
320 #define G_000330_D1VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1)
321 #define C_000330_D1VGA_TIMING_SELECT 0xFFFFFEFF
322 #define S_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9)
323 #define G_000330_D1VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1)
324 #define C_000330_D1VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF
325 #define S_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10)
326 #define G_000330_D1VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1)
327 #define C_000330_D1VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF
328 #define S_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16)
329 #define G_000330_D1VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1)
330 #define C_000330_D1VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF
331 #define S_000330_D1VGA_ROTATE(x) (((x) & 0x3) << 24)
332 #define G_000330_D1VGA_ROTATE(x) (((x) >> 24) & 0x3)
333 #define C_000330_D1VGA_ROTATE 0xFCFFFFFF
334 #define R_000338_D2VGA_CONTROL 0x000338
335 #define S_000338_D2VGA_MODE_ENABLE(x) (((x) & 0x1) << 0)
336 #define G_000338_D2VGA_MODE_ENABLE(x) (((x) >> 0) & 0x1)
337 #define C_000338_D2VGA_MODE_ENABLE 0xFFFFFFFE
338 #define S_000338_D2VGA_TIMING_SELECT(x) (((x) & 0x1) << 8)
339 #define G_000338_D2VGA_TIMING_SELECT(x) (((x) >> 8) & 0x1)
340 #define C_000338_D2VGA_TIMING_SELECT 0xFFFFFEFF
341 #define S_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) & 0x1) << 9)
342 #define G_000338_D2VGA_SYNC_POLARITY_SELECT(x) (((x) >> 9) & 0x1)
343 #define C_000338_D2VGA_SYNC_POLARITY_SELECT 0xFFFFFDFF
344 #define S_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) & 0x1) << 10)
345 #define G_000338_D2VGA_OVERSCAN_TIMING_SELECT(x) (((x) >> 10) & 0x1)
346 #define C_000338_D2VGA_OVERSCAN_TIMING_SELECT 0xFFFFFBFF
347 #define S_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) & 0x1) << 16)
348 #define G_000338_D2VGA_OVERSCAN_COLOR_EN(x) (((x) >> 16) & 0x1)
349 #define C_000338_D2VGA_OVERSCAN_COLOR_EN 0xFFFEFFFF
350 #define S_000338_D2VGA_ROTATE(x) (((x) & 0x3) << 24)
351 #define G_000338_D2VGA_ROTATE(x) (((x) >> 24) & 0x3)
352 #define C_000338_D2VGA_ROTATE 0xFCFFFFFF
353 #define R_0007C0_CP_STAT 0x0007C0
354 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
355 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
356 #define C_0007C0_MRU_BUSY 0xFFFFFFFE
357 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
358 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
359 #define C_0007C0_MWU_BUSY 0xFFFFFFFD
360 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
361 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
362 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB
363 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
364 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
365 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7
366 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
367 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
368 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
369 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
370 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
371 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
372 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
373 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
374 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
375 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
376 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
377 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
378 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
379 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
380 #define C_0007C0_CSI_BUSY 0xFFFFDFFF
381 #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
382 #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
383 #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
384 #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
385 #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
386 #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
387 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
388 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
389 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
390 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
391 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
392 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
393 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
394 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
395 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
396 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
397 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
398 #define C_0007C0_CP_BUSY 0x7FFFFFFF
399 #define R_000E40_RBBM_STATUS 0x000E40
400 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
401 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
402 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
403 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
404 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
405 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
406 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
407 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
408 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
409 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
410 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
411 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
412 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
413 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
414 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
415 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
416 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
417 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
418 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
419 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
420 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
421 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
422 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
423 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
424 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
425 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
426 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
427 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
428 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
429 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
430 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
431 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
432 #define C_000E40_E2_BUSY 0xFFFDFFFF
433 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
434 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
435 #define C_000E40_RB2D_BUSY 0xFFFBFFFF
436 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
437 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
438 #define C_000E40_RB3D_BUSY 0xFFF7FFFF
439 #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
440 #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
441 #define C_000E40_VAP_BUSY 0xFFEFFFFF
442 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
443 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
444 #define C_000E40_RE_BUSY 0xFFDFFFFF
445 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
446 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
447 #define C_000E40_TAM_BUSY 0xFFBFFFFF
448 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
449 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
450 #define C_000E40_TDM_BUSY 0xFF7FFFFF
451 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
452 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
453 #define C_000E40_PB_BUSY 0xFEFFFFFF
454 #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
455 #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
456 #define C_000E40_TIM_BUSY 0xFDFFFFFF
457 #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
458 #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
459 #define C_000E40_GA_BUSY 0xFBFFFFFF
460 #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
461 #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
462 #define C_000E40_CBA2D_BUSY 0xF7FFFFFF
463 #define S_000E40_RBBM_HIBUSY(x) (((x) & 0x1) << 28)
464 #define G_000E40_RBBM_HIBUSY(x) (((x) >> 28) & 0x1)
465 #define C_000E40_RBBM_HIBUSY 0xEFFFFFFF
466 #define S_000E40_SKID_CFBUSY(x) (((x) & 0x1) << 29)
467 #define G_000E40_SKID_CFBUSY(x) (((x) >> 29) & 0x1)
468 #define C_000E40_SKID_CFBUSY 0xDFFFFFFF
469 #define S_000E40_VAP_VF_BUSY(x) (((x) & 0x1) << 30)
470 #define G_000E40_VAP_VF_BUSY(x) (((x) >> 30) & 0x1)
471 #define C_000E40_VAP_VF_BUSY 0xBFFFFFFF
472 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
473 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
474 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF
475 #define R_006080_D1CRTC_CONTROL 0x006080
476 #define S_006080_D1CRTC_MASTER_EN(x) (((x) & 0x1) << 0)
477 #define G_006080_D1CRTC_MASTER_EN(x) (((x) >> 0) & 0x1)
478 #define C_006080_D1CRTC_MASTER_EN 0xFFFFFFFE
479 #define S_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4)
480 #define G_006080_D1CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1)
481 #define C_006080_D1CRTC_SYNC_RESET_SEL 0xFFFFFFEF
482 #define S_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8)
483 #define G_006080_D1CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3)
484 #define C_006080_D1CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF
485 #define S_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16)
486 #define G_006080_D1CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1)
487 #define C_006080_D1CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF
488 #define S_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
489 #define G_006080_D1CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
490 #define C_006080_D1CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF
491 #define R_0060E8_D1CRTC_UPDATE_LOCK 0x0060E8
492 #define S_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0)
493 #define G_0060E8_D1CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1)
494 #define C_0060E8_D1CRTC_UPDATE_LOCK 0xFFFFFFFE
495 #define R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x006110
496 #define S_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
497 #define G_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
498 #define C_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000
499 #define R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x006118
500 #define S_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
501 #define G_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
502 #define C_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000
503 #define R_006880_D2CRTC_CONTROL 0x006880
504 #define S_006880_D2CRTC_MASTER_EN(x) (((x) & 0x1) << 0)
505 #define G_006880_D2CRTC_MASTER_EN(x) (((x) >> 0) & 0x1)
506 #define C_006880_D2CRTC_MASTER_EN 0xFFFFFFFE
507 #define S_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) & 0x1) << 4)
508 #define G_006880_D2CRTC_SYNC_RESET_SEL(x) (((x) >> 4) & 0x1)
509 #define C_006880_D2CRTC_SYNC_RESET_SEL 0xFFFFFFEF
510 #define S_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) & 0x3) << 8)
511 #define G_006880_D2CRTC_DISABLE_POINT_CNTL(x) (((x) >> 8) & 0x3)
512 #define C_006880_D2CRTC_DISABLE_POINT_CNTL 0xFFFFFCFF
513 #define S_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) & 0x1) << 16)
514 #define G_006880_D2CRTC_CURRENT_MASTER_EN_STATE(x) (((x) >> 16) & 0x1)
515 #define C_006880_D2CRTC_CURRENT_MASTER_EN_STATE 0xFFFEFFFF
516 #define S_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) & 0x1) << 24)
517 #define G_006880_D2CRTC_DISP_READ_REQUEST_DISABLE(x) (((x) >> 24) & 0x1)
518 #define C_006880_D2CRTC_DISP_READ_REQUEST_DISABLE 0xFEFFFFFF
519 #define R_0068E8_D2CRTC_UPDATE_LOCK 0x0068E8
520 #define S_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) & 0x1) << 0)
521 #define G_0068E8_D2CRTC_UPDATE_LOCK(x) (((x) >> 0) & 0x1)
522 #define C_0068E8_D2CRTC_UPDATE_LOCK 0xFFFFFFFE
523 #define R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x006910
524 #define S_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
525 #define G_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
526 #define C_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x00000000
527 #define R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x006918
528 #define S_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) & 0xFFFFFFFF) << 0)
529 #define G_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS(x) (((x) >> 0) & 0xFFFFFFFF)
530 #define C_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x00000000
533 #define R_000001_MC_FB_LOCATION 0x000001
534 #define S_000001_MC_FB_START(x) (((x) & 0xFFFF) << 0)
535 #define G_000001_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
536 #define C_000001_MC_FB_START 0xFFFF0000
537 #define S_000001_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
538 #define G_000001_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
539 #define C_000001_MC_FB_TOP 0x0000FFFF
540 #define R_000002_MC_AGP_LOCATION 0x000002
541 #define S_000002_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
542 #define G_000002_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
543 #define C_000002_MC_AGP_START 0xFFFF0000
544 #define S_000002_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
545 #define G_000002_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
546 #define C_000002_MC_AGP_TOP 0x0000FFFF
547 #define R_000003_MC_AGP_BASE 0x000003
548 #define S_000003_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
549 #define G_000003_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
550 #define C_000003_AGP_BASE_ADDR 0x00000000
551 #define R_000004_MC_AGP_BASE_2 0x000004
552 #define S_000004_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
553 #define G_000004_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
554 #define C_000004_AGP_BASE_ADDR_2 0xFFFFFFF0
557 #define R_00000F_CP_DYN_CNTL 0x00000F
558 #define S_00000F_CP_FORCEON(x) (((x) & 0x1) << 0)
559 #define G_00000F_CP_FORCEON(x) (((x) >> 0) & 0x1)
560 #define C_00000F_CP_FORCEON 0xFFFFFFFE
561 #define S_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
562 #define G_00000F_CP_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
563 #define C_00000F_CP_MAX_DYN_STOP_LAT 0xFFFFFFFD
564 #define S_00000F_CP_CLOCK_STATUS(x) (((x) & 0x1) << 2)
565 #define G_00000F_CP_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
566 #define C_00000F_CP_CLOCK_STATUS 0xFFFFFFFB
567 #define S_00000F_CP_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
568 #define G_00000F_CP_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
569 #define C_00000F_CP_PROG_SHUTOFF 0xFFFFFFF7
570 #define S_00000F_CP_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
571 #define G_00000F_CP_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
572 #define C_00000F_CP_PROG_DELAY_VALUE 0xFFFFF00F
573 #define S_00000F_CP_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
574 #define G_00000F_CP_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
575 #define C_00000F_CP_LOWER_POWER_IDLE 0xFFF00FFF
576 #define S_00000F_CP_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
577 #define G_00000F_CP_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
578 #define C_00000F_CP_LOWER_POWER_IGNORE 0xFFEFFFFF
579 #define S_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
580 #define G_00000F_CP_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
581 #define C_00000F_CP_NORMAL_POWER_IGNORE 0xFFDFFFFF
582 #define S_00000F_SPARE(x) (((x) & 0x3) << 22)
583 #define G_00000F_SPARE(x) (((x) >> 22) & 0x3)
584 #define C_00000F_SPARE 0xFF3FFFFF
585 #define S_00000F_CP_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
586 #define G_00000F_CP_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
587 #define C_00000F_CP_NORMAL_POWER_BUSY 0x00FFFFFF
588 #define R_000011_E2_DYN_CNTL 0x000011
589 #define S_000011_E2_FORCEON(x) (((x) & 0x1) << 0)
590 #define G_000011_E2_FORCEON(x) (((x) >> 0) & 0x1)
591 #define C_000011_E2_FORCEON 0xFFFFFFFE
592 #define S_000011_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
593 #define G_000011_E2_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
594 #define C_000011_E2_MAX_DYN_STOP_LAT 0xFFFFFFFD
595 #define S_000011_E2_CLOCK_STATUS(x) (((x) & 0x1) << 2)
596 #define G_000011_E2_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
597 #define C_000011_E2_CLOCK_STATUS 0xFFFFFFFB
598 #define S_000011_E2_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
599 #define G_000011_E2_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
600 #define C_000011_E2_PROG_SHUTOFF 0xFFFFFFF7
601 #define S_000011_E2_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
602 #define G_000011_E2_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
603 #define C_000011_E2_PROG_DELAY_VALUE 0xFFFFF00F
604 #define S_000011_E2_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
605 #define G_000011_E2_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
606 #define C_000011_E2_LOWER_POWER_IDLE 0xFFF00FFF
607 #define S_000011_E2_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
608 #define G_000011_E2_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
609 #define C_000011_E2_LOWER_POWER_IGNORE 0xFFEFFFFF
610 #define S_000011_E2_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
611 #define G_000011_E2_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
612 #define C_000011_E2_NORMAL_POWER_IGNORE 0xFFDFFFFF
613 #define S_000011_SPARE(x) (((x) & 0x3) << 22)
614 #define G_000011_SPARE(x) (((x) >> 22) & 0x3)
615 #define C_000011_SPARE 0xFF3FFFFF
616 #define S_000011_E2_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
617 #define G_000011_E2_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
618 #define C_000011_E2_NORMAL_POWER_BUSY 0x00FFFFFF
619 #define R_000013_IDCT_DYN_CNTL 0x000013
620 #define S_000013_IDCT_FORCEON(x) (((x) & 0x1) << 0)
621 #define G_000013_IDCT_FORCEON(x) (((x) >> 0) & 0x1)
622 #define C_000013_IDCT_FORCEON 0xFFFFFFFE
623 #define S_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 1)
624 #define G_000013_IDCT_MAX_DYN_STOP_LAT(x) (((x) >> 1) & 0x1)
625 #define C_000013_IDCT_MAX_DYN_STOP_LAT 0xFFFFFFFD
626 #define S_000013_IDCT_CLOCK_STATUS(x) (((x) & 0x1) << 2)
627 #define G_000013_IDCT_CLOCK_STATUS(x) (((x) >> 2) & 0x1)
628 #define C_000013_IDCT_CLOCK_STATUS 0xFFFFFFFB
629 #define S_000013_IDCT_PROG_SHUTOFF(x) (((x) & 0x1) << 3)
630 #define G_000013_IDCT_PROG_SHUTOFF(x) (((x) >> 3) & 0x1)
631 #define C_000013_IDCT_PROG_SHUTOFF 0xFFFFFFF7
632 #define S_000013_IDCT_PROG_DELAY_VALUE(x) (((x) & 0xFF) << 4)
633 #define G_000013_IDCT_PROG_DELAY_VALUE(x) (((x) >> 4) & 0xFF)
634 #define C_000013_IDCT_PROG_DELAY_VALUE 0xFFFFF00F
635 #define S_000013_IDCT_LOWER_POWER_IDLE(x) (((x) & 0xFF) << 12)
636 #define G_000013_IDCT_LOWER_POWER_IDLE(x) (((x) >> 12) & 0xFF)
637 #define C_000013_IDCT_LOWER_POWER_IDLE 0xFFF00FFF
638 #define S_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) & 0x1) << 20)
639 #define G_000013_IDCT_LOWER_POWER_IGNORE(x) (((x) >> 20) & 0x1)
640 #define C_000013_IDCT_LOWER_POWER_IGNORE 0xFFEFFFFF
641 #define S_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) & 0x1) << 21)
642 #define G_000013_IDCT_NORMAL_POWER_IGNORE(x) (((x) >> 21) & 0x1)
643 #define C_000013_IDCT_NORMAL_POWER_IGNORE 0xFFDFFFFF
644 #define S_000013_SPARE(x) (((x) & 0x3) << 22)
645 #define G_000013_SPARE(x) (((x) >> 22) & 0x3)
646 #define C_000013_SPARE 0xFF3FFFFF
647 #define S_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) & 0xFF) << 24)
648 #define G_000013_IDCT_NORMAL_POWER_BUSY(x) (((x) >> 24) & 0xFF)
649 #define C_000013_IDCT_NORMAL_POWER_BUSY 0x00FFFFFF
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