2 * Copyright (c) 2006 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $NetBSD: rtw.c,v 1.72 2006/03/28 00:48:10 dyoung Exp $
38 * Copyright (c) 2004, 2005 David Young. All rights reserved.
40 * Programmed for NetBSD by David Young.
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
45 * 1. Redistributions of source code must retain the above copyright
46 * notice, this list of conditions and the following disclaimer.
47 * 2. Redistributions in binary form must reproduce the above copyright
48 * notice, this list of conditions and the following disclaimer in the
49 * documentation and/or other materials provided with the distribution.
50 * 3. The name of David Young may not be used to endorse or promote
51 * products derived from this software without specific prior
54 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
55 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
56 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
57 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
58 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
59 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
60 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
62 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
69 * Device driver for the Realtek RTL8180 802.11 MAC/BBP.
72 #include <sys/param.h>
73 #include <sys/bitops.h>
75 #include <sys/endian.h>
76 #include <sys/kernel.h>
77 #include <sys/interrupt.h>
79 #include <sys/socket.h>
80 #include <sys/sockio.h>
81 #include <sys/serialize.h>
82 #include <sys/sysctl.h>
85 #include <net/if_arp.h>
86 #include <net/if_dl.h>
87 #include <net/if_media.h>
88 #include <net/ifq_var.h>
89 #include <net/ethernet.h>
92 #include <netproto/802_11/ieee80211_var.h>
93 #include <netproto/802_11/ieee80211_radiotap.h>
94 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
96 #include <dev/netif/rtw/rtwreg.h>
97 #include <dev/netif/rtw/rtwvar.h>
98 #include <dev/netif/rtw/rtwphyio.h>
99 #include <dev/netif/rtw/rtwphy.h>
100 #include <dev/netif/rtw/smc93cx6var.h>
101 #include <dev/netif/rtw/sa2400reg.h>
104 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
105 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
106 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
107 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
108 #define IEEE80211_DUR_DS_SLOW_ACK 112
109 #define IEEE80211_DUR_DS_SLOW_CTS 112
110 #define IEEE80211_DUR_DS_SIFS 10
114 bus_dma_segment_t segs[RTW_MAXPKTSEGS];
117 devclass_t rtw_devclass;
119 static const struct ieee80211_rateset rtw_rates_11b = { 4, { 2, 4, 11, 22 } };
121 SYSCTL_NODE(_hw, OID_AUTO, rtw, CTLFLAG_RD, 0,
122 "Realtek RTL818x 802.11 controls");
124 /* [0, __SHIFTOUT(RTW_CONFIG4_RFTYPE_MASK, RTW_CONFIG4_RFTYPE_MASK)] */
125 static int rtw_rfprog_fallback = 0;
126 SYSCTL_INT(_hw_rtw, OID_AUTO, rfprog_fallback, CTLFLAG_RW,
127 &rtw_rfprog_fallback, 0, "fallback RF programming method");
129 static int rtw_host_rfio = 0; /* 0/1 */
130 SYSCTL_INT(_hw_rtw, OID_AUTO, host_rfio, CTLFLAG_RW,
131 &rtw_host_rfio, 0, "enable host control of RF I/O");
134 int rtw_debug = 0; /* [0, RTW_DEBUG_MAX] */
135 SYSCTL_INT(_hw_rtw, OID_AUTO, debug, CTLFLAG_RW, &rtw_debug, 0, "debug level");
137 static int rtw_rxbufs_limit = RTW_RXQLEN; /* [0, RTW_RXQLEN] */
138 SYSCTL_INT(_hw_rtw, OID_AUTO, rxbufs_limit, CTLFLAG_RW, &rtw_rxbufs_limit, 0,
140 #endif /* RTW_DEBUG */
143 static int rtw_xmtr_restart = 0;
144 SYSCTL_INT(_hw_rtw, OID_AUTO, xmtr_restart, CTLFLAG_RW, &rtw_xmtr_restart, 0,
145 "gratuitously reset xmtr on rcvr error");
147 static int rtw_ring_reset = 0;
148 SYSCTL_INT(_hw_rtw, OID_AUTO, ring_reset, CTLFLAG_RW, &rtw_ring_reset, 0,
149 "reset ring pointers on rcvr error");
152 static int rtw_do_chip_reset = 0;
153 SYSCTL_INT(_hw_rtw, OID_AUTO, chip_reset, CTLFLAG_RW, &rtw_do_chip_reset, 0,
154 "gratuitously reset chip on rcvr error");
156 int rtw_dwelltime = 200; /* milliseconds */
159 static struct ieee80211_cipher rtw_cipher_wep;
161 static void rtw_led_init(struct rtw_softc *);
162 static void rtw_led_newstate(struct rtw_softc *, enum ieee80211_state);
163 static void rtw_led_slowblink(void *);
164 static void rtw_led_fastblink(void *);
165 static void rtw_led_set(struct rtw_softc *);
167 static void rtw_init(void *);
168 static void rtw_start(struct ifnet *);
169 static int rtw_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
170 static void rtw_watchdog(struct ifnet *);
171 static void rtw_intr(void *);
173 static void rtw_intr_rx(struct rtw_softc *, uint16_t);
174 static void rtw_intr_tx(struct rtw_softc *, uint16_t);
175 static void rtw_intr_beacon(struct rtw_softc *, uint16_t);
176 static void rtw_intr_atim(struct rtw_softc *);
177 static void rtw_intr_ioerror(struct rtw_softc *, uint16_t);
178 static void rtw_intr_timeout(struct rtw_softc *);
180 static int rtw_dequeue(struct ifnet *, struct rtw_txsoft_blk **,
181 struct rtw_txdesc_blk **, struct mbuf **,
182 struct ieee80211_node **);
183 static struct mbuf *rtw_load_txbuf(struct rtw_softc *, struct rtw_txsoft *,
184 struct rtw_txsegs *, int, struct mbuf *);
186 static void rtw_idle(struct rtw_softc *);
187 static void rtw_txring_fixup(struct rtw_softc *);
188 static void rtw_rxring_fixup(struct rtw_softc *);
189 static int rtw_txring_next(struct rtw_regs *, struct rtw_txdesc_blk *);
190 static void rtw_reset_oactive(struct rtw_softc *);
192 static int rtw_enable(struct rtw_softc *);
193 static void rtw_disable(struct rtw_softc *);
194 static void rtw_io_enable(struct rtw_softc *, uint8_t, int);
195 static int rtw_pwrstate(struct rtw_softc *, enum rtw_pwrstate);
196 static void rtw_set_access(struct rtw_softc *, enum rtw_access);
198 static void rtw_continuous_tx_enable(struct rtw_softc *, int);
199 static void rtw_txdac_enable(struct rtw_softc *, int);
200 static void rtw_anaparm_enable(struct rtw_regs *, int);
201 static void rtw_config0123_enable(struct rtw_regs *, int);
203 static void rtw_transmit_config(struct rtw_regs *);
204 static void rtw_set_rfprog(struct rtw_softc *);
205 static void rtw_enable_interrupts(struct rtw_softc *);
206 static void rtw_pktfilt_load(struct rtw_softc *);
207 static void rtw_wep_setkeys(struct rtw_softc *);
208 static void rtw_resume_ticks(struct rtw_softc *);
209 static void rtw_set_nettype(struct rtw_softc *, enum ieee80211_opmode);
211 static int rtw_reset(struct rtw_softc *);
212 static int rtw_chip_reset(struct rtw_softc *);
213 static int rtw_recall_eeprom(struct rtw_softc *);
214 static int rtw_srom_read(struct rtw_softc *);
215 static int rtw_srom_parse(struct rtw_softc *);
216 static struct rtw_rf *rtw_rf_attach(struct rtw_softc *, enum rtw_rfchipid, int);
218 static uint8_t rtw_check_phydelay(struct rtw_regs *, uint32_t);
219 static void rtw_identify_country(struct rtw_softc *);
220 static int rtw_identify_sta(struct rtw_softc *);
222 static int rtw_swring_setup(struct rtw_softc *);
223 static void rtw_hwring_setup(struct rtw_softc *);
225 static int rtw_desc_blk_alloc(struct rtw_softc *);
226 static void rtw_desc_blk_free(struct rtw_softc *);
227 static int rtw_soft_blk_alloc(struct rtw_softc *);
228 static void rtw_soft_blk_free(struct rtw_softc *);
230 static void rtw_txdesc_blk_init_all(struct rtw_softc *);
231 static void rtw_txsoft_blk_init_all(struct rtw_softc *);
232 static void rtw_rxdesc_blk_init_all(struct rtw_softc *);
233 static int rtw_rxsoft_blk_init_all(struct rtw_softc *);
235 static void rtw_txdesc_blk_reset_all(struct rtw_softc *);
237 static int rtw_rxsoft_alloc(struct rtw_softc *, struct rtw_rxsoft *, int);
238 static void rtw_rxdesc_init(struct rtw_softc *, int idx, int);
241 static void rtw_print_txdesc(struct rtw_softc *, const char *,
242 struct rtw_txsoft *, struct rtw_txdesc_blk *,
244 #endif /* RTW_DEBUG */
246 static int rtw_newstate(struct ieee80211com *, enum ieee80211_state, int);
247 static void rtw_next_scan(void *);
249 static int rtw_key_delete(struct ieee80211com *,
250 const struct ieee80211_key *);
251 static int rtw_key_set(struct ieee80211com *,
252 const struct ieee80211_key *,
253 const u_int8_t[IEEE80211_ADDR_LEN]);
254 static void rtw_key_update_end(struct ieee80211com *);
255 static void rtw_key_update_begin(struct ieee80211com *);
256 static int rtw_wep_decap(struct ieee80211_key *, struct mbuf *, int);
258 static int rtw_compute_duration1(int, int, uint32_t, int,
259 struct rtw_duration *);
260 static int rtw_compute_duration(const struct ieee80211_frame_min *,
261 const struct ieee80211_key *, int,
263 struct rtw_duration *,
264 struct rtw_duration *, int *, int);
266 static int rtw_get_rssi(struct rtw_softc *, uint8_t, uint8_t);
267 static int rtw_maxim_getrssi(uint8_t, uint8_t);
268 static int rtw_gct_getrssi(uint8_t, uint8_t);
269 static int rtw_philips_getrssi(uint8_t, uint8_t);
271 static void *rtw_ratectl_attach(struct ieee80211com *, u_int);
275 rtw_print_regs(struct rtw_regs *regs, const char *dvname, const char *where)
277 #define PRINTREG32(sc, reg) \
278 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
279 ("%s: reg[ " #reg " / %03x ] = %08x\n", \
280 dvname, reg, RTW_READ(regs, reg)))
282 #define PRINTREG16(sc, reg) \
283 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
284 ("%s: reg[ " #reg " / %03x ] = %04x\n", \
285 dvname, reg, RTW_READ16(regs, reg)))
287 #define PRINTREG8(sc, reg) \
288 RTW_DPRINTF(RTW_DEBUG_REGDUMP, \
289 ("%s: reg[ " #reg " / %03x ] = %02x\n", \
290 dvname, reg, RTW_READ8(regs, reg)))
292 RTW_DPRINTF(RTW_DEBUG_REGDUMP, ("%s: %s\n", dvname, where));
294 PRINTREG32(regs, RTW_IDR0);
295 PRINTREG32(regs, RTW_IDR1);
296 PRINTREG32(regs, RTW_MAR0);
297 PRINTREG32(regs, RTW_MAR1);
298 PRINTREG32(regs, RTW_TSFTRL);
299 PRINTREG32(regs, RTW_TSFTRH);
300 PRINTREG32(regs, RTW_TLPDA);
301 PRINTREG32(regs, RTW_TNPDA);
302 PRINTREG32(regs, RTW_THPDA);
303 PRINTREG32(regs, RTW_TCR);
304 PRINTREG32(regs, RTW_RCR);
305 PRINTREG32(regs, RTW_TINT);
306 PRINTREG32(regs, RTW_TBDA);
307 PRINTREG32(regs, RTW_ANAPARM);
308 PRINTREG32(regs, RTW_BB);
309 PRINTREG32(regs, RTW_PHYCFG);
310 PRINTREG32(regs, RTW_WAKEUP0L);
311 PRINTREG32(regs, RTW_WAKEUP0H);
312 PRINTREG32(regs, RTW_WAKEUP1L);
313 PRINTREG32(regs, RTW_WAKEUP1H);
314 PRINTREG32(regs, RTW_WAKEUP2LL);
315 PRINTREG32(regs, RTW_WAKEUP2LH);
316 PRINTREG32(regs, RTW_WAKEUP2HL);
317 PRINTREG32(regs, RTW_WAKEUP2HH);
318 PRINTREG32(regs, RTW_WAKEUP3LL);
319 PRINTREG32(regs, RTW_WAKEUP3LH);
320 PRINTREG32(regs, RTW_WAKEUP3HL);
321 PRINTREG32(regs, RTW_WAKEUP3HH);
322 PRINTREG32(regs, RTW_WAKEUP4LL);
323 PRINTREG32(regs, RTW_WAKEUP4LH);
324 PRINTREG32(regs, RTW_WAKEUP4HL);
325 PRINTREG32(regs, RTW_WAKEUP4HH);
326 PRINTREG32(regs, RTW_DK0);
327 PRINTREG32(regs, RTW_DK1);
328 PRINTREG32(regs, RTW_DK2);
329 PRINTREG32(regs, RTW_DK3);
330 PRINTREG32(regs, RTW_RETRYCTR);
331 PRINTREG32(regs, RTW_RDSAR);
332 PRINTREG32(regs, RTW_FER);
333 PRINTREG32(regs, RTW_FEMR);
334 PRINTREG32(regs, RTW_FPSR);
335 PRINTREG32(regs, RTW_FFER);
337 /* 16-bit registers */
338 PRINTREG16(regs, RTW_BRSR);
339 PRINTREG16(regs, RTW_IMR);
340 PRINTREG16(regs, RTW_ISR);
341 PRINTREG16(regs, RTW_BCNITV);
342 PRINTREG16(regs, RTW_ATIMWND);
343 PRINTREG16(regs, RTW_BINTRITV);
344 PRINTREG16(regs, RTW_ATIMTRITV);
345 PRINTREG16(regs, RTW_CRC16ERR);
346 PRINTREG16(regs, RTW_CRC0);
347 PRINTREG16(regs, RTW_CRC1);
348 PRINTREG16(regs, RTW_CRC2);
349 PRINTREG16(regs, RTW_CRC3);
350 PRINTREG16(regs, RTW_CRC4);
351 PRINTREG16(regs, RTW_CWR);
353 /* 8-bit registers */
354 PRINTREG8(regs, RTW_CR);
355 PRINTREG8(regs, RTW_9346CR);
356 PRINTREG8(regs, RTW_CONFIG0);
357 PRINTREG8(regs, RTW_CONFIG1);
358 PRINTREG8(regs, RTW_CONFIG2);
359 PRINTREG8(regs, RTW_MSR);
360 PRINTREG8(regs, RTW_CONFIG3);
361 PRINTREG8(regs, RTW_CONFIG4);
362 PRINTREG8(regs, RTW_TESTR);
363 PRINTREG8(regs, RTW_PSR);
364 PRINTREG8(regs, RTW_SCR);
365 PRINTREG8(regs, RTW_PHYDELAY);
366 PRINTREG8(regs, RTW_CRCOUNT);
367 PRINTREG8(regs, RTW_PHYADDR);
368 PRINTREG8(regs, RTW_PHYDATAW);
369 PRINTREG8(regs, RTW_PHYDATAR);
370 PRINTREG8(regs, RTW_CONFIG5);
371 PRINTREG8(regs, RTW_TPPOLL);
373 PRINTREG16(regs, RTW_BSSID16);
374 PRINTREG32(regs, RTW_BSSID32);
379 #endif /* RTW_DEBUG */
382 rtw_continuous_tx_enable(struct rtw_softc *sc, int enable)
384 struct rtw_regs *regs = &sc->sc_regs;
387 tcr = RTW_READ(regs, RTW_TCR);
388 tcr &= ~RTW_TCR_LBK_MASK;
390 tcr |= RTW_TCR_LBK_CONT;
392 tcr |= RTW_TCR_LBK_NORMAL;
393 RTW_WRITE(regs, RTW_TCR, tcr);
394 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
395 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
396 rtw_txdac_enable(sc, !enable);
397 rtw_set_access(sc, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */
398 rtw_set_access(sc, RTW_ACCESS_NONE);
403 rtw_access_string(enum rtw_access access)
406 case RTW_ACCESS_NONE:
408 case RTW_ACCESS_CONFIG:
410 case RTW_ACCESS_ANAPARM:
416 #endif /* RTW_DEBUG */
419 rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)
421 KKASSERT(naccess >= RTW_ACCESS_NONE && naccess <= RTW_ACCESS_ANAPARM);
422 KKASSERT(regs->r_access >= RTW_ACCESS_NONE &&
423 regs->r_access <= RTW_ACCESS_ANAPARM);
425 if (naccess == regs->r_access)
429 case RTW_ACCESS_NONE:
430 switch (regs->r_access) {
431 case RTW_ACCESS_ANAPARM:
432 rtw_anaparm_enable(regs, 0);
434 case RTW_ACCESS_CONFIG:
435 rtw_config0123_enable(regs, 0);
437 case RTW_ACCESS_NONE:
441 case RTW_ACCESS_CONFIG:
442 switch (regs->r_access) {
443 case RTW_ACCESS_NONE:
444 rtw_config0123_enable(regs, 1);
446 case RTW_ACCESS_CONFIG:
448 case RTW_ACCESS_ANAPARM:
449 rtw_anaparm_enable(regs, 0);
453 case RTW_ACCESS_ANAPARM:
454 switch (regs->r_access) {
455 case RTW_ACCESS_NONE:
456 rtw_config0123_enable(regs, 1);
458 case RTW_ACCESS_CONFIG:
459 rtw_anaparm_enable(regs, 1);
461 case RTW_ACCESS_ANAPARM:
469 rtw_set_access(struct rtw_softc *sc, enum rtw_access access)
471 struct rtw_regs *regs = &sc->sc_regs;
473 rtw_set_access1(regs, access);
474 RTW_DPRINTF(RTW_DEBUG_ACCESS,
475 ("%s: access %s -> %s\n", sc->sc_ic.ic_if.if_xname,
476 rtw_access_string(regs->r_access),
477 rtw_access_string(access)));
478 regs->r_access = access;
482 * Enable registers, switch register banks.
485 rtw_config0123_enable(struct rtw_regs *regs, int enable)
489 ecr = RTW_READ8(regs, RTW_9346CR);
490 ecr &= ~(RTW_9346CR_EEM_MASK | RTW_9346CR_EECS | RTW_9346CR_EESK);
492 ecr |= RTW_9346CR_EEM_CONFIG;
494 RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));
495 ecr |= RTW_9346CR_EEM_NORMAL;
497 RTW_WRITE8(regs, RTW_9346CR, ecr);
498 RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);
501 /* requires rtw_config0123_enable(, 1) */
503 rtw_anaparm_enable(struct rtw_regs *regs, int enable)
507 cfg3 = RTW_READ8(regs, RTW_CONFIG3);
508 cfg3 |= RTW_CONFIG3_CLKRUNEN;
510 cfg3 |= RTW_CONFIG3_PARMEN;
512 cfg3 &= ~RTW_CONFIG3_PARMEN;
513 RTW_WRITE8(regs, RTW_CONFIG3, cfg3);
514 RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);
517 /* requires rtw_anaparm_enable(, 1) */
519 rtw_txdac_enable(struct rtw_softc *sc, int enable)
522 struct rtw_regs *regs = &sc->sc_regs;
524 anaparm = RTW_READ(regs, RTW_ANAPARM);
526 anaparm &= ~RTW_ANAPARM_TXDACOFF;
528 anaparm |= RTW_ANAPARM_TXDACOFF;
529 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
530 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
534 rtw_chip_reset1(struct rtw_softc *sc)
536 struct rtw_regs *regs = &sc->sc_regs;
540 RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);
542 RTW_WBR(regs, RTW_CR, RTW_CR);
544 for (i = 0; i < 1000; i++) {
545 if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) {
546 RTW_DPRINTF(RTW_DEBUG_RESET,
547 ("%s: reset in %dus\n",
548 sc->sc_ic.ic_if.if_xname, i));
551 RTW_RBR(regs, RTW_CR, RTW_CR);
552 DELAY(10); /* 10us */
555 if_printf(&sc->sc_ic.ic_if, "reset failed\n");
560 rtw_chip_reset(struct rtw_softc *sc)
562 struct rtw_regs *regs = &sc->sc_regs;
565 /* from Linux driver */
566 tcr = RTW_TCR_CWMIN | RTW_TCR_MXDMA_2048 |
567 __SHIFTIN(7, RTW_TCR_SRL_MASK) | __SHIFTIN(7, RTW_TCR_LRL_MASK);
569 RTW_WRITE(regs, RTW_TCR, tcr);
571 RTW_WBW(regs, RTW_CR, RTW_TCR);
573 return rtw_chip_reset1(sc);
577 rtw_wep_decap(struct ieee80211_key *k, struct mbuf *m, int hdrlen)
579 struct ieee80211_key keycopy;
580 const struct ieee80211_cipher *wep_cipher;
582 RTW_DPRINTF(RTW_DEBUG_KEY, ("%s:\n", __func__));
585 keycopy.wk_flags &= ~IEEE80211_KEY_SWCRYPT;
587 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
588 KKASSERT(wep_cipher != NULL);
590 return wep_cipher->ic_decap(&keycopy, m, hdrlen);
594 rtw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
596 struct rtw_softc *sc = ic->ic_ifp->if_softc;
597 u_int keyix = k->wk_keyix;
599 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: delete key %u\n", __func__, keyix));
601 if (keyix >= IEEE80211_WEP_NKID)
603 if (k->wk_keylen != 0)
604 sc->sc_flags &= ~RTW_F_DK_VALID;
609 rtw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
610 const u_int8_t mac[IEEE80211_ADDR_LEN])
612 struct rtw_softc *sc = ic->ic_ifp->if_softc;
614 DPRINTF(sc, RTW_DEBUG_KEY, ("%s: set key %u\n", __func__, k->wk_keyix));
616 if (k->wk_keyix >= IEEE80211_WEP_NKID)
619 sc->sc_flags &= ~RTW_F_DK_VALID;
624 rtw_key_update_begin(struct ieee80211com *ic)
627 struct ifnet *ifp = ic->ic_ifp;
628 struct rtw_softc *sc = ifp->if_softc;
631 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
635 rtw_key_update_end(struct ieee80211com *ic)
637 struct ifnet *ifp = ic->ic_ifp;
638 struct rtw_softc *sc = ifp->if_softc;
640 DPRINTF(sc, RTW_DEBUG_KEY, ("%s:\n", __func__));
642 if ((sc->sc_flags & RTW_F_DK_VALID) != 0 ||
643 (sc->sc_flags & RTW_F_ENABLED) == 0 ||
644 (sc->sc_flags & RTW_F_INVALID) != 0)
647 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
649 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE,
650 (ifp->if_flags & IFF_RUNNING) != 0);
654 rtw_key_hwsupp(uint32_t flags, const struct ieee80211_key *k)
656 if (k->wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
659 return ((flags & RTW_C_RXWEP_40) != 0 && k->wk_keylen == 5) ||
660 ((flags & RTW_C_RXWEP_104) != 0 && k->wk_keylen == 13);
664 rtw_wep_setkeys(struct rtw_softc *sc)
666 struct ieee80211com *ic = &sc->sc_ic;
667 struct ieee80211_key *wk = ic->ic_nw_keys;
668 const struct ieee80211_cipher *wep_cipher;
669 struct rtw_regs *regs = &sc->sc_regs;
670 union rtw_keys *rk = &sc->sc_keys;
674 memset(rk->rk_keys, 0, sizeof(rk->rk_keys));
676 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
677 KKASSERT(wep_cipher != NULL);
679 /* Temporarily use software crypto for all keys. */
680 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
681 if (wk[i].wk_cipher == &rtw_cipher_wep)
682 wk[i].wk_cipher = wep_cipher;
685 rtw_set_access(sc, RTW_ACCESS_CONFIG);
687 psr = RTW_READ8(regs, RTW_PSR);
688 scr = RTW_READ8(regs, RTW_SCR);
689 scr &= ~(RTW_SCR_KM_MASK | RTW_SCR_TXSECON | RTW_SCR_RXSECON);
691 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
694 for (keylen = i = 0; i < IEEE80211_WEP_NKID; i++) {
695 if (!rtw_key_hwsupp(sc->sc_flags, &wk[i]))
697 if (i == ic->ic_def_txkey) {
698 keylen = wk[i].wk_keylen;
701 keylen = MAX(keylen, wk[i].wk_keylen);
705 scr |= RTW_SCR_KM_WEP40 | RTW_SCR_RXSECON;
706 else if (keylen == 13)
707 scr |= RTW_SCR_KM_WEP104 | RTW_SCR_RXSECON;
709 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
710 if (wk[i].wk_keylen != keylen ||
711 wk[i].wk_cipher->ic_cipher != IEEE80211_CIPHER_WEP)
713 /* h/w will decrypt, s/w still strips headers */
714 wk[i].wk_cipher = &rtw_cipher_wep;
715 memcpy(rk->rk_keys[i], wk[i].wk_key, wk[i].wk_keylen);
718 RTW_WRITE8(regs, RTW_PSR, psr & ~RTW_PSR_PSEN);
720 bus_space_write_region_4(regs->r_bt, regs->r_bh, RTW_DK0, rk->rk_words,
721 NELEM(rk->rk_words));
723 RTW_WBW(regs, RTW_DK0, RTW_PSR);
724 RTW_WRITE8(regs, RTW_PSR, psr);
725 RTW_WBW(regs, RTW_PSR, RTW_SCR);
726 RTW_WRITE8(regs, RTW_SCR, scr);
727 RTW_SYNC(regs, RTW_SCR, RTW_SCR);
728 rtw_set_access(sc, RTW_ACCESS_NONE);
729 sc->sc_flags |= RTW_F_DK_VALID;
733 rtw_recall_eeprom(struct rtw_softc *sc)
735 struct rtw_regs *regs = &sc->sc_regs;
739 ecr = RTW_READ8(regs, RTW_9346CR);
740 ecr = (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_AUTOLOAD;
741 RTW_WRITE8(regs, RTW_9346CR, ecr);
743 RTW_WBR(regs, RTW_9346CR, RTW_9346CR);
745 /* wait 25ms for completion */
746 for (i = 0; i < 250; i++) {
747 ecr = RTW_READ8(regs, RTW_9346CR);
748 if ((ecr & RTW_9346CR_EEM_MASK) == RTW_9346CR_EEM_NORMAL) {
749 RTW_DPRINTF(RTW_DEBUG_RESET,
750 ("%s: recall EEPROM in %dus\n",
751 sc->sc_ic.ic_if.if_xname, i * 100));
754 RTW_RBR(regs, RTW_9346CR, RTW_9346CR);
757 if_printf(&sc->sc_ic.ic_if, "recall EEPROM failed\n");
762 rtw_reset(struct rtw_softc *sc)
764 struct rtw_regs *regs = &sc->sc_regs;
768 sc->sc_flags &= ~RTW_F_DK_VALID;
770 rc = rtw_chip_reset(sc);
774 rtw_recall_eeprom(sc); /* ignore err */
776 config1 = RTW_READ8(regs, RTW_CONFIG1);
777 RTW_WRITE8(regs, RTW_CONFIG1, config1 & ~RTW_CONFIG1_PMEN);
778 /* TBD turn off maximum power saving? */
783 rtw_srom_parse(struct rtw_softc *sc)
785 struct rtw_srom *sr = &sc->sc_srom;
786 char scratch[sizeof("unknown 0xXX")];
787 uint8_t mac[IEEE80211_ADDR_LEN];
788 const char *rfname, *paname;
789 uint16_t srom_version;
792 sc->sc_flags &= ~(RTW_F_DIGPHY | RTW_F_DFLANTB | RTW_F_ANTDIV);
793 sc->sc_rcr &= ~(RTW_RCR_ENCS1 | RTW_RCR_ENCS2);
795 srom_version = RTW_SR_GET16(sr, RTW_SR_VERSION);
796 if_printf(&sc->sc_ic.ic_if, "SROM version %d.%d",
797 srom_version >> 8, srom_version & 0xff);
799 if (srom_version <= 0x0101) {
800 kprintf(" is not understood, limping along with defaults\n");
803 sc->sc_flags |= (RTW_F_DIGPHY | RTW_F_ANTDIV);
804 sc->sc_csthr = RTW_SR_ENERGYDETTHR_DEFAULT;
805 sc->sc_rcr |= RTW_RCR_ENCS1;
806 sc->sc_rfchipid = RTW_RFCHIPID_PHILIPS;
811 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
812 mac[i] = RTW_SR_GET(sr, RTW_SR_MAC + i);
814 RTW_DPRINTF(RTW_DEBUG_ATTACH,
815 ("%s: EEPROM MAC %6D\n", sc->sc_ic.ic_if.if_xname, mac, ":"));
817 sc->sc_csthr = RTW_SR_GET(sr, RTW_SR_ENERGYDETTHR);
819 if ((RTW_SR_GET(sr, RTW_SR_CONFIG2) & RTW_CONFIG2_ANT) != 0)
820 sc->sc_flags |= RTW_F_ANTDIV;
823 * Note well: the sense of the RTW_SR_RFPARM_DIGPHY bit seems
826 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DIGPHY) == 0)
827 sc->sc_flags |= RTW_F_DIGPHY;
828 if ((RTW_SR_GET(sr, RTW_SR_RFPARM) & RTW_SR_RFPARM_DFLANTB) != 0)
829 sc->sc_flags |= RTW_F_DFLANTB;
831 sc->sc_rcr |= __SHIFTIN(__SHIFTOUT(RTW_SR_GET(sr, RTW_SR_RFPARM),
832 RTW_SR_RFPARM_CS_MASK), RTW_RCR_ENCS1);
834 if ((RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_WEP104) != 0)
835 sc->sc_flags |= RTW_C_RXWEP_104;
837 sc->sc_flags |= RTW_C_RXWEP_40; /* XXX */
839 sc->sc_rfchipid = RTW_SR_GET(sr, RTW_SR_RFCHIPID);
840 switch (sc->sc_rfchipid) {
841 case RTW_RFCHIPID_GCT: /* this combo seen in the wild */
842 rfname = "GCT GRF5101";
843 paname = "Winspring WS9901";
845 case RTW_RFCHIPID_MAXIM:
846 rfname = "Maxim MAX2820"; /* guess */
847 paname = "Maxim MAX2422"; /* guess */
849 case RTW_RFCHIPID_INTERSIL:
850 rfname = "Intersil HFA3873"; /* guess */
851 paname = "Intersil <unknown>";
853 case RTW_RFCHIPID_PHILIPS: /* this combo seen in the wild */
854 rfname = "Philips SA2400A";
855 paname = "Philips SA2411";
857 case RTW_RFCHIPID_RFMD:
858 /* this is the same front-end as an atw(4)! */
859 rfname = "RFMD RF2948B, " /* mentioned in Realtek docs */
860 "LNA: RFMD RF2494, " /* mentioned in Realtek docs */
861 "SYN: Silicon Labs Si4126"; /* inferred from
864 paname = "RFMD RF2189"; /* mentioned in Realtek docs */
866 case RTW_RFCHIPID_RESERVED:
867 rfname = paname = "reserved";
870 ksnprintf(scratch, sizeof(scratch), "unknown 0x%02x",
872 rfname = paname = scratch;
874 if_printf(&sc->sc_ic.ic_if, "RF: %s, PA: %s\n", rfname, paname);
876 switch (RTW_SR_GET(sr, RTW_SR_CONFIG0) & RTW_CONFIG0_GL_MASK) {
877 case RTW_CONFIG0_GL_USA:
878 case _RTW_CONFIG0_GL_USA:
879 sc->sc_locale = RTW_LOCALE_USA;
881 case RTW_CONFIG0_GL_EUROPE:
882 sc->sc_locale = RTW_LOCALE_EUROPE;
884 case RTW_CONFIG0_GL_JAPAN:
885 sc->sc_locale = RTW_LOCALE_JAPAN;
888 sc->sc_locale = RTW_LOCALE_UNKNOWN;
895 rtw_srom_read(struct rtw_softc *sc)
897 struct rtw_regs *regs = &sc->sc_regs;
898 struct rtw_srom *sr = &sc->sc_srom;
899 struct seeprom_descriptor sd;
903 memset(&sd, 0, sizeof(sd));
905 ecr = RTW_READ8(regs, RTW_9346CR);
907 if ((sc->sc_flags & RTW_F_9356SROM) != 0) {
908 RTW_DPRINTF(RTW_DEBUG_ATTACH,
909 ("%s: 93c56 SROM\n", sc->sc_ic.ic_if.if_xname));
913 RTW_DPRINTF(RTW_DEBUG_ATTACH,
914 ("%s: 93c46 SROM\n", sc->sc_ic.ic_if.if_xname));
919 ecr &= ~(RTW_9346CR_EEDI | RTW_9346CR_EEDO | RTW_9346CR_EESK |
920 RTW_9346CR_EEM_MASK | RTW_9346CR_EECS);
921 ecr |= RTW_9346CR_EEM_PROGRAM;
923 RTW_WRITE8(regs, RTW_9346CR, ecr);
925 sr->sr_content = kmalloc(sr->sr_size, M_DEVBUF, M_WAITOK | M_ZERO);
928 * RTL8180 has a single 8-bit register for controlling the
929 * 93cx6 SROM. There is no "ready" bit. The RTL8180
930 * input/output sense is the reverse of read_seeprom's.
932 sd.sd_tag = regs->r_bt;
933 sd.sd_bsh = regs->r_bh;
935 sd.sd_control_offset = RTW_9346CR;
936 sd.sd_status_offset = RTW_9346CR;
937 sd.sd_dataout_offset = RTW_9346CR;
938 sd.sd_CK = RTW_9346CR_EESK;
939 sd.sd_CS = RTW_9346CR_EECS;
940 sd.sd_DI = RTW_9346CR_EEDO;
941 sd.sd_DO = RTW_9346CR_EEDI;
942 /* make read_seeprom enter EEPROM read/write mode */
946 /* TBD bus barriers */
947 if (!read_seeprom(&sd, sr->sr_content, 0, sr->sr_size / 2)) {
948 if_printf(&sc->sc_ic.ic_if, "could not read SROM\n");
949 kfree(sr->sr_content, M_DEVBUF);
950 sr->sr_content = NULL;
951 return EIO; /* XXX */
954 /* end EEPROM read/write mode */
955 RTW_WRITE8(regs, RTW_9346CR,
956 (ecr & ~RTW_9346CR_EEM_MASK) | RTW_9346CR_EEM_NORMAL);
957 RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);
959 rc = rtw_recall_eeprom(sc);
966 RTW_DPRINTF(RTW_DEBUG_ATTACH,
967 ("\n%s: serial ROM:\n\t", sc->sc_ic.ic_if.if_xname));
968 for (i = 0; i < sr->sr_size/2; i++) {
969 if (((i % 8) == 0) && (i != 0))
970 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n\t"));
971 RTW_DPRINTF(RTW_DEBUG_ATTACH,
972 (" %04x", sr->sr_content[i]));
974 RTW_DPRINTF(RTW_DEBUG_ATTACH, ("\n"));
976 #endif /* RTW_DEBUG */
981 rtw_set_rfprog(struct rtw_softc *sc)
983 struct rtw_regs *regs = &sc->sc_regs;
987 cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;
989 switch (sc->sc_rfchipid) {
991 cfg4 |= __SHIFTIN(rtw_rfprog_fallback, RTW_CONFIG4_RFTYPE_MASK);
994 case RTW_RFCHIPID_INTERSIL:
995 cfg4 |= RTW_CONFIG4_RFTYPE_INTERSIL;
998 case RTW_RFCHIPID_PHILIPS:
999 cfg4 |= RTW_CONFIG4_RFTYPE_PHILIPS;
1002 case RTW_RFCHIPID_GCT: /* XXX a guess */
1003 case RTW_RFCHIPID_RFMD:
1004 cfg4 |= RTW_CONFIG4_RFTYPE_RFMD;
1009 RTW_WRITE8(regs, RTW_CONFIG4, cfg4);
1011 RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);
1013 RTW_DPRINTF(RTW_DEBUG_INIT,
1014 ("%s: %s RF programming method, %#02x\n",
1015 sc->sc_ic.ic_if.if_xname, method,
1016 RTW_READ8(regs, RTW_CONFIG4)));
1019 static __inline void
1020 rtw_init_channels(struct rtw_softc *sc)
1022 const char *name = NULL;
1023 struct ieee80211_channel *chans = sc->sc_ic.ic_channels;
1025 #define ADD_CHANNEL(_chans, _chan) do { \
1026 _chans[_chan].ic_flags = IEEE80211_CHAN_B; \
1027 _chans[_chan].ic_freq = \
1028 ieee80211_ieee2mhz(_chan, _chans[_chan].ic_flags); \
1031 switch (sc->sc_locale) {
1032 case RTW_LOCALE_USA: /* 1-11 */
1034 for (i = 1; i <= 11; i++)
1035 ADD_CHANNEL(chans, i);
1037 case RTW_LOCALE_JAPAN: /* 1-14 */
1039 ADD_CHANNEL(chans, 14);
1040 for (i = 1; i <= 14; i++)
1041 ADD_CHANNEL(chans, i);
1043 case RTW_LOCALE_EUROPE: /* 1-13 */
1045 for (i = 1; i <= 13; i++)
1046 ADD_CHANNEL(chans, i);
1048 default: /* 10-11 allowed by most countries */
1050 for (i = 10; i <= 11; i++)
1051 ADD_CHANNEL(chans, i);
1054 if_printf(&sc->sc_ic.ic_if, "Geographic Location %s\n", name);
1060 rtw_identify_country(struct rtw_softc *sc)
1064 cfg0 = RTW_READ8(&sc->sc_regs, RTW_CONFIG0);
1065 switch (cfg0 & RTW_CONFIG0_GL_MASK) {
1066 case RTW_CONFIG0_GL_USA:
1067 case _RTW_CONFIG0_GL_USA:
1068 sc->sc_locale = RTW_LOCALE_USA;
1070 case RTW_CONFIG0_GL_JAPAN:
1071 sc->sc_locale = RTW_LOCALE_JAPAN;
1073 case RTW_CONFIG0_GL_EUROPE:
1074 sc->sc_locale = RTW_LOCALE_EUROPE;
1077 sc->sc_locale = RTW_LOCALE_UNKNOWN;
1083 rtw_identify_sta(struct rtw_softc *sc)
1085 static const uint8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
1086 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
1088 struct rtw_regs *regs = &sc->sc_regs;
1089 uint8_t *addr = sc->sc_ic.ic_myaddr;
1090 uint32_t idr0, idr1;
1092 idr0 = RTW_READ(regs, RTW_IDR0);
1093 idr1 = RTW_READ(regs, RTW_IDR1);
1095 addr[0] = __SHIFTOUT(idr0, __BITS(0, 7));
1096 addr[1] = __SHIFTOUT(idr0, __BITS(8, 15));
1097 addr[2] = __SHIFTOUT(idr0, __BITS(16, 23));
1098 addr[3] = __SHIFTOUT(idr0, __BITS(24 ,31));
1100 addr[4] = __SHIFTOUT(idr1, __BITS(0, 7));
1101 addr[5] = __SHIFTOUT(idr1, __BITS(8, 15));
1103 if (IEEE80211_ADDR_EQ(addr, empty_macaddr)) {
1104 if_printf(&sc->sc_ic.ic_if, "could not get mac address\n");
1111 rtw_chan2txpower(struct rtw_srom *sr, struct ieee80211com *ic,
1112 struct ieee80211_channel *chan)
1114 u_int idx = RTW_SR_TXPOWER1 + ieee80211_chan2ieee(ic, chan) - 1;
1116 KASSERT(idx >= RTW_SR_TXPOWER1 && idx <= RTW_SR_TXPOWER14,
1117 ("%s: channel %d out of range", __func__,
1118 idx - RTW_SR_TXPOWER1 + 1));
1119 return RTW_SR_GET(sr, idx);
1123 rtw_txdesc_blk_init_all(struct rtw_softc *sc)
1125 /* nfree: the number of free descriptors in each ring.
1126 * The beacon ring is a special case: I do not let the
1127 * driver use all of the descriptors on the beacon ring.
1128 * The reasons are two-fold:
1130 * (1) A BEACON descriptor's OWN bit is (apparently) not
1131 * updated, so the driver cannot easily know if the descriptor
1132 * belongs to it, or if it is racing the NIC. If the NIC
1133 * does not OWN every descriptor, then the driver can safely
1134 * update the descriptors when RTW_TBDA points at tdb_next.
1136 * (2) I hope that the NIC will process more than one BEACON
1137 * descriptor in a single beacon interval, since that will
1138 * enable multiple-BSS support. Since the NIC does not
1139 * clear the OWN bit, there is no natural place for it to
1140 * stop processing BEACON desciptors. Maybe it will *not*
1141 * stop processing them! I do not want to chance the NIC
1142 * looping around and around a saturated beacon ring, so
1143 * I will leave one descriptor unOWNed at all times.
1145 int nfree[RTW_NTXPRI] = {
1151 struct rtw_txdesc_blk *tdb;
1154 for (tdb = sc->sc_txdesc_blk, pri = 0; pri < RTW_NTXPRI; tdb++, pri++) {
1155 tdb->tdb_nfree = nfree[pri];
1158 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1159 BUS_DMASYNC_PREWRITE);
1164 rtw_txsoft_blk_init_all(struct rtw_softc *sc)
1166 struct rtw_txsoft_blk *tsb;
1169 for (tsb = sc->sc_txsoft_blk, pri = 0; pri < RTW_NTXPRI; tsb++, pri++) {
1172 STAILQ_INIT(&tsb->tsb_dirtyq);
1173 STAILQ_INIT(&tsb->tsb_freeq);
1174 for (i = 0; i < tsb->tsb_ndesc; i++) {
1175 struct rtw_txsoft *ts;
1177 ts = &tsb->tsb_desc[i];
1179 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1181 tsb->tsb_tx_timer = 0;
1186 rtw_rxbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
1187 bus_size_t mapsize, int error)
1192 KASSERT(nseg == 1, ("too many rx mbuf seg"));
1194 *((bus_addr_t *)arg) = seg->ds_addr;
1198 rtw_rxsoft_alloc(struct rtw_softc *sc, struct rtw_rxsoft *rs, int waitok)
1205 m = m_getcl(waitok ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1209 m->m_pkthdr.len = m->m_len = MCLBYTES;
1211 rc = bus_dmamap_load_mbuf(sc->sc_rxsoft_dmat, sc->sc_rxsoft_dmamap, m,
1212 rtw_rxbuf_dma_map, &paddr,
1213 waitok ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1215 if_printf(&sc->sc_ic.ic_if, "can't load rx mbuf\n");
1220 if (rs->rs_mbuf != NULL)
1221 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
1224 map = rs->rs_dmamap;
1225 rs->rs_dmamap = sc->sc_rxsoft_dmamap;
1226 sc->sc_rxsoft_dmamap = map;
1229 rs->rs_phyaddr = paddr;
1231 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap, BUS_DMASYNC_PREREAD);
1236 rtw_rxsoft_blk_init_all(struct rtw_softc *sc)
1240 for (i = 0; i < RTW_RXQLEN; i++) {
1241 struct rtw_rxsoft *rs;
1243 rs = &sc->sc_rxsoft[i];
1244 /* we're in rtw_init, so there should be no mbufs allocated */
1245 KKASSERT(rs->rs_mbuf == NULL);
1247 if (i == rtw_rxbufs_limit) {
1248 if_printf(&sc->sc_ic.ic_if,
1249 "TEST hit %d-buffer limit\n", i);
1253 #endif /* RTW_DEBUG */
1254 rc = rtw_rxsoft_alloc(sc, rs, 1);
1262 rtw_rxdesc_init(struct rtw_softc *sc, int idx, int kick)
1264 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1265 struct rtw_rxdesc *rd = &rdb->rdb_desc[idx];
1266 struct rtw_rxsoft *rs = &sc->sc_rxsoft[idx];
1270 uint32_t octl, obuf;
1274 #endif /* RTW_DEBUG */
1276 rd->rd_buf = htole32(rs->rs_phyaddr);
1278 ctl = __SHIFTIN(rs->rs_mbuf->m_len, RTW_RXCTL_LENGTH_MASK) |
1279 RTW_RXCTL_OWN | RTW_RXCTL_FS | RTW_RXCTL_LS;
1281 if (idx == rdb->rdb_ndesc - 1)
1282 ctl |= RTW_RXCTL_EOR;
1284 rd->rd_ctl = htole32(ctl);
1286 RTW_DPRINTF(kick ? (RTW_DEBUG_RECV_DESC | RTW_DEBUG_IO_KICK)
1287 : RTW_DEBUG_RECV_DESC,
1288 ("%s: rd %p buf %08x -> %08x ctl %08x -> %08x\n",
1289 sc->sc_ic.ic_if.if_xname, rd, le32toh(obuf),
1290 le32toh(rd->rd_buf), le32toh(octl), le32toh(rd->rd_ctl)));
1294 rtw_rxdesc_blk_init_all(struct rtw_softc *sc)
1296 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1299 for (i = 0; i < rdb->rdb_ndesc; i++)
1300 rtw_rxdesc_init(sc, i, 1);
1302 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_PREWRITE);
1306 rtw_io_enable(struct rtw_softc *sc, uint8_t flags, int enable)
1308 struct rtw_regs *regs = &sc->sc_regs;
1311 RTW_DPRINTF(RTW_DEBUG_IOSTATE,
1312 ("%s: %s 0x%02x\n", sc->sc_ic.ic_if.if_xname,
1313 enable ? "enable" : "disable", flags));
1315 cr = RTW_READ8(regs, RTW_CR);
1317 /* XXX reference source does not enable MULRW */
1319 /* enable PCI Read/Write Multiple */
1323 RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */
1328 RTW_WRITE8(regs, RTW_CR, cr);
1329 RTW_SYNC(regs, RTW_CR, RTW_CR);
1333 rtw_intr_rx(struct rtw_softc *sc, uint16_t isr)
1335 #define IS_BEACON(__fc0) \
1336 ((__fc0 & (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==\
1337 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_BEACON))
1341 * hardware -> net80211
1343 static const int ratetbl[4] = { 2, 4, 11, 22 };
1344 struct ifnet *ifp = &sc->sc_if;
1345 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1346 int next, nproc = 0, sync = 0;
1348 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1350 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap, BUS_DMASYNC_POSTREAD);
1352 for (next = rdb->rdb_next; ; next = (next + 1) % rdb->rdb_ndesc) {
1353 struct ieee80211_node *ni;
1354 struct ieee80211_frame_min *wh;
1355 struct rtw_rxdesc *rd;
1356 struct rtw_rxsoft *rs;
1358 int hwrate, len, rate, rssi, sq, error;
1359 uint32_t hrssi, hstat, htsfth, htsftl;
1361 rd = &rdb->rdb_desc[next];
1362 rs = &sc->sc_rxsoft[next];
1364 hstat = le32toh(rd->rd_stat);
1365 hrssi = le32toh(rd->rd_rssi);
1366 htsfth = le32toh(rd->rd_tsfth);
1367 htsftl = le32toh(rd->rd_tsftl);
1369 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1370 ("%s: rxdesc[%d] hstat %08x hrssi %08x "
1371 "htsft %08x%08x\n", ifp->if_xname,
1372 next, hstat, hrssi, htsfth, htsftl));
1376 /* still belongs to NIC */
1377 if (hstat & RTW_RXSTAT_OWN) {
1381 /* sometimes the NIC skips to the 0th descriptor */
1382 rd = &rdb->rdb_desc[0];
1383 if (rd->rd_stat & htole32(RTW_RXSTAT_OWN))
1385 RTW_DPRINTF(RTW_DEBUG_BUGS,
1386 ("%s: NIC skipped from rxdesc[%u] "
1387 "to rxdesc[0]\n", ifp->if_xname, next));
1388 next = rdb->rdb_ndesc - 1;
1393 #define PRINTSTAT(flag) do { \
1394 if ((hstat & flag) != 0) { \
1395 kprintf("%s" #flag, delim); \
1399 if (rtw_debug & RTW_DEBUG_RECV_DESC) {
1400 const char *delim = "<";
1402 if_printf(ifp, "%s", "");
1403 if ((hstat & RTW_RXSTAT_DEBUG) != 0) {
1404 kprintf("status %08x", hstat);
1405 PRINTSTAT(RTW_RXSTAT_SPLCP);
1406 PRINTSTAT(RTW_RXSTAT_MAR);
1407 PRINTSTAT(RTW_RXSTAT_PAR);
1408 PRINTSTAT(RTW_RXSTAT_BAR);
1409 PRINTSTAT(RTW_RXSTAT_PWRMGT);
1410 PRINTSTAT(RTW_RXSTAT_CRC32);
1411 PRINTSTAT(RTW_RXSTAT_ICV);
1415 #endif /* RTW_DEBUG */
1417 if (hstat & RTW_RXSTAT_IOERROR) {
1418 if_printf(ifp, "DMA error/FIFO overflow %08x, "
1419 "rx descriptor %d\n",
1420 hstat & RTW_RXSTAT_IOERROR, next);
1425 len = __SHIFTOUT(hstat, RTW_RXSTAT_LENGTH_MASK);
1426 if (len < IEEE80211_MIN_LEN) {
1427 sc->sc_ic.ic_stats.is_rx_tooshort++;
1431 /* CRC is included with the packet; trim it off. */
1432 len -= IEEE80211_CRC_LEN;
1434 hwrate = __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK);
1435 if (hwrate >= NELEM(ratetbl)) {
1436 if_printf(ifp, "unknown rate #%d\n",
1437 __SHIFTOUT(hstat, RTW_RXSTAT_RATE_MASK));
1441 rate = ratetbl[hwrate];
1444 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1445 ("%s rate %d.%d Mb/s, time %08x%08x\n",
1446 ifp->if_xname, (rate * 5) / 10,
1447 (rate * 5) % 10, htsfth, htsftl));
1448 #endif /* RTW_DEBUG */
1450 if ((hstat & RTW_RXSTAT_RES) &&
1451 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR)
1454 /* if bad flags, skip descriptor */
1455 if ((hstat & RTW_RXSTAT_ONESEG) != RTW_RXSTAT_ONESEG) {
1456 if_printf(ifp, "too many rx segments\n");
1460 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
1461 BUS_DMASYNC_POSTREAD);
1465 /* if temporarily out of memory, re-use mbuf */
1466 error = rtw_rxsoft_alloc(sc, rs, 0);
1468 if_printf(ifp, "%s: rtw_rxsoft_alloc(, %d) failed, "
1469 "dropping packet\n", ifp->if_xname, next);
1473 rssi = __SHIFTOUT(hrssi, RTW_RXRSSI_RSSI);
1474 sq = __SHIFTOUT(hrssi, RTW_RXRSSI_SQ);
1476 rssi = rtw_get_rssi(sc, rssi, sq);
1479 * Note well: now we cannot recycle the rs_mbuf unless
1480 * we restore its original length.
1482 m->m_pkthdr.rcvif = ifp;
1483 m->m_pkthdr.len = m->m_len = len;
1485 wh = mtod(m, struct ieee80211_frame_min *);
1487 if (!IS_BEACON(wh->i_fc[0]))
1488 sc->sc_led_state.ls_event |= RTW_LED_S_RX;
1490 /* TBD use _MAR, _BAR, _PAR flags as hints to _find_rxnode? */
1491 ni = ieee80211_find_rxnode(&sc->sc_ic, wh);
1493 sc->sc_tsfth = htsfth;
1496 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
1497 (IFF_DEBUG | IFF_LINK2)) {
1498 ieee80211_dump_pkt(mtod(m, uint8_t *), m->m_pkthdr.len,
1501 #endif /* RTW_DEBUG */
1503 if (sc->sc_radiobpf != NULL) {
1504 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
1507 htole64(((uint64_t)htsfth << 32) | htsftl);
1509 if ((hstat & RTW_RXSTAT_SPLCP) != 0)
1510 rr->rr_flags = IEEE80211_RADIOTAP_F_SHORTPRE;
1514 rr->rr_antsignal = rssi;
1515 rr->rr_barker_lock = htole16(sq);
1517 bpf_ptap(sc->sc_radiobpf, m, rr, sizeof(sc->sc_rxtapu));
1520 ieee80211_input(&sc->sc_ic, m, ni, rssi, htsftl);
1521 ieee80211_free_node(ni);
1523 rtw_rxdesc_init(sc, next, 0);
1528 bus_dmamap_sync(rdb->rdb_dmat, rdb->rdb_dmamap,
1529 BUS_DMASYNC_PREWRITE);
1532 rdb->rdb_next = next;
1533 KKASSERT(rdb->rdb_next < rdb->rdb_ndesc);
1537 static __inline void
1538 rtw_txsoft_release(bus_dma_tag_t dmat, struct rtw_txsoft *ts,
1539 int data_retry, int rts_retry, int error, int ratectl)
1542 struct ieee80211_node *ni;
1544 if (!ts->ts_ratectl)
1549 KKASSERT(m != NULL);
1550 KKASSERT(ni != NULL);
1555 struct ieee80211_ratectl_res rc_res;
1557 rc_res.rc_res_rateidx = ts->ts_rateidx;
1558 rc_res.rc_res_tries = data_retry + 1;
1560 ieee80211_ratectl_tx_complete(ni, m->m_pkthdr.len,
1562 data_retry, rts_retry,
1566 bus_dmamap_sync(dmat, ts->ts_dmamap, BUS_DMASYNC_POSTWRITE);
1567 bus_dmamap_unload(dmat, ts->ts_dmamap);
1569 ieee80211_free_node(ni);
1572 static __inline void
1573 rtw_collect_txpkt(struct rtw_softc *sc, struct rtw_txdesc_blk *tdb,
1574 struct rtw_txsoft *ts, int ndesc)
1577 int data_retry, rts_retry, error;
1578 struct rtw_txdesc *tdn;
1579 const char *condstring;
1580 struct ifnet *ifp = &sc->sc_if;
1582 tdb->tdb_nfree += ndesc;
1584 tdn = &tdb->tdb_desc[ts->ts_last];
1586 hstat = le32toh(tdn->td_stat);
1587 rts_retry = __SHIFTOUT(hstat, RTW_TXSTAT_RTSRETRY_MASK);
1588 data_retry = __SHIFTOUT(hstat, RTW_TXSTAT_DRC_MASK);
1590 ifp->if_collisions += rts_retry + data_retry;
1592 if ((hstat & RTW_TXSTAT_TOK) != 0) {
1597 condstring = "error";
1601 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, data_retry, rts_retry,
1604 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
1605 ("%s: ts %p txdesc[%d, %d] %s tries rts %u data %u\n",
1606 ifp->if_xname, ts, ts->ts_first, ts->ts_last,
1607 condstring, rts_retry, data_retry));
1611 rtw_reset_oactive(struct rtw_softc *sc)
1615 short oflags = sc->sc_if.if_flags;
1618 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1619 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
1620 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1622 if (!STAILQ_EMPTY(&tsb->tsb_freeq) && tdb->tdb_nfree > 0)
1623 sc->sc_if.if_flags &= ~IFF_OACTIVE;
1627 if (oflags != sc->sc_if.if_flags) {
1628 DPRINTF(sc, RTW_DEBUG_OACTIVE,
1629 ("%s: reset OACTIVE\n", sc->sc_ic.ic_if.if_xname));
1634 /* Collect transmitted packets. */
1635 static __inline void
1636 rtw_collect_txring(struct rtw_softc *sc, struct rtw_txsoft_blk *tsb,
1637 struct rtw_txdesc_blk *tdb, int force)
1639 struct rtw_txsoft *ts;
1642 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
1643 ndesc = 1 + ts->ts_last - ts->ts_first;
1644 if (ts->ts_last < ts->ts_first)
1645 ndesc += tdb->tdb_ndesc;
1647 KKASSERT(ndesc > 0);
1649 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1650 BUS_DMASYNC_POSTREAD);
1655 for (i = ts->ts_first; ; i = RTW_NEXT_IDX(tdb, i)) {
1656 tdb->tdb_desc[i].td_stat &=
1657 ~htole32(RTW_TXSTAT_OWN);
1658 if (i == ts->ts_last)
1661 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
1662 BUS_DMASYNC_PREWRITE);
1663 } else if ((tdb->tdb_desc[ts->ts_last].td_stat &
1664 htole32(RTW_TXSTAT_OWN)) != 0) {
1668 rtw_collect_txpkt(sc, tdb, ts, ndesc);
1669 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
1670 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
1672 /* no more pending transmissions, cancel watchdog */
1674 tsb->tsb_tx_timer = 0;
1675 rtw_reset_oactive(sc);
1679 rtw_intr_tx(struct rtw_softc *sc, uint16_t isr)
1683 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1684 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1685 &sc->sc_txdesc_blk[pri], 0);
1688 rtw_start(&sc->sc_ic.ic_if);
1691 static __inline struct mbuf *
1692 rtw_beacon_alloc(struct rtw_softc *sc, struct ieee80211_node *ni)
1694 struct ieee80211com *ic = &sc->sc_ic;
1695 struct ieee80211_beacon_offsets boff;
1698 m = ieee80211_beacon_alloc(ic, ni, &boff);
1700 RTW_DPRINTF(RTW_DEBUG_BEACON,
1701 ("%s: m %p len %u\n", ic->ic_if.if_xname, m,
1708 rtw_intr_beacon(struct rtw_softc *sc, uint16_t isr)
1710 struct ieee80211com *ic = &sc->sc_ic;
1711 struct rtw_regs *regs = &sc->sc_regs;
1712 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[RTW_TXPRIBCN];
1713 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[RTW_TXPRIBCN];
1716 uint32_t tsfth, tsftl;
1718 tsfth = RTW_READ(regs, RTW_TSFTRH);
1719 tsftl = RTW_READ(regs, RTW_TSFTRL);
1722 if (isr & (RTW_INTR_TBDOK | RTW_INTR_TBDER)) {
1724 int next = rtw_txring_next(regs, tdb);
1727 RTW_DPRINTF(RTW_DEBUG_BEACON,
1728 ("%s: beacon ring %sprocessed, "
1729 "isr = %#04x, next %d expected %d, %llu\n",
1731 (next == tdb->tdb_next) ? "" : "un",
1732 isr, next, tdb->tdb_next,
1733 (uint64_t)tsfth << 32 | tsftl));
1735 if ((RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_BQ) == 0){
1736 rtw_collect_txring(sc, tsb, tdb, 1);
1740 /* Start beacon transmission. */
1742 if ((isr & RTW_INTR_BCNINT) && ic->ic_state == IEEE80211_S_RUN &&
1743 STAILQ_EMPTY(&tsb->tsb_dirtyq)) {
1746 RTW_DPRINTF(RTW_DEBUG_BEACON,
1747 ("%s: beacon prep. time, isr = %#04x, %llu\n",
1748 ic->ic_if.if_xname, isr,
1749 (uint64_t)tsfth << 32 | tsftl));
1751 m = rtw_beacon_alloc(sc, ic->ic_bss);
1753 if_printf(&ic->ic_if, "could not allocate beacon\n");
1757 m->m_pkthdr.rcvif = (void *)ieee80211_ref_node(ic->ic_bss);
1759 IF_ENQUEUE(&sc->sc_beaconq, m);
1761 rtw_start(&ic->ic_if);
1766 rtw_intr_atim(struct rtw_softc *sc)
1774 rtw_dump_rings(struct rtw_softc *sc)
1776 struct rtw_rxdesc_blk *rdb;
1779 if ((rtw_debug & RTW_DEBUG_IO_KICK) == 0)
1782 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1783 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1785 if_printf(&sc->sc_ic.ic_if, "txpri %d ndesc %d nfree %d\n",
1786 pri, tdb->tdb_ndesc, tdb->tdb_nfree);
1787 for (desc = 0; desc < tdb->tdb_ndesc; desc++)
1788 rtw_print_txdesc(sc, ".", NULL, tdb, desc);
1791 rdb = &sc->sc_rxdesc_blk;
1793 for (desc = 0; desc < RTW_RXQLEN; desc++) {
1794 struct rtw_rxdesc *rd = &rdb->rdb_desc[desc];
1796 if_printf(&sc->sc_ic.ic_if,
1797 "%sctl %08x rsvd0/rssi %08x buf/tsftl %08x "
1798 "rsvd1/tsfth %08x\n",
1799 (desc >= rdb->rdb_ndesc) ? "UNUSED " : "",
1800 le32toh(rd->rd_ctl), le32toh(rd->rd_rssi),
1801 le32toh(rd->rd_buf), le32toh(rd->rd_tsfth));
1804 #endif /* RTW_DEBUG */
1807 rtw_hwring_setup(struct rtw_softc *sc)
1809 struct rtw_regs *regs = &sc->sc_regs;
1810 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1813 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1814 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1816 RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base);
1817 RTW_DPRINTF(RTW_DEBUG_XMIT_DESC,
1818 ("%s: reg[tdb->tdb_basereg] <- %u\n",
1819 sc->sc_ic.ic_if.if_xname, tdb->tdb_base));
1822 RTW_WRITE(regs, RTW_RDSAR, rdb->rdb_base);
1823 RTW_DPRINTF(RTW_DEBUG_RECV_DESC,
1824 ("%s: reg[RDSAR] <- %u\n", sc->sc_ic.ic_if.if_xname,
1827 RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR);
1831 rtw_swring_setup(struct rtw_softc *sc)
1835 rtw_txdesc_blk_init_all(sc);
1836 rtw_txsoft_blk_init_all(sc);
1838 rc = rtw_rxsoft_blk_init_all(sc);
1840 if_printf(&sc->sc_ic.ic_if, "could not allocate rx buffers\n");
1844 rtw_rxdesc_blk_init_all(sc);
1845 sc->sc_rxdesc_blk.rdb_next = 0;
1850 rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb)
1852 return (le32toh(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) /
1853 sizeof(struct rtw_txdesc);
1857 rtw_txring_fixup(struct rtw_softc *sc)
1859 struct rtw_regs *regs = &sc->sc_regs;
1862 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1863 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[pri];
1866 next = rtw_txring_next(regs, tdb);
1867 if (tdb->tdb_next == next)
1869 if_printf(&sc->sc_ic.ic_if,
1870 "tx-ring %d expected next %d, read %d\n",
1871 pri, tdb->tdb_next, next);
1872 tdb->tdb_next = MIN(next, tdb->tdb_ndesc - 1);
1877 rtw_rxring_fixup(struct rtw_softc *sc)
1879 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
1883 rdsar = le32toh(RTW_READ(&sc->sc_regs, RTW_RDSAR));
1884 next = (rdsar - rdb->rdb_base) / sizeof(struct rtw_rxdesc);
1886 if (rdb->rdb_next != next) {
1887 if_printf(&sc->sc_ic.ic_if,
1888 "rx-ring expected next %d, read %d\n",
1889 rdb->rdb_next, next);
1890 rdb->rdb_next = MIN(next, rdb->rdb_ndesc - 1);
1895 rtw_txdesc_blk_reset_all(struct rtw_softc *sc)
1899 for (pri = 0; pri < RTW_NTXPRI; pri++) {
1900 rtw_collect_txring(sc, &sc->sc_txsoft_blk[pri],
1901 &sc->sc_txdesc_blk[pri], 1);
1906 rtw_intr_ioerror(struct rtw_softc *sc, uint16_t isr)
1908 struct rtw_regs *regs = &sc->sc_regs;
1909 int xmtr = 0, rcvr = 0;
1912 if (isr & RTW_INTR_TXFOVW) {
1913 if_printf(&sc->sc_ic.ic_if, "tx fifo underflow\n");
1915 cr |= RTW_CR_TE | RTW_CR_RE;
1918 if (isr & (RTW_INTR_RDU | RTW_INTR_RXFOVW)) {
1923 RTW_DPRINTF(RTW_DEBUG_BUGS,
1924 ("%s: restarting xmit/recv, isr %04x\n",
1925 sc->sc_ic.ic_if.if_xname, isr));
1929 #endif /* RTW_DEBUG */
1931 rtw_io_enable(sc, cr, 0);
1933 /* Collect rx'd packets. Refresh rx buffers. */
1938 * Collect tx'd packets.
1939 * XXX let's hope this stops the transmit timeouts.
1942 rtw_txdesc_blk_reset_all(sc);
1944 RTW_WRITE16(regs, RTW_IMR, 0);
1945 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1947 if (rtw_do_chip_reset) {
1948 rtw_chip_reset1(sc);
1949 rtw_wep_setkeys(sc);
1952 rtw_rxdesc_blk_init_all(sc);
1956 #endif /* RTW_DEBUG */
1958 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
1959 RTW_SYNC(regs, RTW_IMR, RTW_IMR);
1962 rtw_rxring_fixup(sc);
1964 rtw_io_enable(sc, cr, 1);
1967 rtw_txring_fixup(sc);
1970 static __inline void
1971 rtw_suspend_ticks(struct rtw_softc *sc)
1973 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1974 ("%s: suspending ticks\n", sc->sc_ic.ic_if.if_xname));
1979 rtw_resume_ticks(struct rtw_softc *sc)
1981 uint32_t tsftrl0, tsftrl1, next_tick;
1982 struct rtw_regs *regs = &sc->sc_regs;
1984 tsftrl0 = RTW_READ(regs, RTW_TSFTRL);
1986 tsftrl1 = RTW_READ(regs, RTW_TSFTRL);
1987 next_tick = tsftrl1 + 1000000;
1988 RTW_WRITE(regs, RTW_TINT, next_tick);
1992 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
1993 ("%s: resume ticks delta %#08x now %#08x next %#08x\n",
1994 sc->sc_ic.ic_if.if_xname, tsftrl1 - tsftrl0, tsftrl1,
1999 rtw_intr_timeout(struct rtw_softc *sc)
2001 RTW_DPRINTF(RTW_DEBUG_TIMEOUT,
2002 ("%s: timeout\n", sc->sc_ic.ic_if.if_xname));
2004 rtw_resume_ticks(sc);
2010 struct rtw_softc *sc = arg;
2011 struct rtw_regs *regs = &sc->sc_regs;
2012 struct ifnet *ifp = &sc->sc_if;
2016 * If the interface isn't running, the interrupt couldn't
2017 * possibly have come from us.
2019 if ((sc->sc_flags & RTW_F_ENABLED) == 0 ||
2020 (ifp->if_flags & IFF_RUNNING) == 0) {
2021 RTW_DPRINTF(RTW_DEBUG_INTR,
2022 ("%s: stray interrupt\n", ifp->if_xname));
2026 for (i = 0; i < 10; i++) {
2029 isr = RTW_READ16(regs, RTW_ISR);
2031 RTW_WRITE16(regs, RTW_ISR, isr);
2032 RTW_WBR(regs, RTW_ISR, RTW_ISR);
2034 if (sc->sc_intr_ack != NULL)
2035 sc->sc_intr_ack(regs);
2041 #define PRINTINTR(flag) do { \
2042 if ((isr & flag) != 0) { \
2043 kprintf("%s" #flag, delim); \
2048 if ((rtw_debug & RTW_DEBUG_INTR) != 0 && isr != 0) {
2049 const char *delim = "<";
2051 if_printf(ifp, "reg[ISR] = %x", isr);
2053 PRINTINTR(RTW_INTR_TXFOVW);
2054 PRINTINTR(RTW_INTR_TIMEOUT);
2055 PRINTINTR(RTW_INTR_BCNINT);
2056 PRINTINTR(RTW_INTR_ATIMINT);
2057 PRINTINTR(RTW_INTR_TBDER);
2058 PRINTINTR(RTW_INTR_TBDOK);
2059 PRINTINTR(RTW_INTR_THPDER);
2060 PRINTINTR(RTW_INTR_THPDOK);
2061 PRINTINTR(RTW_INTR_TNPDER);
2062 PRINTINTR(RTW_INTR_TNPDOK);
2063 PRINTINTR(RTW_INTR_RXFOVW);
2064 PRINTINTR(RTW_INTR_RDU);
2065 PRINTINTR(RTW_INTR_TLPDER);
2066 PRINTINTR(RTW_INTR_TLPDOK);
2067 PRINTINTR(RTW_INTR_RER);
2068 PRINTINTR(RTW_INTR_ROK);
2073 #endif /* RTW_DEBUG */
2075 if (isr & RTW_INTR_RX)
2076 rtw_intr_rx(sc, isr & RTW_INTR_RX);
2077 if (isr & RTW_INTR_TX)
2078 rtw_intr_tx(sc, isr & RTW_INTR_TX);
2079 if (isr & RTW_INTR_BEACON)
2080 rtw_intr_beacon(sc, isr & RTW_INTR_BEACON);
2081 if (isr & RTW_INTR_ATIMINT)
2083 if (isr & RTW_INTR_IOERROR)
2084 rtw_intr_ioerror(sc, isr & RTW_INTR_IOERROR);
2085 if (isr & RTW_INTR_TIMEOUT)
2086 rtw_intr_timeout(sc);
2090 /* Must be called at splnet. */
2092 rtw_stop(struct rtw_softc *sc, int disable)
2094 struct ieee80211com *ic = &sc->sc_ic;
2095 struct ifnet *ifp = &ic->ic_if;
2096 struct rtw_regs *regs = &sc->sc_regs;
2099 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2102 rtw_suspend_ticks(sc);
2104 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2106 if ((sc->sc_flags & RTW_F_INVALID) == 0) {
2107 /* Disable interrupts. */
2108 RTW_WRITE16(regs, RTW_IMR, 0);
2110 RTW_WBW(regs, RTW_TPPOLL, RTW_IMR);
2113 * Stop the transmit and receive processes. First stop DMA,
2114 * then disable receiver and transmitter.
2116 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
2118 RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR);
2120 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2123 /* Free pending TX mbufs */
2124 for (i = 0; i < RTW_NTXPRI; ++i) {
2125 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[i];
2126 struct rtw_txsoft *ts;
2128 while ((ts = STAILQ_FIRST(&tsb->tsb_dirtyq)) != NULL) {
2129 rtw_txsoft_release(sc->sc_txsoft_dmat, ts, 0, 0, 0, 0);
2130 STAILQ_REMOVE_HEAD(&tsb->tsb_dirtyq, ts_q);
2131 STAILQ_INSERT_TAIL(&tsb->tsb_freeq, ts, ts_q);
2133 tsb->tsb_tx_timer = 0;
2136 /* Free pending RX mbufs */
2137 for (i = 0; i < RTW_RXQLEN; i++) {
2138 struct rtw_rxsoft *rs = &sc->sc_rxsoft[i];
2140 if (rs->rs_mbuf != NULL) {
2141 bus_dmamap_sync(sc->sc_rxsoft_dmat, rs->rs_dmamap,
2142 BUS_DMASYNC_POSTREAD);
2143 bus_dmamap_unload(sc->sc_rxsoft_dmat, rs->rs_dmamap);
2144 m_freem(rs->rs_mbuf);
2152 /* Mark the interface as not running. Cancel the watchdog timer. */
2153 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2159 rtw_pwrstate_string(enum rtw_pwrstate power)
2172 #endif /* RTW_DEBUG */
2175 * XXX For Maxim, I am using the RFMD settings gleaned from the
2176 * reference driver, plus a magic Maxim "ON" value that comes from
2177 * the Realtek document "Windows PG for Rtl8180."
2180 rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2181 int before_rf, int digphy)
2185 anaparm = RTW_READ(regs, RTW_ANAPARM);
2186 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2192 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_OFF;
2193 anaparm |= RTW_ANAPARM_TXDACOFF;
2198 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_SLEEP;
2199 anaparm |= RTW_ANAPARM_TXDACOFF;
2204 anaparm |= RTW_ANAPARM_RFPOW_MAXIM_ON;
2207 RTW_DPRINTF(RTW_DEBUG_PWR,
2208 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2209 __func__, rtw_pwrstate_string(power),
2210 (before_rf) ? "before" : "after", anaparm));
2212 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2213 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2216 /* XXX I am using the RFMD settings gleaned from the reference
2217 * driver. They agree
2220 rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2221 int before_rf, int digphy)
2225 anaparm = RTW_READ(regs, RTW_ANAPARM);
2226 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2232 anaparm |= RTW_ANAPARM_RFPOW_RFMD_OFF;
2233 anaparm |= RTW_ANAPARM_TXDACOFF;
2238 anaparm |= RTW_ANAPARM_RFPOW_RFMD_SLEEP;
2239 anaparm |= RTW_ANAPARM_TXDACOFF;
2244 anaparm |= RTW_ANAPARM_RFPOW_RFMD_ON;
2247 RTW_DPRINTF(RTW_DEBUG_PWR,
2248 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2249 __func__, rtw_pwrstate_string(power),
2250 (before_rf) ? "before" : "after", anaparm));
2252 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2253 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2257 rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
2258 int before_rf, int digphy)
2262 anaparm = RTW_READ(regs, RTW_ANAPARM);
2263 anaparm &= ~(RTW_ANAPARM_RFPOW_MASK | RTW_ANAPARM_TXDACOFF);
2269 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_OFF;
2270 anaparm |= RTW_ANAPARM_TXDACOFF;
2275 anaparm |= RTW_ANAPARM_RFPOW_PHILIPS_SLEEP;
2276 anaparm |= RTW_ANAPARM_TXDACOFF;
2282 anaparm |= RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON;
2284 anaparm |= RTW_ANAPARM_TXDACOFF;
2286 anaparm |= RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON;
2289 RTW_DPRINTF(RTW_DEBUG_PWR,
2290 ("%s: power state %s, %s RF, reg[ANAPARM] <- %08x\n",
2291 __func__, rtw_pwrstate_string(power),
2292 (before_rf) ? "before" : "after", anaparm));
2294 RTW_WRITE(regs, RTW_ANAPARM, anaparm);
2295 RTW_SYNC(regs, RTW_ANAPARM, RTW_ANAPARM);
2298 static __inline void
2299 rtw_pwrstate0(struct rtw_softc *sc, enum rtw_pwrstate power, int before_rf,
2302 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2303 sc->sc_pwrstate_cb(&sc->sc_regs, power, before_rf, digphy);
2304 rtw_set_access(sc, RTW_ACCESS_NONE);
2308 rtw_pwrstate(struct rtw_softc *sc, enum rtw_pwrstate power)
2312 RTW_DPRINTF(RTW_DEBUG_PWR,
2313 ("%s: %s->%s\n", sc->sc_ic.ic_if.if_xname,
2314 rtw_pwrstate_string(sc->sc_pwrstate),
2315 rtw_pwrstate_string(power)));
2317 if (sc->sc_pwrstate == power)
2320 rtw_pwrstate0(sc, power, 1, sc->sc_flags & RTW_F_DIGPHY);
2321 rc = rtw_rf_pwrstate(sc->sc_rf, power);
2322 rtw_pwrstate0(sc, power, 0, sc->sc_flags & RTW_F_DIGPHY);
2336 sc->sc_pwrstate = power;
2338 sc->sc_pwrstate = RTW_OFF;
2343 rtw_tune(struct rtw_softc *sc)
2345 struct ieee80211com *ic = &sc->sc_ic;
2346 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
2347 struct rtw_rx_radiotap_header *rr = &sc->sc_rxtap;
2349 int rc, antdiv, dflantb;
2351 antdiv = sc->sc_flags & RTW_F_ANTDIV;
2352 dflantb = sc->sc_flags & RTW_F_DFLANTB;
2354 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
2355 if (chan == IEEE80211_CHAN_ANY)
2356 panic("%s: chan == IEEE80211_CHAN_ANY", ic->ic_if.if_xname);
2358 rt->rt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2359 rt->rt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2361 rr->rr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2362 rr->rr_chan_flags = htole16(ic->ic_curchan->ic_flags);
2364 if (chan == sc->sc_cur_chan) {
2365 RTW_DPRINTF(RTW_DEBUG_TUNE,
2366 ("%s: already tuned chan #%d\n",
2367 ic->ic_if.if_xname, chan));
2371 rtw_suspend_ticks(sc);
2373 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 0);
2375 /* TBD wait for Tx to complete */
2377 KKASSERT((sc->sc_flags & RTW_F_ENABLED) != 0);
2379 rc = rtw_phy_init(&sc->sc_regs, sc->sc_rf,
2380 rtw_chan2txpower(&sc->sc_srom, ic, ic->ic_curchan),
2381 sc->sc_csthr, ic->ic_curchan->ic_freq, antdiv,
2384 /* XXX condition on powersaving */
2385 kprintf("%s: phy init failed\n", ic->ic_if.if_xname);
2388 sc->sc_cur_chan = chan;
2390 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2392 rtw_resume_ticks(sc);
2398 rtw_disable(struct rtw_softc *sc)
2402 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
2406 if ((sc->sc_flags & RTW_F_INVALID) == 0 &&
2407 (rc = rtw_pwrstate(sc, RTW_OFF)) != 0)
2408 if_printf(&sc->sc_ic.ic_if, "failed to turn off PHY\n");
2410 sc->sc_flags &= ~RTW_F_ENABLED;
2414 rtw_enable(struct rtw_softc *sc)
2416 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
2417 sc->sc_flags |= RTW_F_ENABLED;
2419 * Power may have been removed, and WEP keys thus reset.
2421 sc->sc_flags &= ~RTW_F_DK_VALID;
2427 rtw_transmit_config(struct rtw_regs *regs)
2431 tcr = RTW_READ(regs, RTW_TCR);
2433 tcr |= RTW_TCR_CWMIN;
2434 tcr &= ~RTW_TCR_MXDMA_MASK;
2435 tcr |= RTW_TCR_MXDMA_256;
2436 tcr |= RTW_TCR_SAT; /* send ACK as fast as possible */
2437 tcr &= ~RTW_TCR_LBK_MASK;
2438 tcr |= RTW_TCR_LBK_NORMAL; /* normal operating mode */
2440 /* set short/long retry limits */
2441 tcr &= ~(RTW_TCR_SRL_MASK|RTW_TCR_LRL_MASK);
2442 tcr |= __SHIFTIN(4, RTW_TCR_SRL_MASK) | __SHIFTIN(4, RTW_TCR_LRL_MASK);
2444 tcr &= ~RTW_TCR_CRC; /* NIC appends CRC32 */
2446 RTW_WRITE(regs, RTW_TCR, tcr);
2447 RTW_SYNC(regs, RTW_TCR, RTW_TCR);
2451 rtw_enable_interrupts(struct rtw_softc *sc)
2453 struct rtw_regs *regs = &sc->sc_regs;
2455 sc->sc_inten = RTW_INTR_RX|RTW_INTR_TX|RTW_INTR_BEACON|RTW_INTR_ATIMINT;
2456 sc->sc_inten |= RTW_INTR_IOERROR|RTW_INTR_TIMEOUT;
2458 RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
2459 RTW_WBW(regs, RTW_IMR, RTW_ISR);
2460 RTW_WRITE16(regs, RTW_ISR, 0xffff);
2461 RTW_SYNC(regs, RTW_IMR, RTW_ISR);
2463 /* XXX necessary? */
2464 if (sc->sc_intr_ack != NULL)
2465 sc->sc_intr_ack(regs);
2469 rtw_set_nettype(struct rtw_softc *sc, enum ieee80211_opmode opmode)
2471 struct rtw_regs *regs = &sc->sc_regs;
2474 /* I'm guessing that MSR is protected as CONFIG[0123] are. */
2475 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2477 msr = RTW_READ8(regs, RTW_MSR) & ~RTW_MSR_NETYPE_MASK;
2480 case IEEE80211_M_AHDEMO:
2481 case IEEE80211_M_IBSS:
2482 msr |= RTW_MSR_NETYPE_ADHOC_OK;
2484 case IEEE80211_M_HOSTAP:
2485 msr |= RTW_MSR_NETYPE_AP_OK;
2487 case IEEE80211_M_MONITOR:
2489 msr |= RTW_MSR_NETYPE_NOLINK;
2491 case IEEE80211_M_STA:
2492 msr |= RTW_MSR_NETYPE_INFRA_OK;
2495 RTW_WRITE8(regs, RTW_MSR, msr);
2497 rtw_set_access(sc, RTW_ACCESS_NONE);
2500 #define rtw_calchash(addr) \
2501 (ether_crc32_be((addr), IEEE80211_ADDR_LEN) >> 26)
2504 rtw_pktfilt_load(struct rtw_softc *sc)
2506 struct rtw_regs *regs = &sc->sc_regs;
2507 struct ieee80211com *ic = &sc->sc_ic;
2508 struct ifnet *ifp = &ic->ic_if;
2509 struct ifmultiaddr *ifma;
2510 uint32_t hashes[2] = { 0, 0 };
2513 /* XXX might be necessary to stop Rx/Tx engines while setting filters */
2515 sc->sc_rcr &= ~RTW_RCR_PKTFILTER_MASK;
2516 sc->sc_rcr &= ~(RTW_RCR_MXDMA_MASK | RTW_RCR_RXFTH_MASK);
2518 sc->sc_rcr |= RTW_RCR_PKTFILTER_DEFAULT;
2519 /* MAC auto-reset PHY (huh?) */
2520 sc->sc_rcr |= RTW_RCR_ENMARP;
2521 /* DMA whole Rx packets, only. Set Tx DMA burst size to 1024 bytes. */
2522 sc->sc_rcr |= RTW_RCR_MXDMA_1024 | RTW_RCR_RXFTH_WHOLE;
2524 switch (ic->ic_opmode) {
2525 case IEEE80211_M_MONITOR:
2526 sc->sc_rcr |= RTW_RCR_MONITOR;
2528 case IEEE80211_M_AHDEMO:
2529 case IEEE80211_M_IBSS:
2530 /* receive broadcasts in our BSS */
2531 sc->sc_rcr |= RTW_RCR_ADD3;
2537 ifp->if_flags &= ~IFF_ALLMULTI;
2539 /* XXX accept all broadcast if scanning */
2540 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2541 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2543 if (ifp->if_flags & IFF_PROMISC) {
2544 sc->sc_rcr |= RTW_RCR_AB; /* accept all broadcast */
2546 ifp->if_flags |= IFF_ALLMULTI;
2551 * Program the 64-bit multicast hash filter.
2553 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2554 if (ifma->ifma_addr->sa_family != AF_LINK)
2557 hash = rtw_calchash(
2558 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
2559 hashes[hash >> 5] |= (1 << (hash & 0x1f));
2560 sc->sc_rcr |= RTW_RCR_AM;
2563 /* all bits set => hash is useless */
2564 if (~(hashes[0] & hashes[1]) == 0)
2568 if (ifp->if_flags & IFF_ALLMULTI) {
2569 sc->sc_rcr |= RTW_RCR_AM; /* accept all multicast */
2570 hashes[0] = hashes[1] = 0xffffffff;
2573 RTW_WRITE(regs, RTW_MAR0, hashes[0]);
2574 RTW_WRITE(regs, RTW_MAR1, hashes[1]);
2575 RTW_WRITE(regs, RTW_RCR, sc->sc_rcr);
2576 RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */
2578 DPRINTF(sc, RTW_DEBUG_PKTFILT,
2579 ("%s: RTW_MAR0 %08x RTW_MAR1 %08x RTW_RCR %08x\n",
2580 ifp->if_xname, RTW_READ(regs, RTW_MAR0),
2581 RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR)));
2584 /* Must be called at splnet. */
2588 struct rtw_softc *sc = xsc;
2589 struct ieee80211com *ic = &sc->sc_ic;
2590 struct ifnet *ifp = &ic->ic_if;
2591 struct rtw_regs *regs = &sc->sc_regs;
2594 rc = rtw_enable(sc);
2598 /* Cancel pending I/O and reset. */
2601 DPRINTF(sc, RTW_DEBUG_TUNE,
2602 ("%s: channel %d freq %d flags 0x%04x\n", ifp->if_xname,
2603 ieee80211_chan2ieee(ic, ic->ic_curchan),
2604 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
2606 rc = rtw_pwrstate(sc, RTW_OFF);
2610 rc = rtw_swring_setup(sc);
2614 rtw_transmit_config(regs);
2616 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2618 RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */
2619 RTW_WBW(regs, RTW_MSR, RTW_BRSR);
2621 /* long PLCP header, 1Mb/2Mb basic rate */
2622 RTW_WRITE16(regs, RTW_BRSR, RTW_BRSR_MBR8180_2MBPS);
2623 RTW_SYNC(regs, RTW_BRSR, RTW_BRSR);
2625 rtw_set_access(sc, RTW_ACCESS_ANAPARM);
2626 rtw_set_access(sc, RTW_ACCESS_NONE);
2628 /* XXX from reference sources */
2629 RTW_WRITE(regs, RTW_FEMR, 0xffff);
2630 RTW_SYNC(regs, RTW_FEMR, RTW_FEMR);
2634 RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay);
2635 /* from Linux driver */
2636 RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC);
2638 RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT);
2640 rtw_enable_interrupts(sc);
2642 rtw_pktfilt_load(sc);
2644 rtw_hwring_setup(sc);
2646 rtw_wep_setkeys(sc);
2648 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
2650 ifp->if_flags |= IFF_RUNNING;
2651 ic->ic_state = IEEE80211_S_INIT;
2653 RTW_WRITE16(regs, RTW_BSSID16, 0x0);
2654 RTW_WRITE(regs, RTW_BSSID32, 0x0);
2656 rtw_resume_ticks(sc);
2658 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
2660 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2661 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
2663 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
2667 if_printf(ifp, "interface not running\n");
2671 rtw_led_init(struct rtw_softc *sc)
2673 struct rtw_regs *regs = &sc->sc_regs;
2676 rtw_set_access(sc, RTW_ACCESS_CONFIG);
2678 cfg0 = RTW_READ8(regs, RTW_CONFIG0);
2679 cfg0 |= RTW_CONFIG0_LEDGPOEN;
2680 RTW_WRITE8(regs, RTW_CONFIG0, cfg0);
2682 cfg1 = RTW_READ8(regs, RTW_CONFIG1);
2683 RTW_DPRINTF(RTW_DEBUG_LED,
2684 ("%s: read %02x from reg[CONFIG1]\n",
2685 sc->sc_ic.ic_if.if_xname, cfg1));
2687 cfg1 &= ~RTW_CONFIG1_LEDS_MASK;
2688 cfg1 |= RTW_CONFIG1_LEDS_TX_RX;
2689 RTW_WRITE8(regs, RTW_CONFIG1, cfg1);
2691 rtw_set_access(sc, RTW_ACCESS_NONE);
2695 * IEEE80211_S_INIT: LED1 off
2698 * IEEE80211_S_ASSOC,
2699 * IEEE80211_S_SCAN: LED1 blinks @ 1 Hz, blinks at 5Hz for tx/rx
2701 * IEEE80211_S_RUN: LED1 on, blinks @ 5Hz for tx/rx
2704 rtw_led_newstate(struct rtw_softc *sc, enum ieee80211_state nstate)
2706 struct rtw_led_state *ls = &sc->sc_led_state;
2709 case IEEE80211_S_INIT:
2711 callout_stop(&ls->ls_slow_ch);
2712 callout_stop(&ls->ls_fast_ch);
2713 ls->ls_slowblink = 0;
2714 ls->ls_actblink = 0;
2717 case IEEE80211_S_SCAN:
2718 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2719 rtw_led_slowblink, sc);
2720 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2721 rtw_led_fastblink, sc);
2723 case IEEE80211_S_AUTH:
2724 case IEEE80211_S_ASSOC:
2725 ls->ls_default = RTW_LED1;
2726 ls->ls_actblink = RTW_LED1;
2727 ls->ls_slowblink = RTW_LED1;
2729 case IEEE80211_S_RUN:
2730 ls->ls_slowblink = 0;
2737 rtw_led_set(struct rtw_softc *sc)
2739 struct rtw_led_state *ls = &sc->sc_led_state;
2740 struct rtw_regs *regs = &sc->sc_regs;
2741 uint8_t led_condition, mask, newval, val;
2744 led_condition = ls->ls_default;
2746 if (ls->ls_state & RTW_LED_S_SLOW)
2747 led_condition ^= ls->ls_slowblink;
2748 if (ls->ls_state & (RTW_LED_S_RX|RTW_LED_S_TX))
2749 led_condition ^= ls->ls_actblink;
2751 RTW_DPRINTF(RTW_DEBUG_LED,
2752 ("%s: LED condition %02x\n", sc->sc_ic.ic_if.if_xname,
2755 switch (sc->sc_hwverid) {
2759 newval = mask = RTW_PSR_LEDGPO0 | RTW_PSR_LEDGPO1;
2760 if (led_condition & RTW_LED0)
2761 newval &= ~RTW_PSR_LEDGPO0;
2762 if (led_condition & RTW_LED1)
2763 newval &= ~RTW_PSR_LEDGPO1;
2767 mask = RTW_9346CR_EEM_MASK | RTW_9346CR_EEDI | RTW_9346CR_EECS;
2768 newval = RTW_9346CR_EEM_PROGRAM;
2769 if (led_condition & RTW_LED0)
2770 newval |= RTW_9346CR_EEDI;
2771 if (led_condition & RTW_LED1)
2772 newval |= RTW_9346CR_EECS;
2775 val = RTW_READ8(regs, ofs);
2776 RTW_DPRINTF(RTW_DEBUG_LED,
2777 ("%s: read %02x from reg[%02x]\n",
2778 sc->sc_ic.ic_if.if_xname, val, ofs));
2781 RTW_WRITE8(regs, ofs, val);
2782 RTW_DPRINTF(RTW_DEBUG_LED,
2783 ("%s: wrote %02x to reg[%02x]\n",
2784 sc->sc_ic.ic_if.if_xname, val, ofs));
2785 RTW_SYNC(regs, ofs, ofs);
2789 rtw_led_fastblink(void *arg)
2791 struct rtw_softc *sc = arg;
2792 struct ifnet *ifp = &sc->sc_ic.ic_if;
2793 struct rtw_led_state *ls = &sc->sc_led_state;
2796 lwkt_serialize_enter(ifp->if_serializer);
2798 ostate = ls->ls_state;
2799 ls->ls_state ^= ls->ls_event;
2801 if ((ls->ls_event & RTW_LED_S_TX) == 0)
2802 ls->ls_state &= ~RTW_LED_S_TX;
2804 if ((ls->ls_event & RTW_LED_S_RX) == 0)
2805 ls->ls_state &= ~RTW_LED_S_RX;
2809 if (ostate != ls->ls_state)
2812 callout_reset(&ls->ls_fast_ch, RTW_LED_FAST_TICKS,
2813 rtw_led_fastblink, sc);
2815 lwkt_serialize_exit(ifp->if_serializer);
2819 rtw_led_slowblink(void *arg)
2821 struct rtw_softc *sc = arg;
2822 struct ifnet *ifp = &sc->sc_ic.ic_if;
2823 struct rtw_led_state *ls = &sc->sc_led_state;
2825 lwkt_serialize_enter(ifp->if_serializer);
2827 ls->ls_state ^= RTW_LED_S_SLOW;
2829 callout_reset(&ls->ls_slow_ch, RTW_LED_SLOW_TICKS,
2830 rtw_led_slowblink, sc);
2832 lwkt_serialize_exit(ifp->if_serializer);
2836 rtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
2838 struct rtw_softc *sc = ifp->if_softc;
2843 if (ifp->if_flags & IFF_UP) {
2844 if ((ifp->if_flags & IFF_RUNNING) == 0)
2846 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2847 } else if (sc->sc_flags & RTW_F_ENABLED) {
2848 RTW_PRINT_REGS(&sc->sc_regs, ifp->if_xname, __func__);
2854 if (ifp->if_flags & IFF_RUNNING)
2855 rtw_pktfilt_load(sc);
2858 rc = ieee80211_ioctl(&sc->sc_ic, cmd, data, cr);
2859 if (rc == ENETRESET) {
2860 if (sc->sc_flags & RTW_F_ENABLED)
2870 * Select a transmit ring with at least one h/w and s/w descriptor free.
2871 * Return 0 on success, -1 on failure.
2874 rtw_txring_choose(struct rtw_softc *sc, struct rtw_txsoft_blk **tsbp,
2875 struct rtw_txdesc_blk **tdbp, int pri)
2877 struct rtw_txsoft_blk *tsb;
2878 struct rtw_txdesc_blk *tdb;
2880 KKASSERT(pri >= 0 && pri < RTW_NTXPRI);
2882 tsb = &sc->sc_txsoft_blk[pri];
2883 tdb = &sc->sc_txdesc_blk[pri];
2885 if (STAILQ_EMPTY(&tsb->tsb_freeq) || tdb->tdb_nfree == 0) {
2886 if (tsb->tsb_tx_timer == 0)
2887 tsb->tsb_tx_timer = 5;
2897 static __inline struct mbuf *
2898 rtw_80211_dequeue(struct rtw_softc *sc, struct ifqueue *ifq, int pri,
2899 struct rtw_txsoft_blk **tsbp, struct rtw_txdesc_blk **tdbp,
2900 struct ieee80211_node **nip, int *if_flagsp)
2903 struct ifnet *ifp = &sc->sc_if;
2907 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2908 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2909 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2910 *if_flagsp |= IFF_OACTIVE;
2915 *nip = (struct ieee80211_node *)m->m_pkthdr.rcvif;
2916 m->m_pkthdr.rcvif = NULL;
2917 KKASSERT(*nip != NULL);
2922 * Point *mp at the next 802.11 frame to transmit. Point *tsbp
2923 * at the driver's selection of transmit control block for the packet.
2926 rtw_dequeue(struct ifnet *ifp, struct rtw_txsoft_blk **tsbp,
2927 struct rtw_txdesc_blk **tdbp, struct mbuf **mp,
2928 struct ieee80211_node **nip)
2930 struct rtw_softc *sc = ifp->if_softc;
2931 int *if_flagsp = &ifp->if_flags;
2932 struct ether_header *eh;
2936 DPRINTF(sc, RTW_DEBUG_XMIT,
2937 ("%s: enter %s\n", ifp->if_xname, __func__));
2939 if (sc->sc_ic.ic_state == IEEE80211_S_RUN &&
2940 (*mp = rtw_80211_dequeue(sc, &sc->sc_beaconq, RTW_TXPRIBCN, tsbp,
2941 tdbp, nip, if_flagsp)) != NULL) {
2942 DPRINTF(sc, RTW_DEBUG_XMIT,
2943 ("%s: dequeue beacon frame\n", ifp->if_xname));
2947 if ((*mp = rtw_80211_dequeue(sc, &sc->sc_ic.ic_mgtq, RTW_TXPRIMD, tsbp,
2948 tdbp, nip, if_flagsp)) != NULL) {
2949 DPRINTF(sc, RTW_DEBUG_XMIT,
2950 ("%s: dequeue mgt frame\n", ifp->if_xname));
2956 if (sc->sc_ic.ic_state != IEEE80211_S_RUN) {
2957 ifq_purge(&ifp->if_snd);
2958 DPRINTF(sc, RTW_DEBUG_XMIT,
2959 ("%s: not running\n", ifp->if_xname));
2963 m0 = ifq_dequeue(&ifp->if_snd, NULL);
2965 DPRINTF(sc, RTW_DEBUG_XMIT,
2966 ("%s: no frame ready\n", ifp->if_xname));
2969 DPRINTF(sc, RTW_DEBUG_XMIT,
2970 ("%s: dequeue data frame\n", ifp->if_xname));
2972 pri = ((m0->m_flags & M_PWR_SAV) != 0) ? RTW_TXPRIHI : RTW_TXPRIMD;
2974 if (rtw_txring_choose(sc, tsbp, tdbp, pri) == -1) {
2975 DPRINTF(sc, RTW_DEBUG_XMIT_RSRC,
2976 ("%s: no ring %d descriptor\n", ifp->if_xname, pri));
2977 *if_flagsp |= IFF_OACTIVE;
2978 ifq_prepend(&ifp->if_snd, m0);
2979 sc->sc_if.if_timer = 1;
2985 eh = mtod(m0, struct ether_header *);
2986 *nip = ieee80211_find_txnode(&sc->sc_ic, eh->ether_dhost);
2988 /* NB: ieee80211_find_txnode does stat+msg */
2993 if ((m0 = ieee80211_encap(&sc->sc_ic, m0, *nip)) == NULL) {
2994 DPRINTF(sc, RTW_DEBUG_XMIT,
2995 ("%s: encap error\n", ifp->if_xname));
2996 ieee80211_free_node(*nip);
3002 DPRINTF(sc, RTW_DEBUG_XMIT,
3003 ("%s: leave %s\n", ifp->if_xname, __func__));
3009 rtw_txsegs_too_short(struct rtw_txsegs *segs)
3013 for (i = 0; i < segs->nseg; i++) {
3014 if (segs->segs[i].ds_len < 4)
3021 rtw_txsegs_too_long(struct rtw_txsegs *segs)
3025 for (i = 0; i < segs->nseg; i++) {
3026 if (segs->segs[i].ds_len > RTW_TXLEN_LENGTH_MASK)
3033 rtw_txbuf_dma_map(void *arg, bus_dma_segment_t *seg, int nseg,
3034 bus_size_t mapsize, int error)
3036 struct rtw_txsegs *s = arg;
3041 KASSERT(nseg <= RTW_MAXPKTSEGS, ("too many tx mbuf seg"));
3044 bcopy(seg, s->segs, sizeof(*seg) * nseg);
3047 static struct mbuf *
3048 rtw_load_txbuf(struct rtw_softc *sc, struct rtw_txsoft *ts,
3049 struct rtw_txsegs *segs, int ndesc_free, struct mbuf *m)
3051 int unload = 0, error;
3053 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap, m,
3054 rtw_txbuf_dma_map, segs, BUS_DMA_NOWAIT);
3055 if (error && error != EFBIG) {
3056 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf1\n");
3060 if (error || segs->nseg > ndesc_free || rtw_txsegs_too_short(segs)) {
3064 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3066 m_new = m_defrag(m, MB_DONTWAIT);
3067 if (m_new == NULL) {
3068 if_printf(&sc->sc_ic.ic_if, "can't defrag tx mbuf\n");
3074 error = bus_dmamap_load_mbuf(sc->sc_txsoft_dmat, ts->ts_dmamap,
3075 m, rtw_txbuf_dma_map, segs,
3078 if_printf(&sc->sc_ic.ic_if, "can't load tx mbuf2\n");
3084 if (segs->nseg > ndesc_free) {
3085 if_printf(&sc->sc_ic.ic_if, "not enough free txdesc\n");
3088 if (rtw_txsegs_too_short(segs)) {
3089 if_printf(&sc->sc_ic.ic_if, "segment too short\n");
3095 if (rtw_txsegs_too_long(segs)) {
3096 if_printf(&sc->sc_ic.ic_if, "segment too long\n");
3104 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3108 bus_dmamap_sync(sc->sc_txsoft_dmat, ts->ts_dmamap,
3109 BUS_DMASYNC_PREWRITE);
3116 rtw_print_txdesc(struct rtw_softc *sc, const char *action,
3117 struct rtw_txsoft *ts, struct rtw_txdesc_blk *tdb, int desc)
3119 struct rtw_txdesc *td = &tdb->tdb_desc[desc];
3121 DPRINTF(sc, RTW_DEBUG_XMIT_DESC,
3122 ("%s: %p %s txdesc[%d] "
3123 "next %#08x buf %#08x "
3124 "ctl0 %#08x ctl1 %#08x len %#08x\n",
3125 sc->sc_ic.ic_if.if_xname, ts, action,
3126 desc, le32toh(td->td_buf), le32toh(td->td_next),
3127 le32toh(td->td_ctl0), le32toh(td->td_ctl1),
3128 le32toh(td->td_len)));
3130 #endif /* RTW_DEBUG */
3133 rtw_start(struct ifnet *ifp)
3135 struct rtw_softc *sc = ifp->if_softc;
3136 struct ieee80211com *ic = &sc->sc_ic;
3137 struct ieee80211_node *ni;
3138 struct rtw_txsoft *ts;
3140 uint32_t proto_ctl0;
3142 DPRINTF(sc, RTW_DEBUG_XMIT,
3143 ("%s: enter %s\n", ifp->if_xname, __func__));
3145 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3148 /* XXX do real rate control */
3149 proto_ctl0 = RTW_TXCTL0_RTSRATE_1MBPS;
3151 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
3152 proto_ctl0 |= RTW_TXCTL0_SPLCP;
3155 struct rtw_txsegs segs;
3156 struct rtw_duration *d0;
3157 struct ieee80211_frame_min *wh;
3158 struct rtw_txsoft_blk *tsb;
3159 struct rtw_txdesc_blk *tdb;
3160 struct rtw_txdesc *td;
3161 struct ieee80211_key *k;
3162 uint32_t ctl0, ctl1;
3164 int desc, i, lastdesc, npkt, rate, rateidx, ratectl;
3166 if (rtw_dequeue(ifp, &tsb, &tdb, &m0, &ni) == -1)
3171 wh = mtod(m0, struct ieee80211_frame_min *);
3173 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) != 0 &&
3174 (k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
3175 ieee80211_free_node(ni);
3182 ts = STAILQ_FIRST(&tsb->tsb_freeq);
3184 m0 = rtw_load_txbuf(sc, ts, &segs, tdb->tdb_nfree, m0);
3185 if (m0 == NULL || segs.nseg == 0) {
3186 DPRINTF(sc, RTW_DEBUG_XMIT,
3187 ("%s: %s failed\n", ifp->if_xname, __func__));
3188 goto post_dequeue_err;
3192 * Note well: rtw_load_txbuf may have created a new chain,
3193 * so we must find the header once more.
3195 wh = mtod(m0, struct ieee80211_frame_min *);
3197 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3198 IEEE80211_FC0_TYPE_MGT) {
3200 rate = 2; /* 1Mbit/s */
3203 ieee80211_ratectl_findrate(ni, m0->m_pkthdr.len,
3205 rate = IEEE80211_RS_RATE(&ni->ni_rates, rateidx);
3209 if_printf(ifp, "incorrect rate\n");
3211 rate = 2; /* 1Mbit/s */
3217 if ((ifp->if_flags & (IFF_DEBUG | IFF_LINK2)) ==
3218 (IFF_DEBUG | IFF_LINK2)) {
3219 ieee80211_dump_pkt(mtod(m0, uint8_t *),
3220 (segs.nseg == 1) ? m0->m_pkthdr.len
3224 #endif /* RTW_DEBUG */
3226 __SHIFTIN(m0->m_pkthdr.len, RTW_TXCTL0_TPKTSIZE_MASK);
3231 ctl0 |= RTW_TXCTL0_RATE_1MBPS;
3234 ctl0 |= RTW_TXCTL0_RATE_2MBPS;
3237 ctl0 |= RTW_TXCTL0_RATE_5MBPS;
3240 ctl0 |= RTW_TXCTL0_RATE_11MBPS;
3243 /* XXX >= ? Compare after fragmentation? */
3244 if (m0->m_pkthdr.len > ic->ic_rtsthreshold)
3245 ctl0 |= RTW_TXCTL0_RTSEN;
3248 * XXX Sometimes writes a bogus keyid; h/w doesn't
3249 * seem to care, since we don't activate h/w Tx
3253 ctl0 |= __SHIFTIN(k->wk_keyix, RTW_TXCTL0_KEYID_MASK) &
3254 RTW_TXCTL0_KEYID_MASK;
3257 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
3258 IEEE80211_FC0_TYPE_MGT) {
3259 ctl0 &= ~(RTW_TXCTL0_SPLCP | RTW_TXCTL0_RTSEN);
3260 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
3261 IEEE80211_FC0_SUBTYPE_BEACON)
3262 ctl0 |= RTW_TXCTL0_BEACON;
3265 if (rtw_compute_duration(wh, k, m0->m_pkthdr.len,
3266 ic->ic_flags, ic->ic_fragthreshold,
3267 rate, &ts->ts_d0, &ts->ts_dn, &npkt,
3268 (ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) ==
3269 (IFF_DEBUG|IFF_LINK2)) == -1) {
3270 DPRINTF(sc, RTW_DEBUG_XMIT,
3271 ("%s: fail compute duration\n", __func__));
3277 *(uint16_t*)wh->i_dur = htole16(d0->d_data_dur);
3279 ctl1 = __SHIFTIN(d0->d_plcp_len, RTW_TXCTL1_LENGTH_MASK) |
3280 __SHIFTIN(d0->d_rts_dur, RTW_TXCTL1_RTSDUR_MASK);
3283 ctl1 |= RTW_TXCTL1_LENGEXT;
3285 /* TBD fragmentation */
3287 ts->ts_first = tdb->tdb_next;
3288 KKASSERT(ts->ts_first < tdb->tdb_ndesc);
3290 if (ic->ic_rawbpf != NULL)
3291 bpf_mtap(ic->ic_rawbpf, m0);
3293 if (sc->sc_radiobpf != NULL) {
3294 struct rtw_tx_radiotap_header *rt = &sc->sc_txtap;
3299 bpf_ptap(sc->sc_radiobpf, m0, rt,
3300 sizeof(sc->sc_txtapu));
3303 for (i = 0, lastdesc = desc = ts->ts_first; i < segs.nseg;
3304 i++, desc = RTW_NEXT_IDX(tdb, desc)) {
3305 td = &tdb->tdb_desc[desc];
3306 td->td_ctl0 = htole32(ctl0);
3308 td->td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3309 td->td_ctl1 = htole32(ctl1);
3310 td->td_buf = htole32(segs.segs[i].ds_addr);
3311 td->td_len = htole32(segs.segs[i].ds_len);
3314 rtw_print_txdesc(sc, "load", ts, tdb, desc);
3315 #endif /* RTW_DEBUG */
3318 KKASSERT(desc < tdb->tdb_ndesc);
3321 KKASSERT(ni != NULL);
3323 ts->ts_rateidx = rateidx;
3324 ts->ts_ratectl = ratectl;
3325 ts->ts_last = lastdesc;
3326 tdb->tdb_desc[ts->ts_last].td_ctl0 |= htole32(RTW_TXCTL0_LS);
3327 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_FS);
3330 rtw_print_txdesc(sc, "FS on", ts, tdb, ts->ts_first);
3331 rtw_print_txdesc(sc, "LS on", ts, tdb, ts->ts_last);
3332 #endif /* RTW_DEBUG */
3334 tdb->tdb_nfree -= segs.nseg;
3335 tdb->tdb_next = desc;
3337 tdb->tdb_desc[ts->ts_first].td_ctl0 |= htole32(RTW_TXCTL0_OWN);
3340 rtw_print_txdesc(sc, "OWN on", ts, tdb, ts->ts_first);
3341 #endif /* RTW_DEBUG */
3343 STAILQ_REMOVE_HEAD(&tsb->tsb_freeq, ts_q);
3344 STAILQ_INSERT_TAIL(&tsb->tsb_dirtyq, ts, ts_q);
3346 if (tsb != &sc->sc_txsoft_blk[RTW_TXPRIBCN])
3347 sc->sc_led_state.ls_event |= RTW_LED_S_TX;
3348 tsb->tsb_tx_timer = 5;
3350 tppoll = RTW_READ8(&sc->sc_regs, RTW_TPPOLL);
3351 tppoll &= ~RTW_TPPOLL_SALL;
3352 tppoll |= tsb->tsb_poll & RTW_TPPOLL_ALL;
3353 RTW_WRITE8(&sc->sc_regs, RTW_TPPOLL, tppoll);
3354 RTW_SYNC(&sc->sc_regs, RTW_TPPOLL, RTW_TPPOLL);
3356 bus_dmamap_sync(tdb->tdb_dmat, tdb->tdb_dmamap,
3357 BUS_DMASYNC_PREWRITE);
3360 DPRINTF(sc, RTW_DEBUG_XMIT,
3361 ("%s: leave %s\n", ifp->if_xname, __func__));
3365 bus_dmamap_unload(sc->sc_txsoft_dmat, ts->ts_dmamap);
3368 ieee80211_free_node(ni);
3370 DPRINTF(sc, RTW_DEBUG_XMIT,
3371 ("%s: leave %s\n", ifp->if_xname, __func__));
3375 rtw_idle(struct rtw_softc *sc)
3377 struct rtw_regs *regs = &sc->sc_regs;
3380 /* request stop DMA; wait for packets to stop transmitting. */
3382 RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
3383 RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL);
3387 (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0;
3390 if_printf(&sc->sc_ic.ic_if, "transmit DMA idle in %dus\n", active * 10);
3394 rtw_watchdog(struct ifnet *ifp)
3396 int pri, tx_timeouts = 0;
3397 struct rtw_softc *sc = ifp->if_softc;
3401 if ((sc->sc_flags & RTW_F_ENABLED) == 0)
3404 for (pri = 0; pri < RTW_NTXPRI; pri++) {
3405 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[pri];
3407 if (tsb->tsb_tx_timer == 0)
3409 else if (--tsb->tsb_tx_timer == 0) {
3410 if (STAILQ_EMPTY(&tsb->tsb_dirtyq))
3412 if_printf(ifp, "transmit timeout, priority %d\n", pri);
3420 if (tx_timeouts > 0) {
3422 * Stop Tx DMA, disable xmtr, flush Tx rings, enable xmtr,
3423 * reset s/w tx-ring pointers, and start transmission.
3425 * TBD Stop/restart just the broken rings?
3428 rtw_io_enable(sc, RTW_CR_TE, 0);
3429 rtw_txdesc_blk_reset_all(sc);
3430 rtw_io_enable(sc, RTW_CR_TE, 1);
3431 rtw_txring_fixup(sc);
3434 ieee80211_watchdog(&sc->sc_ic);
3438 rtw_next_scan(void *arg)
3440 struct ieee80211com *ic = arg;
3441 struct ifnet *ifp = &ic->ic_if;
3443 lwkt_serialize_enter(ifp->if_serializer);
3445 /* don't call rtw_start w/o network interrupts blocked */
3446 if (ic->ic_state == IEEE80211_S_SCAN)
3447 ieee80211_next_scan(ic);
3449 lwkt_serialize_exit(ifp->if_serializer);
3453 rtw_join_bss(struct rtw_softc *sc, uint8_t *bssid, uint16_t intval0)
3455 uint16_t bcnitv, bintritv, intval;
3457 struct rtw_regs *regs = &sc->sc_regs;
3459 for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3460 RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]);
3462 RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32);
3464 rtw_set_access(sc, RTW_ACCESS_CONFIG);
3466 intval = MIN(intval0, __SHIFTOUT_MASK(RTW_BCNITV_BCNITV_MASK));
3468 bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK;
3469 bcnitv |= __SHIFTIN(intval, RTW_BCNITV_BCNITV_MASK);
3470 RTW_WRITE16(regs, RTW_BCNITV, bcnitv);
3471 /* interrupt host 1ms before the TBTT */
3472 bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV;
3473 bintritv |= __SHIFTIN(1000, RTW_BINTRITV_BINTRITV);
3474 RTW_WRITE16(regs, RTW_BINTRITV, bintritv);
3475 /* magic from Linux */
3476 RTW_WRITE16(regs, RTW_ATIMWND, __SHIFTIN(1, RTW_ATIMWND_ATIMWND));
3477 RTW_WRITE16(regs, RTW_ATIMTRITV, __SHIFTIN(2, RTW_ATIMTRITV_ATIMTRITV));
3478 rtw_set_access(sc, RTW_ACCESS_NONE);
3480 rtw_io_enable(sc, RTW_CR_RE | RTW_CR_TE, 1);
3483 /* Synchronize the hardware state with the software state. */
3485 rtw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
3487 struct ifnet *ifp = ic->ic_ifp;
3488 struct rtw_softc *sc = ifp->if_softc;
3489 enum ieee80211_state ostate;
3492 ostate = ic->ic_state;
3494 ieee80211_ratectl_newstate(ic, nstate);
3495 rtw_led_newstate(sc, nstate);
3497 if (nstate == IEEE80211_S_INIT) {
3498 callout_stop(&sc->sc_scan_ch);
3499 sc->sc_cur_chan = IEEE80211_CHAN_ANY;
3500 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3503 if (ostate == IEEE80211_S_INIT && nstate != IEEE80211_S_INIT)
3504 rtw_pwrstate(sc, RTW_ON);
3506 error = rtw_tune(sc);
3511 case IEEE80211_S_INIT:
3512 panic("%s: unexpected state IEEE80211_S_INIT", __func__);
3514 case IEEE80211_S_SCAN:
3515 if (ostate != IEEE80211_S_SCAN) {
3516 memset(ic->ic_bss->ni_bssid, 0, IEEE80211_ADDR_LEN);
3517 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3520 callout_reset(&sc->sc_scan_ch, rtw_dwelltime * hz / 1000,
3524 case IEEE80211_S_RUN:
3525 switch (ic->ic_opmode) {
3526 case IEEE80211_M_HOSTAP:
3527 case IEEE80211_M_IBSS:
3528 rtw_set_nettype(sc, IEEE80211_M_MONITOR);
3530 case IEEE80211_M_AHDEMO:
3531 case IEEE80211_M_STA:
3532 rtw_join_bss(sc, ic->ic_bss->ni_bssid,
3533 ic->ic_bss->ni_intval);
3535 case IEEE80211_M_MONITOR:
3538 rtw_set_nettype(sc, ic->ic_opmode);
3540 case IEEE80211_S_ASSOC:
3541 case IEEE80211_S_AUTH:
3545 if (nstate != IEEE80211_S_SCAN)
3546 callout_stop(&sc->sc_scan_ch);
3548 return sc->sc_mtbl.mt_newstate(ic, nstate, arg);
3551 /* Extend a 32-bit TSF timestamp to a 64-bit timestamp. */
3553 rtw_tsf_extend(struct rtw_regs *regs, uint32_t rstamp)
3555 uint32_t tsftl, tsfth;
3557 tsfth = RTW_READ(regs, RTW_TSFTRH);
3558 tsftl = RTW_READ(regs, RTW_TSFTRL);
3559 if (tsftl < rstamp) /* Compensate for rollover. */
3561 return ((uint64_t)tsfth << 32) | rstamp;
3565 rtw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
3566 struct ieee80211_node *ni, int subtype, int rssi, uint32_t rstamp)
3568 struct ifnet *ifp = &ic->ic_if;
3569 struct rtw_softc *sc = ifp->if_softc;
3571 sc->sc_mtbl.mt_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
3574 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3575 case IEEE80211_FC0_SUBTYPE_BEACON:
3576 if (ic->ic_opmode == IEEE80211_M_IBSS &&
3577 ic->ic_state == IEEE80211_S_RUN) {
3578 uint64_t tsf = rtw_tsf_extend(&sc->sc_regs, rstamp);
3580 if (le64toh(ni->ni_tstamp.tsf) >= tsf)
3581 ieee80211_ibss_merge(ni);
3590 static struct ieee80211_node *
3591 rtw_node_alloc(struct ieee80211_node_table *nt)
3593 struct ifnet *ifp = nt->nt_ic->ic_ifp;
3594 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3595 struct ieee80211_node *ni = (*sc->sc_mtbl.mt_node_alloc)(nt);
3597 DPRINTF(sc, RTW_DEBUG_NODE,
3598 ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni));
3603 rtw_node_free(struct ieee80211_node *ni)
3605 struct ieee80211com *ic = ni->ni_ic;
3606 struct ifnet *ifp = ic->ic_ifp;
3607 struct rtw_softc *sc = (struct rtw_softc *)ifp->if_softc;
3609 DPRINTF(sc, RTW_DEBUG_NODE,
3610 ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni,
3611 ether_sprintf(ni->ni_bssid)));
3612 sc->sc_mtbl.mt_node_free(ni);
3617 rtw_media_change(struct ifnet *ifp)
3621 error = ieee80211_media_change(ifp);
3622 if (error == ENETRESET) {
3623 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) ==
3624 (IFF_RUNNING|IFF_UP))
3625 rtw_init(ifp); /* XXX lose error */
3632 rtw_media_status(struct ifnet *ifp, struct ifmediareq *imr)
3634 struct rtw_softc *sc = ifp->if_softc;
3636 if ((sc->sc_flags & RTW_F_ENABLED) == 0) {
3637 imr->ifm_active = IFM_IEEE80211 | IFM_NONE;
3638 imr->ifm_status = 0;
3641 ieee80211_media_status(ifp, imr);
3644 static __inline void
3645 rtw_set80211methods(struct rtw_mtbl *mtbl, struct ieee80211com *ic)
3647 mtbl->mt_newstate = ic->ic_newstate;
3648 ic->ic_newstate = rtw_newstate;
3650 mtbl->mt_recv_mgmt = ic->ic_recv_mgmt;
3651 ic->ic_recv_mgmt = rtw_recv_mgmt;
3654 mtbl->mt_node_free = ic->ic_node_free;
3655 ic->ic_node_free = rtw_node_free;
3657 mtbl->mt_node_alloc = ic->ic_node_alloc;
3658 ic->ic_node_alloc = rtw_node_alloc;
3661 ic->ic_crypto.cs_key_delete = rtw_key_delete;
3662 ic->ic_crypto.cs_key_set = rtw_key_set;
3663 ic->ic_crypto.cs_key_update_begin = rtw_key_update_begin;
3664 ic->ic_crypto.cs_key_update_end = rtw_key_update_end;
3667 static __inline void
3668 rtw_init_radiotap(struct rtw_softc *sc)
3670 sc->sc_rxtap.rr_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
3671 sc->sc_rxtap.rr_ihdr.it_present = htole32(RTW_RX_RADIOTAP_PRESENT);
3673 sc->sc_txtap.rt_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
3674 sc->sc_txtap.rt_ihdr.it_present = htole32(RTW_TX_RADIOTAP_PRESENT);
3677 static struct rtw_rf *
3678 rtw_rf_attach(struct rtw_softc *sc, enum rtw_rfchipid rfchipid, int digphy)
3680 rtw_rf_write_t rf_write;
3685 rf_write = rtw_rf_hostwrite;
3687 case RTW_RFCHIPID_INTERSIL:
3688 case RTW_RFCHIPID_PHILIPS:
3689 case RTW_RFCHIPID_GCT: /* XXX a guess */
3690 case RTW_RFCHIPID_RFMD:
3691 rf_write = (rtw_host_rfio) ? rtw_rf_hostwrite : rtw_rf_macwrite;
3696 case RTW_RFCHIPID_GCT:
3697 rf = rtw_grf5101_create(&sc->sc_regs, rf_write, 0);
3698 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3699 sc->sc_getrssi = rtw_gct_getrssi;
3701 case RTW_RFCHIPID_MAXIM:
3702 rf = rtw_max2820_create(&sc->sc_regs, rf_write, 0);
3703 sc->sc_pwrstate_cb = rtw_maxim_pwrstate;
3704 sc->sc_getrssi = rtw_maxim_getrssi;
3706 case RTW_RFCHIPID_PHILIPS:
3707 rf = rtw_sa2400_create(&sc->sc_regs, rf_write, digphy);
3708 sc->sc_pwrstate_cb = rtw_philips_pwrstate;
3709 sc->sc_getrssi = rtw_philips_getrssi;
3711 case RTW_RFCHIPID_RFMD:
3712 /* XXX RFMD has no RF constructor */
3713 sc->sc_pwrstate_cb = rtw_rfmd_pwrstate;
3718 rf->rf_continuous_tx_cb =
3719 (rtw_continuous_tx_cb_t)rtw_continuous_tx_enable;
3720 rf->rf_continuous_tx_arg = sc;
3724 /* Revision C and later use a different PHY delay setting than
3725 * revisions A and B.
3728 rtw_check_phydelay(struct rtw_regs *regs, uint32_t old_rcr)
3730 #define REVAB (RTW_RCR_MXDMA_UNLIMITED | RTW_RCR_AICV)
3731 #define REVC (REVAB | RTW_RCR_RXFTH_WHOLE)
3733 uint8_t phydelay = __SHIFTIN(0x6, RTW_PHYDELAY_PHYDELAY);
3735 RTW_WRITE(regs, RTW_RCR, REVAB);
3736 RTW_WBW(regs, RTW_RCR, RTW_RCR);
3737 RTW_WRITE(regs, RTW_RCR, REVC);
3739 RTW_WBR(regs, RTW_RCR, RTW_RCR);
3740 if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
3741 phydelay |= RTW_PHYDELAY_REVC_MAGIC;
3743 RTW_WRITE(regs, RTW_RCR, old_rcr); /* restore RCR */
3744 RTW_SYNC(regs, RTW_RCR, RTW_RCR);
3752 rtw_attach(device_t dev)
3754 struct rtw_softc *sc = device_get_softc(dev);
3755 struct ieee80211com *ic = &sc->sc_ic;
3756 const struct ieee80211_cipher *wep_cipher;
3757 struct ifnet *ifp = &ic->ic_if;
3760 wep_cipher = ieee80211_crypto_cipher(IEEE80211_CIPHER_WEP);
3761 KKASSERT(wep_cipher != NULL);
3763 memcpy(&rtw_cipher_wep, wep_cipher, sizeof(rtw_cipher_wep));
3764 rtw_cipher_wep.ic_decap = rtw_wep_decap;
3766 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3768 switch (RTW_READ(&sc->sc_regs, RTW_TCR) & RTW_TCR_HWVERID_MASK) {
3769 case RTW_TCR_HWVERID_F:
3770 sc->sc_hwverid = 'F';
3772 case RTW_TCR_HWVERID_D:
3773 sc->sc_hwverid = 'D';
3776 sc->sc_hwverid = '?';
3780 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3782 RF_ACTIVE | RF_SHAREABLE);
3783 if (sc->sc_irq_res == NULL) {
3784 device_printf(dev, "could not alloc irq res\n");
3788 /* Allocate h/w desc blocks */
3789 rc = rtw_desc_blk_alloc(sc);
3793 /* Allocate s/w desc blocks */
3794 rc = rtw_soft_blk_alloc(sc);
3798 /* Reset the chip to a known state. */
3801 device_printf(dev, "could not reset\n");
3805 sc->sc_rcr = RTW_READ(&sc->sc_regs, RTW_RCR);
3807 if ((sc->sc_rcr & RTW_RCR_9356SEL) != 0)
3808 sc->sc_flags |= RTW_F_9356SROM;
3810 rc = rtw_srom_read(sc);
3814 rc = rtw_srom_parse(sc);
3816 device_printf(dev, "malformed serial ROM\n");
3820 device_printf(dev, "%s PHY\n",
3821 ((sc->sc_flags & RTW_F_DIGPHY) != 0) ? "digital"
3824 device_printf(dev, "CS threshold %u\n", sc->sc_csthr);
3826 sc->sc_rf = rtw_rf_attach(sc, sc->sc_rfchipid,
3827 sc->sc_flags & RTW_F_DIGPHY);
3828 if (sc->sc_rf == NULL) {
3829 device_printf(dev, "could not attach RF\n");
3834 sc->sc_phydelay = rtw_check_phydelay(&sc->sc_regs, sc->sc_rcr);
3836 RTW_DPRINTF(RTW_DEBUG_ATTACH,
3837 ("%s: PHY delay %d\n", ifp->if_xname, sc->sc_phydelay));
3839 if (sc->sc_locale == RTW_LOCALE_UNKNOWN)
3840 rtw_identify_country(sc);
3842 rtw_init_channels(sc);
3844 rc = rtw_identify_sta(sc);
3849 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
3850 ifp->if_init = rtw_init;
3851 ifp->if_ioctl = rtw_ioctl;
3852 ifp->if_start = rtw_start;
3853 ifp->if_watchdog = rtw_watchdog;
3854 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
3855 ifq_set_ready(&ifp->if_snd);
3857 ic->ic_phytype = IEEE80211_T_DS;
3858 ic->ic_opmode = IEEE80211_M_STA;
3859 ic->ic_caps = IEEE80211_C_PMGT |
3861 IEEE80211_C_HOSTAP |
3862 IEEE80211_C_MONITOR;
3863 ic->ic_sup_rates[IEEE80211_MODE_11B] = rtw_rates_11b;
3865 /* initialize led callout */
3866 callout_init(&sc->sc_led_state.ls_fast_ch);
3867 callout_init(&sc->sc_led_state.ls_slow_ch);
3869 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
3870 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
3871 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
3872 ic->ic_ratectl.rc_st_attach = rtw_ratectl_attach;
3875 * Call MI attach routines.
3877 ieee80211_ifattach(&sc->sc_ic);
3879 /* Override some ieee80211 methods */
3880 rtw_set80211methods(&sc->sc_mtbl, &sc->sc_ic);
3883 * possibly we should fill in our own sc_send_prresp, since
3884 * the RTL8180 is probably sending probe responses in ad hoc
3888 /* complete initialization */
3889 ieee80211_media_init(&sc->sc_ic, rtw_media_change, rtw_media_status);
3890 callout_init(&sc->sc_scan_ch);
3892 rtw_init_radiotap(sc);
3894 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
3895 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
3897 rc = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, rtw_intr, sc,
3898 &sc->sc_irq_handle, ifp->if_serializer);
3900 device_printf(dev, "can't set up interrupt\n");
3902 ieee80211_ifdetach(ic);
3906 ifp->if_cpuid = rman_get_cpuid(sc->sc_irq_res);
3907 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3909 device_printf(dev, "hardware version %c\n", sc->sc_hwverid);
3911 ieee80211_announce(ic);
3919 rtw_detach(device_t dev)
3921 struct rtw_softc *sc = device_get_softc(dev);
3922 struct ifnet *ifp = &sc->sc_ic.ic_if;
3924 if (device_is_attached(dev)) {
3925 lwkt_serialize_enter(ifp->if_serializer);
3928 sc->sc_flags |= RTW_F_INVALID;
3930 callout_stop(&sc->sc_scan_ch);
3931 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
3933 lwkt_serialize_exit(ifp->if_serializer);
3935 ieee80211_ifdetach(&sc->sc_ic);
3938 if (sc->sc_rf != NULL)
3939 rtw_rf_destroy(sc->sc_rf);
3941 if (sc->sc_srom.sr_content != NULL)
3942 kfree(sc->sc_srom.sr_content, M_DEVBUF);
3944 if (sc->sc_irq_res != NULL) {
3945 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
3949 rtw_soft_blk_free(sc);
3950 rtw_desc_blk_free(sc);
3955 rtw_desc_dma_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3960 KASSERT(nseg == 1, ("too many desc segments"));
3961 *((uint32_t *)arg) = seg->ds_addr; /* XXX bus_addr_t */
3965 rtw_dma_alloc(struct rtw_softc *sc, bus_dma_tag_t *dmat, int len,
3966 void **desc, uint32_t *phyaddr, bus_dmamap_t *dmamap)
3970 error = bus_dma_tag_create(NULL, RTW_DESC_ALIGNMENT, 0,
3971 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
3972 NULL, NULL, len, 1, len, 0, dmat);
3974 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA tag");
3978 error = bus_dmamem_alloc(*dmat, desc, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3981 if_printf(&sc->sc_ic.ic_if, "could not alloc desc DMA mem");
3985 error = bus_dmamap_load(*dmat, *dmamap, *desc, len,
3986 rtw_desc_dma_addr, phyaddr, BUS_DMA_WAITOK);
3988 if_printf(&sc->sc_ic.ic_if, "could not load desc DMA mem");
3989 bus_dmamem_free(*dmat, *desc, *dmamap);
3997 rtw_dma_free(struct rtw_softc *sc __unused, bus_dma_tag_t *dmat, void **desc,
3998 bus_dmamap_t *dmamap)
4000 if (*desc != NULL) {
4001 bus_dmamap_unload(*dmat, *dmamap);
4002 bus_dmamem_free(*dmat, *desc, *dmamap);
4006 if (*dmat != NULL) {
4007 bus_dma_tag_destroy(*dmat);
4013 rtw_txdesc_blk_free(struct rtw_softc *sc, int q_no)
4015 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4017 rtw_dma_free(sc, &tdb->tdb_dmat, (void **)&tdb->tdb_desc,
4022 rtw_txdesc_blk_alloc(struct rtw_softc *sc, int q_len, int q_no,
4023 bus_size_t q_basereg)
4025 struct rtw_txdesc_blk *tdb = &sc->sc_txdesc_blk[q_no];
4031 error = rtw_dma_alloc(sc, &tdb->tdb_dmat,
4032 q_len * sizeof(*tdb->tdb_desc),
4033 (void **)&tdb->tdb_desc, &tdb->tdb_base,
4036 kprintf("%dth tx\n", q_no);
4039 tdb->tdb_basereg = q_basereg;
4041 tdb->tdb_ndesc = q_len;
4042 for (i = 0; i < tdb->tdb_ndesc; ++i)
4043 tdb->tdb_desc[i].td_next = htole32(RTW_NEXT_DESC(tdb, i));
4049 rtw_rxdesc_blk_free(struct rtw_softc *sc)
4051 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4053 rtw_dma_free(sc, &rdb->rdb_dmat, (void **)&rdb->rdb_desc,
4058 rtw_rxdesc_blk_alloc(struct rtw_softc *sc, int q_len)
4060 struct rtw_rxdesc_blk *rdb = &sc->sc_rxdesc_blk;
4066 error = rtw_dma_alloc(sc, &rdb->rdb_dmat,
4067 q_len * sizeof(*rdb->rdb_desc),
4068 (void **)&rdb->rdb_desc, &rdb->rdb_base,
4073 rdb->rdb_ndesc = q_len;
4080 rtw_txsoft_blk_free(struct rtw_softc *sc, int n_sd, int q_no)
4082 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4084 if (tsb->tsb_desc != NULL) {
4087 for (i = 0; i < n_sd; ++i) {
4088 bus_dmamap_destroy(sc->sc_txsoft_dmat,
4089 tsb->tsb_desc[i].ts_dmamap);
4091 kfree(tsb->tsb_desc, M_DEVBUF);
4092 tsb->tsb_desc = NULL;
4097 rtw_txsoft_blk_alloc(struct rtw_softc *sc, int q_len, int q_no, uint8_t q_poll)
4099 struct rtw_txsoft_blk *tsb = &sc->sc_txsoft_blk[q_no];
4102 STAILQ_INIT(&tsb->tsb_dirtyq);
4103 STAILQ_INIT(&tsb->tsb_freeq);
4104 tsb->tsb_ndesc = q_len;
4105 tsb->tsb_desc = kmalloc(q_len * sizeof(*tsb->tsb_desc), M_DEVBUF,
4107 tsb->tsb_poll = q_poll;
4109 for (i = 0; i < tsb->tsb_ndesc; ++i) {
4110 error = bus_dmamap_create(sc->sc_txsoft_dmat, 0,
4111 &tsb->tsb_desc[i].ts_dmamap);
4113 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4114 "for soft tx desc\n");
4115 rtw_txsoft_blk_free(sc, i, q_no);
4123 rtw_rxsoft_blk_free(struct rtw_softc *sc, int n_sd)
4125 if (sc->sc_rxsoft_free) {
4128 for (i = 0; i < n_sd; ++i) {
4129 bus_dmamap_destroy(sc->sc_rxsoft_dmat,
4130 sc->sc_rxsoft[i].rs_dmamap);
4132 sc->sc_rxsoft_free = 0;
4137 rtw_rxsoft_blk_alloc(struct rtw_softc *sc, int q_len)
4141 sc->sc_rxsoft_free = 1;
4146 for (i = 0; i < q_len; ++i) {
4147 error = bus_dmamap_create(sc->sc_rxsoft_dmat, 0,
4148 &sc->sc_rxsoft[i].rs_dmamap);
4150 if_printf(&sc->sc_ic.ic_if, "could not create DMA map "
4151 "for soft rx desc\n");
4152 rtw_rxsoft_blk_free(sc, i);
4159 #define TXQ_PARAM(q, poll, breg) \
4160 [RTW_TXPRI ## q] = { \
4161 .txq_len = RTW_TXQLEN ## q, \
4163 .txq_basereg = breg \
4165 static const struct {
4168 bus_size_t txq_basereg;
4169 } txq_params[RTW_NTXPRI] = {
4170 TXQ_PARAM(LO, RTW_TPPOLL_LPQ | RTW_TPPOLL_SLPQ, RTW_TLPDA),
4171 TXQ_PARAM(MD, RTW_TPPOLL_NPQ | RTW_TPPOLL_SNPQ, RTW_TNPDA),
4172 TXQ_PARAM(HI, RTW_TPPOLL_HPQ | RTW_TPPOLL_SHPQ, RTW_THPDA),
4173 TXQ_PARAM(BCN, RTW_TPPOLL_BQ | RTW_TPPOLL_SBQ, RTW_TBDA)
4178 rtw_desc_blk_alloc(struct rtw_softc *sc)
4182 /* Create h/w TX desc */
4183 for (i = 0; i < RTW_NTXPRI; ++i) {
4184 error = rtw_txdesc_blk_alloc(sc, txq_params[i].txq_len, i,
4185 txq_params[i].txq_basereg);
4190 /* Create h/w RX desc */
4191 return rtw_rxdesc_blk_alloc(sc, RTW_RXQLEN);
4195 rtw_desc_blk_free(struct rtw_softc *sc)
4199 for (i = 0; i < RTW_NTXPRI; ++i)
4200 rtw_txdesc_blk_free(sc, i);
4201 rtw_rxdesc_blk_free(sc);
4205 rtw_soft_blk_alloc(struct rtw_softc *sc)
4209 /* Create DMA tag for TX mbuf */
4210 error = bus_dma_tag_create(NULL, 1, 0,
4211 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
4213 MCLBYTES, RTW_MAXPKTSEGS, MCLBYTES,
4214 0, &sc->sc_txsoft_dmat);
4216 if_printf(&sc->sc_ic.ic_if, "could not alloc txsoft DMA tag\n");
4220 /* Create DMA tag for RX mbuf */
4221 error = bus_dma_tag_create(NULL, 1, 0,
4222 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
4224 MCLBYTES, 1, MCLBYTES,
4225 0, &sc->sc_rxsoft_dmat);
4227 if_printf(&sc->sc_ic.ic_if, "could not alloc rxsoft DMA tag\n");
4231 /* Create a spare DMA map for RX mbuf */
4232 error = bus_dmamap_create(sc->sc_rxsoft_dmat, 0, &sc->sc_rxsoft_dmamap);
4234 if_printf(&sc->sc_ic.ic_if, "could not alloc spare rxsoft "
4236 bus_dma_tag_destroy(sc->sc_rxsoft_dmat);
4237 sc->sc_rxsoft_dmat = NULL;
4241 /* Create s/w TX desc */
4242 for (i = 0; i < RTW_NTXPRI; ++i) {
4243 error = rtw_txsoft_blk_alloc(sc, txq_params[i].txq_len, i,
4244 txq_params[i].txq_poll);
4249 /* Create s/w RX desc */
4250 return rtw_rxsoft_blk_alloc(sc, RTW_RXQLEN);
4254 rtw_soft_blk_free(struct rtw_softc *sc)
4258 for (i = 0; i < RTW_NTXPRI; ++i)
4259 rtw_txsoft_blk_free(sc, txq_params[i].txq_len, i);
4261 rtw_rxsoft_blk_free(sc, RTW_RXQLEN);
4263 if (sc->sc_txsoft_dmat != NULL) {
4264 bus_dma_tag_destroy(sc->sc_txsoft_dmat);
4265 sc->sc_txsoft_dmat = NULL;
4268 if (sc->sc_rxsoft_dmat != NULL) {
4269 bus_dmamap_destroy(sc->sc_rxsoft_dmat, sc->sc_rxsoft_dmamap);
4270 bus_dma_tag_destroy(sc->sc_rxsoft_dmat);
4271 sc->sc_rxsoft_dmat = NULL;
4278 * paylen: payload length (no FCS, no WEP header)
4280 * hdrlen: header length
4282 * rate: MSDU speed, units 500kb/s
4284 * flags: IEEE80211_F_SHPREAMBLE (use short preamble),
4285 * IEEE80211_F_SHSLOT (use short slot length)
4289 * d: 802.11 Duration field for RTS,
4290 * 802.11 Duration field for data frame,
4291 * PLCP Length for data frame,
4292 * residual octets at end of data slot
4295 rtw_compute_duration1(int len, int use_ack, uint32_t icflags, int rate,
4296 struct rtw_duration *d)
4299 int ack, bitlen, data_dur, remainder;
4302 * RTS reserves medium for SIFS | CTS | SIFS | (DATA) | SIFS | ACK
4303 * DATA reserves medium for SIFS | ACK
4305 * XXXMYC: no ACK on multicast/broadcast or control packets
4310 pre = IEEE80211_DUR_DS_SIFS;
4311 if (icflags & IEEE80211_F_SHPREAMBLE) {
4312 pre += IEEE80211_DUR_DS_SHORT_PREAMBLE +
4313 IEEE80211_DUR_DS_FAST_PLCPHDR;
4315 pre += IEEE80211_DUR_DS_LONG_PREAMBLE +
4316 IEEE80211_DUR_DS_SLOW_PLCPHDR;
4320 data_dur = (bitlen * 2) / rate;
4321 remainder = (bitlen * 2) % rate;
4322 if (remainder != 0) {
4323 d->d_residue = (rate - remainder) / 16;
4328 case 2: /* 1 Mb/s */
4329 case 4: /* 2 Mb/s */
4330 /* 1 - 2 Mb/s WLAN: send ACK/CTS at 1 Mb/s */
4333 case 11: /* 5.5 Mb/s */
4334 case 22: /* 11 Mb/s */
4335 case 44: /* 22 Mb/s */
4336 /* 5.5 - 11 Mb/s WLAN: send ACK/CTS at 2 Mb/s */
4344 d->d_plcp_len = data_dur;
4346 ack = (use_ack) ? pre + (IEEE80211_DUR_DS_SLOW_ACK * 2) / ctsrate : 0;
4348 d->d_rts_dur = pre + (IEEE80211_DUR_DS_SLOW_CTS * 2) / ctsrate +
4352 d->d_data_dur = ack;
4361 * paylen: payload length (no FCS, no WEP header)
4363 * rate: MSDU speed, units 500kb/s
4365 * fraglen: fragment length, set to maximum (or higher) for no
4368 * flags: IEEE80211_F_PRIVACY (hardware adds WEP),
4369 * IEEE80211_F_SHPREAMBLE (use short preamble),
4370 * IEEE80211_F_SHSLOT (use short slot length)
4374 * d0: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields
4375 * of first/only fragment
4377 * dn: 802.11 Duration fields (RTS/Data), PLCP Length, Service fields
4380 * rtw_compute_duration assumes crypto-encapsulation, if any,
4381 * has already taken place.
4384 rtw_compute_duration(const struct ieee80211_frame_min *wh,
4385 const struct ieee80211_key *wk, int len,
4386 uint32_t icflags, int fraglen, int rate,
4387 struct rtw_duration *d0, struct rtw_duration *dn,
4388 int *npktp, int debug)
4391 int cryptolen, /* crypto overhead: header+trailer */
4392 firstlen, /* first fragment's payload + overhead length */
4393 hdrlen, /* header length w/o driver padding */
4394 lastlen, /* last fragment's payload length w/ overhead */
4395 lastlen0, /* last fragment's payload length w/o overhead */
4396 npkt, /* number of fragments */
4397 overlen, /* non-802.11 header overhead per fragment */
4398 paylen; /* payload length w/o overhead */
4400 hdrlen = ieee80211_anyhdrsize((const void *)wh);
4402 /* Account for padding required by the driver. */
4403 if (icflags & IEEE80211_F_DATAPAD)
4404 paylen = len - roundup(hdrlen, sizeof(u_int32_t));
4406 paylen = len - hdrlen;
4408 overlen = IEEE80211_CRC_LEN;
4411 cryptolen = wk->wk_cipher->ic_header +
4412 wk->wk_cipher->ic_trailer;
4413 paylen -= cryptolen;
4414 overlen += cryptolen;
4417 npkt = paylen / fraglen;
4418 lastlen0 = paylen % fraglen;
4420 if (npkt == 0) { /* no fragments */
4421 lastlen = paylen + overlen;
4422 } else if (lastlen0 != 0) { /* a short "tail" fragment */
4423 lastlen = lastlen0 + overlen;
4425 } else { /* full-length "tail" fragment */
4426 lastlen = fraglen + overlen;
4433 firstlen = fraglen + overlen;
4435 firstlen = paylen + overlen;
4438 kprintf("%s: npkt %d firstlen %d lastlen0 %d lastlen %d "
4439 "fraglen %d overlen %d len %d rate %d icflags %08x\n",
4440 __func__, npkt, firstlen, lastlen0, lastlen, fraglen,
4441 overlen, len, rate, icflags);
4444 ack = (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
4445 (wh->i_fc[1] & IEEE80211_FC0_TYPE_MASK) !=
4446 IEEE80211_FC0_TYPE_CTL);
4448 rc = rtw_compute_duration1(firstlen + hdrlen, ack, icflags, rate, d0);
4456 return rtw_compute_duration1(lastlen + hdrlen, ack, icflags, rate, dn);
4460 rtw_get_rssi(struct rtw_softc *sc, uint8_t raw, uint8_t sq)
4464 rssi = sc->sc_getrssi(raw, sq);
4468 else if (rssi > 100)
4471 if (rssi > (RTW_NOISE_FLOOR + RTW_RSSI_CORR))
4472 rssi -= (RTW_NOISE_FLOOR + RTW_RSSI_CORR);
4480 rtw_maxim_getrssi(uint8_t raw, uint8_t sq __unused)
4495 rtw_gct_getrssi(uint8_t raw, uint8_t sq __unused)
4500 if ((raw & 0x1) == 0 || rssi > 0x3c)
4503 rssi = (100 * rssi) / 0x3c;
4510 rtw_philips_getrssi(uint8_t raw, uint8_t sq)
4512 static const uint8_t sq_rssi_map[SA2400_SQ_RSSI_MAP_MAX] =
4513 { SA2400_SQ_RSSI_MAP };
4515 if (sq < SA2400_SQ_RSSI_MAP_MAX - 1) /* NB: -1 is intended */
4516 return sq_rssi_map[sq];
4525 rtw_ratectl_attach(struct ieee80211com *ic, u_int rc)
4527 struct rtw_softc *sc = ic->ic_if.if_softc;
4530 case IEEE80211_RATECTL_ONOE:
4531 return &sc->sc_onoe_param;
4532 case IEEE80211_RATECTL_NONE:
4533 /* This could only happen during detaching */
4536 panic("unknown rate control algo %u", rc);