1 @c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc.
2 @c Contributed by ARM Ltd.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @node AArch64-Dependent
10 @chapter AArch64 Dependent Features
14 @node Machine Dependencies
15 @chapter AArch64 Dependent Features
18 @cindex AArch64 support
21 * AArch64 Options:: Options
22 * AArch64 Syntax:: Syntax
23 * AArch64 Floating Point:: Floating Point
24 * AArch64 Directives:: AArch64 Machine Directives
25 * AArch64 Opcodes:: Opcodes
26 * AArch64 Mapping Symbols:: Mapping Symbols
31 @cindex AArch64 options (none)
32 @cindex options for AArch64 (none)
37 @cindex @code{-EB} command line option, AArch64
39 This option specifies that the output generated by the assembler should
40 be marked as being encoded for a big-endian processor.
42 @cindex @code{-EL} command line option, AArch64
44 This option specifies that the output generated by the assembler should
45 be marked as being encoded for a little-endian processor.
47 @cindex @code{-mabi=} command line option, AArch64
49 Specify which ABI the source code uses. The recognized arguments
50 are: @code{ilp32} and @code{lp64}, which decides the generated object
51 file in ELF32 and ELF64 format respectively. The default is @code{lp64}.
59 * AArch64-Chars:: Special Characters
60 * AArch64-Regs:: Register Names
61 * AArch64-Relocations:: Relocations
65 @subsection Special Characters
67 @cindex line comment character, AArch64
68 @cindex AArch64 line comment character
69 The presence of a @samp{//} on a line indicates the start of a comment
70 that extends to the end of the current line. If a @samp{#} appears as
71 the first character of a line, the whole line is treated as a comment.
73 @cindex line separator, AArch64
74 @cindex statement separator, AArch64
75 @cindex AArch64 line separator
76 The @samp{;} character can be used instead of a newline to separate
79 @cindex immediate character, AArch64
80 @cindex AArch64 immediate character
81 The @samp{#} can be optionally used to indicate immediate operands.
84 @subsection Register Names
86 @cindex AArch64 register names
87 @cindex register names, AArch64
88 Please refer to the section @samp{4.4 Register Names} of
89 @samp{ARMv8 Instruction Set Overview}, which is available at
90 @uref{http://infocenter.arm.com}.
92 @node AArch64-Relocations
93 @subsection Relocations
95 @cindex relocations, AArch64
96 @cindex AArch64 relocations
97 @cindex MOVN, MOVZ and MOVK group relocations, AArch64
98 Relocations for @samp{MOVZ} and @samp{MOVK} instructions can be generated
99 by prefixing the label with @samp{#:abs_g2:} etc.
100 For example to load the 48-bit absolute address of @var{foo} into x0:
103 movz x0, #:abs_g2:foo // bits 32-47, overflow check
104 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check
105 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check
108 @cindex ADRP, ADD, LDR/STR group relocations, AArch64
109 Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR}
110 instructions can be generated by prefixing the label with
111 @samp{#:pg_hi21:} and @samp{#:lo12:} respectively.
113 For example to use 33-bit (+/-4GB) pc-relative addressing to
114 load the address of @var{foo} into x0:
117 adrp x0, #:pg_hi21:foo
118 add x0, x0, #:lo12:foo
121 Or to load the value of @var{foo} into x0:
124 adrp x0, #:pg_hi21:foo
125 ldr x0, [x0, #:lo12:foo]
128 Note that @samp{#:pg_hi21:} is optional.
137 adrp x0, #:pg_hi21:foo
140 @node AArch64 Floating Point
141 @section Floating Point
143 @cindex floating point, AArch64 (@sc{ieee})
144 @cindex AArch64 floating point (@sc{ieee})
145 The AArch64 architecture uses @sc{ieee} floating-point numbers.
147 @node AArch64 Directives
148 @section AArch64 Machine Directives
150 @cindex machine directives, AArch64
151 @cindex AArch64 machine directives
154 @c AAAAAAAAAAAAAAAAAAAAAAAAA
155 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
157 @cindex @code{.bss} directive, AArch64
159 This directive switches to the @code{.bss} section.
161 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
162 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
163 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
164 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
165 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
166 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
167 @c IIIIIIIIIIIIIIIIIIIIIIIIII
168 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
169 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
170 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
172 @cindex @code{.ltorg} directive, AArch64
174 This directive causes the current contents of the literal pool to be
175 dumped into the current section (which is assumed to be the .text
176 section) at the current location (aligned to a word boundary).
177 @code{GAS} maintains a separate literal pool for each section and each
178 sub-section. The @code{.ltorg} directive will only affect the literal
179 pool of the current section and sub-section. At the end of assembly
180 all remaining, un-empty literal pools will automatically be dumped.
182 Note - older versions of @code{GAS} would dump the current literal
183 pool any time a section change occurred. This is no longer done, since
184 it prevents accurate control of the placement of literal pools.
186 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
188 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
189 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
191 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
193 @cindex @code{.pool} directive, AArch64
195 This is a synonym for .ltorg.
197 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
198 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
200 @cindex @code{.req} directive, AArch64
201 @item @var{name} .req @var{register name}
202 This creates an alias for @var{register name} called @var{name}. For
209 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
211 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
213 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
215 @cindex @code{.unreq} directive, AArch64
216 @item .unreq @var{alias-name}
217 This undefines a register alias which was previously defined using the
218 @code{req} directive. For example:
225 An error occurs if the name is undefined. Note - this pseudo op can
226 be used to delete builtin in register name aliases (eg 'w0'). This
227 should only be done if it is really necessary.
229 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
231 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
232 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
233 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
234 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
238 @node AArch64 Opcodes
241 @cindex AArch64 opcodes
242 @cindex opcodes for AArch64
243 @code{@value{AS}} implements all the standard AArch64 opcodes. It also
244 implements several pseudo opcodes, including several synthetic load
249 @cindex @code{LDR reg,=<expr>} pseudo op, AArch64
252 ldr <register> , =<expression>
255 The constant expression will be placed into the nearest literal pool (if it not
256 already there) and a PC-relative LDR instruction will be generated.
260 For more information on the AArch64 instruction set and assembly language
261 notation, see @samp{ARMv8 Instruction Set Overview} available at
262 @uref{http://infocenter.arm.com}.
265 @node AArch64 Mapping Symbols
266 @section Mapping Symbols
268 The AArch64 ELF specification requires that special symbols be inserted
269 into object files to mark certain features:
275 At the start of a region of code containing AArch64 instructions.
279 At the start of a region of data.