2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
37 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
38 * documentation not available, but ask me nicely.
40 * Written by Bill Paul <william.paul@windriver.com>
45 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
46 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
47 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
48 * are three supported methods for data transfer between host and
49 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
50 * Propulsion Technology (tm) DMA. The latter mechanism is a form
51 * of double buffer DMA where the packet data is copied to a
52 * pre-allocated DMA buffer who's physical address has been loaded
53 * into a table at device initialization time. The rationale is that
54 * the virtual to physical address translation needed for normal
55 * scatter/gather DMA is more expensive than the data copy needed
56 * for double buffering. This may be true in Windows NT and the like,
57 * but it isn't true for us, at least on the x86 arch. This driver
58 * uses the scatter/gather I/O method for both TX and RX.
60 * The LXT1001 only supports TCP/IP checksum offload on receive.
61 * Also, the VLAN tagging is done using a 16-entry table which allows
62 * the chip to perform hardware filtering based on VLAN tags. Sadly,
63 * our vlan support doesn't currently play well with this kind of
67 * - Jeff James at Intel, for arranging to have the LXT1001 manual
68 * released (at long last)
69 * - Beny Chen at D-Link, for actually sending it to me
70 * - Brad Short and Keith Alexis at SMC, for sending me sample
71 * SMC9462SX and SMC9462TX adapters for testing
72 * - Paul Saab at Y!, for not killing me (though it remains to be seen
73 * if in fact he did me much of a favor)
76 #include <sys/param.h>
77 #include <sys/systm.h>
78 #include <sys/sockio.h>
80 #include <sys/malloc.h>
81 #include <sys/kernel.h>
82 #include <sys/interrupt.h>
83 #include <sys/socket.h>
84 #include <sys/serialize.h>
85 #include <sys/thread2.h>
88 #include <net/ifq_var.h>
89 #include <net/if_arp.h>
90 #include <net/ethernet.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
96 #include <vm/vm.h> /* for vtophys */
97 #include <vm/pmap.h> /* for vtophys */
101 #include <dev/netif/mii_layer/mii.h>
102 #include <dev/netif/mii_layer/miivar.h>
104 #include <bus/pci/pcidevs.h>
105 #include <bus/pci/pcireg.h>
106 #include <bus/pci/pcivar.h>
108 #define LGE_USEIOSPACE
110 #include "if_lgereg.h"
112 /* "controller miibus0" required. See GENERIC if you get errors here. */
113 #include "miibus_if.h"
116 * Various supported device vendors/types and their names.
118 static struct lge_type lge_devs[] = {
119 { PCI_VENDOR_LEVELONE, PCI_PRODUCT_LEVELONE_LXT1001,
120 "Level 1 Gigabit Ethernet" },
124 static int lge_probe(device_t);
125 static int lge_attach(device_t);
126 static int lge_detach(device_t);
128 static int lge_alloc_jumbo_mem(struct lge_softc *);
129 static void lge_free_jumbo_mem(struct lge_softc *);
130 static struct lge_jslot
131 *lge_jalloc(struct lge_softc *);
132 static void lge_jfree(void *);
133 static void lge_jref(void *);
135 static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *,
137 static int lge_encap(struct lge_softc *, struct mbuf *, uint32_t *);
138 static void lge_rxeof(struct lge_softc *, int);
139 static void lge_rxeoc(struct lge_softc *);
140 static void lge_txeof(struct lge_softc *);
141 static void lge_intr(void *);
142 static void lge_tick(void *);
143 static void lge_tick_serialized(void *);
144 static void lge_start(struct ifnet *);
145 static int lge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
146 static void lge_init(void *);
147 static void lge_stop(struct lge_softc *);
148 static void lge_watchdog(struct ifnet *);
149 static void lge_shutdown(device_t);
150 static int lge_ifmedia_upd(struct ifnet *);
151 static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
153 static void lge_eeprom_getword(struct lge_softc *, int, uint16_t *);
154 static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int);
156 static int lge_miibus_readreg(device_t, int, int);
157 static int lge_miibus_writereg(device_t, int, int, int);
158 static void lge_miibus_statchg(device_t);
160 static void lge_setmulti(struct lge_softc *);
161 static void lge_reset(struct lge_softc *);
162 static int lge_list_rx_init(struct lge_softc *);
163 static int lge_list_tx_init(struct lge_softc *);
165 #ifdef LGE_USEIOSPACE
166 #define LGE_RES SYS_RES_IOPORT
167 #define LGE_RID LGE_PCI_LOIO
169 #define LGE_RES SYS_RES_MEMORY
170 #define LGE_RID LGE_PCI_LOMEM
173 static device_method_t lge_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, lge_probe),
176 DEVMETHOD(device_attach, lge_attach),
177 DEVMETHOD(device_detach, lge_detach),
178 DEVMETHOD(device_shutdown, lge_shutdown),
181 DEVMETHOD(bus_print_child, bus_generic_print_child),
182 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
185 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
186 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
187 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
192 static DEFINE_CLASS_0(lge, lge_driver, lge_methods, sizeof(struct lge_softc));
193 static devclass_t lge_devclass;
195 DECLARE_DUMMY_MODULE(if_lge);
196 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, NULL, NULL);
197 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, NULL, NULL);
199 #define LGE_SETBIT(sc, reg, x) \
200 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
202 #define LGE_CLRBIT(sc, reg, x) \
203 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
206 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x))
209 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x))
212 * Read a word of data stored in the EEPROM at address 'addr.'
215 lge_eeprom_getword(struct lge_softc *sc, int addr, uint16_t *dest)
220 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
221 LGE_EECTL_SINGLEACCESS | ((addr >> 1) << 8));
223 for (i = 0; i < LGE_TIMEOUT; i++) {
224 if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0)
228 if (i == LGE_TIMEOUT) {
229 kprintf("lge%d: EEPROM read timed out\n", sc->lge_unit);
233 val = CSR_READ_4(sc, LGE_EEDATA);
236 *dest = (val >> 16) & 0xFFFF;
238 *dest = val & 0xFFFF;
242 * Read a sequence of words from the EEPROM.
245 lge_read_eeprom(struct lge_softc *sc, caddr_t dest, int off, int cnt)
248 uint16_t word = 0, *ptr;
250 for (i = 0; i < cnt; i++) {
251 lge_eeprom_getword(sc, off + i, &word);
252 ptr = (uint16_t *)(dest + (i * 2));
258 lge_miibus_readreg(device_t dev, int phy, int reg)
260 struct lge_softc *sc = device_get_softc(dev);
264 * If we have a non-PCS PHY, pretend that the internal
265 * autoneg stuff at PHY address 0 isn't there so that
266 * the miibus code will find only the GMII PHY.
268 if (sc->lge_pcs == 0 && phy == 0)
271 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
273 for (i = 0; i < LGE_TIMEOUT; i++) {
274 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
278 if (i == LGE_TIMEOUT) {
279 kprintf("lge%d: PHY read timed out\n", sc->lge_unit);
283 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
287 lge_miibus_writereg(device_t dev, int phy, int reg, int data)
289 struct lge_softc *sc = device_get_softc(dev);
292 CSR_WRITE_4(sc, LGE_GMIICTL,
293 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
295 for (i = 0; i < LGE_TIMEOUT; i++) {
296 if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)
300 if (i == LGE_TIMEOUT) {
301 kprintf("lge%d: PHY write timed out\n", sc->lge_unit);
309 lge_miibus_statchg(device_t dev)
311 struct lge_softc *sc = device_get_softc(dev);
312 struct mii_data *mii = device_get_softc(sc->lge_miibus);
314 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
315 switch (IFM_SUBTYPE(mii->mii_media_active)) {
318 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
321 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
324 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
328 * Choose something, even if it's wrong. Clearing
329 * all the bits will hose autoneg on the internal
332 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
336 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
337 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
343 lge_setmulti(struct lge_softc *sc)
345 struct ifnet *ifp = &sc->arpcom.ac_if;
346 struct ifmultiaddr *ifma;
347 uint32_t h = 0, hashes[2] = { 0, 0 };
349 /* Make sure multicast hash table is enabled. */
350 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_MCAST);
352 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
353 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
354 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
358 /* first, zot all the existing hash bits */
359 CSR_WRITE_4(sc, LGE_MAR0, 0);
360 CSR_WRITE_4(sc, LGE_MAR1, 0);
362 /* now program new ones */
363 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
364 if (ifma->ifma_addr->sa_family != AF_LINK)
366 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
367 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
369 hashes[0] |= (1 << h);
371 hashes[1] |= (1 << (h - 32));
374 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
375 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
381 lge_reset(struct lge_softc *sc)
385 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_SOFTRST);
387 for (i = 0; i < LGE_TIMEOUT; i++) {
388 if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0)
392 if (i == LGE_TIMEOUT)
393 kprintf("lge%d: reset never completed\n", sc->lge_unit);
395 /* Wait a little while for the chip to get its brains in order. */
400 * Probe for a Level 1 chip. Check the PCI vendor and device
401 * IDs against our list and return a device name if we find a match.
404 lge_probe(device_t dev)
407 uint16_t vendor, product;
409 vendor = pci_get_vendor(dev);
410 product = pci_get_device(dev);
412 for (t = lge_devs; t->lge_name != NULL; t++) {
413 if (vendor == t->lge_vid && product == t->lge_did) {
414 device_set_desc(dev, t->lge_name);
423 * Attach the interface. Allocate softc structures, do ifmedia
424 * setup and ethernet/BPF attach.
427 lge_attach(device_t dev)
429 uint8_t eaddr[ETHER_ADDR_LEN];
430 struct lge_softc *sc;
432 int unit, error = 0, rid;
434 sc = device_get_softc(dev);
435 unit = device_get_unit(dev);
436 callout_init(&sc->lge_stat_timer);
437 lwkt_serialize_init(&sc->lge_jslot_serializer);
440 * Handle power management nonsense.
442 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
443 uint32_t iobase, membase, irq;
445 /* Save important PCI config data. */
446 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
447 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
448 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
450 /* Reset the power state. */
451 device_printf(dev, "chip is in D%d power mode "
452 "-- setting to D0\n", pci_get_powerstate(dev));
454 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
456 /* Restore PCI config data. */
457 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
458 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
459 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
462 pci_enable_busmaster(dev);
465 sc->lge_res = bus_alloc_resource_any(dev, LGE_RES, &rid, RF_ACTIVE);
467 if (sc->lge_res == NULL) {
468 kprintf("lge%d: couldn't map ports/memory\n", unit);
473 sc->lge_btag = rman_get_bustag(sc->lge_res);
474 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
476 /* Allocate interrupt */
478 sc->lge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
479 RF_SHAREABLE | RF_ACTIVE);
481 if (sc->lge_irq == NULL) {
482 kprintf("lge%d: couldn't map interrupt\n", unit);
487 /* Reset the adapter. */
491 * Get station address from the EEPROM.
493 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1);
494 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1);
495 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1);
499 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
500 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
502 if (sc->lge_ldata == NULL) {
503 kprintf("lge%d: no memory for list buffers!\n", unit);
508 /* Try to allocate memory for jumbo buffers. */
509 if (lge_alloc_jumbo_mem(sc)) {
510 kprintf("lge%d: jumbo buffer allocation failed\n",
516 ifp = &sc->arpcom.ac_if;
518 if_initname(ifp, "lge", unit);
519 ifp->if_mtu = ETHERMTU;
520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
521 ifp->if_ioctl = lge_ioctl;
522 ifp->if_start = lge_start;
523 ifp->if_watchdog = lge_watchdog;
524 ifp->if_init = lge_init;
525 ifp->if_baudrate = 1000000000;
526 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1);
527 ifq_set_ready(&ifp->if_snd);
528 ifp->if_capabilities = IFCAP_RXCSUM;
529 ifp->if_capenable = ifp->if_capabilities;
531 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
539 if (mii_phy_probe(dev, &sc->lge_miibus,
540 lge_ifmedia_upd, lge_ifmedia_sts)) {
541 kprintf("lge%d: MII without any PHY!\n", sc->lge_unit);
547 * Call MI attach routine.
549 ether_ifattach(ifp, eaddr, NULL);
551 error = bus_setup_intr(dev, sc->lge_irq, INTR_MPSAFE,
552 lge_intr, sc, &sc->lge_intrhand,
556 kprintf("lge%d: couldn't set up irq\n", unit);
560 ifp->if_cpuid = rman_get_cpuid(sc->lge_irq);
561 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
571 lge_detach(device_t dev)
573 struct lge_softc *sc= device_get_softc(dev);
574 struct ifnet *ifp = &sc->arpcom.ac_if;
576 if (device_is_attached(dev)) {
577 lwkt_serialize_enter(ifp->if_serializer);
580 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
581 lwkt_serialize_exit(ifp->if_serializer);
587 device_delete_child(dev, sc->lge_miibus);
588 bus_generic_detach(dev);
591 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
593 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
596 contigfree(sc->lge_ldata, sizeof(struct lge_list_data),
598 lge_free_jumbo_mem(sc);
604 * Initialize the transmit descriptors.
607 lge_list_tx_init(struct lge_softc *sc)
609 struct lge_list_data *ld;
610 struct lge_ring_data *cd;
615 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
616 ld->lge_tx_list[i].lge_mbuf = NULL;
617 ld->lge_tx_list[i].lge_ctl = 0;
620 cd->lge_tx_prod = cd->lge_tx_cons = 0;
627 * Initialize the RX descriptors and allocate mbufs for them. Note that
628 * we arralge the descriptors in a closed ring, so that the last descriptor
629 * points back to the first.
632 lge_list_rx_init(struct lge_softc *sc)
634 struct lge_list_data *ld;
635 struct lge_ring_data *cd;
641 cd->lge_rx_prod = cd->lge_rx_cons = 0;
643 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
645 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
646 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
648 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
652 /* Clear possible 'rx command queue empty' interrupt. */
653 CSR_READ_4(sc, LGE_ISR);
659 * Initialize an RX descriptor and attach an MBUF cluster.
662 lge_newbuf(struct lge_softc *sc, struct lge_rx_desc *c, struct mbuf *m)
664 struct mbuf *m_new = NULL;
665 struct lge_jslot *buf;
668 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
670 kprintf("lge%d: no memory for rx list "
671 "-- packet dropped!\n", sc->lge_unit);
675 /* Allocate the jumbo buffer */
676 buf = lge_jalloc(sc);
679 kprintf("lge%d: jumbo allocation failed "
680 "-- packet dropped!\n", sc->lge_unit);
685 /* Attach the buffer to the mbuf */
686 m_new->m_ext.ext_arg = buf;
687 m_new->m_ext.ext_buf = buf->lge_buf;
688 m_new->m_ext.ext_free = lge_jfree;
689 m_new->m_ext.ext_ref = lge_jref;
690 m_new->m_ext.ext_size = LGE_JUMBO_FRAMELEN;
692 m_new->m_data = m_new->m_ext.ext_buf;
693 m_new->m_flags |= M_EXT;
694 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
697 m_new->m_len = m_new->m_pkthdr.len = LGE_JLEN;
698 m_new->m_data = m_new->m_ext.ext_buf;
702 * Adjust alignment so packet payload begins on a
703 * longword boundary. Mandatory for Alpha, useful on
706 m_adj(m_new, ETHER_ALIGN);
709 c->lge_fragptr_hi = 0;
710 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
711 c->lge_fraglen = m_new->m_len;
712 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
716 * Put this buffer in the RX command FIFO. To do this,
717 * we just write the physical address of the descriptor
718 * into the RX descriptor address registers. Note that
719 * there are two registers, one high DWORD and one low
720 * DWORD, which lets us specify a 64-bit address if
721 * desired. We only use a 32-bit address for now.
722 * Writing to the low DWORD register is what actually
723 * causes the command to be issued, so we do that
726 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
727 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
733 lge_alloc_jumbo_mem(struct lge_softc *sc)
735 struct lge_jslot *entry;
739 /* Grab a big chunk o' storage. */
740 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
741 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
743 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
744 kprintf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
748 SLIST_INIT(&sc->lge_jfree_listhead);
751 * Now divide it up into 9K pieces and save the addresses
754 ptr = sc->lge_cdata.lge_jumbo_buf;
755 for (i = 0; i < LGE_JSLOTS; i++) {
756 entry = &sc->lge_cdata.lge_jslots[i];
758 entry->lge_buf = ptr;
759 entry->lge_inuse = 0;
761 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jslot_link);
769 lge_free_jumbo_mem(struct lge_softc *sc)
771 if (sc->lge_cdata.lge_jumbo_buf)
772 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
776 * Allocate a jumbo buffer.
778 static struct lge_jslot *
779 lge_jalloc(struct lge_softc *sc)
781 struct lge_jslot *entry;
783 lwkt_serialize_enter(&sc->lge_jslot_serializer);
784 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
786 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jslot_link);
787 entry->lge_inuse = 1;
790 kprintf("lge%d: no free jumbo buffers\n", sc->lge_unit);
793 lwkt_serialize_exit(&sc->lge_jslot_serializer);
798 * Adjust usage count on a jumbo buffer. In general this doesn't
799 * get used much because our jumbo buffers don't get passed around
800 * a lot, but it's implemented for correctness.
805 struct lge_jslot *entry = (struct lge_jslot *)arg;
806 struct lge_softc *sc = entry->lge_sc;
808 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry)
809 panic("lge_jref: asked to reference buffer "
810 "that we don't manage!");
811 else if (entry->lge_inuse == 0)
812 panic("lge_jref: buffer already free!");
814 atomic_add_int(&entry->lge_inuse, 1);
818 * Release a jumbo buffer.
823 struct lge_jslot *entry = (struct lge_jslot *)arg;
824 struct lge_softc *sc = entry->lge_sc;
827 panic("lge_jfree: can't find softc pointer!");
829 if (&sc->lge_cdata.lge_jslots[entry->lge_slot] != entry) {
830 panic("lge_jfree: asked to free buffer that we don't manage!");
831 } else if (entry->lge_inuse == 0) {
832 panic("lge_jfree: buffer already free!");
834 lwkt_serialize_enter(&sc->lge_jslot_serializer);
835 atomic_subtract_int(&entry->lge_inuse, 1);
836 if (entry->lge_inuse == 0) {
837 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
840 lwkt_serialize_exit(&sc->lge_jslot_serializer);
845 * A frame has been uploaded: pass the resulting mbuf chain up to
846 * the higher level protocols.
849 lge_rxeof(struct lge_softc *sc, int cnt)
851 struct ifnet *ifp = &sc->arpcom.ac_if;
853 struct lge_rx_desc *cur_rx;
854 int c, i, total_len = 0;
855 uint32_t rxsts, rxctl;
858 /* Find out how many frames were processed. */
860 i = sc->lge_cdata.lge_rx_cons;
864 struct mbuf *m0 = NULL;
866 cur_rx = &sc->lge_ldata->lge_rx_list[i];
867 rxctl = cur_rx->lge_ctl;
868 rxsts = cur_rx->lge_sts;
869 m = cur_rx->lge_mbuf;
870 cur_rx->lge_mbuf = NULL;
871 total_len = LGE_RXBYTES(cur_rx);
872 LGE_INC(i, LGE_RX_LIST_CNT);
876 * If an error occurs, update stats, clear the
877 * status word and leave the mbuf cluster in place:
878 * it should simply get re-used next time this descriptor
879 * comes up in the ring.
881 if (rxctl & LGE_RXCTL_ERRMASK) {
883 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
887 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
888 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
889 total_len + ETHER_ALIGN, 0, ifp, NULL);
890 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
892 kprintf("lge%d: no receive buffers "
893 "available -- packet dropped!\n",
898 m_adj(m0, ETHER_ALIGN);
901 m->m_pkthdr.rcvif = ifp;
902 m->m_pkthdr.len = m->m_len = total_len;
907 /* Do IP checksum checking. */
908 if (rxsts & LGE_RXSTS_ISIP)
909 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
910 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
911 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
912 if ((rxsts & LGE_RXSTS_ISTCP &&
913 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
914 (rxsts & LGE_RXSTS_ISUDP &&
915 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
916 m->m_pkthdr.csum_flags |=
917 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
918 CSUM_FRAG_NOT_CHECKED;
919 m->m_pkthdr.csum_data = 0xffff;
922 ifp->if_input(ifp, m);
925 sc->lge_cdata.lge_rx_cons = i;
929 lge_rxeoc(struct lge_softc *sc)
931 struct ifnet *ifp = &sc->arpcom.ac_if;
933 ifp->if_flags &= ~IFF_RUNNING;
938 * A frame was downloaded to the chip. It's safe for us to clean up
942 lge_txeof(struct lge_softc *sc)
944 struct ifnet *ifp = &sc->arpcom.ac_if;
945 struct lge_tx_desc *cur_tx = NULL;
946 uint32_t idx, txdone;
948 /* Clear the timeout timer. */
952 * Go through our tx list and free mbufs for those
953 * frames that have been transmitted.
955 idx = sc->lge_cdata.lge_tx_cons;
956 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
958 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
959 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
962 if (cur_tx->lge_mbuf != NULL) {
963 m_freem(cur_tx->lge_mbuf);
964 cur_tx->lge_mbuf = NULL;
969 LGE_INC(idx, LGE_TX_LIST_CNT);
973 sc->lge_cdata.lge_tx_cons = idx;
976 ifp->if_flags &= ~IFF_OACTIVE;
982 struct lge_softc *sc = xsc;
983 struct ifnet *ifp = &sc->arpcom.ac_if;
985 lwkt_serialize_enter(ifp->if_serializer);
986 lge_tick_serialized(xsc);
987 lwkt_serialize_exit(ifp->if_serializer);
991 lge_tick_serialized(void *xsc)
993 struct lge_softc *sc = xsc;
994 struct mii_data *mii;
995 struct ifnet *ifp = &sc->arpcom.ac_if;
997 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
998 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
999 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1000 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1002 if (!sc->lge_link) {
1003 mii = device_get_softc(sc->lge_miibus);
1006 if (mii->mii_media_status & IFM_ACTIVE &&
1007 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1009 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1010 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1011 kprintf("lge%d: gigabit link up\n",
1013 if (!ifq_is_empty(&ifp->if_snd))
1018 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1024 struct lge_softc *sc = arg;
1025 struct ifnet *ifp = &sc->arpcom.ac_if;
1028 /* Supress unwanted interrupts */
1029 if ((ifp->if_flags & IFF_UP) == 0) {
1036 * Reading the ISR register clears all interrupts, and
1037 * clears the 'interrupts enabled' bit in the IMR
1040 status = CSR_READ_4(sc, LGE_ISR);
1042 if ((status & LGE_INTRS) == 0)
1045 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1048 if (status & LGE_ISR_RXDMA_DONE)
1049 lge_rxeof(sc, LGE_RX_DMACNT(status));
1051 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1054 if (status & LGE_ISR_PHY_INTR) {
1056 callout_stop(&sc->lge_stat_timer);
1057 lge_tick_serialized(sc);
1061 /* Re-enable interrupts. */
1062 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1064 if (!ifq_is_empty(&ifp->if_snd))
1069 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1070 * pointers to the fragment pointers.
1073 lge_encap(struct lge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1075 struct lge_frag *f = NULL;
1076 struct lge_tx_desc *cur_tx;
1078 int frag = 0, tot_len = 0;
1081 * Start packing the mbufs in this chain into
1082 * the fragment pointers. Stop when we run out
1083 * of fragments or hit the end of the mbuf chain.
1086 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1089 for (m = m_head; m != NULL; m = m->m_next) {
1090 if (m->m_len != 0) {
1091 if (frag == LGE_FRAG_CNT)
1094 tot_len += m->m_len;
1095 f = &cur_tx->lge_frags[frag];
1096 f->lge_fraglen = m->m_len;
1097 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1098 f->lge_fragptr_hi = 0;
1102 /* Caller should make sure that 'm_head' is not excessive fragmented */
1103 KASSERT(m == NULL, ("too many fragments"));
1105 cur_tx->lge_mbuf = m_head;
1106 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1107 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1109 /* Queue for transmit */
1110 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1116 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1117 * to the mbuf data regions directly in the transmit lists. We also save a
1118 * copy of the pointers since the transmit list fragment pointers are
1119 * physical addresses.
1123 lge_start(struct ifnet *ifp)
1125 struct lge_softc *sc = ifp->if_softc;
1126 struct mbuf *m_head = NULL, *m_defragged;
1130 if (!sc->lge_link) {
1131 ifq_purge(&ifp->if_snd);
1135 idx = sc->lge_cdata.lge_tx_prod;
1137 if (ifp->if_flags & IFF_OACTIVE)
1141 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1145 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) {
1146 ifp->if_flags |= IFF_OACTIVE;
1151 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1157 for (m = m_head; m != NULL; m = m->m_next)
1159 if (frags > LGE_FRAG_CNT) {
1160 if (m_defragged != NULL) {
1162 * Even after defragmentation, there
1163 * are still too many fragments, so
1170 m_defragged = m_defrag(m_head, MB_DONTWAIT);
1171 if (m_defragged == NULL) {
1175 m_head = m_defragged;
1177 /* Recount # of fragments */
1181 lge_encap(sc, m_head, &idx);
1184 BPF_MTAP(ifp, m_head);
1190 sc->lge_cdata.lge_tx_prod = idx;
1193 * Set a timeout in case the chip goes out to lunch.
1201 struct lge_softc *sc = xsc;
1202 struct ifnet *ifp = &sc->arpcom.ac_if;
1203 struct mii_data *mii;
1205 if (ifp->if_flags & IFF_RUNNING)
1209 * Cancel pending I/O and free all RX/TX buffers.
1214 mii = device_get_softc(sc->lge_miibus);
1216 /* Set MAC address */
1217 CSR_WRITE_4(sc, LGE_PAR0, *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1218 CSR_WRITE_4(sc, LGE_PAR1, *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1220 /* Init circular RX list. */
1221 if (lge_list_rx_init(sc) == ENOBUFS) {
1222 kprintf("lge%d: initialization failed: no "
1223 "memory for rx buffers\n", sc->lge_unit);
1229 * Init tx descriptors.
1231 lge_list_tx_init(sc);
1233 /* Set initial value for MODE1 register. */
1234 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST |
1235 LGE_MODE1_TX_CRC | LGE_MODE1_TXPAD |
1236 LGE_MODE1_RX_FLOWCTL | LGE_MODE1_SETRST_CTL0 |
1237 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_SETRST_CTL2);
1239 /* If we want promiscuous mode, set the allframes bit. */
1240 if (ifp->if_flags & IFF_PROMISC) {
1241 CSR_WRITE_4(sc, LGE_MODE1,
1242 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_PROMISC);
1244 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1248 * Set the capture broadcast bit to capture broadcast frames.
1250 if (ifp->if_flags & IFF_BROADCAST) {
1251 CSR_WRITE_4(sc, LGE_MODE1,
1252 LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_BCAST);
1254 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1257 /* Packet padding workaround? */
1258 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1260 /* No error frames */
1261 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1263 /* Receive large frames */
1264 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_GIANTS);
1266 /* Workaround: disable RX/TX flow control */
1267 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1268 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1270 /* Make sure to strip CRC from received frames */
1271 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1273 /* Turn off magic packet mode */
1274 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1276 /* Turn off all VLAN stuff */
1277 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX | LGE_MODE1_VLAN_TX |
1278 LGE_MODE1_VLAN_STRIP | LGE_MODE1_VLAN_INSERT);
1280 /* Workarond: FIFO overflow */
1281 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1282 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1285 * Load the multicast filter.
1290 * Enable hardware checksum validation for all received IPv4
1291 * packets, do not reject packets with bad checksums.
1293 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM |
1294 LGE_MODE2_RX_TCPCSUM | LGE_MODE2_RX_UDPCSUM |
1295 LGE_MODE2_RX_ERRCSUM);
1298 * Enable the delivery of PHY interrupts based on
1299 * link/speed/duplex status chalges.
1301 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0 | LGE_MODE1_GMIIPOLL);
1303 /* Enable receiver and transmitter. */
1304 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1305 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_RX_ENB);
1307 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1308 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1 | LGE_MODE1_TX_ENB);
1311 * Enable interrupts.
1313 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0 |
1314 LGE_IMR_SETRST_CTL1 | LGE_IMR_INTR_ENB|LGE_INTRS);
1316 lge_ifmedia_upd(ifp);
1318 ifp->if_flags |= IFF_RUNNING;
1319 ifp->if_flags &= ~IFF_OACTIVE;
1321 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1325 * Set media options.
1328 lge_ifmedia_upd(struct ifnet *ifp)
1330 struct lge_softc *sc = ifp->if_softc;
1331 struct mii_data *mii = device_get_softc(sc->lge_miibus);
1334 if (mii->mii_instance) {
1335 struct mii_softc *miisc;
1336 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1337 mii_phy_reset(miisc);
1345 * Report current media status.
1348 lge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1350 struct lge_softc *sc = ifp->if_softc;
1351 struct mii_data *mii;
1353 mii = device_get_softc(sc->lge_miibus);
1355 ifmr->ifm_active = mii->mii_media_active;
1356 ifmr->ifm_status = mii->mii_media_status;
1360 lge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1362 struct lge_softc *sc = ifp->if_softc;
1363 struct ifreq *ifr = (struct ifreq *) data;
1364 struct mii_data *mii;
1369 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1372 ifp->if_mtu = ifr->ifr_mtu;
1375 if (ifp->if_flags & IFF_UP) {
1376 if (ifp->if_flags & IFF_RUNNING &&
1377 ifp->if_flags & IFF_PROMISC &&
1378 !(sc->lge_if_flags & IFF_PROMISC)) {
1379 CSR_WRITE_4(sc, LGE_MODE1,
1380 LGE_MODE1_SETRST_CTL1|
1381 LGE_MODE1_RX_PROMISC);
1382 } else if (ifp->if_flags & IFF_RUNNING &&
1383 !(ifp->if_flags & IFF_PROMISC) &&
1384 sc->lge_if_flags & IFF_PROMISC) {
1385 CSR_WRITE_4(sc, LGE_MODE1,
1386 LGE_MODE1_RX_PROMISC);
1388 ifp->if_flags &= ~IFF_RUNNING;
1392 if (ifp->if_flags & IFF_RUNNING)
1395 sc->lge_if_flags = ifp->if_flags;
1405 mii = device_get_softc(sc->lge_miibus);
1406 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1409 error = ether_ioctl(ifp, command, data);
1417 lge_watchdog(struct ifnet *ifp)
1419 struct lge_softc *sc = ifp->if_softc;
1422 kprintf("lge%d: watchdog timeout\n", sc->lge_unit);
1426 ifp->if_flags &= ~IFF_RUNNING;
1429 if (!ifq_is_empty(&ifp->if_snd))
1434 * Stop the adapter and free any mbufs allocated to the
1438 lge_stop(struct lge_softc *sc)
1440 struct ifnet *ifp = &sc->arpcom.ac_if;
1444 callout_stop(&sc->lge_stat_timer);
1445 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1447 /* Disable receiver and transmitter. */
1448 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1452 * Free data in the RX lists.
1454 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1455 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1456 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1457 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1460 bzero(&sc->lge_ldata->lge_rx_list, sizeof(sc->lge_ldata->lge_rx_list));
1463 * Free the TX list buffers.
1465 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1466 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1467 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1468 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1472 bzero(&sc->lge_ldata->lge_tx_list, sizeof(sc->lge_ldata->lge_tx_list));
1474 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1478 * Stop all chip I/O so that the kernel's probe routines don't
1479 * get confused by errant DMAs when rebooting.
1482 lge_shutdown(device_t dev)
1484 struct lge_softc *sc = device_get_softc(dev);