2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
28 * This driver exists largely as a result of other people's efforts.
29 * Much of register handling is based on NetBSD CMI8x38 audio driver
30 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
31 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
32 * registers and the 8738 mixer devices. His Linux driver was also a
33 * useful reference point.
37 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
39 * This card/code does not always manage to sample at 44100 - actual
40 * rate drifts slightly between recordings (usually 0-3%). No
41 * differences visible in register dumps between times that work and
45 #ifdef HAVE_KERNEL_OPTION_HEADERS
49 #include <dev/sound/pcm/sound.h>
50 #include <dev/sound/pci/cmireg.h>
51 #include <dev/sound/pci/sb.h>
53 #include <bus/pci/pcireg.h>
54 #include <bus/pci/pcivar.h>
56 #include <sys/sysctl.h>
60 SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cmi.c 254263 2013-08-12 23:30:01Z scottl $");
62 /* Supported chip ID's */
63 #define CMI8338A_PCI_ID 0x010013f6
64 #define CMI8338B_PCI_ID 0x010113f6
65 #define CMI8738_PCI_ID 0x011113f6
66 #define CMI8738B_PCI_ID 0x011213f6
67 #define CMI120_USB_ID 0x01030d8c
69 /* Buffer size max is 64k for permitted DMA boundaries */
70 #define CMI_DEFAULT_BUFSZ 16384
72 /* Interrupts per length of buffer */
73 #define CMI_INTR_PER_BUFFER 2
75 /* Clarify meaning of named defines in cmireg.h */
76 #define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
77 #define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
78 #define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
79 #define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
81 /* Our indication of custom mixer control */
82 #define CMPCI_NON_SB16_CONTROL 0xff
84 /* Debugging macro's */
87 #define DEB(x) /* x */
91 #define DEBMIX(x) /* x */
94 /* ------------------------------------------------------------------------- */
100 struct sc_info *parent;
101 struct pcm_channel *channel;
102 struct snd_dbuf *buffer;
103 u_int32_t fmt, spd, phys_buf, bps;
104 u_int32_t dma_active:1, dma_was_active:1;
112 bus_space_handle_t sh;
113 bus_dma_tag_t parent_dmat;
114 struct resource *reg, *irq;
121 struct sc_chinfo pch, rch;
126 static u_int32_t cmi_fmt[] = {
127 SND_FORMAT(AFMT_U8, 1, 0),
128 SND_FORMAT(AFMT_U8, 2, 0),
129 SND_FORMAT(AFMT_S16_LE, 1, 0),
130 SND_FORMAT(AFMT_S16_LE, 2, 0),
134 static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
136 /* ------------------------------------------------------------------------- */
137 /* Register Utilities */
140 cmi_rd(struct sc_info *sc, int regno, int size)
144 return bus_space_read_1(sc->st, sc->sh, regno);
146 return bus_space_read_2(sc->st, sc->sh, regno);
148 return bus_space_read_4(sc->st, sc->sh, regno);
150 DEB(kprintf("cmi_rd: failed 0x%04x %d\n", regno, size));
156 cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
160 bus_space_write_1(sc->st, sc->sh, regno, data);
163 bus_space_write_2(sc->st, sc->sh, regno, data);
166 bus_space_write_4(sc->st, sc->sh, regno, data);
172 cmi_partial_wr4(struct sc_info *sc,
173 int reg, int shift, u_int32_t mask, u_int32_t val)
177 r = cmi_rd(sc, reg, 4);
178 r &= ~(mask << shift);
180 cmi_wr(sc, reg, r, 4);
184 cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
188 r = cmi_rd(sc, reg, 4);
190 cmi_wr(sc, reg, r, 4);
194 cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
198 r = cmi_rd(sc, reg, 4);
200 cmi_wr(sc, reg, r, 4);
203 /* ------------------------------------------------------------------------- */
206 static int cmi_rates[] = {5512, 8000, 11025, 16000,
207 22050, 32000, 44100, 48000};
208 #define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
210 /* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
211 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
214 cmpci_rate_to_regvalue(int rate)
218 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
219 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
224 DEB(kprintf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
226 r = ((i >> 1) | (i << 2)) & 0x07;
231 cmpci_regvalue_to_rate(u_int32_t r)
235 i = ((r << 1) | (r >> 2)) & 0x07;
236 DEB(kprintf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
240 /* ------------------------------------------------------------------------- */
241 /* ADC/DAC control - there are 2 dma channels on 8738, either can be
242 * playback or capture. We use ch0 for playback and ch1 for capture. */
245 cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
249 ch->phys_buf = sndbuf_getbufaddr(ch->buffer);
251 cmi_wr(sc, base, ch->phys_buf, 4);
252 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
254 s = sz / ch->bps - 1;
255 cmi_wr(sc, base + 4, s, 2);
257 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
258 cmi_wr(sc, base + 6, i, 2);
263 cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
265 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
267 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
268 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
269 CMPCI_REG_CH0_INTR_ENABLE);
275 cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
277 u_int32_t r = ch->dma_active;
279 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
280 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
281 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
282 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
288 cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
290 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
291 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
292 /* Enable Interrupts */
293 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
294 CMPCI_REG_CH1_INTR_ENABLE);
295 DEB(kprintf("cmi_ch1_start: dma prog\n"));
300 cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
302 u_int32_t r = ch->dma_active;
304 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
305 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
306 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
307 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
313 cmi_spdif_speed(struct sc_info *sc, int speed) {
314 u_int32_t fcr1, lcr, mcr;
316 if (speed >= 44100) {
317 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
318 lcr = CMPCI_REG_XSPDIF_ENABLE;
319 mcr = (speed == 48000) ?
320 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
322 fcr1 = mcr = lcr = 0;
325 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
326 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
327 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
328 CMPCI_REG_SPDIF0_ENABLE, fcr1);
329 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
330 CMPCI_REG_XSPDIF_ENABLE, lcr);
333 /* ------------------------------------------------------------------------- */
334 /* Channel Interface implementation */
337 cmichan_init(kobj_t obj, void *devinfo,
338 struct snd_dbuf *b, struct pcm_channel *c, int dir)
340 struct sc_info *sc = devinfo;
341 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
346 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
347 ch->spd = DSP_DEFAULT_SPEED;
350 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, 0, sc->bufsz) != 0) {
351 DEB(kprintf("cmichan_init failed\n"));
356 snd_mtxlock(sc->lock);
357 if (ch->dir == PCMDIR_PLAY) {
358 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
360 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
362 snd_mtxunlock(sc->lock);
368 cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
370 struct sc_chinfo *ch = data;
371 struct sc_info *sc = ch->parent;
374 if (format & AFMT_S16_LE) {
375 f = CMPCI_REG_FORMAT_16BIT;
378 f = CMPCI_REG_FORMAT_8BIT;
382 if (AFMT_CHANNEL(format) > 1) {
383 f |= CMPCI_REG_FORMAT_STEREO;
386 f |= CMPCI_REG_FORMAT_MONO;
389 snd_mtxlock(sc->lock);
390 if (ch->dir == PCMDIR_PLAY) {
391 cmi_partial_wr4(ch->parent,
392 CMPCI_REG_CHANNEL_FORMAT,
393 CMPCI_REG_CH0_FORMAT_SHIFT,
394 CMPCI_REG_CH0_FORMAT_MASK,
397 cmi_partial_wr4(ch->parent,
398 CMPCI_REG_CHANNEL_FORMAT,
399 CMPCI_REG_CH1_FORMAT_SHIFT,
400 CMPCI_REG_CH1_FORMAT_MASK,
403 snd_mtxunlock(sc->lock);
410 cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
412 struct sc_chinfo *ch = data;
413 struct sc_info *sc = ch->parent;
416 r = cmpci_rate_to_regvalue(speed);
417 snd_mtxlock(sc->lock);
418 if (ch->dir == PCMDIR_PLAY) {
420 /* disable if req before rate change */
421 cmi_spdif_speed(ch->parent, speed);
423 cmi_partial_wr4(ch->parent,
425 CMPCI_REG_DAC_FS_SHIFT,
426 CMPCI_REG_DAC_FS_MASK,
428 if (speed >= 44100 && ch->parent->spdif_enabled) {
429 /* enable if req after rate change */
430 cmi_spdif_speed(ch->parent, speed);
432 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
433 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
434 rsp &= CMPCI_REG_DAC_FS_MASK;
436 cmi_partial_wr4(ch->parent,
438 CMPCI_REG_ADC_FS_SHIFT,
439 CMPCI_REG_ADC_FS_MASK,
441 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
442 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
443 rsp &= CMPCI_REG_ADC_FS_MASK;
445 snd_mtxunlock(sc->lock);
446 ch->spd = cmpci_regvalue_to_rate(r);
448 DEB(kprintf("cmichan_setspeed (%s) %d -> %d (%d)\n",
449 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
450 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
456 cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
458 struct sc_chinfo *ch = data;
459 struct sc_info *sc = ch->parent;
461 /* user has requested interrupts every blocksize bytes */
462 if (blocksize > sc->bufsz / CMI_INTR_PER_BUFFER) {
463 blocksize = sc->bufsz / CMI_INTR_PER_BUFFER;
465 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
471 cmichan_trigger(kobj_t obj, void *data, int go)
473 struct sc_chinfo *ch = data;
474 struct sc_info *sc = ch->parent;
476 if (!PCMTRIG_COMMON(go))
479 snd_mtxlock(sc->lock);
480 if (ch->dir == PCMDIR_PLAY) {
483 cmi_ch0_start(sc, ch);
487 cmi_ch0_stop(sc, ch);
493 cmi_ch1_start(sc, ch);
497 cmi_ch1_stop(sc, ch);
501 snd_mtxunlock(sc->lock);
506 cmichan_getptr(kobj_t obj, void *data)
508 struct sc_chinfo *ch = data;
509 struct sc_info *sc = ch->parent;
510 u_int32_t physptr, bufptr, sz;
512 snd_mtxlock(sc->lock);
513 if (ch->dir == PCMDIR_PLAY) {
514 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
516 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
518 snd_mtxunlock(sc->lock);
520 sz = sndbuf_getsize(ch->buffer);
521 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
529 struct sc_info *sc = data;
533 snd_mtxlock(sc->lock);
534 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
535 if ((intrstat & CMPCI_REG_ANY_INTR) != 0) {
538 if (intrstat & CMPCI_REG_CH0_INTR) {
539 toclear |= CMPCI_REG_CH0_INTR_ENABLE;
540 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
543 if (intrstat & CMPCI_REG_CH1_INTR) {
544 toclear |= CMPCI_REG_CH1_INTR_ENABLE;
545 //cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
549 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, toclear);
550 snd_mtxunlock(sc->lock);
552 /* Signal interrupts to channel */
553 if (intrstat & CMPCI_REG_CH0_INTR) {
554 chn_intr(sc->pch.channel);
557 if (intrstat & CMPCI_REG_CH1_INTR) {
558 chn_intr(sc->rch.channel);
561 snd_mtxlock(sc->lock);
562 cmi_set4(sc, CMPCI_REG_INTR_CTRL, toclear);
566 snd_mtxunlock(sc->lock);
570 static struct pcmchan_caps *
571 cmichan_getcaps(kobj_t obj, void *data)
576 static kobj_method_t cmichan_methods[] = {
577 KOBJMETHOD(channel_init, cmichan_init),
578 KOBJMETHOD(channel_setformat, cmichan_setformat),
579 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
580 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
581 KOBJMETHOD(channel_trigger, cmichan_trigger),
582 KOBJMETHOD(channel_getptr, cmichan_getptr),
583 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
586 CHANNEL_DECLARE(cmichan);
588 /* ------------------------------------------------------------------------- */
589 /* Mixer - sb16 with kinks */
592 cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
594 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
595 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
599 cmimix_rd(struct sc_info *sc, u_int8_t port)
601 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
602 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
606 u_int8_t rreg; /* right reg chan register */
607 u_int8_t stereo:1; /* (no explanation needed, honest) */
608 u_int8_t rec:1; /* recording source */
609 u_int8_t bits:3; /* num bits to represent maximum gain rep */
610 u_int8_t oselect; /* output select mask */
611 u_int8_t iselect; /* right input select mask */
614 static const struct sb16props cmt[SOUND_MIXER_NRDEVICES] = {
615 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
616 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
617 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
618 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
619 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
620 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
621 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
622 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
623 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
624 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
625 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
626 /* These controls are not implemented in CMI8738, but maybe at a
627 future date. They are not documented in C-Media documentation,
628 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
630 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
631 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
632 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
633 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
634 /* The mic pre-amp is implemented with non-SB16 compatible
636 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
639 #define MIXER_GAIN_REG_RTOL(r) (r - 1)
642 cmimix_init(struct snd_mixer *m)
644 struct sc_info *sc = mix_getdevinfo(m);
647 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
648 if (cmt[i].bits) v |= 1 << i;
652 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
653 if (cmt[i].rec) v |= 1 << i;
655 mix_setrecdevs(m, v);
657 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
658 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
659 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
660 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
661 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
666 cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
668 struct sc_info *sc = mix_getdevinfo(m);
672 max = (1 << cmt[dev].bits) - 1;
674 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
675 /* For time being this can only be one thing (mic in
677 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
678 l = left * max / 100;
679 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
680 v |= ((l << 1) | (~l >> 3)) & 0x0f;
681 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
685 l = (left * max / 100) << (8 - cmt[dev].bits);
686 if (cmt[dev].stereo) {
687 r = (right * max / 100) << (8 - cmt[dev].bits);
688 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
689 cmimix_wr(sc, cmt[dev].rreg, r);
690 DEBMIX(kprintf("Mixer stereo write dev %d reg 0x%02x "\
691 "value 0x%02x:0x%02x\n",
692 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
695 cmimix_wr(sc, cmt[dev].rreg, l);
696 DEBMIX(kprintf("Mixer mono write dev %d reg 0x%02x " \
697 "value 0x%02x:0x%02x\n",
698 dev, cmt[dev].rreg, l, l));
701 /* Zero gain does not mute channel from output, but this does... */
702 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
703 if (l == 0 && r == 0) {
704 v &= ~cmt[dev].oselect;
706 v |= cmt[dev].oselect;
708 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
714 cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
716 struct sc_info *sc = mix_getdevinfo(m);
720 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
723 sl |= cmt[i].iselect;
725 ml |= cmt[i].iselect;
729 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
730 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
731 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
732 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
733 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
734 DEBMIX(kprintf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
735 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
740 /* Optional SPDIF support. */
743 cmi_initsys(struct sc_info* sc)
745 /* XXX: an user should be able to set this with a control tool,
746 if not done before 7.0-RELEASE, this needs to be converted
747 to a device specific sysctl "dev.pcm.X.yyy" via
748 device_get_sysctl_*() as discussed on multimedia@ in msg-id
749 <861wujij2q.fsf@xps.des.no> */
750 SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev),
751 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
752 OID_AUTO, "spdif_enabled", CTLFLAG_RW,
753 &sc->spdif_enabled, 0,
754 "enable SPDIF output at 44.1 kHz and above");
759 /* ------------------------------------------------------------------------- */
760 static kobj_method_t cmi_mixer_methods[] = {
761 KOBJMETHOD(mixer_init, cmimix_init),
762 KOBJMETHOD(mixer_set, cmimix_set),
763 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
766 MIXER_DECLARE(cmi_mixer);
768 /* ------------------------------------------------------------------------- */
769 /* Power and reset */
772 cmi_power(struct sc_info *sc, int state)
775 case 0: /* full power */
776 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
780 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
786 cmi_init(struct sc_info *sc)
789 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
791 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
793 /* Disable interrupts and channels */
794 cmi_clr4(sc, CMPCI_REG_FUNC_0,
795 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
796 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
797 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
799 /* Configure DMA channels, ch0 = play, ch1 = capture */
800 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
801 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
803 /* Attempt to enable 4 Channel output */
804 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
806 /* Disable SPDIF1 - not compatible with config */
807 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
808 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
814 cmi_uninit(struct sc_info *sc)
816 /* Disable interrupts and channels */
817 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
818 CMPCI_REG_CH0_INTR_ENABLE |
819 CMPCI_REG_CH1_INTR_ENABLE |
820 CMPCI_REG_TDMA_INTR_ENABLE);
821 cmi_clr4(sc, CMPCI_REG_FUNC_0,
822 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
823 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_UART_ENABLE);
826 /* ------------------------------------------------------------------------- */
827 /* Bus and device registration */
829 cmi_probe(device_t dev)
831 switch(pci_get_devid(dev)) {
832 case CMI8338A_PCI_ID:
833 device_set_desc(dev, "CMedia CMI8338A");
834 return BUS_PROBE_DEFAULT;
835 case CMI8338B_PCI_ID:
836 device_set_desc(dev, "CMedia CMI8338B");
837 return BUS_PROBE_DEFAULT;
839 device_set_desc(dev, "CMedia CMI8738");
840 return BUS_PROBE_DEFAULT;
841 case CMI8738B_PCI_ID:
842 device_set_desc(dev, "CMedia CMI8738B");
843 return BUS_PROBE_DEFAULT;
845 device_set_desc(dev, "CMedia CMI120");
846 return BUS_PROBE_DEFAULT;
853 cmi_attach(device_t dev)
856 char status[SND_STATUSLEN];
858 sc = kmalloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
859 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_cmi softc");
860 pci_enable_busmaster(dev);
863 sc->regid = PCIR_BAR(0);
864 sc->reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->regid,
867 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
870 sc->st = rman_get_bustag(sc->reg);
871 sc->sh = rman_get_bushandle(sc->reg);
874 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
875 RF_ACTIVE | RF_SHAREABLE);
877 snd_setup_intr(dev, sc->irq, INTR_MPSAFE, cmi_intr, sc, &sc->ih)) {
878 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
882 sc->bufsz = pcm_getbuffersize(dev, 4096, CMI_DEFAULT_BUFSZ, 65536);
884 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
886 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
887 /*highaddr*/BUS_SPACE_MAXADDR,
888 /*filter*/NULL, /*filterarg*/NULL,
889 /*maxsize*/sc->bufsz, /*nsegments*/1,
890 /*maxsegz*/0x3ffff, /*flags*/0,
891 &sc->parent_dmat) != 0) {
892 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
900 if (mixer_init(dev, &cmi_mixer_class, sc))
903 if (pcm_register(dev, sc, 1, 1))
908 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
909 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
911 ksnprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld %s",
912 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cmi));
913 pcm_setstatus(dev, status);
915 DEB(kprintf("cmi_attach: succeeded\n"));
920 bus_dma_tag_destroy(sc->parent_dmat);
922 bus_teardown_intr(dev, sc->irq, sc->ih);
924 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
926 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
928 snd_mtxfree(sc->lock);
936 cmi_detach(device_t dev)
941 r = pcm_unregister(dev);
944 sc = pcm_getdevinfo(dev);
948 bus_dma_tag_destroy(sc->parent_dmat);
949 bus_teardown_intr(dev, sc->irq, sc->ih);
950 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
951 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
952 snd_mtxfree(sc->lock);
959 cmi_suspend(device_t dev)
961 struct sc_info *sc = pcm_getdevinfo(dev);
963 snd_mtxlock(sc->lock);
964 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
965 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
967 snd_mtxunlock(sc->lock);
972 cmi_resume(device_t dev)
974 struct sc_info *sc = pcm_getdevinfo(dev);
976 snd_mtxlock(sc->lock);
978 if (cmi_init(sc) != 0) {
979 device_printf(dev, "unable to reinitialize the card\n");
980 snd_mtxunlock(sc->lock);
984 if (mixer_reinit(dev) == -1) {
985 device_printf(dev, "unable to reinitialize the mixer\n");
986 snd_mtxunlock(sc->lock);
990 if (sc->pch.dma_was_active) {
991 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
992 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
993 cmi_ch0_start(sc, &sc->pch);
996 if (sc->rch.dma_was_active) {
997 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
998 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
999 cmi_ch1_start(sc, &sc->rch);
1001 snd_mtxunlock(sc->lock);
1005 static device_method_t cmi_methods[] = {
1006 DEVMETHOD(device_probe, cmi_probe),
1007 DEVMETHOD(device_attach, cmi_attach),
1008 DEVMETHOD(device_detach, cmi_detach),
1009 DEVMETHOD(device_resume, cmi_resume),
1010 DEVMETHOD(device_suspend, cmi_suspend),
1014 static driver_t cmi_driver = {
1020 DRIVER_MODULE(snd_cmi, pci, cmi_driver, pcm_devclass, 0, 0);
1021 MODULE_DEPEND(snd_cmi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1022 MODULE_VERSION(snd_cmi, 1);