2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116 if (sc->rss_debug >= lvl) \
117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119 #else /* !EMX_RSS_DEBUG */
120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121 #endif /* EMX_RSS_DEBUG */
123 #define EMX_TX_SERIALIZE 1
124 #define EMX_RX_SERIALIZE 3
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 /* required last entry */
169 static int emx_probe(device_t);
170 static int emx_attach(device_t);
171 static int emx_detach(device_t);
172 static int emx_shutdown(device_t);
173 static int emx_suspend(device_t);
174 static int emx_resume(device_t);
176 static void emx_init(void *);
177 static void emx_stop(struct emx_softc *);
178 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179 static void emx_start(struct ifnet *, struct ifaltq_subque *);
181 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
182 static void emx_npoll_status(struct ifnet *);
183 static void emx_npoll_tx(struct ifnet *, void *, int);
184 static void emx_npoll_rx(struct ifnet *, void *, int);
186 static void emx_watchdog(struct ifaltq_subque *);
187 static void emx_media_status(struct ifnet *, struct ifmediareq *);
188 static int emx_media_change(struct ifnet *);
189 static void emx_timer(void *);
190 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
191 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
192 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
194 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
198 static void emx_intr(void *);
199 static void emx_intr_mask(void *);
200 static void emx_intr_body(struct emx_softc *, boolean_t);
201 static void emx_rxeof(struct emx_rxdata *, int);
202 static void emx_txeof(struct emx_txdata *);
203 static void emx_tx_collect(struct emx_txdata *);
204 static void emx_tx_purge(struct emx_softc *);
205 static void emx_enable_intr(struct emx_softc *);
206 static void emx_disable_intr(struct emx_softc *);
208 static int emx_dma_alloc(struct emx_softc *);
209 static void emx_dma_free(struct emx_softc *);
210 static void emx_init_tx_ring(struct emx_txdata *);
211 static int emx_init_rx_ring(struct emx_rxdata *);
212 static void emx_free_tx_ring(struct emx_txdata *);
213 static void emx_free_rx_ring(struct emx_rxdata *);
214 static int emx_create_tx_ring(struct emx_txdata *);
215 static int emx_create_rx_ring(struct emx_rxdata *);
216 static void emx_destroy_tx_ring(struct emx_txdata *, int);
217 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
218 static int emx_newbuf(struct emx_rxdata *, int, int);
219 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
220 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
221 uint32_t *, uint32_t *);
222 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
223 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
224 uint32_t *, uint32_t *);
225 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
227 static int emx_is_valid_eaddr(const uint8_t *);
228 static int emx_reset(struct emx_softc *);
229 static void emx_setup_ifp(struct emx_softc *);
230 static void emx_init_tx_unit(struct emx_softc *);
231 static void emx_init_rx_unit(struct emx_softc *);
232 static void emx_update_stats(struct emx_softc *);
233 static void emx_set_promisc(struct emx_softc *);
234 static void emx_disable_promisc(struct emx_softc *);
235 static void emx_set_multi(struct emx_softc *);
236 static void emx_update_link_status(struct emx_softc *);
237 static void emx_smartspeed(struct emx_softc *);
238 static void emx_set_itr(struct emx_softc *, uint32_t);
239 static void emx_disable_aspm(struct emx_softc *);
241 static void emx_print_debug_info(struct emx_softc *);
242 static void emx_print_nvm_info(struct emx_softc *);
243 static void emx_print_hw_stats(struct emx_softc *);
245 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
246 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
247 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
248 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
249 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
251 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
252 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
254 static void emx_add_sysctl(struct emx_softc *);
256 static void emx_serialize_skipmain(struct emx_softc *);
257 static void emx_deserialize_skipmain(struct emx_softc *);
259 /* Management and WOL Support */
260 static void emx_get_mgmt(struct emx_softc *);
261 static void emx_rel_mgmt(struct emx_softc *);
262 static void emx_get_hw_control(struct emx_softc *);
263 static void emx_rel_hw_control(struct emx_softc *);
264 static void emx_enable_wol(device_t);
266 static device_method_t emx_methods[] = {
267 /* Device interface */
268 DEVMETHOD(device_probe, emx_probe),
269 DEVMETHOD(device_attach, emx_attach),
270 DEVMETHOD(device_detach, emx_detach),
271 DEVMETHOD(device_shutdown, emx_shutdown),
272 DEVMETHOD(device_suspend, emx_suspend),
273 DEVMETHOD(device_resume, emx_resume),
277 static driver_t emx_driver = {
280 sizeof(struct emx_softc),
283 static devclass_t emx_devclass;
285 DECLARE_DUMMY_MODULE(if_emx);
286 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
287 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
292 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
293 static int emx_rxd = EMX_DEFAULT_RXD;
294 static int emx_txd = EMX_DEFAULT_TXD;
295 static int emx_smart_pwr_down = 0;
296 static int emx_rxr = 0;
297 static int emx_txr = 1;
299 /* Controls whether promiscuous also shows bad packets */
300 static int emx_debug_sbp = 0;
302 static int emx_82573_workaround = 1;
303 static int emx_msi_enable = 1;
305 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
306 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
307 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
308 TUNABLE_INT("hw.emx.txd", &emx_txd);
309 TUNABLE_INT("hw.emx.txr", &emx_txr);
310 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
311 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
312 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
313 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
315 /* Global used in WOL setup with multiport cards */
316 static int emx_global_quad_port_a = 0;
318 /* Set this to one to display debug statistics */
319 static int emx_display_debug_stats = 0;
321 #if !defined(KTR_IF_EMX)
322 #define KTR_IF_EMX KTR_ALL
324 KTR_INFO_MASTER(if_emx);
325 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
326 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
327 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
328 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
329 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
330 #define logif(name) KTR_LOG(if_emx_ ## name)
333 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
335 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
336 /* DD bit must be cleared */
337 rxd->rxd_staterr = 0;
341 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
343 /* Ignore Checksum bit is set */
344 if (staterr & E1000_RXD_STAT_IXSM)
347 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
349 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
351 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
352 E1000_RXD_STAT_TCPCS) {
353 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
355 CSUM_FRAG_NOT_CHECKED;
356 mp->m_pkthdr.csum_data = htons(0xffff);
360 static __inline struct pktinfo *
361 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
362 uint32_t mrq, uint32_t hash, uint32_t staterr)
364 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
365 case EMX_RXDMRQ_IPV4_TCP:
366 pi->pi_netisr = NETISR_IP;
368 pi->pi_l3proto = IPPROTO_TCP;
371 case EMX_RXDMRQ_IPV6_TCP:
372 pi->pi_netisr = NETISR_IPV6;
374 pi->pi_l3proto = IPPROTO_TCP;
377 case EMX_RXDMRQ_IPV4:
378 if (staterr & E1000_RXD_STAT_IXSM)
382 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
383 E1000_RXD_STAT_TCPCS) {
384 pi->pi_netisr = NETISR_IP;
386 pi->pi_l3proto = IPPROTO_UDP;
394 m->m_flags |= M_HASH;
395 m->m_pkthdr.hash = toeplitz_hash(hash);
400 emx_probe(device_t dev)
402 const struct emx_device *d;
405 vid = pci_get_vendor(dev);
406 did = pci_get_device(dev);
408 for (d = emx_devices; d->desc != NULL; ++d) {
409 if (vid == d->vid && did == d->did) {
410 device_set_desc(dev, d->desc);
411 device_set_async_attach(dev, TRUE);
419 emx_attach(device_t dev)
421 struct emx_softc *sc = device_get_softc(dev);
422 int error = 0, i, throttle, msi_enable, tx_ring_max;
424 uint16_t eeprom_data, device_id, apme_mask;
425 driver_intr_t *intr_func;
427 int offset, offset_def;
433 for (i = 0; i < EMX_NRX_RING; ++i) {
434 sc->rx_data[i].sc = sc;
435 sc->rx_data[i].idx = i;
441 for (i = 0; i < EMX_NTX_RING; ++i) {
442 sc->tx_data[i].sc = sc;
443 sc->tx_data[i].idx = i;
447 * Initialize serializers
449 lwkt_serialize_init(&sc->main_serialize);
450 for (i = 0; i < EMX_NTX_RING; ++i)
451 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
452 for (i = 0; i < EMX_NRX_RING; ++i)
453 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
456 * Initialize serializer array
459 sc->serializes[i++] = &sc->main_serialize;
461 KKASSERT(i == EMX_TX_SERIALIZE);
462 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
463 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
465 KKASSERT(i == EMX_RX_SERIALIZE);
466 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
467 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
468 KKASSERT(i == EMX_NSERIALIZE);
470 callout_init_mp(&sc->timer);
472 sc->dev = sc->osdep.dev = dev;
475 * Determine hardware and mac type
477 sc->hw.vendor_id = pci_get_vendor(dev);
478 sc->hw.device_id = pci_get_device(dev);
479 sc->hw.revision_id = pci_get_revid(dev);
480 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
481 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
483 if (e1000_set_mac_type(&sc->hw))
486 /* Enable bus mastering */
487 pci_enable_busmaster(dev);
492 sc->memory_rid = EMX_BAR_MEM;
493 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
494 &sc->memory_rid, RF_ACTIVE);
495 if (sc->memory == NULL) {
496 device_printf(dev, "Unable to allocate bus resource: memory\n");
500 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
501 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
503 /* XXX This is quite goofy, it is not actually used */
504 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
507 * Don't enable MSI-X on 82574, see:
508 * 82574 specification update errata #15
510 * Don't enable MSI on 82571/82572, see:
511 * 82571/82572 specification update errata #63
513 msi_enable = emx_msi_enable;
515 (sc->hw.mac.type == e1000_82571 ||
516 sc->hw.mac.type == e1000_82572))
522 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
523 &sc->intr_rid, &intr_flags);
525 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
528 unshared = device_getenv_int(dev, "irq.unshared", 0);
530 sc->flags |= EMX_FLAG_SHARED_INTR;
532 device_printf(dev, "IRQ shared\n");
534 intr_flags &= ~RF_SHAREABLE;
536 device_printf(dev, "IRQ unshared\n");
540 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
542 if (sc->intr_res == NULL) {
543 device_printf(dev, "Unable to allocate bus resource: "
549 /* Save PCI command register for Shared Code */
550 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
551 sc->hw.back = &sc->osdep;
553 /* Do Shared Code initialization */
554 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
555 device_printf(dev, "Setup of Shared code failed\n");
559 e1000_get_bus_info(&sc->hw);
561 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
562 sc->hw.phy.autoneg_wait_to_complete = FALSE;
563 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
566 * Interrupt throttle rate
568 throttle = device_getenv_int(dev, "int_throttle_ceil",
569 emx_int_throttle_ceil);
571 sc->int_throttle_ceil = 0;
574 throttle = EMX_DEFAULT_ITR;
576 /* Recalculate the tunable value to get the exact frequency. */
577 throttle = 1000000000 / 256 / throttle;
579 /* Upper 16bits of ITR is reserved and should be zero */
580 if (throttle & 0xffff0000)
581 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
583 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
586 e1000_init_script_state_82541(&sc->hw, TRUE);
587 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
590 if (sc->hw.phy.media_type == e1000_media_type_copper) {
591 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
592 sc->hw.phy.disable_polarity_correction = FALSE;
593 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
596 /* Set the frame limits assuming standard ethernet sized frames. */
597 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
598 sc->min_frame_size = ETHER_MIN_LEN;
600 /* This controls when hardware reports transmit completion status. */
601 sc->hw.mac.report_tx_early = 1;
603 /* Calculate # of RX rings */
604 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
605 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
608 * Calculate # of TX rings
611 * Don't enable multiple TX queues on 82574; it always gives
612 * watchdog timeout on TX queue0, when multiple TCP streams are
613 * received. It was originally suspected that the hardware TX
614 * checksum offloading caused this watchdog timeout, since only
615 * TCP ACKs are sent during TCP receiving tests. However, even
616 * if the hardware TX checksum offloading is disable, TX queue0
617 * still will give watchdog.
620 if (sc->hw.mac.type == e1000_82571 ||
621 sc->hw.mac.type == e1000_82572 ||
622 sc->hw.mac.type == e1000_80003es2lan)
623 tx_ring_max = EMX_NTX_RING;
624 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
625 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
627 /* Allocate RX/TX rings' busdma(9) stuffs */
628 error = emx_dma_alloc(sc);
632 /* Allocate multicast array memory. */
633 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
636 /* Indicate SOL/IDER usage */
637 if (e1000_check_reset_block(&sc->hw)) {
639 "PHY reset is blocked due to SOL/IDER session.\n");
643 * Start from a known state, this is important in reading the
644 * nvm and mac from that.
646 e1000_reset_hw(&sc->hw);
648 /* Make sure we have a good EEPROM before we read from it */
649 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
651 * Some PCI-E parts fail the first check due to
652 * the link being in sleep state, call it again,
653 * if it fails a second time its a real issue.
655 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
657 "The EEPROM Checksum Is Not Valid\n");
663 /* Copy the permanent MAC address out of the EEPROM */
664 if (e1000_read_mac_addr(&sc->hw) < 0) {
665 device_printf(dev, "EEPROM read error while reading MAC"
670 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
671 device_printf(dev, "Invalid MAC address\n");
676 /* Determine if we have to control management hardware */
677 if (e1000_enable_mng_pass_thru(&sc->hw))
678 sc->flags |= EMX_FLAG_HAS_MGMT;
683 apme_mask = EMX_EEPROM_APME;
685 switch (sc->hw.mac.type) {
687 sc->flags |= EMX_FLAG_HAS_AMT;
692 case e1000_80003es2lan:
693 if (sc->hw.bus.func == 1) {
694 e1000_read_nvm(&sc->hw,
695 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
697 e1000_read_nvm(&sc->hw,
698 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
703 e1000_read_nvm(&sc->hw,
704 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
707 if (eeprom_data & apme_mask)
708 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
711 * We have the eeprom settings, now apply the special cases
712 * where the eeprom may be wrong or the board won't support
713 * wake on lan on a particular port
715 device_id = pci_get_device(dev);
717 case E1000_DEV_ID_82571EB_FIBER:
719 * Wake events only supported on port A for dual fiber
720 * regardless of eeprom setting
722 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
727 case E1000_DEV_ID_82571EB_QUAD_COPPER:
728 case E1000_DEV_ID_82571EB_QUAD_FIBER:
729 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
730 /* if quad port sc, disable WoL on all but port A */
731 if (emx_global_quad_port_a != 0)
733 /* Reset for multiple quad port adapters */
734 if (++emx_global_quad_port_a == 4)
735 emx_global_quad_port_a = 0;
739 /* XXX disable wol */
744 * NPOLLING RX CPU offset
746 if (sc->rx_ring_cnt == ncpus2) {
749 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
750 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
751 if (offset >= ncpus2 ||
752 offset % sc->rx_ring_cnt != 0) {
753 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
758 sc->rx_npoll_off = offset;
761 * NPOLLING TX CPU offset
763 if (sc->tx_ring_cnt == ncpus2) {
766 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
767 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
768 if (offset >= ncpus2 ||
769 offset % sc->tx_ring_cnt != 0) {
770 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
775 sc->tx_npoll_off = offset;
777 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
779 /* Setup OS specific network interface */
782 /* Add sysctl tree, must after em_setup_ifp() */
785 /* Reset the hardware */
786 error = emx_reset(sc);
788 device_printf(dev, "Unable to reset the hardware\n");
792 /* Initialize statistics */
793 emx_update_stats(sc);
795 sc->hw.mac.get_link_status = 1;
796 emx_update_link_status(sc);
798 /* Non-AMT based hardware can now take control from firmware */
799 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
801 emx_get_hw_control(sc);
804 * Missing Interrupt Following ICR read:
806 * 82571/82572 specification update errata #76
807 * 82573 specification update errata #31
808 * 82574 specification update errata #12
810 intr_func = emx_intr;
811 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
812 (sc->hw.mac.type == e1000_82571 ||
813 sc->hw.mac.type == e1000_82572 ||
814 sc->hw.mac.type == e1000_82573 ||
815 sc->hw.mac.type == e1000_82574))
816 intr_func = emx_intr_mask;
818 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
819 &sc->intr_tag, &sc->main_serialize);
821 device_printf(dev, "Failed to register interrupt handler");
822 ether_ifdetach(&sc->arpcom.ac_if);
832 emx_detach(device_t dev)
834 struct emx_softc *sc = device_get_softc(dev);
836 if (device_is_attached(dev)) {
837 struct ifnet *ifp = &sc->arpcom.ac_if;
839 ifnet_serialize_all(ifp);
843 e1000_phy_hw_reset(&sc->hw);
846 emx_rel_hw_control(sc);
849 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
850 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
854 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
856 ifnet_deserialize_all(ifp);
859 } else if (sc->memory != NULL) {
860 emx_rel_hw_control(sc);
862 bus_generic_detach(dev);
864 if (sc->intr_res != NULL) {
865 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
869 if (sc->intr_type == PCI_INTR_TYPE_MSI)
870 pci_release_msi(dev);
872 if (sc->memory != NULL) {
873 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
879 /* Free sysctl tree */
880 if (sc->sysctl_tree != NULL)
881 sysctl_ctx_free(&sc->sysctl_ctx);
884 kfree(sc->mta, M_DEVBUF);
890 emx_shutdown(device_t dev)
892 return emx_suspend(dev);
896 emx_suspend(device_t dev)
898 struct emx_softc *sc = device_get_softc(dev);
899 struct ifnet *ifp = &sc->arpcom.ac_if;
901 ifnet_serialize_all(ifp);
906 emx_rel_hw_control(sc);
909 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
910 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
914 ifnet_deserialize_all(ifp);
916 return bus_generic_suspend(dev);
920 emx_resume(device_t dev)
922 struct emx_softc *sc = device_get_softc(dev);
923 struct ifnet *ifp = &sc->arpcom.ac_if;
926 ifnet_serialize_all(ifp);
930 for (i = 0; i < sc->tx_ring_inuse; ++i)
931 ifsq_devstart_sched(sc->tx_data[i].ifsq);
933 ifnet_deserialize_all(ifp);
935 return bus_generic_resume(dev);
939 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
941 struct emx_softc *sc = ifp->if_softc;
942 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
944 int idx = -1, nsegs = 0;
946 KKASSERT(tdata->ifsq == ifsq);
947 ASSERT_SERIALIZED(&tdata->tx_serialize);
949 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
952 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
957 while (!ifsq_is_empty(ifsq)) {
958 /* Now do we at least have a minimal? */
959 if (EMX_IS_OACTIVE(tdata)) {
960 emx_tx_collect(tdata);
961 if (EMX_IS_OACTIVE(tdata)) {
962 ifsq_set_oactive(ifsq);
968 m_head = ifsq_dequeue(ifsq, NULL);
972 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
973 IFNET_STAT_INC(ifp, oerrors, 1);
974 emx_tx_collect(tdata);
978 if (nsegs >= tdata->tx_wreg_nsegs) {
979 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
984 /* Send a copy of the frame to the BPF listener */
985 ETHER_BPF_MTAP(ifp, m_head);
987 /* Set timeout in case hardware has problems transmitting. */
988 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
991 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
995 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
997 struct emx_softc *sc = ifp->if_softc;
998 struct ifreq *ifr = (struct ifreq *)data;
999 uint16_t eeprom_data = 0;
1000 int max_frame_size, mask, reinit;
1003 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1007 switch (sc->hw.mac.type) {
1010 * 82573 only supports jumbo frames
1011 * if ASPM is disabled.
1013 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1015 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1016 max_frame_size = ETHER_MAX_LEN;
1021 /* Limit Jumbo Frame size */
1025 case e1000_80003es2lan:
1026 max_frame_size = 9234;
1030 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1033 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1039 ifp->if_mtu = ifr->ifr_mtu;
1040 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1043 if (ifp->if_flags & IFF_RUNNING)
1048 if (ifp->if_flags & IFF_UP) {
1049 if ((ifp->if_flags & IFF_RUNNING)) {
1050 if ((ifp->if_flags ^ sc->if_flags) &
1051 (IFF_PROMISC | IFF_ALLMULTI)) {
1052 emx_disable_promisc(sc);
1053 emx_set_promisc(sc);
1058 } else if (ifp->if_flags & IFF_RUNNING) {
1061 sc->if_flags = ifp->if_flags;
1066 if (ifp->if_flags & IFF_RUNNING) {
1067 emx_disable_intr(sc);
1069 #ifdef IFPOLL_ENABLE
1070 if (!(ifp->if_flags & IFF_NPOLLING))
1072 emx_enable_intr(sc);
1077 /* Check SOL/IDER usage */
1078 if (e1000_check_reset_block(&sc->hw)) {
1079 device_printf(sc->dev, "Media change is"
1080 " blocked due to SOL/IDER session.\n");
1086 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1091 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1092 if (mask & IFCAP_RXCSUM) {
1093 ifp->if_capenable ^= IFCAP_RXCSUM;
1096 if (mask & IFCAP_VLAN_HWTAGGING) {
1097 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1100 if (mask & IFCAP_TXCSUM) {
1101 ifp->if_capenable ^= IFCAP_TXCSUM;
1102 if (ifp->if_capenable & IFCAP_TXCSUM)
1103 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1105 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1107 if (mask & IFCAP_TSO) {
1108 ifp->if_capenable ^= IFCAP_TSO;
1109 if (ifp->if_capenable & IFCAP_TSO)
1110 ifp->if_hwassist |= CSUM_TSO;
1112 ifp->if_hwassist &= ~CSUM_TSO;
1114 if (mask & IFCAP_RSS)
1115 ifp->if_capenable ^= IFCAP_RSS;
1116 if (reinit && (ifp->if_flags & IFF_RUNNING))
1121 error = ether_ioctl(ifp, command, data);
1128 emx_watchdog(struct ifaltq_subque *ifsq)
1130 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1131 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1132 struct emx_softc *sc = ifp->if_softc;
1135 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1138 * The timer is set to 5 every time start queues a packet.
1139 * Then txeof keeps resetting it as long as it cleans at
1140 * least one descriptor.
1141 * Finally, anytime all descriptors are clean the timer is
1145 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1146 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1148 * If we reach here, all TX jobs are completed and
1149 * the TX engine should have been idled for some time.
1150 * We don't need to call ifsq_devstart_sched() here.
1152 ifsq_clr_oactive(ifsq);
1153 tdata->tx_watchdog.wd_timer = 0;
1158 * If we are in this routine because of pause frames, then
1159 * don't reset the hardware.
1161 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1162 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1166 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1168 IFNET_STAT_INC(ifp, oerrors, 1);
1171 for (i = 0; i < sc->tx_ring_inuse; ++i)
1172 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1178 struct emx_softc *sc = xsc;
1179 struct ifnet *ifp = &sc->arpcom.ac_if;
1180 device_t dev = sc->dev;
1184 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1188 /* Get the latest mac address, User can use a LAA */
1189 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1191 /* Put the address into the Receive Address Array */
1192 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1195 * With the 82571 sc, RAR[0] may be overwritten
1196 * when the other port is reset, we make a duplicate
1197 * in RAR[14] for that eventuality, this assures
1198 * the interface continues to function.
1200 if (sc->hw.mac.type == e1000_82571) {
1201 e1000_set_laa_state_82571(&sc->hw, TRUE);
1202 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1203 E1000_RAR_ENTRIES - 1);
1206 /* Initialize the hardware */
1207 if (emx_reset(sc)) {
1208 device_printf(dev, "Unable to reset the hardware\n");
1209 /* XXX emx_stop()? */
1212 emx_update_link_status(sc);
1214 /* Setup VLAN support, basic and offload if available */
1215 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1217 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1220 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1221 ctrl |= E1000_CTRL_VME;
1222 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1225 /* Configure for OS presence */
1229 #ifdef IFPOLL_ENABLE
1230 if (ifp->if_flags & IFF_NPOLLING)
1233 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1234 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1236 /* Prepare transmit descriptors and buffers */
1237 for (i = 0; i < sc->tx_ring_inuse; ++i)
1238 emx_init_tx_ring(&sc->tx_data[i]);
1239 emx_init_tx_unit(sc);
1241 /* Setup Multicast table */
1244 /* Prepare receive descriptors and buffers */
1245 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1246 if (emx_init_rx_ring(&sc->rx_data[i])) {
1248 "Could not setup receive structures\n");
1253 emx_init_rx_unit(sc);
1255 /* Don't lose promiscuous settings */
1256 emx_set_promisc(sc);
1258 ifp->if_flags |= IFF_RUNNING;
1259 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1260 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1261 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1264 callout_reset(&sc->timer, hz, emx_timer, sc);
1265 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1267 /* MSI/X configuration for 82574 */
1268 if (sc->hw.mac.type == e1000_82574) {
1271 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1272 tmp |= E1000_CTRL_EXT_PBA_CLR;
1273 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1276 * Set the IVAR - interrupt vector routing.
1277 * Each nibble represents a vector, high bit
1278 * is enable, other 3 bits are the MSIX table
1279 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1280 * Link (other) to 2, hence the magic number.
1282 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1286 * Only enable interrupts if we are not polling, make sure
1287 * they are off otherwise.
1290 emx_disable_intr(sc);
1292 emx_enable_intr(sc);
1294 /* AMT based hardware can now take control from firmware */
1295 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1296 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1297 emx_get_hw_control(sc);
1303 emx_intr_body(xsc, TRUE);
1307 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1309 struct ifnet *ifp = &sc->arpcom.ac_if;
1313 ASSERT_SERIALIZED(&sc->main_serialize);
1315 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1317 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1323 * XXX: some laptops trigger several spurious interrupts
1324 * on emx(4) when in the resume cycle. The ICR register
1325 * reports all-ones value in this case. Processing such
1326 * interrupts would lead to a freeze. I don't know why.
1328 if (reg_icr == 0xffffffff) {
1333 if (ifp->if_flags & IFF_RUNNING) {
1335 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1338 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1339 lwkt_serialize_enter(
1340 &sc->rx_data[i].rx_serialize);
1341 emx_rxeof(&sc->rx_data[i], -1);
1342 lwkt_serialize_exit(
1343 &sc->rx_data[i].rx_serialize);
1346 if (reg_icr & E1000_ICR_TXDW) {
1347 struct emx_txdata *tdata = &sc->tx_data[0];
1349 lwkt_serialize_enter(&tdata->tx_serialize);
1351 if (!ifsq_is_empty(tdata->ifsq))
1352 ifsq_devstart(tdata->ifsq);
1353 lwkt_serialize_exit(&tdata->tx_serialize);
1357 /* Link status change */
1358 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1359 emx_serialize_skipmain(sc);
1361 callout_stop(&sc->timer);
1362 sc->hw.mac.get_link_status = 1;
1363 emx_update_link_status(sc);
1365 /* Deal with TX cruft when link lost */
1368 callout_reset(&sc->timer, hz, emx_timer, sc);
1370 emx_deserialize_skipmain(sc);
1373 if (reg_icr & E1000_ICR_RXO)
1380 emx_intr_mask(void *xsc)
1382 struct emx_softc *sc = xsc;
1384 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1387 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1388 * so don't check it.
1390 emx_intr_body(sc, FALSE);
1391 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1395 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1397 struct emx_softc *sc = ifp->if_softc;
1399 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1401 emx_update_link_status(sc);
1403 ifmr->ifm_status = IFM_AVALID;
1404 ifmr->ifm_active = IFM_ETHER;
1406 if (!sc->link_active)
1409 ifmr->ifm_status |= IFM_ACTIVE;
1411 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1412 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1413 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1415 switch (sc->link_speed) {
1417 ifmr->ifm_active |= IFM_10_T;
1420 ifmr->ifm_active |= IFM_100_TX;
1424 ifmr->ifm_active |= IFM_1000_T;
1427 if (sc->link_duplex == FULL_DUPLEX)
1428 ifmr->ifm_active |= IFM_FDX;
1430 ifmr->ifm_active |= IFM_HDX;
1435 emx_media_change(struct ifnet *ifp)
1437 struct emx_softc *sc = ifp->if_softc;
1438 struct ifmedia *ifm = &sc->media;
1440 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1442 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1445 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1447 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1448 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1454 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1455 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1459 sc->hw.mac.autoneg = FALSE;
1460 sc->hw.phy.autoneg_advertised = 0;
1461 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1462 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1464 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1468 sc->hw.mac.autoneg = FALSE;
1469 sc->hw.phy.autoneg_advertised = 0;
1470 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1471 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1473 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1477 if_printf(ifp, "Unsupported media type\n");
1487 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1488 int *segs_used, int *idx)
1490 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1492 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1493 struct e1000_tx_desc *ctxd = NULL;
1494 struct mbuf *m_head = *m_headp;
1495 uint32_t txd_upper, txd_lower, cmd = 0;
1496 int maxsegs, nsegs, i, j, first, last = 0, error;
1498 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1499 error = emx_tso_pullup(tdata, m_headp);
1505 txd_upper = txd_lower = 0;
1508 * Capture the first descriptor index, this descriptor
1509 * will have the index of the EOP which is the only one
1510 * that now gets a DONE bit writeback.
1512 first = tdata->next_avail_tx_desc;
1513 tx_buffer = &tdata->tx_buf[first];
1514 tx_buffer_mapped = tx_buffer;
1515 map = tx_buffer->map;
1517 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1518 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1519 if (maxsegs > EMX_MAX_SCATTER)
1520 maxsegs = EMX_MAX_SCATTER;
1522 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1523 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1529 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1532 tdata->tx_nsegs += nsegs;
1533 *segs_used += nsegs;
1535 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1536 /* TSO will consume one TX desc */
1537 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1538 tdata->tx_nsegs += i;
1540 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1541 /* TX csum offloading will consume one TX desc */
1542 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1543 tdata->tx_nsegs += i;
1546 i = tdata->next_avail_tx_desc;
1548 /* Set up our transmit descriptors */
1549 for (j = 0; j < nsegs; j++) {
1550 tx_buffer = &tdata->tx_buf[i];
1551 ctxd = &tdata->tx_desc_base[i];
1553 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1554 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1555 txd_lower | segs[j].ds_len);
1556 ctxd->upper.data = htole32(txd_upper);
1559 if (++i == tdata->num_tx_desc)
1563 tdata->next_avail_tx_desc = i;
1565 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1566 tdata->num_tx_desc_avail -= nsegs;
1568 /* Handle VLAN tag */
1569 if (m_head->m_flags & M_VLANTAG) {
1570 /* Set the vlan id. */
1571 ctxd->upper.fields.special =
1572 htole16(m_head->m_pkthdr.ether_vlantag);
1574 /* Tell hardware to add tag */
1575 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1578 tx_buffer->m_head = m_head;
1579 tx_buffer_mapped->map = tx_buffer->map;
1580 tx_buffer->map = map;
1582 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1583 tdata->tx_nsegs = 0;
1586 * Report Status (RS) is turned on
1587 * every tx_intr_nsegs descriptors.
1589 cmd = E1000_TXD_CMD_RS;
1592 * Keep track of the descriptor, which will
1593 * be written back by hardware.
1595 tdata->tx_dd[tdata->tx_dd_tail] = last;
1596 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1597 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1601 * Last Descriptor of Packet needs End Of Packet (EOP)
1603 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1606 * Defer TDT updating, until enough descriptors are setup
1610 #ifdef EMX_TSS_DEBUG
1618 emx_set_promisc(struct emx_softc *sc)
1620 struct ifnet *ifp = &sc->arpcom.ac_if;
1623 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1625 if (ifp->if_flags & IFF_PROMISC) {
1626 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1627 /* Turn this on if you want to see bad packets */
1629 reg_rctl |= E1000_RCTL_SBP;
1630 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1631 } else if (ifp->if_flags & IFF_ALLMULTI) {
1632 reg_rctl |= E1000_RCTL_MPE;
1633 reg_rctl &= ~E1000_RCTL_UPE;
1634 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1639 emx_disable_promisc(struct emx_softc *sc)
1643 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1645 reg_rctl &= ~E1000_RCTL_UPE;
1646 reg_rctl &= ~E1000_RCTL_MPE;
1647 reg_rctl &= ~E1000_RCTL_SBP;
1648 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1652 emx_set_multi(struct emx_softc *sc)
1654 struct ifnet *ifp = &sc->arpcom.ac_if;
1655 struct ifmultiaddr *ifma;
1656 uint32_t reg_rctl = 0;
1661 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1663 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1664 if (ifma->ifma_addr->sa_family != AF_LINK)
1667 if (mcnt == EMX_MCAST_ADDR_MAX)
1670 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1671 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1675 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1676 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1677 reg_rctl |= E1000_RCTL_MPE;
1678 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1680 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1685 * This routine checks for link status and updates statistics.
1688 emx_timer(void *xsc)
1690 struct emx_softc *sc = xsc;
1691 struct ifnet *ifp = &sc->arpcom.ac_if;
1693 lwkt_serialize_enter(&sc->main_serialize);
1695 emx_update_link_status(sc);
1696 emx_update_stats(sc);
1698 /* Reset LAA into RAR[0] on 82571 */
1699 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1700 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1702 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1703 emx_print_hw_stats(sc);
1707 callout_reset(&sc->timer, hz, emx_timer, sc);
1709 lwkt_serialize_exit(&sc->main_serialize);
1713 emx_update_link_status(struct emx_softc *sc)
1715 struct e1000_hw *hw = &sc->hw;
1716 struct ifnet *ifp = &sc->arpcom.ac_if;
1717 device_t dev = sc->dev;
1718 uint32_t link_check = 0;
1720 /* Get the cached link value or read phy for real */
1721 switch (hw->phy.media_type) {
1722 case e1000_media_type_copper:
1723 if (hw->mac.get_link_status) {
1724 /* Do the work to read phy */
1725 e1000_check_for_link(hw);
1726 link_check = !hw->mac.get_link_status;
1727 if (link_check) /* ESB2 fix */
1728 e1000_cfg_on_link_up(hw);
1734 case e1000_media_type_fiber:
1735 e1000_check_for_link(hw);
1736 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1739 case e1000_media_type_internal_serdes:
1740 e1000_check_for_link(hw);
1741 link_check = sc->hw.mac.serdes_has_link;
1744 case e1000_media_type_unknown:
1749 /* Now check for a transition */
1750 if (link_check && sc->link_active == 0) {
1751 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1755 * Check if we should enable/disable SPEED_MODE bit on
1758 if (sc->link_speed != SPEED_1000 &&
1759 (hw->mac.type == e1000_82571 ||
1760 hw->mac.type == e1000_82572)) {
1763 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1764 tarc0 &= ~EMX_TARC_SPEED_MODE;
1765 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1768 device_printf(dev, "Link is up %d Mbps %s\n",
1770 ((sc->link_duplex == FULL_DUPLEX) ?
1771 "Full Duplex" : "Half Duplex"));
1773 sc->link_active = 1;
1775 ifp->if_baudrate = sc->link_speed * 1000000;
1776 ifp->if_link_state = LINK_STATE_UP;
1777 if_link_state_change(ifp);
1778 } else if (!link_check && sc->link_active == 1) {
1779 ifp->if_baudrate = sc->link_speed = 0;
1780 sc->link_duplex = 0;
1782 device_printf(dev, "Link is Down\n");
1783 sc->link_active = 0;
1784 ifp->if_link_state = LINK_STATE_DOWN;
1785 if_link_state_change(ifp);
1790 emx_stop(struct emx_softc *sc)
1792 struct ifnet *ifp = &sc->arpcom.ac_if;
1795 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1797 emx_disable_intr(sc);
1799 callout_stop(&sc->timer);
1801 ifp->if_flags &= ~IFF_RUNNING;
1802 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1803 struct emx_txdata *tdata = &sc->tx_data[i];
1805 ifsq_clr_oactive(tdata->ifsq);
1806 ifsq_watchdog_stop(&tdata->tx_watchdog);
1807 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1811 * Disable multiple receive queues.
1814 * We should disable multiple receive queues before
1815 * resetting the hardware.
1817 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1819 e1000_reset_hw(&sc->hw);
1820 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1822 for (i = 0; i < sc->tx_ring_cnt; ++i)
1823 emx_free_tx_ring(&sc->tx_data[i]);
1824 for (i = 0; i < sc->rx_ring_cnt; ++i)
1825 emx_free_rx_ring(&sc->rx_data[i]);
1829 emx_reset(struct emx_softc *sc)
1831 device_t dev = sc->dev;
1832 uint16_t rx_buffer_size;
1835 /* Set up smart power down as default off on newer adapters. */
1836 if (!emx_smart_pwr_down &&
1837 (sc->hw.mac.type == e1000_82571 ||
1838 sc->hw.mac.type == e1000_82572)) {
1839 uint16_t phy_tmp = 0;
1841 /* Speed up time to link by disabling smart power down. */
1842 e1000_read_phy_reg(&sc->hw,
1843 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1844 phy_tmp &= ~IGP02E1000_PM_SPD;
1845 e1000_write_phy_reg(&sc->hw,
1846 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1850 * Packet Buffer Allocation (PBA)
1851 * Writing PBA sets the receive portion of the buffer
1852 * the remainder is used for the transmit buffer.
1854 switch (sc->hw.mac.type) {
1855 /* Total Packet Buffer on these is 48K */
1858 case e1000_80003es2lan:
1859 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1862 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1863 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1867 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1871 /* Devices before 82547 had a Packet Buffer of 64K. */
1872 if (sc->max_frame_size > 8192)
1873 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1875 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1877 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1880 * These parameters control the automatic generation (Tx) and
1881 * response (Rx) to Ethernet PAUSE frames.
1882 * - High water mark should allow for at least two frames to be
1883 * received after sending an XOFF.
1884 * - Low water mark works best when it is very near the high water mark.
1885 * This allows the receiver to restart by sending XON when it has
1886 * drained a bit. Here we use an arbitary value of 1500 which will
1887 * restart after one full frame is pulled from the buffer. There
1888 * could be several smaller frames in the buffer and if so they will
1889 * not trigger the XON until their total number reduces the buffer
1891 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1893 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1895 sc->hw.fc.high_water = rx_buffer_size -
1896 roundup2(sc->max_frame_size, 1024);
1897 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1899 if (sc->hw.mac.type == e1000_80003es2lan)
1900 sc->hw.fc.pause_time = 0xFFFF;
1902 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1903 sc->hw.fc.send_xon = TRUE;
1904 sc->hw.fc.requested_mode = e1000_fc_full;
1906 /* Issue a global reset */
1907 e1000_reset_hw(&sc->hw);
1908 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1909 emx_disable_aspm(sc);
1911 if (e1000_init_hw(&sc->hw) < 0) {
1912 device_printf(dev, "Hardware Initialization Failed\n");
1916 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1917 e1000_get_phy_info(&sc->hw);
1918 e1000_check_for_link(&sc->hw);
1924 emx_setup_ifp(struct emx_softc *sc)
1926 struct ifnet *ifp = &sc->arpcom.ac_if;
1929 if_initname(ifp, device_get_name(sc->dev),
1930 device_get_unit(sc->dev));
1932 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1933 ifp->if_init = emx_init;
1934 ifp->if_ioctl = emx_ioctl;
1935 ifp->if_start = emx_start;
1936 #ifdef IFPOLL_ENABLE
1937 ifp->if_npoll = emx_npoll;
1939 ifp->if_serialize = emx_serialize;
1940 ifp->if_deserialize = emx_deserialize;
1941 ifp->if_tryserialize = emx_tryserialize;
1943 ifp->if_serialize_assert = emx_serialize_assert;
1946 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
1947 ifq_set_ready(&ifp->if_snd);
1948 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1950 ifp->if_mapsubq = ifq_mapsubq_mask;
1951 ifq_set_subq_mask(&ifp->if_snd, 0);
1953 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1955 ifp->if_capabilities = IFCAP_HWCSUM |
1956 IFCAP_VLAN_HWTAGGING |
1959 if (sc->rx_ring_cnt > 1)
1960 ifp->if_capabilities |= IFCAP_RSS;
1961 ifp->if_capenable = ifp->if_capabilities;
1962 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
1965 * Tell the upper layer(s) we support long frames.
1967 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1969 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1970 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1971 struct emx_txdata *tdata = &sc->tx_data[i];
1973 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
1974 ifsq_set_priv(ifsq, tdata);
1975 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
1978 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
1982 * Specify the media types supported by this sc and register
1983 * callbacks to update media and link information
1985 ifmedia_init(&sc->media, IFM_IMASK,
1986 emx_media_change, emx_media_status);
1987 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1988 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1989 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1991 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1993 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1994 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1996 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1997 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1999 if (sc->hw.phy.type != e1000_phy_ife) {
2000 ifmedia_add(&sc->media,
2001 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2002 ifmedia_add(&sc->media,
2003 IFM_ETHER | IFM_1000_T, 0, NULL);
2006 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2007 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2011 * Workaround for SmartSpeed on 82541 and 82547 controllers
2014 emx_smartspeed(struct emx_softc *sc)
2018 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2019 sc->hw.mac.autoneg == 0 ||
2020 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2023 if (sc->smartspeed == 0) {
2025 * If Master/Slave config fault is asserted twice,
2026 * we assume back-to-back
2028 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2029 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2031 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2032 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2033 e1000_read_phy_reg(&sc->hw,
2034 PHY_1000T_CTRL, &phy_tmp);
2035 if (phy_tmp & CR_1000T_MS_ENABLE) {
2036 phy_tmp &= ~CR_1000T_MS_ENABLE;
2037 e1000_write_phy_reg(&sc->hw,
2038 PHY_1000T_CTRL, phy_tmp);
2040 if (sc->hw.mac.autoneg &&
2041 !e1000_phy_setup_autoneg(&sc->hw) &&
2042 !e1000_read_phy_reg(&sc->hw,
2043 PHY_CONTROL, &phy_tmp)) {
2044 phy_tmp |= MII_CR_AUTO_NEG_EN |
2045 MII_CR_RESTART_AUTO_NEG;
2046 e1000_write_phy_reg(&sc->hw,
2047 PHY_CONTROL, phy_tmp);
2052 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2053 /* If still no link, perhaps using 2/3 pair cable */
2054 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2055 phy_tmp |= CR_1000T_MS_ENABLE;
2056 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2057 if (sc->hw.mac.autoneg &&
2058 !e1000_phy_setup_autoneg(&sc->hw) &&
2059 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2060 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2061 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2065 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2066 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2071 emx_create_tx_ring(struct emx_txdata *tdata)
2073 device_t dev = tdata->sc->dev;
2074 struct emx_txbuf *tx_buffer;
2075 int error, i, tsize, ntxd;
2078 * Validate number of transmit descriptors. It must not exceed
2079 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2081 ntxd = device_getenv_int(dev, "txd", emx_txd);
2082 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2083 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2084 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2085 EMX_DEFAULT_TXD, ntxd);
2086 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2088 tdata->num_tx_desc = ntxd;
2092 * Allocate Transmit Descriptor ring
2094 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2096 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2097 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2098 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2099 &tdata->tx_desc_paddr);
2100 if (tdata->tx_desc_base == NULL) {
2101 device_printf(dev, "Unable to allocate tx_desc memory\n");
2105 tsize = __VM_CACHELINE_ALIGN(
2106 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2107 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2110 * Create DMA tags for tx buffers
2112 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2113 1, 0, /* alignment, bounds */
2114 BUS_SPACE_MAXADDR, /* lowaddr */
2115 BUS_SPACE_MAXADDR, /* highaddr */
2116 NULL, NULL, /* filter, filterarg */
2117 EMX_TSO_SIZE, /* maxsize */
2118 EMX_MAX_SCATTER, /* nsegments */
2119 EMX_MAX_SEGSIZE, /* maxsegsize */
2120 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2121 BUS_DMA_ONEBPAGE, /* flags */
2124 device_printf(dev, "Unable to allocate TX DMA tag\n");
2125 kfree(tdata->tx_buf, M_DEVBUF);
2126 tdata->tx_buf = NULL;
2131 * Create DMA maps for tx buffers
2133 for (i = 0; i < tdata->num_tx_desc; i++) {
2134 tx_buffer = &tdata->tx_buf[i];
2136 error = bus_dmamap_create(tdata->txtag,
2137 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2140 device_printf(dev, "Unable to create TX DMA map\n");
2141 emx_destroy_tx_ring(tdata, i);
2147 * Setup TX parameters
2149 tdata->spare_tx_desc = EMX_TX_SPARE;
2150 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2153 * Keep following relationship between spare_tx_desc, oact_tx_desc
2154 * and tx_intr_nsegs:
2155 * (spare_tx_desc + EMX_TX_RESERVED) <=
2156 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2158 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2159 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2160 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2161 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2162 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2164 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2165 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2166 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2169 * Pullup extra 4bytes into the first data segment, see:
2170 * 82571/82572 specification update errata #7
2173 * 4bytes instead of 2bytes, which are mentioned in the errata,
2174 * are pulled; mainly to keep rest of the data properly aligned.
2176 if (tdata->sc->hw.mac.type == e1000_82571 ||
2177 tdata->sc->hw.mac.type == e1000_82572)
2178 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2184 emx_init_tx_ring(struct emx_txdata *tdata)
2186 /* Clear the old ring contents */
2187 bzero(tdata->tx_desc_base,
2188 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2191 tdata->next_avail_tx_desc = 0;
2192 tdata->next_tx_to_clean = 0;
2193 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2195 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2196 if (tdata->sc->tx_ring_inuse > 1) {
2197 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2199 if_printf(&tdata->sc->arpcom.ac_if,
2200 "TX %d force ctx setup\n", tdata->idx);
2206 emx_init_tx_unit(struct emx_softc *sc)
2208 uint32_t tctl, tarc, tipg = 0;
2211 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2212 struct emx_txdata *tdata = &sc->tx_data[i];
2215 /* Setup the Base and Length of the Tx Descriptor Ring */
2216 bus_addr = tdata->tx_desc_paddr;
2217 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2218 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2219 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2220 (uint32_t)(bus_addr >> 32));
2221 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2222 (uint32_t)bus_addr);
2223 /* Setup the HW Tx Head and Tail descriptor pointers */
2224 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2225 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2228 /* Set the default values for the Tx Inter Packet Gap timer */
2229 switch (sc->hw.mac.type) {
2230 case e1000_80003es2lan:
2231 tipg = DEFAULT_82543_TIPG_IPGR1;
2232 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2233 E1000_TIPG_IPGR2_SHIFT;
2237 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2238 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2239 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2241 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2242 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2243 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2247 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2249 /* NOTE: 0 is not allowed for TIDV */
2250 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2251 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2253 if (sc->hw.mac.type == e1000_82571 ||
2254 sc->hw.mac.type == e1000_82572) {
2255 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2256 tarc |= EMX_TARC_SPEED_MODE;
2257 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2258 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2259 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2261 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2262 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2264 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2267 /* Program the Transmit Control Register */
2268 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2269 tctl &= ~E1000_TCTL_CT;
2270 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2271 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2272 tctl |= E1000_TCTL_MULR;
2274 /* This write will effectively turn on the transmit unit. */
2275 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2277 if (sc->hw.mac.type == e1000_82571 ||
2278 sc->hw.mac.type == e1000_82572 ||
2279 sc->hw.mac.type == e1000_80003es2lan) {
2280 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2281 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2283 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2286 if (sc->tx_ring_inuse > 1) {
2287 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2288 tarc &= ~EMX_TARC_COUNT_MASK;
2290 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2292 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2293 tarc &= ~EMX_TARC_COUNT_MASK;
2295 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2300 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2302 struct emx_txbuf *tx_buffer;
2305 /* Free Transmit Descriptor ring */
2306 if (tdata->tx_desc_base) {
2307 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2308 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2309 tdata->tx_desc_dmap);
2310 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2312 tdata->tx_desc_base = NULL;
2315 if (tdata->tx_buf == NULL)
2318 for (i = 0; i < ndesc; i++) {
2319 tx_buffer = &tdata->tx_buf[i];
2321 KKASSERT(tx_buffer->m_head == NULL);
2322 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2324 bus_dma_tag_destroy(tdata->txtag);
2326 kfree(tdata->tx_buf, M_DEVBUF);
2327 tdata->tx_buf = NULL;
2331 * The offload context needs to be set when we transfer the first
2332 * packet of a particular protocol (TCP/UDP). This routine has been
2333 * enhanced to deal with inserted VLAN headers.
2335 * If the new packet's ether header length, ip header length and
2336 * csum offloading type are same as the previous packet, we should
2337 * avoid allocating a new csum context descriptor; mainly to take
2338 * advantage of the pipeline effect of the TX data read request.
2340 * This function returns number of TX descrptors allocated for
2344 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2345 uint32_t *txd_upper, uint32_t *txd_lower)
2347 struct e1000_context_desc *TXD;
2348 int curr_txd, ehdrlen, csum_flags;
2349 uint32_t cmd, hdr_len, ip_hlen;
2351 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2352 ip_hlen = mp->m_pkthdr.csum_iphlen;
2353 ehdrlen = mp->m_pkthdr.csum_lhlen;
2355 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2356 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2357 tdata->csum_flags == csum_flags) {
2359 * Same csum offload context as the previous packets;
2362 *txd_upper = tdata->csum_txd_upper;
2363 *txd_lower = tdata->csum_txd_lower;
2368 * Setup a new csum offload context.
2371 curr_txd = tdata->next_avail_tx_desc;
2372 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2376 /* Setup of IP header checksum. */
2377 if (csum_flags & CSUM_IP) {
2379 * Start offset for header checksum calculation.
2380 * End offset for header checksum calculation.
2381 * Offset of place to put the checksum.
2383 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2384 TXD->lower_setup.ip_fields.ipcse =
2385 htole16(ehdrlen + ip_hlen - 1);
2386 TXD->lower_setup.ip_fields.ipcso =
2387 ehdrlen + offsetof(struct ip, ip_sum);
2388 cmd |= E1000_TXD_CMD_IP;
2389 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2391 hdr_len = ehdrlen + ip_hlen;
2393 if (csum_flags & CSUM_TCP) {
2395 * Start offset for payload checksum calculation.
2396 * End offset for payload checksum calculation.
2397 * Offset of place to put the checksum.
2399 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2400 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2401 TXD->upper_setup.tcp_fields.tucso =
2402 hdr_len + offsetof(struct tcphdr, th_sum);
2403 cmd |= E1000_TXD_CMD_TCP;
2404 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2405 } else if (csum_flags & CSUM_UDP) {
2407 * Start offset for header checksum calculation.
2408 * End offset for header checksum calculation.
2409 * Offset of place to put the checksum.
2411 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2412 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2413 TXD->upper_setup.tcp_fields.tucso =
2414 hdr_len + offsetof(struct udphdr, uh_sum);
2415 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2418 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2419 E1000_TXD_DTYP_D; /* Data descr */
2421 /* Save the information for this csum offloading context */
2422 tdata->csum_lhlen = ehdrlen;
2423 tdata->csum_iphlen = ip_hlen;
2424 tdata->csum_flags = csum_flags;
2425 tdata->csum_txd_upper = *txd_upper;
2426 tdata->csum_txd_lower = *txd_lower;
2428 TXD->tcp_seg_setup.data = htole32(0);
2429 TXD->cmd_and_length =
2430 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2432 if (++curr_txd == tdata->num_tx_desc)
2435 KKASSERT(tdata->num_tx_desc_avail > 0);
2436 tdata->num_tx_desc_avail--;
2438 tdata->next_avail_tx_desc = curr_txd;
2443 emx_txeof(struct emx_txdata *tdata)
2445 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2446 struct emx_txbuf *tx_buffer;
2447 int first, num_avail;
2449 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2452 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2455 num_avail = tdata->num_tx_desc_avail;
2456 first = tdata->next_tx_to_clean;
2458 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2459 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2460 struct e1000_tx_desc *tx_desc;
2462 tx_desc = &tdata->tx_desc_base[dd_idx];
2463 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2464 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2466 if (++dd_idx == tdata->num_tx_desc)
2469 while (first != dd_idx) {
2474 tx_buffer = &tdata->tx_buf[first];
2475 if (tx_buffer->m_head) {
2476 IFNET_STAT_INC(ifp, opackets, 1);
2477 bus_dmamap_unload(tdata->txtag,
2479 m_freem(tx_buffer->m_head);
2480 tx_buffer->m_head = NULL;
2483 if (++first == tdata->num_tx_desc)
2490 tdata->next_tx_to_clean = first;
2491 tdata->num_tx_desc_avail = num_avail;
2493 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2494 tdata->tx_dd_head = 0;
2495 tdata->tx_dd_tail = 0;
2498 if (!EMX_IS_OACTIVE(tdata)) {
2499 ifsq_clr_oactive(tdata->ifsq);
2501 /* All clean, turn off the timer */
2502 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2503 tdata->tx_watchdog.wd_timer = 0;
2508 emx_tx_collect(struct emx_txdata *tdata)
2510 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2511 struct emx_txbuf *tx_buffer;
2512 int tdh, first, num_avail, dd_idx = -1;
2514 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2517 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2518 if (tdh == tdata->next_tx_to_clean)
2521 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2522 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2524 num_avail = tdata->num_tx_desc_avail;
2525 first = tdata->next_tx_to_clean;
2527 while (first != tdh) {
2532 tx_buffer = &tdata->tx_buf[first];
2533 if (tx_buffer->m_head) {
2534 IFNET_STAT_INC(ifp, opackets, 1);
2535 bus_dmamap_unload(tdata->txtag,
2537 m_freem(tx_buffer->m_head);
2538 tx_buffer->m_head = NULL;
2541 if (first == dd_idx) {
2542 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2543 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2544 tdata->tx_dd_head = 0;
2545 tdata->tx_dd_tail = 0;
2548 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2552 if (++first == tdata->num_tx_desc)
2555 tdata->next_tx_to_clean = first;
2556 tdata->num_tx_desc_avail = num_avail;
2558 if (!EMX_IS_OACTIVE(tdata)) {
2559 ifsq_clr_oactive(tdata->ifsq);
2561 /* All clean, turn off the timer */
2562 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2563 tdata->tx_watchdog.wd_timer = 0;
2568 * When Link is lost sometimes there is work still in the TX ring
2569 * which will result in a watchdog, rather than allow that do an
2570 * attempted cleanup and then reinit here. Note that this has been
2571 * seens mostly with fiber adapters.
2574 emx_tx_purge(struct emx_softc *sc)
2578 if (sc->link_active)
2581 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2582 struct emx_txdata *tdata = &sc->tx_data[i];
2584 if (tdata->tx_watchdog.wd_timer) {
2585 emx_tx_collect(tdata);
2586 if (tdata->tx_watchdog.wd_timer) {
2587 if_printf(&sc->arpcom.ac_if,
2588 "Link lost, TX pending, reinit\n");
2597 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2600 bus_dma_segment_t seg;
2602 struct emx_rxbuf *rx_buffer;
2605 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2608 if_printf(&rdata->sc->arpcom.ac_if,
2609 "Unable to allocate RX mbuf\n");
2613 m->m_len = m->m_pkthdr.len = MCLBYTES;
2615 if (rdata->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2616 m_adj(m, ETHER_ALIGN);
2618 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2619 rdata->rx_sparemap, m,
2620 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2624 if_printf(&rdata->sc->arpcom.ac_if,
2625 "Unable to load RX mbuf\n");
2630 rx_buffer = &rdata->rx_buf[i];
2631 if (rx_buffer->m_head != NULL)
2632 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2634 map = rx_buffer->map;
2635 rx_buffer->map = rdata->rx_sparemap;
2636 rdata->rx_sparemap = map;
2638 rx_buffer->m_head = m;
2639 rx_buffer->paddr = seg.ds_addr;
2641 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2646 emx_create_rx_ring(struct emx_rxdata *rdata)
2648 device_t dev = rdata->sc->dev;
2649 struct emx_rxbuf *rx_buffer;
2650 int i, error, rsize, nrxd;
2653 * Validate number of receive descriptors. It must not exceed
2654 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2656 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2657 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2658 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2659 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2660 EMX_DEFAULT_RXD, nrxd);
2661 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2663 rdata->num_rx_desc = nrxd;
2667 * Allocate Receive Descriptor ring
2669 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2671 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2672 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2673 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2674 &rdata->rx_desc_paddr);
2675 if (rdata->rx_desc == NULL) {
2676 device_printf(dev, "Unable to allocate rx_desc memory\n");
2680 rsize = __VM_CACHELINE_ALIGN(
2681 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2682 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2685 * Create DMA tag for rx buffers
2687 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2688 1, 0, /* alignment, bounds */
2689 BUS_SPACE_MAXADDR, /* lowaddr */
2690 BUS_SPACE_MAXADDR, /* highaddr */
2691 NULL, NULL, /* filter, filterarg */
2692 MCLBYTES, /* maxsize */
2694 MCLBYTES, /* maxsegsize */
2695 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2698 device_printf(dev, "Unable to allocate RX DMA tag\n");
2699 kfree(rdata->rx_buf, M_DEVBUF);
2700 rdata->rx_buf = NULL;
2705 * Create spare DMA map for rx buffers
2707 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2708 &rdata->rx_sparemap);
2710 device_printf(dev, "Unable to create spare RX DMA map\n");
2711 bus_dma_tag_destroy(rdata->rxtag);
2712 kfree(rdata->rx_buf, M_DEVBUF);
2713 rdata->rx_buf = NULL;
2718 * Create DMA maps for rx buffers
2720 for (i = 0; i < rdata->num_rx_desc; i++) {
2721 rx_buffer = &rdata->rx_buf[i];
2723 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2726 device_printf(dev, "Unable to create RX DMA map\n");
2727 emx_destroy_rx_ring(rdata, i);
2735 emx_free_rx_ring(struct emx_rxdata *rdata)
2739 for (i = 0; i < rdata->num_rx_desc; i++) {
2740 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2742 if (rx_buffer->m_head != NULL) {
2743 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2744 m_freem(rx_buffer->m_head);
2745 rx_buffer->m_head = NULL;
2749 if (rdata->fmp != NULL)
2750 m_freem(rdata->fmp);
2756 emx_free_tx_ring(struct emx_txdata *tdata)
2760 for (i = 0; i < tdata->num_tx_desc; i++) {
2761 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2763 if (tx_buffer->m_head != NULL) {
2764 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2765 m_freem(tx_buffer->m_head);
2766 tx_buffer->m_head = NULL;
2770 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2772 tdata->csum_flags = 0;
2773 tdata->csum_lhlen = 0;
2774 tdata->csum_iphlen = 0;
2775 tdata->csum_thlen = 0;
2776 tdata->csum_mss = 0;
2777 tdata->csum_pktlen = 0;
2779 tdata->tx_dd_head = 0;
2780 tdata->tx_dd_tail = 0;
2781 tdata->tx_nsegs = 0;
2785 emx_init_rx_ring(struct emx_rxdata *rdata)
2789 /* Reset descriptor ring */
2790 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2792 /* Allocate new ones. */
2793 for (i = 0; i < rdata->num_rx_desc; i++) {
2794 error = emx_newbuf(rdata, i, 1);
2799 /* Setup our descriptor pointers */
2800 rdata->next_rx_desc_to_check = 0;
2806 emx_init_rx_unit(struct emx_softc *sc)
2808 struct ifnet *ifp = &sc->arpcom.ac_if;
2810 uint32_t rctl, itr, rfctl;
2814 * Make sure receives are disabled while setting
2815 * up the descriptor ring
2817 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2818 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2821 * Set the interrupt throttling rate. Value is calculated
2822 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2824 if (sc->int_throttle_ceil)
2825 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2828 emx_set_itr(sc, itr);
2830 /* Use extended RX descriptor */
2831 rfctl = E1000_RFCTL_EXTEN;
2833 /* Disable accelerated ackknowledge */
2834 if (sc->hw.mac.type == e1000_82574)
2835 rfctl |= E1000_RFCTL_ACK_DIS;
2837 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2840 * Receive Checksum Offload for TCP and UDP
2842 * Checksum offloading is also enabled if multiple receive
2843 * queue is to be supported, since we need it to figure out
2846 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2847 sc->rx_ring_cnt > 1) {
2850 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2854 * PCSD must be enabled to enable multiple
2857 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2859 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2863 * Configure multiple receive queue (RSS)
2865 if (sc->rx_ring_cnt > 1) {
2866 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2869 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2870 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2874 * When we reach here, RSS has already been disabled
2875 * in emx_stop(), so we could safely configure RSS key
2876 * and redirect table.
2882 toeplitz_get_key(key, sizeof(key));
2883 for (i = 0; i < EMX_NRSSRK; ++i) {
2886 rssrk = EMX_RSSRK_VAL(key, i);
2887 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2889 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2893 * Configure RSS redirect table in following fashion:
2894 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2897 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2900 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2901 reta |= q << (8 * i);
2903 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2905 for (i = 0; i < EMX_NRETA; ++i)
2906 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2909 * Enable multiple receive queues.
2910 * Enable IPv4 RSS standard hash functions.
2911 * Disable RSS interrupt.
2913 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2914 E1000_MRQC_ENABLE_RSS_2Q |
2915 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2916 E1000_MRQC_RSS_FIELD_IPV4);
2920 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2921 * long latencies are observed, like Lenovo X60. This
2922 * change eliminates the problem, but since having positive
2923 * values in RDTR is a known source of problems on other
2924 * platforms another solution is being sought.
2926 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2927 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2928 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2931 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2932 struct emx_rxdata *rdata = &sc->rx_data[i];
2935 * Setup the Base and Length of the Rx Descriptor Ring
2937 bus_addr = rdata->rx_desc_paddr;
2938 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2939 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2940 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2941 (uint32_t)(bus_addr >> 32));
2942 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2943 (uint32_t)bus_addr);
2946 * Setup the HW Rx Head and Tail Descriptor Pointers
2948 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2949 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2950 sc->rx_data[i].num_rx_desc - 1);
2953 /* Setup the Receive Control Register */
2954 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2955 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2956 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2957 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2959 /* Make sure VLAN Filters are off */
2960 rctl &= ~E1000_RCTL_VFE;
2962 /* Don't store bad paket */
2963 rctl &= ~E1000_RCTL_SBP;
2966 rctl |= E1000_RCTL_SZ_2048;
2968 if (ifp->if_mtu > ETHERMTU)
2969 rctl |= E1000_RCTL_LPE;
2971 rctl &= ~E1000_RCTL_LPE;
2973 /* Enable Receives */
2974 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2978 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
2980 struct emx_rxbuf *rx_buffer;
2983 /* Free Receive Descriptor ring */
2984 if (rdata->rx_desc) {
2985 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2986 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2987 rdata->rx_desc_dmap);
2988 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2990 rdata->rx_desc = NULL;
2993 if (rdata->rx_buf == NULL)
2996 for (i = 0; i < ndesc; i++) {
2997 rx_buffer = &rdata->rx_buf[i];
2999 KKASSERT(rx_buffer->m_head == NULL);
3000 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3002 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3003 bus_dma_tag_destroy(rdata->rxtag);
3005 kfree(rdata->rx_buf, M_DEVBUF);
3006 rdata->rx_buf = NULL;
3010 emx_rxeof(struct emx_rxdata *rdata, int count)
3012 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3014 emx_rxdesc_t *current_desc;
3018 i = rdata->next_rx_desc_to_check;
3019 current_desc = &rdata->rx_desc[i];
3020 staterr = le32toh(current_desc->rxd_staterr);
3022 if (!(staterr & E1000_RXD_STAT_DD))
3025 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3026 struct pktinfo *pi = NULL, pi0;
3027 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3028 struct mbuf *m = NULL;
3033 mp = rx_buf->m_head;
3036 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3037 * needs to access the last received byte in the mbuf.
3039 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3040 BUS_DMASYNC_POSTREAD);
3042 len = le16toh(current_desc->rxd_length);
3043 if (staterr & E1000_RXD_STAT_EOP) {
3050 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3052 uint32_t mrq, rss_hash;
3055 * Save several necessary information,
3056 * before emx_newbuf() destroy it.
3058 if ((staterr & E1000_RXD_STAT_VP) && eop)
3059 vlan = le16toh(current_desc->rxd_vlan);
3061 mrq = le32toh(current_desc->rxd_mrq);
3062 rss_hash = le32toh(current_desc->rxd_rss);
3064 EMX_RSS_DPRINTF(rdata->sc, 10,
3065 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3066 rdata->idx, mrq, rss_hash);
3068 if (emx_newbuf(rdata, i, 0) != 0) {
3069 IFNET_STAT_INC(ifp, iqdrops, 1);
3073 /* Assign correct length to the current fragment */
3076 if (rdata->fmp == NULL) {
3077 mp->m_pkthdr.len = len;
3078 rdata->fmp = mp; /* Store the first mbuf */
3082 * Chain mbuf's together
3084 rdata->lmp->m_next = mp;
3085 rdata->lmp = rdata->lmp->m_next;
3086 rdata->fmp->m_pkthdr.len += len;
3090 rdata->fmp->m_pkthdr.rcvif = ifp;
3091 IFNET_STAT_INC(ifp, ipackets, 1);
3093 if (ifp->if_capenable & IFCAP_RXCSUM)
3094 emx_rxcsum(staterr, rdata->fmp);
3096 if (staterr & E1000_RXD_STAT_VP) {
3097 rdata->fmp->m_pkthdr.ether_vlantag =
3099 rdata->fmp->m_flags |= M_VLANTAG;
3105 if (ifp->if_capenable & IFCAP_RSS) {
3106 pi = emx_rssinfo(m, &pi0, mrq,
3109 #ifdef EMX_RSS_DEBUG
3114 IFNET_STAT_INC(ifp, ierrors, 1);
3116 emx_setup_rxdesc(current_desc, rx_buf);
3117 if (rdata->fmp != NULL) {
3118 m_freem(rdata->fmp);
3126 ether_input_pkt(ifp, m, pi);
3128 /* Advance our pointers to the next descriptor. */
3129 if (++i == rdata->num_rx_desc)
3132 current_desc = &rdata->rx_desc[i];
3133 staterr = le32toh(current_desc->rxd_staterr);
3135 rdata->next_rx_desc_to_check = i;
3137 /* Advance the E1000's Receive Queue "Tail Pointer". */
3139 i = rdata->num_rx_desc - 1;
3140 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3144 emx_enable_intr(struct emx_softc *sc)
3146 uint32_t ims_mask = IMS_ENABLE_MASK;
3148 lwkt_serialize_handler_enable(&sc->main_serialize);
3151 if (sc->hw.mac.type == e1000_82574) {
3152 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3153 ims_mask |= EM_MSIX_MASK;
3156 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3160 emx_disable_intr(struct emx_softc *sc)
3162 if (sc->hw.mac.type == e1000_82574)
3163 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3164 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3166 lwkt_serialize_handler_disable(&sc->main_serialize);
3170 * Bit of a misnomer, what this really means is
3171 * to enable OS management of the system... aka
3172 * to disable special hardware management features
3175 emx_get_mgmt(struct emx_softc *sc)
3177 /* A shared code workaround */
3178 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3179 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3180 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3182 /* disable hardware interception of ARP */
3183 manc &= ~(E1000_MANC_ARP_EN);
3185 /* enable receiving management packets to the host */
3186 manc |= E1000_MANC_EN_MNG2HOST;
3187 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3188 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3189 manc2h |= E1000_MNG2HOST_PORT_623;
3190 manc2h |= E1000_MNG2HOST_PORT_664;
3191 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3193 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3198 * Give control back to hardware management
3199 * controller if there is one.
3202 emx_rel_mgmt(struct emx_softc *sc)
3204 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3205 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3207 /* re-enable hardware interception of ARP */
3208 manc |= E1000_MANC_ARP_EN;
3209 manc &= ~E1000_MANC_EN_MNG2HOST;
3211 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3216 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3217 * For ASF and Pass Through versions of f/w this means that
3218 * the driver is loaded. For AMT version (only with 82573)
3219 * of the f/w this means that the network i/f is open.
3222 emx_get_hw_control(struct emx_softc *sc)
3224 /* Let firmware know the driver has taken over */
3225 if (sc->hw.mac.type == e1000_82573) {
3228 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3229 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3230 swsm | E1000_SWSM_DRV_LOAD);
3234 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3235 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3236 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3238 sc->flags |= EMX_FLAG_HW_CTRL;
3242 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3243 * For ASF and Pass Through versions of f/w this means that the
3244 * driver is no longer loaded. For AMT version (only with 82573)
3245 * of the f/w this means that the network i/f is closed.
3248 emx_rel_hw_control(struct emx_softc *sc)
3250 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3252 sc->flags &= ~EMX_FLAG_HW_CTRL;
3254 /* Let firmware taken over control of h/w */
3255 if (sc->hw.mac.type == e1000_82573) {
3258 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3259 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3260 swsm & ~E1000_SWSM_DRV_LOAD);
3264 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3265 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3266 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3271 emx_is_valid_eaddr(const uint8_t *addr)
3273 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3275 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3282 * Enable PCI Wake On Lan capability
3285 emx_enable_wol(device_t dev)
3287 uint16_t cap, status;
3290 /* First find the capabilities pointer*/
3291 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3293 /* Read the PM Capabilities */
3294 id = pci_read_config(dev, cap, 1);
3295 if (id != PCIY_PMG) /* Something wrong */
3299 * OK, we have the power capabilities,
3300 * so now get the status register
3302 cap += PCIR_POWER_STATUS;
3303 status = pci_read_config(dev, cap, 2);
3304 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3305 pci_write_config(dev, cap, status, 2);
3309 emx_update_stats(struct emx_softc *sc)
3311 struct ifnet *ifp = &sc->arpcom.ac_if;
3313 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3314 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3315 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3316 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3318 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3319 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3320 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3321 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3323 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3324 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3325 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3326 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3327 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3328 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3329 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3330 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3331 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3332 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3333 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3334 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3335 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3336 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3337 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3338 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3339 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3340 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3341 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3342 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3344 /* For the 64-bit byte counters the low dword must be read first. */
3345 /* Both registers clear on the read of the high dword */
3347 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3348 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3350 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3351 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3352 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3353 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3354 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3356 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3357 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3359 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3360 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3361 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3362 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3363 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3364 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3365 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3366 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3367 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3368 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3370 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3371 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3372 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3373 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3374 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3375 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3377 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3380 IFNET_STAT_SET(ifp, ierrors,
3381 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3382 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3385 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3389 emx_print_debug_info(struct emx_softc *sc)
3391 device_t dev = sc->dev;
3392 uint8_t *hw_addr = sc->hw.hw_addr;
3395 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3396 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3397 E1000_READ_REG(&sc->hw, E1000_CTRL),
3398 E1000_READ_REG(&sc->hw, E1000_RCTL));
3399 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3400 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3401 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3402 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3403 sc->hw.fc.high_water, sc->hw.fc.low_water);
3404 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3405 E1000_READ_REG(&sc->hw, E1000_TIDV),
3406 E1000_READ_REG(&sc->hw, E1000_TADV));
3407 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3408 E1000_READ_REG(&sc->hw, E1000_RDTR),
3409 E1000_READ_REG(&sc->hw, E1000_RADV));
3411 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3412 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3413 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3414 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3416 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3417 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3418 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3419 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3422 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3423 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3424 sc->tx_data[i].num_tx_desc_avail);
3425 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3426 sc->tx_data[i].tso_segments);
3427 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3428 sc->tx_data[i].tso_ctx_reused);
3433 emx_print_hw_stats(struct emx_softc *sc)
3435 device_t dev = sc->dev;
3437 device_printf(dev, "Excessive collisions = %lld\n",
3438 (long long)sc->stats.ecol);
3439 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3440 device_printf(dev, "Symbol errors = %lld\n",
3441 (long long)sc->stats.symerrs);
3443 device_printf(dev, "Sequence errors = %lld\n",
3444 (long long)sc->stats.sec);
3445 device_printf(dev, "Defer count = %lld\n",
3446 (long long)sc->stats.dc);
3447 device_printf(dev, "Missed Packets = %lld\n",
3448 (long long)sc->stats.mpc);
3449 device_printf(dev, "Receive No Buffers = %lld\n",
3450 (long long)sc->stats.rnbc);
3451 /* RLEC is inaccurate on some hardware, calculate our own. */
3452 device_printf(dev, "Receive Length Errors = %lld\n",
3453 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3454 device_printf(dev, "Receive errors = %lld\n",
3455 (long long)sc->stats.rxerrc);
3456 device_printf(dev, "Crc errors = %lld\n",
3457 (long long)sc->stats.crcerrs);
3458 device_printf(dev, "Alignment errors = %lld\n",
3459 (long long)sc->stats.algnerrc);
3460 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3461 (long long)sc->stats.cexterr);
3462 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3463 device_printf(dev, "XON Rcvd = %lld\n",
3464 (long long)sc->stats.xonrxc);
3465 device_printf(dev, "XON Xmtd = %lld\n",
3466 (long long)sc->stats.xontxc);
3467 device_printf(dev, "XOFF Rcvd = %lld\n",
3468 (long long)sc->stats.xoffrxc);
3469 device_printf(dev, "XOFF Xmtd = %lld\n",
3470 (long long)sc->stats.xofftxc);
3471 device_printf(dev, "Good Packets Rcvd = %lld\n",
3472 (long long)sc->stats.gprc);
3473 device_printf(dev, "Good Packets Xmtd = %lld\n",
3474 (long long)sc->stats.gptc);
3478 emx_print_nvm_info(struct emx_softc *sc)
3480 uint16_t eeprom_data;
3483 /* Its a bit crude, but it gets the job done */
3484 kprintf("\nInterface EEPROM Dump:\n");
3485 kprintf("Offset\n0x0000 ");
3486 for (i = 0, j = 0; i < 32; i++, j++) {
3487 if (j == 8) { /* Make the offset block */
3489 kprintf("\n0x00%x0 ",row);
3491 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3492 kprintf("%04x ", eeprom_data);
3498 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3500 struct emx_softc *sc;
3505 error = sysctl_handle_int(oidp, &result, 0, req);
3506 if (error || !req->newptr)
3509 sc = (struct emx_softc *)arg1;
3510 ifp = &sc->arpcom.ac_if;
3512 ifnet_serialize_all(ifp);
3515 emx_print_debug_info(sc);
3518 * This value will cause a hex dump of the
3519 * first 32 16-bit words of the EEPROM to
3523 emx_print_nvm_info(sc);
3525 ifnet_deserialize_all(ifp);
3531 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3536 error = sysctl_handle_int(oidp, &result, 0, req);
3537 if (error || !req->newptr)
3541 struct emx_softc *sc = (struct emx_softc *)arg1;
3542 struct ifnet *ifp = &sc->arpcom.ac_if;
3544 ifnet_serialize_all(ifp);
3545 emx_print_hw_stats(sc);
3546 ifnet_deserialize_all(ifp);
3552 emx_add_sysctl(struct emx_softc *sc)
3554 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3559 sysctl_ctx_init(&sc->sysctl_ctx);
3560 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3561 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3562 device_get_nameunit(sc->dev),
3564 if (sc->sysctl_tree == NULL) {
3565 device_printf(sc->dev, "can't add sysctl node\n");
3569 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3570 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3571 emx_sysctl_debug_info, "I", "Debug Information");
3573 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3574 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3575 emx_sysctl_stats, "I", "Statistics");
3577 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3578 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3580 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3581 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3584 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3585 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3586 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3587 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3588 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3589 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3590 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3591 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3592 emx_sysctl_tx_wreg_nsegs, "I",
3593 "# segments sent before write to hardware register");
3595 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3596 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3598 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3599 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3601 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3602 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3603 "# of TX rings used");
3605 #ifdef IFPOLL_ENABLE
3606 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3607 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3608 sc, 0, emx_sysctl_npoll_rxoff, "I",
3609 "NPOLLING RX cpu offset");
3610 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3611 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3612 sc, 0, emx_sysctl_npoll_txoff, "I",
3613 "NPOLLING TX cpu offset");
3616 #ifdef EMX_RSS_DEBUG
3617 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3618 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3619 0, "RSS debug level");
3620 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3621 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3622 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
3623 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3624 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3628 #ifdef EMX_TSS_DEBUG
3629 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3630 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3631 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
3632 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3633 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3640 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3642 struct emx_softc *sc = (void *)arg1;
3643 struct ifnet *ifp = &sc->arpcom.ac_if;
3644 int error, throttle;
3646 throttle = sc->int_throttle_ceil;
3647 error = sysctl_handle_int(oidp, &throttle, 0, req);
3648 if (error || req->newptr == NULL)
3650 if (throttle < 0 || throttle > 1000000000 / 256)
3655 * Set the interrupt throttling rate in 256ns increments,
3656 * recalculate sysctl value assignment to get exact frequency.
3658 throttle = 1000000000 / 256 / throttle;
3660 /* Upper 16bits of ITR is reserved and should be zero */
3661 if (throttle & 0xffff0000)
3665 ifnet_serialize_all(ifp);
3668 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3670 sc->int_throttle_ceil = 0;
3672 if (ifp->if_flags & IFF_RUNNING)
3673 emx_set_itr(sc, throttle);
3675 ifnet_deserialize_all(ifp);
3678 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3679 sc->int_throttle_ceil);
3685 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3687 struct emx_softc *sc = (void *)arg1;
3688 struct ifnet *ifp = &sc->arpcom.ac_if;
3689 struct emx_txdata *tdata = &sc->tx_data[0];
3692 segs = tdata->tx_intr_nsegs;
3693 error = sysctl_handle_int(oidp, &segs, 0, req);
3694 if (error || req->newptr == NULL)
3699 ifnet_serialize_all(ifp);
3702 * Don't allow tx_intr_nsegs to become:
3703 * o Less the oact_tx_desc
3704 * o Too large that no TX desc will cause TX interrupt to
3705 * be generated (OACTIVE will never recover)
3706 * o Too small that will cause tx_dd[] overflow
3708 if (segs < tdata->oact_tx_desc ||
3709 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3710 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3716 for (i = 0; i < sc->tx_ring_cnt; ++i)
3717 sc->tx_data[i].tx_intr_nsegs = segs;
3720 ifnet_deserialize_all(ifp);
3726 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3728 struct emx_softc *sc = (void *)arg1;
3729 struct ifnet *ifp = &sc->arpcom.ac_if;
3730 int error, nsegs, i;
3732 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3733 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3734 if (error || req->newptr == NULL)
3737 ifnet_serialize_all(ifp);
3738 for (i = 0; i < sc->tx_ring_cnt; ++i)
3739 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3740 ifnet_deserialize_all(ifp);
3745 #ifdef IFPOLL_ENABLE
3748 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3750 struct emx_softc *sc = (void *)arg1;
3751 struct ifnet *ifp = &sc->arpcom.ac_if;
3754 off = sc->rx_npoll_off;
3755 error = sysctl_handle_int(oidp, &off, 0, req);
3756 if (error || req->newptr == NULL)
3761 ifnet_serialize_all(ifp);
3762 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3766 sc->rx_npoll_off = off;
3768 ifnet_deserialize_all(ifp);
3774 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3776 struct emx_softc *sc = (void *)arg1;
3777 struct ifnet *ifp = &sc->arpcom.ac_if;
3780 off = sc->tx_npoll_off;
3781 error = sysctl_handle_int(oidp, &off, 0, req);
3782 if (error || req->newptr == NULL)
3787 ifnet_serialize_all(ifp);
3788 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3792 sc->tx_npoll_off = off;
3794 ifnet_deserialize_all(ifp);
3799 #endif /* IFPOLL_ENABLE */
3802 emx_dma_alloc(struct emx_softc *sc)
3807 * Create top level busdma tag
3809 error = bus_dma_tag_create(NULL, 1, 0,
3810 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3812 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3813 0, &sc->parent_dtag);
3815 device_printf(sc->dev, "could not create top level DMA tag\n");
3820 * Allocate transmit descriptors ring and buffers
3822 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3823 error = emx_create_tx_ring(&sc->tx_data[i]);
3825 device_printf(sc->dev,
3826 "Could not setup transmit structures\n");
3832 * Allocate receive descriptors ring and buffers
3834 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3835 error = emx_create_rx_ring(&sc->rx_data[i]);
3837 device_printf(sc->dev,
3838 "Could not setup receive structures\n");
3846 emx_dma_free(struct emx_softc *sc)
3850 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3851 emx_destroy_tx_ring(&sc->tx_data[i],
3852 sc->tx_data[i].num_tx_desc);
3855 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3856 emx_destroy_rx_ring(&sc->rx_data[i],
3857 sc->rx_data[i].num_rx_desc);
3860 /* Free top level busdma tag */
3861 if (sc->parent_dtag != NULL)
3862 bus_dma_tag_destroy(sc->parent_dtag);
3866 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3868 struct emx_softc *sc = ifp->if_softc;
3870 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3871 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3875 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3877 struct emx_softc *sc = ifp->if_softc;
3879 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3880 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3884 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3886 struct emx_softc *sc = ifp->if_softc;
3888 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3889 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3893 emx_serialize_skipmain(struct emx_softc *sc)
3895 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3899 emx_deserialize_skipmain(struct emx_softc *sc)
3901 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3907 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3908 boolean_t serialized)
3910 struct emx_softc *sc = ifp->if_softc;
3912 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3913 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
3916 #endif /* INVARIANTS */
3918 #ifdef IFPOLL_ENABLE
3921 emx_npoll_status(struct ifnet *ifp)
3923 struct emx_softc *sc = ifp->if_softc;
3926 ASSERT_SERIALIZED(&sc->main_serialize);
3928 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3929 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3930 callout_stop(&sc->timer);
3931 sc->hw.mac.get_link_status = 1;
3932 emx_update_link_status(sc);
3933 callout_reset(&sc->timer, hz, emx_timer, sc);
3938 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3940 struct emx_txdata *tdata = arg;
3942 ASSERT_SERIALIZED(&tdata->tx_serialize);
3945 if (!ifsq_is_empty(tdata->ifsq))
3946 ifsq_devstart(tdata->ifsq);
3950 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3952 struct emx_rxdata *rdata = arg;
3954 ASSERT_SERIALIZED(&rdata->rx_serialize);
3956 emx_rxeof(rdata, cycle);
3960 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3962 struct emx_softc *sc = ifp->if_softc;
3965 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3970 info->ifpi_status.status_func = emx_npoll_status;
3971 info->ifpi_status.serializer = &sc->main_serialize;
3973 txr_cnt = emx_get_txring_inuse(sc, TRUE);
3974 off = sc->tx_npoll_off;
3975 for (i = 0; i < txr_cnt; ++i) {
3976 struct emx_txdata *tdata = &sc->tx_data[i];
3979 KKASSERT(idx < ncpus2);
3980 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
3981 info->ifpi_tx[idx].arg = tdata;
3982 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
3983 ifsq_set_cpuid(tdata->ifsq, idx);
3986 off = sc->rx_npoll_off;
3987 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3988 struct emx_rxdata *rdata = &sc->rx_data[i];
3991 KKASSERT(idx < ncpus2);
3992 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
3993 info->ifpi_rx[idx].arg = rdata;
3994 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
3997 if (ifp->if_flags & IFF_RUNNING) {
3998 if (txr_cnt == sc->tx_ring_inuse)
3999 emx_disable_intr(sc);
4004 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4005 struct emx_txdata *tdata = &sc->tx_data[i];
4007 ifsq_set_cpuid(tdata->ifsq,
4008 rman_get_cpuid(sc->intr_res));
4011 if (ifp->if_flags & IFF_RUNNING) {
4012 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4013 if (txr_cnt == sc->tx_ring_inuse)
4014 emx_enable_intr(sc);
4021 #endif /* IFPOLL_ENABLE */
4024 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4026 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4027 if (sc->hw.mac.type == e1000_82574) {
4031 * When using MSIX interrupts we need to
4032 * throttle using the EITR register
4034 for (i = 0; i < 4; ++i)
4035 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4040 * Disable the L0s, 82574L Errata #20
4043 emx_disable_aspm(struct emx_softc *sc)
4045 uint16_t link_cap, link_ctrl, disable;
4046 uint8_t pcie_ptr, reg;
4047 device_t dev = sc->dev;
4049 switch (sc->hw.mac.type) {
4054 * 82573 specification update
4055 * errata #8 disable L0s
4056 * errata #41 disable L1
4058 * 82571/82572 specification update
4059 # errata #13 disable L1
4060 * errata #68 disable L0s
4062 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4067 * 82574 specification update errata #20
4069 * There is no need to disable L1
4071 disable = PCIEM_LNKCTL_ASPM_L0S;
4078 pcie_ptr = pci_get_pciecap_ptr(dev);
4082 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4083 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4087 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4089 reg = pcie_ptr + PCIER_LINKCTRL;
4090 link_ctrl = pci_read_config(dev, reg, 2);
4091 link_ctrl &= ~disable;
4092 pci_write_config(dev, reg, link_ctrl, 2);
4096 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4098 int iphlen, hoff, thoff, ex = 0;
4103 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4105 iphlen = m->m_pkthdr.csum_iphlen;
4106 thoff = m->m_pkthdr.csum_thlen;
4107 hoff = m->m_pkthdr.csum_lhlen;
4109 KASSERT(iphlen > 0, ("invalid ip hlen"));
4110 KASSERT(thoff > 0, ("invalid tcp hlen"));
4111 KASSERT(hoff > 0, ("invalid ether hlen"));
4113 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4116 if (m->m_len < hoff + iphlen + thoff + ex) {
4117 m = m_pullup(m, hoff + iphlen + thoff + ex);
4124 ip = mtodoff(m, struct ip *, hoff);
4131 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4132 uint32_t *txd_upper, uint32_t *txd_lower)
4134 struct e1000_context_desc *TXD;
4135 int hoff, iphlen, thoff, hlen;
4136 int mss, pktlen, curr_txd;
4138 #ifdef EMX_TSO_DEBUG
4139 tdata->tso_segments++;
4142 iphlen = mp->m_pkthdr.csum_iphlen;
4143 thoff = mp->m_pkthdr.csum_thlen;
4144 hoff = mp->m_pkthdr.csum_lhlen;
4145 mss = mp->m_pkthdr.tso_segsz;
4146 pktlen = mp->m_pkthdr.len;
4148 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4149 tdata->csum_flags == CSUM_TSO &&
4150 tdata->csum_iphlen == iphlen &&
4151 tdata->csum_lhlen == hoff &&
4152 tdata->csum_thlen == thoff &&
4153 tdata->csum_mss == mss &&
4154 tdata->csum_pktlen == pktlen) {
4155 *txd_upper = tdata->csum_txd_upper;
4156 *txd_lower = tdata->csum_txd_lower;
4157 #ifdef EMX_TSO_DEBUG
4158 tdata->tso_ctx_reused++;
4162 hlen = hoff + iphlen + thoff;
4165 * Setup a new TSO context.
4168 curr_txd = tdata->next_avail_tx_desc;
4169 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4171 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4172 E1000_TXD_DTYP_D | /* Data descr type */
4173 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4175 /* IP and/or TCP header checksum calculation and insertion. */
4176 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4179 * Start offset for header checksum calculation.
4180 * End offset for header checksum calculation.
4181 * Offset of place put the checksum.
4183 TXD->lower_setup.ip_fields.ipcss = hoff;
4184 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4185 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4188 * Start offset for payload checksum calculation.
4189 * End offset for payload checksum calculation.
4190 * Offset of place to put the checksum.
4192 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4193 TXD->upper_setup.tcp_fields.tucse = 0;
4194 TXD->upper_setup.tcp_fields.tucso =
4195 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4198 * Payload size per packet w/o any headers.
4199 * Length of all headers up to payload.
4201 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4202 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4203 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4204 E1000_TXD_CMD_DEXT | /* Extended descr */
4205 E1000_TXD_CMD_TSE | /* TSE context */
4206 E1000_TXD_CMD_IP | /* Do IP csum */
4207 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4208 (pktlen - hlen)); /* Total len */
4210 /* Save the information for this TSO context */
4211 tdata->csum_flags = CSUM_TSO;
4212 tdata->csum_lhlen = hoff;
4213 tdata->csum_iphlen = iphlen;
4214 tdata->csum_thlen = thoff;
4215 tdata->csum_mss = mss;
4216 tdata->csum_pktlen = pktlen;
4217 tdata->csum_txd_upper = *txd_upper;
4218 tdata->csum_txd_lower = *txd_lower;
4220 if (++curr_txd == tdata->num_tx_desc)
4223 KKASSERT(tdata->num_tx_desc_avail > 0);
4224 tdata->num_tx_desc_avail--;
4226 tdata->next_avail_tx_desc = curr_txd;
4231 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4234 return sc->tx_ring_cnt;