2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * The order of pokes in the initiation sequence is based on Linux
27 * driver by Thomas Sailer, gw boynton (wesb@crystal.cirrus.com), tom
28 * woller (twoller@crystal.cirrus.com). Shingo Watanabe (nabe@nabechan.org)
29 * contributed towards power management.
31 * $FreeBSD: src/sys/dev/sound/pci/cs4281.c,v 1.22 2005/03/01 08:58:05 imp Exp $
32 * $DragonFly: src/sys/dev/sound/pci/cs4281.c,v 1.10 2007/01/04 21:47:02 corecode Exp $
35 #include <dev/sound/pcm/sound.h>
36 #include <dev/sound/pcm/ac97.h>
38 #include <bus/pci/pcireg.h>
39 #include <bus/pci/pcivar.h>
41 #include <dev/sound/pci/cs4281.h>
43 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/cs4281.c,v 1.10 2007/01/04 21:47:02 corecode Exp $");
45 #define CS4281_DEFAULT_BUFSZ 16384
47 /* Max fifo size for full duplex is 64 */
48 #define CS4281_FIFO_SIZE 15
50 /* DMA Engine Indices */
51 #define CS4281_DMA_PLAY 0
52 #define CS4281_DMA_REC 1
56 #define inline __inline
59 #define DEB(x) /* x */
62 /* ------------------------------------------------------------------------- */
67 /* channel registers */
69 struct sc_info *parent;
71 struct snd_dbuf *buffer;
72 struct pcm_channel *channel;
74 u_int32_t spd, fmt, bps, blksz;
76 int dma_setup, dma_active, dma_chan;
79 /* device private data */
85 bus_space_handle_t sh;
86 bus_dma_tag_t parent_dmat;
88 struct resource *reg, *irq, *mem;
89 int regtype, regid, irqid, memid;
98 /* -------------------------------------------------------------------- */
101 /* ADC/DAC control */
102 static u_int32_t adcdac_go(struct sc_chinfo *ch, u_int32_t go);
103 static void adcdac_prog(struct sc_chinfo *ch);
105 /* power management and interrupt control */
106 static void cs4281_intr(void *);
107 static int cs4281_power(struct sc_info *, int);
108 static int cs4281_init(struct sc_info *);
110 /* talk to the card */
111 static u_int32_t cs4281_rd(struct sc_info *, int);
112 static void cs4281_wr(struct sc_info *, int, u_int32_t);
115 static u_int8_t cs4281_rate_to_rv(u_int32_t);
116 static u_int32_t cs4281_format_to_dmr(u_int32_t);
117 static u_int32_t cs4281_format_to_bps(u_int32_t);
119 /* -------------------------------------------------------------------- */
120 /* formats (do not add formats without editing cs_fmt_tab) */
122 static u_int32_t cs4281_fmts[] = {
124 AFMT_U8 | AFMT_STEREO,
126 AFMT_S8 | AFMT_STEREO,
128 AFMT_S16_LE | AFMT_STEREO,
130 AFMT_U16_LE | AFMT_STEREO,
132 AFMT_S16_BE | AFMT_STEREO,
134 AFMT_U16_BE | AFMT_STEREO,
138 static struct pcmchan_caps cs4281_caps = {6024, 48000, cs4281_fmts, 0};
140 /* -------------------------------------------------------------------- */
143 static inline u_int32_t
144 cs4281_rd(struct sc_info *sc, int regno)
146 return bus_space_read_4(sc->st, sc->sh, regno);
150 cs4281_wr(struct sc_info *sc, int regno, u_int32_t data)
152 bus_space_write_4(sc->st, sc->sh, regno, data);
157 cs4281_clr4(struct sc_info *sc, int regno, u_int32_t mask)
160 r = cs4281_rd(sc, regno);
161 cs4281_wr(sc, regno, r & ~mask);
165 cs4281_set4(struct sc_info *sc, int regno, u_int32_t mask)
168 v = cs4281_rd(sc, regno);
169 cs4281_wr(sc, regno, v | mask);
173 cs4281_waitset(struct sc_info *sc, int regno, u_int32_t mask, int tries)
179 v = cs4281_rd(sc, regno);
180 if ((v & mask) == mask) break;
187 cs4281_waitclr(struct sc_info *sc, int regno, u_int32_t mask, int tries)
193 v = ~ cs4281_rd(sc, regno);
200 /* ------------------------------------------------------------------------- */
201 /* Register value mapping functions */
203 static u_int32_t cs4281_rates[] = {48000, 44100, 22050, 16000, 11025, 8000};
204 #define CS4281_NUM_RATES sizeof(cs4281_rates)/sizeof(cs4281_rates[0])
207 cs4281_rate_to_rv(u_int32_t rate)
211 for (v = 0; v < CS4281_NUM_RATES; v++) {
212 if (rate == cs4281_rates[v]) return v;
216 if (v > 255 || v < 32) v = 5; /* default to 8k */
221 cs4281_rv_to_rate(u_int8_t rv)
225 if (rv < CS4281_NUM_RATES) return cs4281_rates[rv];
230 static inline u_int32_t
231 cs4281_format_to_dmr(u_int32_t format)
234 if (AFMT_8BIT & format) dmr |= CS4281PCI_DMR_SIZE8;
235 if (!(AFMT_STEREO & format)) dmr |= CS4281PCI_DMR_MONO;
236 if (AFMT_BIGENDIAN & format) dmr |= CS4281PCI_DMR_BEND;
237 if (!(AFMT_SIGNED & format)) dmr |= CS4281PCI_DMR_USIGN;
241 static inline u_int32_t
242 cs4281_format_to_bps(u_int32_t format)
244 return ((AFMT_8BIT & format) ? 1 : 2) * ((AFMT_STEREO & format) ? 2 : 1);
247 /* -------------------------------------------------------------------- */
251 cs4281_rdcd(kobj_t obj, void *devinfo, int regno)
253 struct sc_info *sc = (struct sc_info *)devinfo;
256 codecno = regno >> 8;
259 /* Remove old state */
260 cs4281_rd(sc, CS4281PCI_ACSDA);
262 /* Fill in AC97 register value request form */
263 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
264 cs4281_wr(sc, CS4281PCI_ACCDA, 0);
265 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
266 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV |
267 CS4281PCI_ACCTL_CRW);
269 /* Wait for read to complete */
270 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
271 device_printf(sc->dev, "cs4281_rdcd: DCV did not go\n");
275 /* Wait for valid status */
276 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_VSTS, 250) == 0) {
277 device_printf(sc->dev,"cs4281_rdcd: VSTS did not come\n");
281 return cs4281_rd(sc, CS4281PCI_ACSDA);
285 cs4281_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
287 struct sc_info *sc = (struct sc_info *)devinfo;
290 codecno = regno >> 8;
293 cs4281_wr(sc, CS4281PCI_ACCAD, regno);
294 cs4281_wr(sc, CS4281PCI_ACCDA, data);
295 cs4281_wr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_ESYN |
296 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_DCV);
298 if (cs4281_waitclr(sc, CS4281PCI_ACCTL, CS4281PCI_ACCTL_DCV, 250) == 0) {
299 device_printf(sc->dev,"cs4281_wrcd: DCV did not go\n");
303 static kobj_method_t cs4281_ac97_methods[] = {
304 KOBJMETHOD(ac97_read, cs4281_rdcd),
305 KOBJMETHOD(ac97_write, cs4281_wrcd),
308 AC97_DECLARE(cs4281_ac97);
310 /* ------------------------------------------------------------------------- */
311 /* shared rec/play channel interface */
314 cs4281chan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
316 struct sc_info *sc = devinfo;
317 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
320 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) != 0) {
327 ch->spd = DSP_DEFAULT_SPEED;
329 ch->blksz = sndbuf_getsize(ch->buffer);
331 ch->dma_chan = (dir == PCMDIR_PLAY) ? CS4281_DMA_PLAY : CS4281_DMA_REC;
341 cs4281chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
343 struct sc_chinfo *ch = data;
344 struct sc_info *sc = ch->parent;
347 go = adcdac_go(ch, 0);
349 /* 2 interrupts are possible and used in buffer (half-empty,empty),
350 * hence factor of 2. */
351 ch->blksz = MIN(blocksize, sc->bufsz / 2);
352 sndbuf_resize(ch->buffer, 2, ch->blksz);
357 DEB(kprintf("cs4281chan_setblocksize: blksz %d Setting %d\n", blocksize, ch->blksz));
363 cs4281chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
365 struct sc_chinfo *ch = data;
366 struct sc_info *sc = ch->parent;
369 go = adcdac_go(ch, 0); /* pause */
370 r = (ch->dma_chan == CS4281_DMA_PLAY) ? CS4281PCI_DACSR : CS4281PCI_ADCSR;
371 v = cs4281_rate_to_rv(speed);
373 adcdac_go(ch, go); /* unpause */
375 ch->spd = cs4281_rv_to_rate(v);
380 cs4281chan_setformat(kobj_t obj, void *data, u_int32_t format)
382 struct sc_chinfo *ch = data;
383 struct sc_info *sc = ch->parent;
386 go = adcdac_go(ch, 0); /* pause */
388 if (ch->dma_chan == CS4281_DMA_PLAY)
389 v = CS4281PCI_DMR_TR_PLAY;
391 v = CS4281PCI_DMR_TR_REC;
392 v |= CS4281PCI_DMR_DMA | CS4281PCI_DMR_AUTO;
393 v |= cs4281_format_to_dmr(format);
394 cs4281_wr(sc, CS4281PCI_DMR(ch->dma_chan), v);
396 adcdac_go(ch, go); /* unpause */
399 ch->bps = cs4281_format_to_bps(format);
406 cs4281chan_getptr(kobj_t obj, void *data)
408 struct sc_chinfo *ch = data;
409 struct sc_info *sc = ch->parent;
410 u_int32_t dba, dca, ptr;
413 sz = sndbuf_getsize(ch->buffer);
414 dba = cs4281_rd(sc, CS4281PCI_DBA(ch->dma_chan));
415 dca = cs4281_rd(sc, CS4281PCI_DCA(ch->dma_chan));
416 ptr = (dca - dba + sz) % sz;
422 cs4281chan_trigger(kobj_t obj, void *data, int go)
424 struct sc_chinfo *ch = data;
442 static struct pcmchan_caps *
443 cs4281chan_getcaps(kobj_t obj, void *data)
448 static kobj_method_t cs4281chan_methods[] = {
449 KOBJMETHOD(channel_init, cs4281chan_init),
450 KOBJMETHOD(channel_setformat, cs4281chan_setformat),
451 KOBJMETHOD(channel_setspeed, cs4281chan_setspeed),
452 KOBJMETHOD(channel_setblocksize, cs4281chan_setblocksize),
453 KOBJMETHOD(channel_trigger, cs4281chan_trigger),
454 KOBJMETHOD(channel_getptr, cs4281chan_getptr),
455 KOBJMETHOD(channel_getcaps, cs4281chan_getcaps),
458 CHANNEL_DECLARE(cs4281chan);
460 /* -------------------------------------------------------------------- */
461 /* ADC/DAC control */
463 /* adcdac_go enables/disable DMA channel, returns non-zero if DMA was
464 * active before call */
467 adcdac_go(struct sc_chinfo *ch, u_int32_t go)
469 struct sc_info *sc = ch->parent;
472 going = !(cs4281_rd(sc, CS4281PCI_DCR(ch->dma_chan)) & CS4281PCI_DCR_MSK);
475 cs4281_clr4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
477 cs4281_set4(sc, CS4281PCI_DCR(ch->dma_chan), CS4281PCI_DCR_MSK);
479 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
485 adcdac_prog(struct sc_chinfo *ch)
487 struct sc_info *sc = ch->parent;
490 if (!ch->dma_setup) {
491 go = adcdac_go(ch, 0);
492 cs4281_wr(sc, CS4281PCI_DBA(ch->dma_chan),
493 sndbuf_getbufaddr(ch->buffer));
494 cs4281_wr(sc, CS4281PCI_DBC(ch->dma_chan),
495 sndbuf_getsize(ch->buffer) / ch->bps - 1);
501 /* -------------------------------------------------------------------- */
502 /* The interrupt handler */
507 struct sc_info *sc = (struct sc_info *)p;
510 hisr = cs4281_rd(sc, CS4281PCI_HISR);
512 if (hisr == 0) return;
514 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_PLAY)) {
515 chn_intr(sc->pch.channel);
516 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_PLAY)); /* Clear interrupt */
519 if (hisr & CS4281PCI_HISR_DMA(CS4281_DMA_REC)) {
520 chn_intr(sc->rch.channel);
521 cs4281_rd(sc, CS4281PCI_HDSR(CS4281_DMA_REC)); /* Clear interrupt */
524 /* Signal End-of-Interrupt */
525 cs4281_wr(sc, CS4281PCI_HICR, CS4281PCI_HICR_EOI);
528 /* -------------------------------------------------------------------- */
529 /* power management related */
532 cs4281_power(struct sc_info *sc, int state)
537 /* Permit r/w access to all BA0 registers */
538 cs4281_wr(sc, CS4281PCI_CWPR, CS4281PCI_CWPR_MAGIC);
540 cs4281_clr4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
543 /* Power off card and codec */
544 cs4281_set4(sc, CS4281PCI_EPPMC, CS4281PCI_EPPMC_FPDN);
545 cs4281_clr4(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
549 DEB(kprintf("cs4281_power %d -> %d\n", sc->power, state));
556 cs4281_init(struct sc_info *sc)
560 /* (0) Blast clock register and serial port */
561 cs4281_wr(sc, CS4281PCI_CLKCR1, 0);
562 cs4281_wr(sc, CS4281PCI_SERMC, 0);
564 /* (1) Make ESYN 0 to turn sync pulse on AC97 link */
565 cs4281_wr(sc, CS4281PCI_ACCTL, 0);
568 /* (2) Effect Reset */
569 cs4281_wr(sc, CS4281PCI_SPMC, 0);
571 cs4281_wr(sc, CS4281PCI_SPMC, CS4281PCI_SPMC_RSTN);
572 /* Wait 50ms for ABITCLK to become stable */
575 /* (3) Enable Sound System Clocks */
576 cs4281_wr(sc, CS4281PCI_CLKCR1, CS4281PCI_CLKCR1_DLLP);
577 DELAY(50000); /* Wait for PLL to stabilize */
578 cs4281_wr(sc, CS4281PCI_CLKCR1,
579 CS4281PCI_CLKCR1_DLLP | CS4281PCI_CLKCR1_SWCE);
581 /* (4) Power Up - this combination is essential. */
582 cs4281_set4(sc, CS4281PCI_SSPM,
583 CS4281PCI_SSPM_ACLEN | CS4281PCI_SSPM_PSRCEN |
584 CS4281PCI_SSPM_CSRCEN | CS4281PCI_SSPM_MIXEN);
586 /* (5) Wait for clock stabilization */
587 if (cs4281_waitset(sc,
589 CS4281PCI_CLKCR1_DLLRDY,
591 device_printf(sc->dev, "Clock stabilization failed\n");
595 /* (6) Enable ASYNC generation. */
596 cs4281_wr(sc, CS4281PCI_ACCTL,CS4281PCI_ACCTL_ESYN);
598 /* Wait to allow AC97 to start generating clock bit */
601 /* Set AC97 timing */
602 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
604 /* (7) Wait for AC97 ready signal */
605 if (cs4281_waitset(sc, CS4281PCI_ACSTS, CS4281PCI_ACSTS_CRDY, 250) == 0) {
606 device_printf(sc->dev, "codec did not avail\n");
610 /* (8) Assert valid frame signal to begin sending commands to
614 CS4281PCI_ACCTL_VFRM | CS4281PCI_ACCTL_ESYN);
616 /* (9) Wait for codec calibration */
617 for(i = 0 ; i < 1000; i++) {
619 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
620 if ((v & 0x0f) == 0x0f) {
625 device_printf(sc->dev, "codec failed to calibrate\n");
629 /* (10) Set AC97 timing */
630 cs4281_wr(sc, CS4281PCI_SERMC, CS4281PCI_SERMC_PTC_AC97);
632 /* (11) Wait for valid data to arrive */
633 if (cs4281_waitset(sc,
635 CS4281PCI_ACISV_ISV(3) | CS4281PCI_ACISV_ISV(4),
637 device_printf(sc->dev, "cs4281 never got valid data\n");
641 /* (12) Start digital data transfer of audio data to codec */
644 CS4281PCI_ACOSV_SLV(3) | CS4281PCI_ACOSV_SLV(4));
646 /* Set Master and headphone to max */
647 cs4281_wrcd(0, sc, AC97_MIX_AUXOUT, 0);
648 cs4281_wrcd(0, sc, AC97_MIX_MASTER, 0);
650 /* Power on the DAC */
651 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfdff;
652 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
654 /* Wait until DAC state ready */
655 for(i = 0; i < 320; i++) {
657 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
661 /* Power on the ADC */
662 v = cs4281_rdcd(0, sc, AC97_REG_POWER) & 0xfeff;
663 cs4281_wrcd(0, sc, AC97_REG_POWER, v);
665 /* Wait until ADC state ready */
666 for(i = 0; i < 320; i++) {
668 v = cs4281_rdcd(0, sc, AC97_REG_POWER);
672 /* FIFO configuration (driver is DMA orientated, implicit FIFO) */
675 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_PLAY_SLOT) |
676 CS4281PCI_FCR_LS(CS4281PCI_LPCM_PLAY_SLOT) |
677 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
679 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v);
681 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_PLAY), v | CS4281PCI_FCR_FEN);
684 v = CS4281PCI_FCR_RS(CS4281PCI_RPCM_REC_SLOT) |
685 CS4281PCI_FCR_LS(CS4281PCI_LPCM_REC_SLOT) |
686 CS4281PCI_FCR_SZ(CS4281_FIFO_SIZE)|
687 CS4281PCI_FCR_OF(CS4281_FIFO_SIZE + 1);
688 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_PSH);
689 cs4281_wr(sc, CS4281PCI_FCR(CS4281_DMA_REC), v | CS4281PCI_FCR_FEN);
691 /* Match AC97 slots to FIFOs */
692 v = CS4281PCI_SRCSA_PLSS(CS4281PCI_LPCM_PLAY_SLOT) |
693 CS4281PCI_SRCSA_PRSS(CS4281PCI_RPCM_PLAY_SLOT) |
694 CS4281PCI_SRCSA_CLSS(CS4281PCI_LPCM_REC_SLOT) |
695 CS4281PCI_SRCSA_CRSS(CS4281PCI_RPCM_REC_SLOT);
696 cs4281_wr(sc, CS4281PCI_SRCSA, v);
698 /* Set Auto-Initialize and set directions */
700 CS4281PCI_DMR(CS4281_DMA_PLAY),
703 CS4281PCI_DMR_TR_PLAY);
705 CS4281PCI_DMR(CS4281_DMA_REC),
708 CS4281PCI_DMR_TR_REC);
710 /* Enable half and empty buffer interrupts keeping DMA paused */
712 CS4281PCI_DCR(CS4281_DMA_PLAY),
713 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
715 CS4281PCI_DCR(CS4281_DMA_REC),
716 CS4281PCI_DCR_TCIE | CS4281PCI_DCR_HTCIE | CS4281PCI_DCR_MSK);
718 /* Enable Interrupts */
721 CS4281PCI_HIMR_DMAI |
722 CS4281PCI_HIMR_DMA(CS4281_DMA_PLAY) |
723 CS4281PCI_HIMR_DMA(CS4281_DMA_REC));
725 /* Set playback volume */
726 cs4281_wr(sc, CS4281PCI_PPLVC, 7);
727 cs4281_wr(sc, CS4281PCI_PPRVC, 7);
732 /* -------------------------------------------------------------------- */
733 /* Probe and attach the card */
736 cs4281_pci_probe(device_t dev)
740 switch (pci_get_devid(dev)) {
742 s = "Crystal Semiconductor CS4281";
747 device_set_desc(dev, s);
748 return s ? BUS_PROBE_DEFAULT : ENXIO;
752 cs4281_pci_attach(device_t dev)
755 struct ac97_info *codec = NULL;
757 char status[SND_STATUSLEN];
759 if ((sc = kmalloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
760 device_printf(dev, "cannot allocate softc\n");
765 sc->type = pci_get_devid(dev);
767 data = pci_read_config(dev, PCIR_COMMAND, 2);
768 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
769 pci_write_config(dev, PCIR_COMMAND, data, 2);
771 #if __FreeBSD_version > 500000
772 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
773 /* Reset the power state. */
774 device_printf(dev, "chip is in D%d power mode "
775 "-- setting to D0\n", pci_get_powerstate(dev));
777 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
780 data = pci_read_config(dev, CS4281PCI_PMCS_OFFSET, 4);
781 if (data & CS4281PCI_PMCS_PS_MASK) {
782 /* Reset the power state. */
783 device_printf(dev, "chip is in D%d power mode "
784 "-- setting to D0\n",
785 data & CS4281PCI_PMCS_PS_MASK);
786 pci_write_config(dev, CS4281PCI_PMCS_OFFSET,
787 data & ~CS4281PCI_PMCS_PS_MASK, 4);
791 sc->regid = PCIR_BAR(0);
792 sc->regtype = SYS_RES_MEMORY;
793 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
794 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
796 sc->regtype = SYS_RES_IOPORT;
797 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
798 0, ~0, CS4281PCI_BA0_SIZE, RF_ACTIVE);
800 device_printf(dev, "unable to allocate register space\n");
804 sc->st = rman_get_bustag(sc->reg);
805 sc->sh = rman_get_bushandle(sc->reg);
807 sc->memid = PCIR_BAR(1);
808 sc->mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid, 0,
809 ~0, CS4281PCI_BA1_SIZE, RF_ACTIVE);
810 if (sc->mem == NULL) {
811 device_printf(dev, "unable to allocate fifo space\n");
816 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
817 RF_ACTIVE | RF_SHAREABLE);
819 device_printf(dev, "unable to allocate interrupt\n");
823 if (snd_setup_intr(dev, sc->irq, 0, cs4281_intr, sc, &sc->ih)) {
824 device_printf(dev, "unable to setup interrupt\n");
828 sc->bufsz = pcm_getbuffersize(dev, 4096, CS4281_DEFAULT_BUFSZ, 65536);
830 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
831 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
832 /*highaddr*/BUS_SPACE_MAXADDR,
833 /*filter*/NULL, /*filterarg*/NULL,
834 /*maxsize*/sc->bufsz, /*nsegments*/1,
837 &sc->parent_dmat) != 0) {
838 device_printf(dev, "unable to create dma tag\n");
846 if (cs4281_init(sc) == -1) {
847 device_printf(dev, "unable to initialize the card\n");
851 /* create/init mixer */
852 codec = AC97_CREATE(dev, sc, cs4281_ac97);
856 mixer_init(dev, ac97_getmixerclass(), codec);
858 if (pcm_register(dev, sc, 1, 1))
861 pcm_addchan(dev, PCMDIR_PLAY, &cs4281chan_class, sc);
862 pcm_addchan(dev, PCMDIR_REC, &cs4281chan_class, sc);
864 ksnprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld %s",
865 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
866 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_cs4281));
867 pcm_setstatus(dev, status);
875 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
877 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
879 bus_teardown_intr(dev, sc->irq, sc->ih);
881 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
883 bus_dma_tag_destroy(sc->parent_dmat);
890 cs4281_pci_detach(device_t dev)
895 r = pcm_unregister(dev);
899 sc = pcm_getdevinfo(dev);
904 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
905 bus_release_resource(dev, SYS_RES_MEMORY, sc->memid, sc->mem);
906 bus_teardown_intr(dev, sc->irq, sc->ih);
907 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
908 bus_dma_tag_destroy(sc->parent_dmat);
915 cs4281_pci_suspend(device_t dev)
919 sc = pcm_getdevinfo(dev);
921 sc->rch.dma_active = adcdac_go(&sc->rch, 0);
922 sc->pch.dma_active = adcdac_go(&sc->pch, 0);
930 cs4281_pci_resume(device_t dev)
934 sc = pcm_getdevinfo(dev);
939 /* initialize chip */
940 if (cs4281_init(sc) == -1) {
941 device_printf(dev, "unable to reinitialize the card\n");
945 /* restore mixer state */
946 if (mixer_reinit(dev) == -1) {
947 device_printf(dev, "unable to reinitialize the mixer\n");
951 /* restore chip state */
952 cs4281chan_setspeed(NULL, &sc->rch, sc->rch.spd);
953 cs4281chan_setblocksize(NULL, &sc->rch, sc->rch.blksz);
954 cs4281chan_setformat(NULL, &sc->rch, sc->rch.fmt);
955 adcdac_go(&sc->rch, sc->rch.dma_active);
957 cs4281chan_setspeed(NULL, &sc->pch, sc->pch.spd);
958 cs4281chan_setblocksize(NULL, &sc->pch, sc->pch.blksz);
959 cs4281chan_setformat(NULL, &sc->pch, sc->pch.fmt);
960 adcdac_go(&sc->pch, sc->pch.dma_active);
965 static device_method_t cs4281_methods[] = {
966 /* Device interface */
967 DEVMETHOD(device_probe, cs4281_pci_probe),
968 DEVMETHOD(device_attach, cs4281_pci_attach),
969 DEVMETHOD(device_detach, cs4281_pci_detach),
970 DEVMETHOD(device_suspend, cs4281_pci_suspend),
971 DEVMETHOD(device_resume, cs4281_pci_resume),
975 static driver_t cs4281_driver = {
981 DRIVER_MODULE(snd_cs4281, pci, cs4281_driver, pcm_devclass, 0, 0);
982 MODULE_DEPEND(snd_cs4281, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
983 MODULE_VERSION(snd_cs4281, 1);