1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <drm/i915_drm.h>
32 #include "intel_drv.h"
33 #include "intel_ringbuffer.h"
34 #include <linux/workqueue.h>
36 extern struct drm_i915_private *i915_mch_dev;
38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
40 #define BEGIN_LP_RING(n) \
41 intel_ring_begin(LP_RING(dev_priv), (n))
44 intel_ring_emit(LP_RING(dev_priv), x)
46 #define ADVANCE_LP_RING() \
47 intel_ring_advance(LP_RING(dev_priv))
50 * Lock test for when it's just for synchronization of ring access.
52 * In that case, we don't need to do it when GEM is initialized as nobody else
53 * has access to the ring.
55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
56 if (LP_RING(dev->dev_private)->obj == NULL) \
57 LOCK_TEST_WITH_RETURN(dev, file); \
61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
63 if (I915_NEED_GFX_HWS(dev_priv->dev))
64 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
66 return intel_read_status_page(LP_RING(dev_priv), reg);
69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
71 #define I915_BREADCRUMB_INDEX 0x21
73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
76 * The dri breadcrumb update races against the drm master disappearing.
77 * Instead of trying to fix this (this is by far not the only ums issue)
78 * just don't do the update in kms mode.
80 if (drm_core_check_feature(dev, DRIVER_MODESET))
83 /* XXX: don't do it at all actually */
87 static void i915_write_hws_pga(struct drm_device *dev)
89 drm_i915_private_t *dev_priv = dev->dev_private;
92 addr = dev_priv->status_page_dmah->busaddr;
93 if (INTEL_INFO(dev)->gen >= 4)
94 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
95 I915_WRITE(HWS_PGA, addr);
99 * Sets up the hardware status page for devices that need a physical address
102 static int i915_init_phys_hws(struct drm_device *dev)
104 drm_i915_private_t *dev_priv = dev->dev_private;
105 struct intel_ring_buffer *ring = LP_RING(dev_priv);
108 * Program Hardware Status Page
109 * XXXKIB Keep 4GB limit for allocation for now. This method
110 * of allocation is used on <= 965 hardware, that has several
111 * erratas regarding the use of physical memory > 4 GB.
114 dev_priv->status_page_dmah =
115 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
117 if (!dev_priv->status_page_dmah) {
118 DRM_ERROR("Can not allocate hardware status page\n");
121 ring->status_page.page_addr = dev_priv->hw_status_page =
122 dev_priv->status_page_dmah->vaddr;
123 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
125 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
127 i915_write_hws_pga(dev);
128 DRM_DEBUG("Enabled hardware status page, phys %jx\n",
129 (uintmax_t)dev_priv->dma_status_page);
134 * Frees the hardware status page, whether it's a physical address or a virtual
135 * address set up by the X Server.
137 static void i915_free_hws(struct drm_device *dev)
139 drm_i915_private_t *dev_priv = dev->dev_private;
140 struct intel_ring_buffer *ring = LP_RING(dev_priv);
142 if (dev_priv->status_page_dmah) {
143 drm_pci_free(dev, dev_priv->status_page_dmah);
144 dev_priv->status_page_dmah = NULL;
147 if (dev_priv->status_gfx_addr) {
148 dev_priv->status_gfx_addr = 0;
149 ring->status_page.gfx_addr = 0;
150 drm_core_ioremapfree(&dev_priv->hws_map, dev);
153 /* Need to rewrite hardware status page */
154 I915_WRITE(HWS_PGA, 0x1ffff000);
157 void i915_kernel_lost_context(struct drm_device * dev)
159 drm_i915_private_t *dev_priv = dev->dev_private;
160 struct intel_ring_buffer *ring = LP_RING(dev_priv);
163 * We should never lose context on the ring with modesetting
164 * as we don't expose it to userspace
166 if (drm_core_check_feature(dev, DRIVER_MODESET))
169 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
170 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
171 ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
173 ring->space += ring->size;
178 if (!dev->primary->master)
182 if (ring->head == ring->tail && dev_priv->sarea_priv)
183 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
186 static int i915_dma_cleanup(struct drm_device * dev)
188 drm_i915_private_t *dev_priv = dev->dev_private;
192 /* Make sure interrupts are disabled here because the uninstall ioctl
193 * may not have been called from userspace and after dev_private
194 * is freed, it's too late.
196 if (dev->irq_enabled)
197 drm_irq_uninstall(dev);
200 for (i = 0; i < I915_NUM_RINGS; i++)
201 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
204 /* Clear the HWS virtual address at teardown */
205 if (I915_NEED_GFX_HWS(dev))
211 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
213 drm_i915_private_t *dev_priv = dev->dev_private;
216 dev_priv->sarea = drm_getsarea(dev);
217 if (!dev_priv->sarea) {
218 DRM_ERROR("can not find sarea!\n");
219 i915_dma_cleanup(dev);
223 dev_priv->sarea_priv = (drm_i915_sarea_t *)
224 ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
226 if (init->ring_size != 0) {
227 if (LP_RING(dev_priv)->obj != NULL) {
228 i915_dma_cleanup(dev);
229 DRM_ERROR("Client tried to initialize ringbuffer in "
234 ret = intel_render_ring_init_dri(dev,
238 i915_dma_cleanup(dev);
243 dev_priv->cpp = init->cpp;
244 dev_priv->back_offset = init->back_offset;
245 dev_priv->front_offset = init->front_offset;
246 dev_priv->current_page = 0;
247 dev_priv->sarea_priv->pf_current_page = 0;
249 /* Allow hardware batchbuffers unless told otherwise.
251 dev_priv->dri1.allow_batchbuffer = 1;
256 static int i915_dma_resume(struct drm_device * dev)
258 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
259 struct intel_ring_buffer *ring = LP_RING(dev_priv);
263 if (ring->virtual_start == NULL) {
264 DRM_ERROR("can not ioremap virtual address for"
269 /* Program Hardware Status Page */
270 if (!ring->status_page.page_addr) {
271 DRM_ERROR("Can not find hardware status page\n");
274 DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
275 if (ring->status_page.gfx_addr != 0)
276 intel_ring_setup_status_page(ring);
278 i915_write_hws_pga(dev);
280 DRM_DEBUG("Enabled hardware status page\n");
285 static int i915_dma_init(struct drm_device *dev, void *data,
286 struct drm_file *file_priv)
288 drm_i915_init_t *init = data;
291 switch (init->func) {
293 retcode = i915_initialize(dev, init);
295 case I915_CLEANUP_DMA:
296 retcode = i915_dma_cleanup(dev);
298 case I915_RESUME_DMA:
299 retcode = i915_dma_resume(dev);
309 /* Implement basically the same security restrictions as hardware does
310 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
312 * Most of the calculations below involve calculating the size of a
313 * particular instruction. It's important to get the size right as
314 * that tells us where the next instruction to check is. Any illegal
315 * instruction detected will be given a size of zero, which is a
316 * signal to abort the rest of the buffer.
318 static int do_validate_cmd(int cmd)
320 switch (((cmd >> 29) & 0x7)) {
322 switch ((cmd >> 23) & 0x3f) {
324 return 1; /* MI_NOOP */
326 return 1; /* MI_FLUSH */
328 return 0; /* disallow everything else */
332 return 0; /* reserved */
334 return (cmd & 0xff) + 2; /* 2d commands */
336 if (((cmd >> 24) & 0x1f) <= 0x18)
339 switch ((cmd >> 24) & 0x1f) {
343 switch ((cmd >> 16) & 0xff) {
345 return (cmd & 0x1f) + 2;
347 return (cmd & 0xf) + 2;
349 return (cmd & 0xffff) + 2;
353 return (cmd & 0xffff) + 1;
357 if ((cmd & (1 << 23)) == 0) /* inline vertices */
358 return (cmd & 0x1ffff) + 2;
359 else if (cmd & (1 << 17)) /* indirect random */
360 if ((cmd & 0xffff) == 0)
361 return 0; /* unknown length, too hard */
363 return (((cmd & 0xffff) + 1) / 2) + 1;
365 return 2; /* indirect sequential */
376 static int validate_cmd(int cmd)
378 int ret = do_validate_cmd(cmd);
380 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
385 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
388 drm_i915_private_t *dev_priv = dev->dev_private;
391 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
394 ret = BEGIN_LP_RING((dwords+1)&~1);
398 for (i = 0; i < dwords;) {
401 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
404 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
410 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
427 i915_emit_box(struct drm_device *dev,
428 struct drm_clip_rect *box,
431 struct drm_i915_private *dev_priv = dev->dev_private;
434 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
435 box->y2 <= 0 || box->x2 <= 0) {
436 DRM_ERROR("Bad box %d,%d..%d,%d\n",
437 box->x1, box->y1, box->x2, box->y2);
441 if (INTEL_INFO(dev)->gen >= 4) {
442 ret = BEGIN_LP_RING(4);
446 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
447 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
448 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
451 ret = BEGIN_LP_RING(6);
455 OUT_RING(GFX_OP_DRAWRECT_INFO);
457 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
458 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
467 /* XXX: Emitting the counter should really be moved to part of the IRQ
468 * emit. For now, do it in both places:
471 static void i915_emit_breadcrumb(struct drm_device *dev)
473 drm_i915_private_t *dev_priv = dev->dev_private;
475 dev_priv->dri1.counter++;
476 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
477 dev_priv->dri1.counter = 0;
478 if (dev_priv->sarea_priv)
479 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
481 if (BEGIN_LP_RING(4) == 0) {
482 OUT_RING(MI_STORE_DWORD_INDEX);
483 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
484 OUT_RING(dev_priv->dri1.counter);
490 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
491 drm_i915_cmdbuffer_t *cmd,
492 struct drm_clip_rect *cliprects,
495 int nbox = cmd->num_cliprects;
496 int i = 0, count, ret;
499 DRM_ERROR("alignment");
503 i915_kernel_lost_context(dev);
505 count = nbox ? nbox : 1;
507 for (i = 0; i < count; i++) {
509 ret = i915_emit_box(dev, &cliprects[i],
515 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
520 i915_emit_breadcrumb(dev);
524 static int i915_dispatch_batchbuffer(struct drm_device * dev,
525 drm_i915_batchbuffer_t * batch,
526 struct drm_clip_rect *cliprects)
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 int nbox = batch->num_cliprects;
532 if ((batch->start | batch->used) & 0x7) {
533 DRM_ERROR("alignment");
537 i915_kernel_lost_context(dev);
539 count = nbox ? nbox : 1;
540 for (i = 0; i < count; i++) {
542 ret = i915_emit_box(dev, &cliprects[i],
543 batch->DR1, batch->DR4);
548 if (!IS_I830(dev) && !IS_845G(dev)) {
549 ret = BEGIN_LP_RING(2);
553 if (INTEL_INFO(dev)->gen >= 4) {
554 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
555 OUT_RING(batch->start);
557 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
558 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
561 ret = BEGIN_LP_RING(4);
565 OUT_RING(MI_BATCH_BUFFER);
566 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
567 OUT_RING(batch->start + batch->used - 4);
574 if (IS_G4X(dev) || IS_GEN5(dev)) {
575 if (BEGIN_LP_RING(2) == 0) {
576 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
582 i915_emit_breadcrumb(dev);
586 static int i915_dispatch_flip(struct drm_device * dev)
588 drm_i915_private_t *dev_priv = dev->dev_private;
591 if (!dev_priv->sarea_priv)
594 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
596 dev_priv->dri1.current_page,
597 dev_priv->sarea_priv->pf_current_page);
599 i915_kernel_lost_context(dev);
601 ret = BEGIN_LP_RING(10);
605 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
608 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
610 if (dev_priv->dri1.current_page == 0) {
611 OUT_RING(dev_priv->dri1.back_offset);
612 dev_priv->dri1.current_page = 1;
614 OUT_RING(dev_priv->dri1.front_offset);
615 dev_priv->dri1.current_page = 0;
619 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
624 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
626 if (BEGIN_LP_RING(4) == 0) {
627 OUT_RING(MI_STORE_DWORD_INDEX);
628 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
629 OUT_RING(dev_priv->dri1.counter);
634 dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
638 static int i915_quiescent(struct drm_device *dev)
640 i915_kernel_lost_context(dev);
641 return intel_ring_idle(LP_RING(dev->dev_private));
645 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
649 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
652 ret = i915_quiescent(dev);
658 static int i915_batchbuffer(struct drm_device *dev, void *data,
659 struct drm_file *file_priv)
661 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
662 drm_i915_sarea_t *sarea_priv;
663 drm_i915_batchbuffer_t *batch = data;
664 struct drm_clip_rect *cliprects;
668 if (!dev_priv->dri1.allow_batchbuffer) {
669 DRM_ERROR("Batchbuffer ioctl disabled\n");
673 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
674 batch->start, batch->used, batch->num_cliprects);
676 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
678 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
679 if (batch->num_cliprects < 0)
681 if (batch->num_cliprects != 0) {
682 cliprects = kmalloc(batch->num_cliprects *
683 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
686 ret = -copyin(batch->cliprects, cliprects,
687 batch->num_cliprects * sizeof(struct drm_clip_rect));
696 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
699 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
701 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
704 drm_free(cliprects, DRM_MEM_DMA);
708 static int i915_cmdbuffer(struct drm_device *dev, void *data,
709 struct drm_file *file_priv)
711 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
712 drm_i915_sarea_t *sarea_priv;
713 drm_i915_cmdbuffer_t *cmdbuf = data;
714 struct drm_clip_rect *cliprects = NULL;
718 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
719 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
721 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
723 if (cmdbuf->num_cliprects < 0)
726 batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
728 ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
731 goto fail_batch_free;
734 if (cmdbuf->num_cliprects) {
735 cliprects = kmalloc(cmdbuf->num_cliprects *
736 sizeof(struct drm_clip_rect), DRM_MEM_DMA,
738 ret = -copyin(cmdbuf->cliprects, cliprects,
739 cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
748 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
751 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
755 sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
757 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
760 drm_free(cliprects, DRM_MEM_DMA);
762 drm_free(batch_data, DRM_MEM_DMA);
766 static int i915_emit_irq(struct drm_device * dev)
768 drm_i915_private_t *dev_priv = dev->dev_private;
770 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
773 i915_kernel_lost_context(dev);
775 DRM_DEBUG_DRIVER("\n");
777 dev_priv->dri1.counter++;
778 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
779 dev_priv->dri1.counter = 1;
780 if (dev_priv->sarea_priv)
781 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
783 if (BEGIN_LP_RING(4) == 0) {
784 OUT_RING(MI_STORE_DWORD_INDEX);
785 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
786 OUT_RING(dev_priv->dri1.counter);
787 OUT_RING(MI_USER_INTERRUPT);
791 return dev_priv->dri1.counter;
794 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
796 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
798 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
801 struct intel_ring_buffer *ring = LP_RING(dev_priv);
803 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
804 READ_BREADCRUMB(dev_priv));
807 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
808 if (master_priv->sarea_priv)
809 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
813 if (master_priv->sarea_priv)
814 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
816 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
817 if (dev_priv->sarea_priv) {
818 dev_priv->sarea_priv->last_dispatch =
819 READ_BREADCRUMB(dev_priv);
824 if (dev_priv->sarea_priv)
825 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
828 if (ring->irq_get(ring)) {
829 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
830 READ_BREADCRUMB(dev_priv) >= irq_nr);
832 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
836 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
837 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
843 /* Needs the lock as it touches the ring.
845 int i915_irq_emit(struct drm_device *dev, void *data,
846 struct drm_file *file_priv)
848 drm_i915_private_t *dev_priv = dev->dev_private;
849 drm_i915_irq_emit_t *emit = data;
852 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
853 DRM_ERROR("called with no initialization\n");
857 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
860 result = i915_emit_irq(dev);
863 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
864 DRM_ERROR("copy_to_user\n");
871 /* Doesn't need the hardware lock.
873 int i915_irq_wait(struct drm_device *dev, void *data,
874 struct drm_file *file_priv)
876 drm_i915_private_t *dev_priv = dev->dev_private;
877 drm_i915_irq_wait_t *irqwait = data;
880 DRM_ERROR("called with no initialization\n");
884 return i915_wait_irq(dev, irqwait->irq_seq);
887 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
888 struct drm_file *file_priv)
890 drm_i915_private_t *dev_priv = dev->dev_private;
891 drm_i915_vblank_pipe_t *pipe = data;
893 if (drm_core_check_feature(dev, DRIVER_MODESET))
897 DRM_ERROR("called with no initialization\n");
901 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
907 * Schedule buffer swap at given vertical blank.
909 static int i915_vblank_swap(struct drm_device *dev, void *data,
910 struct drm_file *file_priv)
912 /* The delayed swap mechanism was fundamentally racy, and has been
913 * removed. The model was that the client requested a delayed flip/swap
914 * from the kernel, then waited for vblank before continuing to perform
915 * rendering. The problem was that the kernel might wake the client
916 * up before it dispatched the vblank swap (since the lock has to be
917 * held while touching the ringbuffer), in which case the client would
918 * clear and start the next frame before the swap occurred, and
919 * flicker would occur in addition to likely missing the vblank.
921 * In the absence of this ioctl, userland falls back to a correct path
922 * of waiting for a vblank, then dispatching the swap on its own.
923 * Context switching to userland and back is plenty fast enough for
924 * meeting the requirements of vblank swapping.
929 static int i915_flip_bufs(struct drm_device *dev, void *data,
930 struct drm_file *file_priv)
934 DRM_DEBUG("%s\n", __func__);
936 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
939 ret = i915_dispatch_flip(dev);
945 static int i915_getparam(struct drm_device *dev, void *data,
946 struct drm_file *file_priv)
948 drm_i915_private_t *dev_priv = dev->dev_private;
949 drm_i915_getparam_t *param = data;
953 DRM_ERROR("called with no initialization\n");
957 switch (param->param) {
958 case I915_PARAM_IRQ_ACTIVE:
959 value = dev->irq_enabled ? 1 : 0;
961 case I915_PARAM_ALLOW_BATCHBUFFER:
962 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
964 case I915_PARAM_LAST_DISPATCH:
965 value = READ_BREADCRUMB(dev_priv);
967 case I915_PARAM_CHIPSET_ID:
968 value = dev->pci_device;
970 case I915_PARAM_HAS_GEM:
973 case I915_PARAM_NUM_FENCES_AVAIL:
974 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
976 case I915_PARAM_HAS_OVERLAY:
977 value = dev_priv->overlay ? 1 : 0;
979 case I915_PARAM_HAS_PAGEFLIPPING:
982 case I915_PARAM_HAS_EXECBUF2:
986 case I915_PARAM_HAS_BSD:
987 value = intel_ring_initialized(&dev_priv->ring[VCS]);
989 case I915_PARAM_HAS_BLT:
990 value = intel_ring_initialized(&dev_priv->ring[BCS]);
992 case I915_PARAM_HAS_RELAXED_FENCING:
995 case I915_PARAM_HAS_COHERENT_RINGS:
998 case I915_PARAM_HAS_EXEC_CONSTANTS:
999 value = INTEL_INFO(dev)->gen >= 4;
1001 case I915_PARAM_HAS_RELAXED_DELTA:
1004 case I915_PARAM_HAS_GEN7_SOL_RESET:
1007 case I915_PARAM_HAS_LLC:
1008 value = HAS_LLC(dev);
1010 case I915_PARAM_HAS_ALIASING_PPGTT:
1011 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1013 case I915_PARAM_HAS_PINNED_BATCHES:
1017 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1022 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1023 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1030 static int i915_setparam(struct drm_device *dev, void *data,
1031 struct drm_file *file_priv)
1033 drm_i915_private_t *dev_priv = dev->dev_private;
1034 drm_i915_setparam_t *param = data;
1037 DRM_ERROR("called with no initialization\n");
1041 switch (param->param) {
1042 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1044 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1046 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1047 dev_priv->dri1.allow_batchbuffer = param->value;
1049 case I915_SETPARAM_NUM_USED_FENCES:
1050 if (param->value > dev_priv->num_fence_regs ||
1053 /* Userspace can use first N regs */
1054 dev_priv->fence_reg_start = param->value;
1057 DRM_DEBUG("unknown parameter %d\n", param->param);
1064 static int i915_set_status_page(struct drm_device *dev, void *data,
1065 struct drm_file *file_priv)
1067 drm_i915_private_t *dev_priv = dev->dev_private;
1068 drm_i915_hws_addr_t *hws = data;
1069 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1071 if (!I915_NEED_GFX_HWS(dev))
1075 DRM_ERROR("called with no initialization\n");
1079 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1080 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1081 DRM_ERROR("tried to set status page when mode setting active\n");
1085 ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1086 hws->addr & (0x1ffff<<12);
1088 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1089 dev_priv->hws_map.size = 4*1024;
1090 dev_priv->hws_map.type = 0;
1091 dev_priv->hws_map.flags = 0;
1092 dev_priv->hws_map.mtrr = 0;
1094 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1095 if (dev_priv->hws_map.virtual == NULL) {
1096 i915_dma_cleanup(dev);
1097 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1098 DRM_ERROR("can not ioremap virtual address for"
1099 " G33 hw status page\n");
1102 ring->status_page.page_addr = dev_priv->hw_status_page =
1103 dev_priv->hws_map.virtual;
1105 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1106 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1107 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
1108 dev_priv->status_gfx_addr);
1109 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1113 static int i915_load_modeset_init(struct drm_device *dev)
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1118 ret = intel_parse_bios(dev);
1120 DRM_INFO("failed to find VBIOS tables\n");
1123 /* If we have > 1 VGA cards, then we need to arbitrate access
1124 * to the common VGA resources.
1126 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1127 * then we do not take part in VGA arbitration and the
1128 * vga_client_register() fails with -ENODEV.
1130 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1131 if (ret && ret != -ENODEV)
1134 intel_register_dsm_handler();
1136 ret = vga_switcheroo_register_client(dev->pdev,
1137 i915_switcheroo_set_state,
1139 i915_switcheroo_can_switch);
1141 goto cleanup_vga_client;
1143 /* Initialise stolen first so that we may reserve preallocated
1144 * objects for the BIOS to KMS transition.
1146 ret = i915_gem_init_stolen(dev);
1148 goto cleanup_vga_switcheroo;
1151 intel_modeset_init(dev);
1153 ret = i915_gem_init(dev);
1155 goto cleanup_gem_stolen;
1157 intel_modeset_gem_init(dev);
1159 ret = drm_irq_install(dev);
1163 /* Always safe in the mode setting case. */
1164 /* FIXME: do pre/post-mode set stuff in core KMS code */
1165 dev->vblank_disable_allowed = 1;
1167 ret = intel_fbdev_init(dev);
1171 drm_kms_helper_poll_init(dev);
1173 /* We're off and running w/KMS */
1174 dev_priv->mm.suspended = 0;
1179 drm_irq_uninstall(dev);
1182 i915_gem_cleanup_ringbuffer(dev);
1184 i915_gem_cleanup_aliasing_ppgtt(dev);
1187 i915_gem_cleanup_stolen(dev);
1188 cleanup_vga_switcheroo:
1189 vga_switcheroo_unregister_client(dev->pdev);
1191 vga_client_register(dev->pdev, NULL, NULL, NULL);
1197 static int i915_get_bridge_dev(struct drm_device *dev)
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1201 dev_priv->bridge_dev = pci_find_dbsf(0, 0, 0, 0);
1202 if (!dev_priv->bridge_dev) {
1203 DRM_ERROR("bridge device not found\n");
1209 #define MCHBAR_I915 0x44
1210 #define MCHBAR_I965 0x48
1211 #define MCHBAR_SIZE (4*4096)
1213 #define DEVEN_REG 0x54
1214 #define DEVEN_MCHBAR_EN (1 << 28)
1216 /* Allocate space for the MCH regs if needed, return nonzero on error */
1218 intel_alloc_mchbar_resource(struct drm_device *dev)
1220 drm_i915_private_t *dev_priv;
1223 u32 temp_lo, temp_hi;
1224 u64 mchbar_addr, temp;
1226 dev_priv = dev->dev_private;
1227 reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1229 if (INTEL_INFO(dev)->gen >= 4)
1230 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1233 temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1234 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1236 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1237 #ifdef XXX_CONFIG_PNP
1239 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1243 /* Get some space for it */
1244 vga = device_get_parent(dev->dev);
1245 dev_priv->mch_res_rid = 0x100;
1246 dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1247 dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1248 MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1249 if (dev_priv->mch_res == NULL) {
1250 DRM_ERROR("failed mchbar resource alloc\n");
1254 if (INTEL_INFO(dev)->gen >= 4) {
1255 temp = rman_get_start(dev_priv->mch_res);
1257 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1259 pci_write_config(dev_priv->bridge_dev, reg,
1260 rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1265 intel_setup_mchbar(struct drm_device *dev)
1267 drm_i915_private_t *dev_priv;
1272 dev_priv = dev->dev_private;
1273 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1275 dev_priv->mchbar_need_disable = false;
1277 if (IS_I915G(dev) || IS_I915GM(dev)) {
1278 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1279 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1281 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1285 /* If it's already enabled, don't have to do anything */
1287 DRM_DEBUG("mchbar already enabled\n");
1291 if (intel_alloc_mchbar_resource(dev))
1294 dev_priv->mchbar_need_disable = true;
1296 /* Space is allocated or reserved, so enable it. */
1297 if (IS_I915G(dev) || IS_I915GM(dev)) {
1298 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1299 temp | DEVEN_MCHBAR_EN, 4);
1301 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1302 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1307 intel_teardown_mchbar(struct drm_device *dev)
1309 drm_i915_private_t *dev_priv;
1314 dev_priv = dev->dev_private;
1315 mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1317 if (dev_priv->mchbar_need_disable) {
1318 if (IS_I915G(dev) || IS_I915GM(dev)) {
1319 temp = pci_read_config(dev_priv->bridge_dev,
1321 temp &= ~DEVEN_MCHBAR_EN;
1322 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1325 temp = pci_read_config(dev_priv->bridge_dev,
1328 pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1333 if (dev_priv->mch_res != NULL) {
1334 vga = device_get_parent(dev->dev);
1335 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1336 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1337 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1338 SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1339 dev_priv->mch_res = NULL;
1344 * i915_driver_load - setup chip and create an initial config
1346 * @flags: startup flags
1348 * The driver load routine has to do several things:
1349 * - drive output discovery via intel_modeset_init()
1350 * - initialize the memory manager
1351 * - allocate initial config memory
1352 * - setup the DRM framebuffer with the allocated memory
1354 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 unsigned long base, size;
1362 /* i915 has 4 more counters */
1364 dev->types[6] = _DRM_STAT_IRQ;
1365 dev->types[7] = _DRM_STAT_PRIMARY;
1366 dev->types[8] = _DRM_STAT_SECONDARY;
1367 dev->types[9] = _DRM_STAT_DMA;
1369 dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1371 if (dev_priv == NULL)
1374 dev->dev_private = (void *)dev_priv;
1375 dev_priv->dev = dev;
1376 dev_priv->info = i915_get_device_id(dev->pci_device);
1378 if (i915_get_bridge_dev(dev)) {
1379 drm_free(dev_priv, DRM_MEM_DRIVER);
1382 dev_priv->mm.gtt = intel_gtt_get();
1384 /* Add register map (needed for suspend/resume) */
1385 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1386 base = drm_get_resource_start(dev, mmio_bar);
1387 size = drm_get_resource_len(dev, mmio_bar);
1389 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1390 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1392 /* The i915 workqueue is primarily used for batched retirement of
1393 * requests (and thus managing bo) once the task has been completed
1394 * by the GPU. i915_gem_retire_requests() is called directly when we
1395 * need high-priority retirement, such as waiting for an explicit
1398 * It is also used for periodic low-priority events, such as
1399 * idle-timers and recording error state.
1401 * All tasks on the workqueue are expected to acquire the dev mutex
1402 * so there is no point in running more than one instance of the
1403 * workqueue at any time. Use an ordered one.
1405 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1406 if (dev_priv->wq == NULL) {
1407 DRM_ERROR("Failed to create our workqueue.\n");
1412 /* This must be called before any calls to HAS_PCH_* */
1413 intel_detect_pch(dev);
1415 intel_irq_init(dev);
1418 /* Try to make sure MCHBAR is enabled before poking at it */
1419 intel_setup_mchbar(dev);
1420 intel_setup_gmbus(dev);
1421 intel_opregion_setup(dev);
1423 intel_setup_bios(dev);
1427 /* On the 945G/GM, the chipset reports the MSI capability on the
1428 * integrated graphics even though the support isn't actually there
1429 * according to the published specs. It doesn't appear to function
1430 * correctly in testing on 945G.
1431 * This may be a side effect of MSI having been made available for PEG
1432 * and the registers being closely associated.
1434 * According to chipset errata, on the 965GM, MSI interrupts may
1435 * be lost or delayed, but we use them anyways to avoid
1436 * stuck interrupts on some machines.
1439 lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1440 lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1441 spin_init(&dev_priv->rps.lock);
1442 spin_init(&dev_priv->dpio_lock);
1444 lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1447 if (!I915_NEED_GFX_HWS(dev)) {
1448 ret = i915_init_phys_hws(dev);
1450 drm_rmmap(dev, dev_priv->mmio_map);
1451 drm_free(dev_priv, DRM_MEM_DRIVER);
1456 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1457 dev_priv->num_pipe = 3;
1458 else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1459 dev_priv->num_pipe = 2;
1461 dev_priv->num_pipe = 1;
1463 ret = drm_vblank_init(dev, dev_priv->num_pipe);
1465 goto out_gem_unload;
1467 /* Start out suspended */
1468 dev_priv->mm.suspended = 1;
1470 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1471 ret = i915_load_modeset_init(dev);
1473 DRM_ERROR("failed to init modeset\n");
1474 goto out_gem_unload;
1478 /* Must be done after probing outputs */
1479 intel_opregion_init(dev);
1481 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1482 (unsigned long) dev);
1485 intel_gpu_ips_init(dev_priv);
1490 intel_teardown_gmbus(dev);
1491 intel_teardown_mchbar(dev);
1492 destroy_workqueue(dev_priv->wq);
1497 int i915_driver_unload(struct drm_device *dev)
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1502 intel_gpu_ips_teardown();
1505 ret = i915_gpu_idle(dev);
1507 DRM_ERROR("failed to idle hardware: %d\n", ret);
1508 i915_gem_retire_requests(dev);
1511 /* Cancel the retire work handler, which should be idle now. */
1512 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1516 intel_teardown_mchbar(dev);
1518 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1519 intel_fbdev_fini(dev);
1520 intel_modeset_cleanup(dev);
1523 /* Free error state after interrupts are fully disabled. */
1524 del_timer_sync(&dev_priv->hangcheck_timer);
1525 cancel_work_sync(&dev_priv->error_work);
1526 i915_destroy_error_state(dev);
1528 intel_opregion_fini(dev);
1530 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1531 /* Flush any outstanding unpin_work. */
1532 flush_workqueue(dev_priv->wq);
1535 i915_gem_free_all_phys_object(dev);
1536 i915_gem_cleanup_ringbuffer(dev);
1538 i915_gem_cleanup_aliasing_ppgtt(dev);
1539 drm_mm_takedown(&dev_priv->mm.stolen);
1541 intel_cleanup_overlay(dev);
1543 if (!I915_NEED_GFX_HWS(dev))
1547 i915_gem_unload(dev);
1549 bus_generic_detach(dev->dev);
1550 drm_rmmap(dev, dev_priv->mmio_map);
1551 intel_teardown_gmbus(dev);
1553 destroy_workqueue(dev_priv->wq);
1555 drm_free(dev->dev_private, DRM_MEM_DRIVER);
1561 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1563 struct drm_i915_file_private *i915_file_priv;
1565 i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1568 spin_init(&i915_file_priv->mm.lock);
1569 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1570 file_priv->driver_priv = i915_file_priv;
1576 i915_driver_lastclose(struct drm_device * dev)
1578 drm_i915_private_t *dev_priv = dev->dev_private;
1580 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1584 drm_fb_helper_restore();
1585 vga_switcheroo_process_delayed_switch();
1589 i915_gem_lastclose(dev);
1590 i915_dma_cleanup(dev);
1593 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1596 i915_gem_release(dev, file_priv);
1599 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1601 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1603 spin_uninit(&i915_file_priv->mm.lock);
1604 drm_free(i915_file_priv, DRM_MEM_FILES);
1607 struct drm_ioctl_desc i915_ioctls[] = {
1608 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1609 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1610 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1611 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1612 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1613 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1614 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1615 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1616 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1617 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1618 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1619 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1620 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1621 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1622 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
1623 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1624 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1625 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1626 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1627 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1628 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1629 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1630 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1631 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1632 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1633 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1634 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1635 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1636 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1637 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1638 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1639 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1640 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1641 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1642 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1643 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1644 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1645 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1646 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1647 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1648 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1649 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1652 struct drm_driver i915_driver_info = {
1653 .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1654 DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1655 DRIVER_GEM /*| DRIVER_MODESET*/,
1657 .buf_priv_size = sizeof(drm_i915_private_t),
1658 .load = i915_driver_load,
1659 .open = i915_driver_open,
1660 .unload = i915_driver_unload,
1661 .preclose = i915_driver_preclose,
1662 .lastclose = i915_driver_lastclose,
1663 .postclose = i915_driver_postclose,
1664 .device_is_agp = i915_driver_device_is_agp,
1665 .gem_init_object = i915_gem_init_object,
1666 .gem_free_object = i915_gem_free_object,
1667 .gem_pager_ops = &i915_gem_pager_ops,
1668 .dumb_create = i915_gem_dumb_create,
1669 .dumb_map_offset = i915_gem_mmap_gtt,
1670 .dumb_destroy = i915_gem_dumb_destroy,
1672 .ioctls = i915_ioctls,
1673 .max_ioctl = DRM_ARRAY_SIZE(i915_ioctls),
1675 .name = DRIVER_NAME,
1676 .desc = DRIVER_DESC,
1677 .date = DRIVER_DATE,
1678 .major = DRIVER_MAJOR,
1679 .minor = DRIVER_MINOR,
1680 .patchlevel = DRIVER_PATCHLEVEL,
1684 * Determine if the device really is AGP or not.
1686 * All Intel graphics chipsets are treated as AGP, even if they are really
1689 * \param dev The device to be tested.
1692 * A value of 1 is always retured to indictate every i9x5 is AGP.
1694 int i915_driver_device_is_agp(struct drm_device * dev)