2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.33 2006/10/25 20:55:51 dillon Exp $
34 #include "opt_simos.h"
35 #include "opt_compat_oldpci.h"
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/module.h>
41 #include <sys/fcntl.h>
43 #include <sys/kernel.h>
44 #include <sys/queue.h>
45 #include <sys/types.h>
50 #include <vm/vm_extern.h>
54 #include <machine/smp.h>
56 #include <bus/pci/i386/pci_cfgreg.h>
59 #include <sys/pciio.h>
62 #include "pci_private.h"
66 devclass_t pci_devclass;
67 const char *pcib_owner;
69 static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
72 u_int32_t devid; /* Vendor/device of the card */
74 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
79 struct pci_quirk pci_quirks[] = {
81 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
83 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
84 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
85 /* As does the Serverworks OSB4 (the SMBus mapping register) */
86 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
91 /* map register information */
92 #define PCI_MAPMEM 0x01 /* memory map */
93 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
94 #define PCI_MAPPORT 0x04 /* port map */
96 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
97 u_int32_t pci_numdevs = 0;
98 static u_int32_t pci_generation = 0;
101 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
103 struct pci_devinfo *dinfo;
105 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
106 if ((dinfo->cfg.bus == bus) &&
107 (dinfo->cfg.slot == slot) &&
108 (dinfo->cfg.func == func)) {
109 return (dinfo->cfg.dev);
117 pci_find_device (u_int16_t vendor, u_int16_t device)
119 struct pci_devinfo *dinfo;
121 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
122 if ((dinfo->cfg.vendor == vendor) &&
123 (dinfo->cfg.device == device)) {
124 return (dinfo->cfg.dev);
131 /* return base address of memory or port map */
134 pci_mapbase(unsigned mapreg)
137 if ((mapreg & 0x01) == 0)
139 return (mapreg & ~mask);
142 /* return map type of memory or port map */
145 pci_maptype(unsigned mapreg)
147 static u_int8_t maptype[0x10] = {
148 PCI_MAPMEM, PCI_MAPPORT,
150 PCI_MAPMEM, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
153 PCI_MAPMEM|PCI_MAPMEMP, 0,
154 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
158 return maptype[mapreg & 0x0f];
161 /* return log2 of map size decoded for memory or port map */
164 pci_mapsize(unsigned testval)
168 testval = pci_mapbase(testval);
171 while ((testval & 1) == 0)
180 /* return log2 of address range supported by map register */
183 pci_maprange(unsigned mapreg)
186 switch (mapreg & 0x07) {
202 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
205 pci_fixancient(pcicfgregs *cfg)
207 if (cfg->hdrtype != 0)
210 /* PCI to PCI bridges use header type 1 */
211 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
215 /* read config data specific to header type 1 device (PCI to PCI bridge) */
218 pci_readppb(device_t pcib, int b, int s, int f)
222 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
226 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
227 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
229 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
231 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
233 PCIB_READ_CONFIG(pcib, b, s, f,
235 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIB_READ_CONFIG(pcib, b, s, f,
238 PCIR_IOLIMITL_1, 1));
240 p->membase = PCI_PPBMEMBASE (0,
241 PCIB_READ_CONFIG(pcib, b, s, f,
243 p->memlimit = PCI_PPBMEMLIMIT (0,
244 PCIB_READ_CONFIG(pcib, b, s, f,
245 PCIR_MEMLIMIT_1, 2));
247 p->pmembase = PCI_PPBMEMBASE (
248 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
249 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
251 p->pmemlimit = PCI_PPBMEMLIMIT (
252 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
254 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
259 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
262 pci_readpcb(device_t pcib, int b, int s, int f)
266 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
270 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
271 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
273 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
275 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
276 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
277 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
278 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
280 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
281 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
282 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
283 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
285 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
289 /* extract header type specific config data */
292 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
294 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
295 switch (cfg->hdrtype) {
297 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
298 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
299 cfg->nummaps = PCI_MAXMAPS_0;
302 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
303 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
304 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
305 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
306 cfg->nummaps = PCI_MAXMAPS_1;
307 cfg->hdrspec = pci_readppb(pcib, b, s, f);
310 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
311 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
312 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
313 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
314 cfg->nummaps = PCI_MAXMAPS_2;
315 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
321 /* read configuration header into pcicfgrect structure */
324 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
326 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
328 pcicfgregs *cfg = NULL;
329 struct pci_devinfo *devlist_entry;
330 struct devlist *devlist_head;
332 devlist_head = &pci_devq;
334 devlist_entry = NULL;
336 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
338 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
339 if (devlist_entry == NULL)
342 cfg = &devlist_entry->cfg;
347 cfg->vendor = REG(PCIR_VENDOR, 2);
348 cfg->device = REG(PCIR_DEVICE, 2);
349 cfg->cmdreg = REG(PCIR_COMMAND, 2);
350 cfg->statreg = REG(PCIR_STATUS, 2);
351 cfg->baseclass = REG(PCIR_CLASS, 1);
352 cfg->subclass = REG(PCIR_SUBCLASS, 1);
353 cfg->progif = REG(PCIR_PROGIF, 1);
354 cfg->revid = REG(PCIR_REVID, 1);
355 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
356 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
357 cfg->lattimer = REG(PCIR_LATTIMER, 1);
358 cfg->intpin = REG(PCIR_INTPIN, 1);
359 cfg->intline = REG(PCIR_INTLINE, 1);
363 * If using the APIC the intpin is probably wrong, since it
364 * is often setup by the BIOS with the PIC in mind.
366 if (cfg->intpin != 0) {
369 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
371 /* PCI specific entry found in MP table */
372 if (airq != cfg->intline) {
373 undirect_pci_irq(cfg->intline);
378 * PCI interrupts might be redirected to the
379 * ISA bus according to some MP tables. Use the
380 * same methods as used by the ISA devices
381 * devices to find the proper IOAPIC int pin.
383 airq = isa_apic_irq(cfg->intline);
384 if ((airq >= 0) && (airq != cfg->intline)) {
385 /* XXX: undirect_pci_irq() ? */
386 undirect_isa_irq(cfg->intline);
393 cfg->mingnt = REG(PCIR_MINGNT, 1);
394 cfg->maxlat = REG(PCIR_MAXLAT, 1);
396 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
397 cfg->hdrtype &= ~PCIM_MFDEV;
400 pci_hdrtypedata(pcib, b, s, f, cfg);
402 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
403 pci_read_extcap(pcib, cfg);
405 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
407 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
408 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
409 devlist_entry->conf.pc_sel.pc_func = cfg->func;
410 devlist_entry->conf.pc_hdr = cfg->hdrtype;
412 devlist_entry->conf.pc_subvendor = cfg->subvendor;
413 devlist_entry->conf.pc_subdevice = cfg->subdevice;
414 devlist_entry->conf.pc_vendor = cfg->vendor;
415 devlist_entry->conf.pc_device = cfg->device;
417 devlist_entry->conf.pc_class = cfg->baseclass;
418 devlist_entry->conf.pc_subclass = cfg->subclass;
419 devlist_entry->conf.pc_progif = cfg->progif;
420 devlist_entry->conf.pc_revid = cfg->revid;
425 return (devlist_entry);
430 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
432 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
433 int ptr, nextptr, ptrptr;
435 switch (cfg->hdrtype) {
443 return; /* no extended capabilities support */
445 nextptr = REG(ptrptr, 1); /* sanity check? */
448 * Read capability entries.
450 while (nextptr != 0) {
453 printf("illegal PCI extended capability offset %d\n",
457 /* Find the next entry */
459 nextptr = REG(ptr + 1, 1);
461 /* Process this entry */
462 switch (REG(ptr, 1)) {
463 case 0x01: /* PCI power management */
464 if (cfg->pp_cap == 0) {
465 cfg->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
466 cfg->pp_status = ptr + PCIR_POWER_STATUS;
467 cfg->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
468 if ((nextptr - ptr) > PCIR_POWER_DATA)
469 cfg->pp_data = ptr + PCIR_POWER_DATA;
479 /* free pcicfgregs structure and all depending data structures */
482 pci_freecfg(struct pci_devinfo *dinfo)
484 struct devlist *devlist_head;
486 devlist_head = &pci_devq;
488 if (dinfo->cfg.hdrspec != NULL)
489 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
490 /* XXX this hasn't been tested */
491 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
492 kfree(dinfo, M_DEVBUF);
494 /* increment the generation count */
497 /* we're losing one device */
504 * PCI power manangement
507 pci_set_powerstate_method(device_t dev, device_t child, int state)
509 struct pci_devinfo *dinfo = device_get_ivars(child);
510 pcicfgregs *cfg = &dinfo->cfg;
514 if (cfg->pp_cap != 0) {
515 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2) & ~PCIM_PSTAT_DMASK;
518 case PCI_POWERSTATE_D0:
519 status |= PCIM_PSTAT_D0;
521 case PCI_POWERSTATE_D1:
522 if (cfg->pp_cap & PCIM_PCAP_D1SUPP) {
523 status |= PCIM_PSTAT_D1;
528 case PCI_POWERSTATE_D2:
529 if (cfg->pp_cap & PCIM_PCAP_D2SUPP) {
530 status |= PCIM_PSTAT_D2;
535 case PCI_POWERSTATE_D3:
536 status |= PCIM_PSTAT_D3;
542 PCI_WRITE_CONFIG(dev, child, cfg->pp_status, status, 2);
550 pci_get_powerstate_method(device_t dev, device_t child)
552 struct pci_devinfo *dinfo = device_get_ivars(child);
553 pcicfgregs *cfg = &dinfo->cfg;
557 if (cfg->pp_cap != 0) {
558 status = PCI_READ_CONFIG(dev, child, cfg->pp_status, 2);
559 switch (status & PCIM_PSTAT_DMASK) {
561 result = PCI_POWERSTATE_D0;
564 result = PCI_POWERSTATE_D1;
567 result = PCI_POWERSTATE_D2;
570 result = PCI_POWERSTATE_D3;
573 result = PCI_POWERSTATE_UNKNOWN;
577 /* No support, device is always at D0 */
578 result = PCI_POWERSTATE_D0;
584 * Some convenience functions for PCI device drivers.
588 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
592 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
594 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
598 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
602 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
604 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
608 pci_enable_busmaster_method(device_t dev, device_t child)
610 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
615 pci_disable_busmaster_method(device_t dev, device_t child)
617 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
622 pci_enable_io_method(device_t dev, device_t child, int space)
633 bit = PCIM_CMD_PORTEN;
637 bit = PCIM_CMD_MEMEN;
643 pci_set_command_bit(dev, child, bit);
644 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
647 device_printf(child, "failed to enable %s mapping!\n", error);
652 pci_disable_io_method(device_t dev, device_t child, int space)
663 bit = PCIM_CMD_PORTEN;
667 bit = PCIM_CMD_MEMEN;
673 pci_clear_command_bit(dev, child, bit);
674 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
676 device_printf(child, "failed to disable %s mapping!\n", error);
683 * This is the user interface to PCI configuration space.
687 pci_open(struct dev_open_args *ap)
689 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
696 pci_close(struct dev_close_args *ap)
702 * Match a single pci_conf structure against an array of pci_match_conf
703 * structures. The first argument, 'matches', is an array of num_matches
704 * pci_match_conf structures. match_buf is a pointer to the pci_conf
705 * structure that will be compared to every entry in the matches array.
706 * This function returns 1 on failure, 0 on success.
709 pci_conf_match(struct pci_match_conf *matches, int num_matches,
710 struct pci_conf *match_buf)
714 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
717 for (i = 0; i < num_matches; i++) {
719 * I'm not sure why someone would do this...but...
721 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
725 * Look at each of the match flags. If it's set, do the
726 * comparison. If the comparison fails, we don't have a
727 * match, go on to the next item if there is one.
729 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
730 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
733 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
734 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
737 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
738 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
741 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
742 && (match_buf->pc_vendor != matches[i].pc_vendor))
745 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
746 && (match_buf->pc_device != matches[i].pc_device))
749 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
750 && (match_buf->pc_class != matches[i].pc_class))
753 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
754 && (match_buf->pd_unit != matches[i].pd_unit))
757 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
758 && (strncmp(matches[i].pd_name, match_buf->pd_name,
759 sizeof(match_buf->pd_name)) != 0))
769 * Locate the parent of a PCI device by scanning the PCI devlist
770 * and return the entry for the parent.
771 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
772 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
776 pci_devlist_get_parent(pcicfgregs *cfg)
778 struct devlist *devlist_head;
779 struct pci_devinfo *dinfo;
780 pcicfgregs *bridge_cfg;
783 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
785 /* If the device is on PCI bus 0, look for the host */
787 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
788 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
789 bridge_cfg = &dinfo->cfg;
790 if (bridge_cfg->baseclass == PCIC_BRIDGE
791 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
792 && bridge_cfg->bus == cfg->bus) {
798 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
800 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
801 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
802 bridge_cfg = &dinfo->cfg;
803 if (bridge_cfg->baseclass == PCIC_BRIDGE
804 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
805 && bridge_cfg->secondarybus == cfg->bus) {
815 pci_ioctl(struct dev_ioctl_args *ap)
822 if (!(ap->a_fflag & FWRITE))
828 struct pci_devinfo *dinfo;
829 struct pci_conf_io *cio;
830 struct devlist *devlist_head;
831 struct pci_match_conf *pattern_buf;
836 cio = (struct pci_conf_io *)ap->a_data;
842 * Hopefully the user won't pass in a null pointer, but it
843 * can't hurt to check.
851 * If the user specified an offset into the device list,
852 * but the list has changed since they last called this
853 * ioctl, tell them that the list has changed. They will
854 * have to get the list from the beginning.
856 if ((cio->offset != 0)
857 && (cio->generation != pci_generation)){
858 cio->num_matches = 0;
859 cio->status = PCI_GETCONF_LIST_CHANGED;
865 * Check to see whether the user has asked for an offset
866 * past the end of our list.
868 if (cio->offset >= pci_numdevs) {
869 cio->num_matches = 0;
870 cio->status = PCI_GETCONF_LAST_DEVICE;
875 /* get the head of the device queue */
876 devlist_head = &pci_devq;
879 * Determine how much room we have for pci_conf structures.
880 * Round the user's buffer size down to the nearest
881 * multiple of sizeof(struct pci_conf) in case the user
882 * didn't specify a multiple of that size.
884 iolen = min(cio->match_buf_len -
885 (cio->match_buf_len % sizeof(struct pci_conf)),
886 pci_numdevs * sizeof(struct pci_conf));
889 * Since we know that iolen is a multiple of the size of
890 * the pciconf union, it's okay to do this.
892 ionum = iolen / sizeof(struct pci_conf);
895 * If this test is true, the user wants the pci_conf
896 * structures returned to match the supplied entries.
898 if ((cio->num_patterns > 0)
899 && (cio->pat_buf_len > 0)) {
901 * pat_buf_len needs to be:
902 * num_patterns * sizeof(struct pci_match_conf)
903 * While it is certainly possible the user just
904 * allocated a large buffer, but set the number of
905 * matches correctly, it is far more likely that
906 * their kernel doesn't match the userland utility
907 * they're using. It's also possible that the user
908 * forgot to initialize some variables. Yes, this
909 * may be overly picky, but I hazard to guess that
910 * it's far more likely to just catch folks that
911 * updated their kernel but not their userland.
913 if ((cio->num_patterns *
914 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
915 /* The user made a mistake, return an error*/
916 cio->status = PCI_GETCONF_ERROR;
917 printf("pci_ioctl: pat_buf_len %d != "
918 "num_patterns (%d) * sizeof(struct "
919 "pci_match_conf) (%d)\npci_ioctl: "
920 "pat_buf_len should be = %d\n",
921 cio->pat_buf_len, cio->num_patterns,
922 (int)sizeof(struct pci_match_conf),
923 (int)sizeof(struct pci_match_conf) *
925 printf("pci_ioctl: do your headers match your "
927 cio->num_matches = 0;
933 * Check the user's buffer to make sure it's readable.
935 if (!useracc((caddr_t)cio->patterns,
936 cio->pat_buf_len, VM_PROT_READ)) {
937 printf("pci_ioctl: pattern buffer %p, "
938 "length %u isn't user accessible for"
939 " READ\n", cio->patterns,
945 * Allocate a buffer to hold the patterns.
947 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
949 error = copyin(cio->patterns, pattern_buf,
953 num_patterns = cio->num_patterns;
955 } else if ((cio->num_patterns > 0)
956 || (cio->pat_buf_len > 0)) {
958 * The user made a mistake, spit out an error.
960 cio->status = PCI_GETCONF_ERROR;
961 cio->num_matches = 0;
962 printf("pci_ioctl: invalid GETCONF arguments\n");
969 * Make sure we can write to the match buffer.
971 if (!useracc((caddr_t)cio->matches,
972 cio->match_buf_len, VM_PROT_WRITE)) {
973 printf("pci_ioctl: match buffer %p, length %u "
974 "isn't user accessible for WRITE\n",
975 cio->matches, cio->match_buf_len);
981 * Go through the list of devices and copy out the devices
982 * that match the user's criteria.
984 for (cio->num_matches = 0, error = 0, i = 0,
985 dinfo = STAILQ_FIRST(devlist_head);
986 (dinfo != NULL) && (cio->num_matches < ionum)
987 && (error == 0) && (i < pci_numdevs);
988 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
993 /* Populate pd_name and pd_unit */
995 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
996 name = device_get_name(dinfo->cfg.dev);
998 strncpy(dinfo->conf.pd_name, name,
999 sizeof(dinfo->conf.pd_name));
1000 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1001 dinfo->conf.pd_unit =
1002 device_get_unit(dinfo->cfg.dev);
1005 if ((pattern_buf == NULL) ||
1006 (pci_conf_match(pattern_buf, num_patterns,
1007 &dinfo->conf) == 0)) {
1010 * If we've filled up the user's buffer,
1011 * break out at this point. Since we've
1012 * got a match here, we'll pick right back
1013 * up at the matching entry. We can also
1014 * tell the user that there are more matches
1017 if (cio->num_matches >= ionum)
1020 error = copyout(&dinfo->conf,
1021 &cio->matches[cio->num_matches],
1022 sizeof(struct pci_conf));
1028 * Set the pointer into the list, so if the user is getting
1029 * n records at a time, where n < pci_numdevs,
1034 * Set the generation, the user will need this if they make
1035 * another ioctl call with offset != 0.
1037 cio->generation = pci_generation;
1040 * If this is the last device, inform the user so he won't
1041 * bother asking for more devices. If dinfo isn't NULL, we
1042 * know that there are more matches in the list because of
1043 * the way the traversal is done.
1046 cio->status = PCI_GETCONF_LAST_DEVICE;
1048 cio->status = PCI_GETCONF_MORE_DEVS;
1050 if (pattern_buf != NULL)
1051 kfree(pattern_buf, M_TEMP);
1056 io = (struct pci_io *)ap->a_data;
1057 switch(io->pi_width) {
1062 * Assume that the user-level bus number is
1063 * actually the pciN instance number. We map
1064 * from that to the real pcib+bus combination.
1066 pci = devclass_get_device(pci_devclass,
1070 * pci is the pci device and may contain
1071 * several children (for each function code).
1072 * The governing pci bus is the parent to
1077 pcib = device_get_parent(pci);
1078 b = pcib_get_bus(pcib);
1080 PCIB_READ_CONFIG(pcib,
1098 io = (struct pci_io *)ap->a_data;
1099 switch(io->pi_width) {
1104 * Assume that the user-level bus number is
1105 * actually the pciN instance number. We map
1106 * from that to the real pcib+bus combination.
1108 pci = devclass_get_device(pci_devclass,
1112 * pci is the pci device and may contain
1113 * several children (for each function code).
1114 * The governing pci bus is the parent to
1119 pcib = device_get_parent(pci);
1120 b = pcib_get_bus(pcib);
1121 PCIB_WRITE_CONFIG(pcib,
1149 static struct dev_ops pcic_ops = {
1150 { "pci", PCI_CDEV, 0 },
1152 .d_close = pci_close,
1153 .d_ioctl = pci_ioctl,
1159 * New style pci driver. Parent device is either a pci-host-bridge or a
1160 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1163 pci_class_to_string(int baseclass)
1180 case PCIC_MULTIMEDIA:
1181 name = "MULTIMEDIA";
1189 case PCIC_SIMPLECOMM:
1190 name = "SIMPLECOMM";
1192 case PCIC_BASEPERIPH:
1193 name = "BASEPERIPH";
1201 case PCIC_PROCESSOR:
1204 case PCIC_SERIALBUS:
1213 case PCIC_SATELLITE:
1233 pci_print_verbose(struct pci_devinfo *dinfo)
1236 pcicfgregs *cfg = &dinfo->cfg;
1238 printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1239 cfg->vendor, cfg->device, cfg->revid);
1240 printf("\tbus=%d, slot=%d, func=%d\n",
1241 cfg->bus, cfg->slot, cfg->func);
1242 printf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1243 pci_class_to_string(cfg->baseclass),
1244 cfg->baseclass, cfg->subclass, cfg->progif,
1245 cfg->hdrtype, cfg->mfdev);
1246 printf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1247 cfg->subordinatebus, cfg->secondarybus);
1249 printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1250 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1251 printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1252 cfg->lattimer, cfg->lattimer * 30,
1253 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1254 #endif /* PCI_DEBUG */
1255 if (cfg->intpin > 0)
1256 printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1261 pci_porten(device_t pcib, int b, int s, int f)
1263 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1264 & PCIM_CMD_PORTEN) != 0;
1268 pci_memen(device_t pcib, int b, int s, int f)
1270 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1271 & PCIM_CMD_MEMEN) != 0;
1275 * Add a resource based on a pci map register. Return 1 if the map
1276 * register is a 32bit map register or 2 if it is a 64bit register.
1279 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1280 struct resource_list *rl)
1289 #ifdef PCI_ENABLE_IO_MODES
1294 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1296 if (map == 0 || map == 0xffffffff)
1297 return 1; /* skip invalid entry */
1299 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1300 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1301 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1303 base = pci_mapbase(map);
1304 if (pci_maptype(map) & PCI_MAPMEM)
1305 type = SYS_RES_MEMORY;
1307 type = SYS_RES_IOPORT;
1308 ln2size = pci_mapsize(testval);
1309 ln2range = pci_maprange(testval);
1310 if (ln2range == 64) {
1311 /* Read the other half of a 64bit map register */
1312 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1316 * This code theoretically does the right thing, but has
1317 * undesirable side effects in some cases where
1318 * peripherals respond oddly to having these bits
1319 * enabled. Leave them alone by default.
1321 #ifdef PCI_ENABLE_IO_MODES
1322 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1323 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1324 cmd |= PCIM_CMD_PORTEN;
1325 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1327 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1328 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1329 cmd |= PCIM_CMD_MEMEN;
1330 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1333 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1335 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1339 resource_list_add(rl, type, reg,
1340 base, base + (1 << ln2size) - 1,
1344 printf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1345 reg, pci_maptype(base), ln2range,
1346 (unsigned int) base, ln2size);
1349 return (ln2range == 64) ? 2 : 1;
1353 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1355 struct pci_devinfo *dinfo = device_get_ivars(dev);
1356 pcicfgregs *cfg = &dinfo->cfg;
1357 struct resource_list *rl = &dinfo->resources;
1358 struct pci_quirk *q;
1360 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1367 for (i = 0; i < cfg->nummaps;) {
1368 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1371 for (q = &pci_quirks[0]; q->devid; q++) {
1372 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1373 && q->type == PCI_QUIRK_MAP_REG)
1374 pci_add_map(pcib, b, s, f, q->arg1, rl);
1377 if (cfg->intpin > 0 && cfg->intline != 255)
1378 resource_list_add(rl, SYS_RES_IRQ, 0,
1379 cfg->intline, cfg->intline, 1);
1383 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1385 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1386 device_t pcib = device_get_parent(dev);
1387 struct pci_devinfo *dinfo;
1389 int s, f, pcifunchigh;
1392 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1394 maxslots = PCIB_MAXSLOTS(pcib);
1396 for (s = 0; s <= maxslots; s++) {
1399 hdrtype = REG(PCIR_HDRTYPE, 1);
1400 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1402 if (hdrtype & PCIM_MFDEV)
1403 pcifunchigh = PCI_FUNCMAX;
1404 for (f = 0; f <= pcifunchigh; f++) {
1405 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1406 if (dinfo != NULL) {
1407 pci_add_child(dev, dinfo);
1415 * The actual PCI child that we add has a NULL driver whos parent
1416 * device will be "pci". The child contains the ivars, not the parent.
1419 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1423 pcib = device_get_parent(bus);
1424 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1425 device_set_ivars(dinfo->cfg.dev, dinfo);
1426 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1427 pci_print_verbose(dinfo);
1431 * Probe the PCI bus. Note: probe code is not supposed to add children
1435 pci_probe(device_t dev)
1437 device_set_desc(dev, "PCI bus");
1439 /* Allow other subclasses to override this driver */
1444 pci_attach(device_t dev)
1447 int lunit = device_get_unit(dev);
1449 dev_ops_add(&pcic_ops, -1, lunit);
1450 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1453 * Since there can be multiple independantly numbered PCI
1454 * busses on some large alpha systems, we can't use the unit
1455 * number to decide what bus we are probing. We ask the parent
1456 * pcib what our bus number is.
1458 * pcib_get_bus() must act on the pci bus device, not on the pci
1459 * device, because it uses badly hacked nexus-based ivars to
1460 * store and retrieve the physical bus number. XXX
1462 busno = pcib_get_bus(device_get_parent(dev));
1464 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
1466 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1468 return (bus_generic_attach(dev));
1472 pci_print_resources(struct resource_list *rl, const char *name, int type,
1475 struct resource_list_entry *rle;
1476 int printed, retval;
1480 /* Yes, this is kinda cheating */
1481 SLIST_FOREACH(rle, rl, link) {
1482 if (rle->type == type) {
1484 retval += printf(" %s ", name);
1485 else if (printed > 0)
1486 retval += printf(",");
1488 retval += printf(format, rle->start);
1489 if (rle->count > 1) {
1490 retval += printf("-");
1491 retval += printf(format, rle->start +
1500 pci_print_child(device_t dev, device_t child)
1502 struct pci_devinfo *dinfo;
1503 struct resource_list *rl;
1507 dinfo = device_get_ivars(child);
1509 rl = &dinfo->resources;
1511 retval += bus_print_child_header(dev, child);
1513 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1514 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1515 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1516 if (device_get_flags(dev))
1517 retval += printf(" flags %#x", device_get_flags(dev));
1519 retval += printf(" at device %d.%d", pci_get_slot(child),
1520 pci_get_function(child));
1522 retval += bus_print_child_footer(dev, child);
1528 pci_probe_nomatch(device_t dev, device_t child)
1530 struct pci_devinfo *dinfo;
1536 dinfo = device_get_ivars(child);
1538 desc = pci_ata_match(child);
1539 if (!desc) desc = pci_usb_match(child);
1540 if (!desc) desc = pci_vga_match(child);
1541 if (!desc) desc = pci_chip_match(child);
1543 desc = "unknown card";
1546 device_printf(dev, "<%s>", desc);
1547 if (bootverbose || unknown) {
1548 printf(" (vendor=0x%04x, dev=0x%04x)",
1553 pci_get_slot(child),
1554 pci_get_function(child));
1555 if (cfg->intpin > 0 && cfg->intline != 255) {
1556 printf(" irq %d", cfg->intline);
1564 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1566 struct pci_devinfo *dinfo;
1569 dinfo = device_get_ivars(child);
1573 case PCI_IVAR_SUBVENDOR:
1574 *result = cfg->subvendor;
1576 case PCI_IVAR_SUBDEVICE:
1577 *result = cfg->subdevice;
1579 case PCI_IVAR_VENDOR:
1580 *result = cfg->vendor;
1582 case PCI_IVAR_DEVICE:
1583 *result = cfg->device;
1585 case PCI_IVAR_DEVID:
1586 *result = (cfg->device << 16) | cfg->vendor;
1588 case PCI_IVAR_CLASS:
1589 *result = cfg->baseclass;
1591 case PCI_IVAR_SUBCLASS:
1592 *result = cfg->subclass;
1594 case PCI_IVAR_PROGIF:
1595 *result = cfg->progif;
1597 case PCI_IVAR_REVID:
1598 *result = cfg->revid;
1600 case PCI_IVAR_INTPIN:
1601 *result = cfg->intpin;
1604 *result = cfg->intline;
1610 *result = cfg->slot;
1612 case PCI_IVAR_FUNCTION:
1613 *result = cfg->func;
1615 case PCI_IVAR_SECONDARYBUS:
1616 *result = cfg->secondarybus;
1618 case PCI_IVAR_SUBORDINATEBUS:
1619 *result = cfg->subordinatebus;
1621 case PCI_IVAR_ETHADDR:
1623 * The generic accessor doesn't deal with failure, so
1624 * we set the return value, then return an error.
1635 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1637 struct pci_devinfo *dinfo;
1640 dinfo = device_get_ivars(child);
1644 case PCI_IVAR_SUBVENDOR:
1645 case PCI_IVAR_SUBDEVICE:
1646 case PCI_IVAR_VENDOR:
1647 case PCI_IVAR_DEVICE:
1648 case PCI_IVAR_DEVID:
1649 case PCI_IVAR_CLASS:
1650 case PCI_IVAR_SUBCLASS:
1651 case PCI_IVAR_PROGIF:
1652 case PCI_IVAR_REVID:
1653 case PCI_IVAR_INTPIN:
1657 case PCI_IVAR_FUNCTION:
1658 case PCI_IVAR_ETHADDR:
1659 return EINVAL; /* disallow for now */
1661 case PCI_IVAR_SECONDARYBUS:
1662 cfg->secondarybus = value;
1664 case PCI_IVAR_SUBORDINATEBUS:
1665 cfg->subordinatebus = value;
1674 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1675 u_long start, u_long end, u_long count, u_int flags)
1677 struct pci_devinfo *dinfo = device_get_ivars(child);
1678 struct resource_list *rl = &dinfo->resources;
1679 pcicfgregs *cfg = &dinfo->cfg;
1682 * Perform lazy resource allocation
1684 * XXX add support here for SYS_RES_IOPORT and SYS_RES_MEMORY
1686 if (device_get_parent(child) == dev) {
1691 * If device doesn't have an interrupt routed, and is
1692 * deserving of an interrupt, try to assign it one.
1694 if ((cfg->intline == 255 || cfg->intline == 0) &&
1695 (cfg->intpin != 0) &&
1696 (start == 0) && (end == ~0UL)) {
1697 cfg->intline = PCIB_ROUTE_INTERRUPT(
1698 device_get_parent(dev), child,
1700 if (cfg->intline != 255) {
1701 pci_write_config(child, PCIR_INTLINE,
1703 resource_list_add(rl, SYS_RES_IRQ, 0,
1704 cfg->intline, cfg->intline, 1);
1709 case SYS_RES_IOPORT:
1710 case SYS_RES_MEMORY:
1711 if (*rid < PCIR_BAR(cfg->nummaps)) {
1713 * Enable the I/O mode. We should
1714 * also be assigning resources too
1715 * when none are present. The
1716 * resource_list_alloc kind of sorta does
1719 if (PCI_ENABLE_IO(dev, child, type))
1725 return resource_list_alloc(rl, dev, child, type, rid,
1726 start, end, count, flags);
1730 pci_release_resource(device_t dev, device_t child, int type, int rid,
1733 struct pci_devinfo *dinfo = device_get_ivars(child);
1734 struct resource_list *rl = &dinfo->resources;
1736 return resource_list_release(rl, dev, child, type, rid, r);
1740 pci_set_resource(device_t dev, device_t child, int type, int rid,
1741 u_long start, u_long count)
1743 struct pci_devinfo *dinfo = device_get_ivars(child);
1744 struct resource_list *rl = &dinfo->resources;
1746 resource_list_add(rl, type, rid, start, start + count - 1, count);
1751 pci_get_resource(device_t dev, device_t child, int type, int rid,
1752 u_long *startp, u_long *countp)
1754 struct pci_devinfo *dinfo = device_get_ivars(child);
1755 struct resource_list *rl = &dinfo->resources;
1756 struct resource_list_entry *rle;
1758 rle = resource_list_find(rl, type, rid);
1763 *startp = rle->start;
1765 *countp = rle->count;
1771 pci_delete_resource(device_t dev, device_t child, int type, int rid)
1773 printf("pci_delete_resource: PCI resources can not be deleted\n");
1776 struct resource_list *
1777 pci_get_resource_list (device_t dev, device_t child)
1779 struct pci_devinfo * dinfo = device_get_ivars(child);
1780 struct resource_list * rl = &dinfo->resources;
1789 pci_read_config_method(device_t dev, device_t child, int reg, int width)
1791 struct pci_devinfo *dinfo = device_get_ivars(child);
1792 pcicfgregs *cfg = &dinfo->cfg;
1794 return PCIB_READ_CONFIG(device_get_parent(dev),
1795 cfg->bus, cfg->slot, cfg->func,
1800 pci_write_config_method(device_t dev, device_t child, int reg,
1801 u_int32_t val, int width)
1803 struct pci_devinfo *dinfo = device_get_ivars(child);
1804 pcicfgregs *cfg = &dinfo->cfg;
1806 PCIB_WRITE_CONFIG(device_get_parent(dev),
1807 cfg->bus, cfg->slot, cfg->func,
1812 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
1815 struct pci_devinfo *dinfo;
1817 dinfo = device_get_ivars(child);
1818 snprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
1819 pci_get_function(child));
1824 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
1827 struct pci_devinfo *dinfo;
1830 dinfo = device_get_ivars(child);
1832 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
1833 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
1834 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
1840 pci_assign_interrupt_method(device_t dev, device_t child)
1842 struct pci_devinfo *dinfo = device_get_ivars(child);
1843 pcicfgregs *cfg = &dinfo->cfg;
1845 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
1850 pci_modevent(module_t mod, int what, void *arg)
1854 STAILQ_INIT(&pci_devq);
1864 pci_resume(device_t dev)
1870 struct pci_devinfo *dinfo;
1873 device_get_children(dev, &children, &numdevs);
1875 for (i = 0; i < numdevs; i++) {
1876 child = children[i];
1878 dinfo = device_get_ivars(child);
1880 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
1881 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
1882 if (PCI_INTERRUPT_VALID(cfg->intline)) {
1883 pci_write_config(child, PCIR_INTLINE,
1889 kfree(children, M_TEMP);
1891 return (bus_generic_resume(dev));
1894 static device_method_t pci_methods[] = {
1895 /* Device interface */
1896 DEVMETHOD(device_probe, pci_probe),
1897 DEVMETHOD(device_attach, pci_attach),
1898 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1899 DEVMETHOD(device_suspend, bus_generic_suspend),
1900 DEVMETHOD(device_resume, pci_resume),
1903 DEVMETHOD(bus_print_child, pci_print_child),
1904 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
1905 DEVMETHOD(bus_read_ivar, pci_read_ivar),
1906 DEVMETHOD(bus_write_ivar, pci_write_ivar),
1907 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
1908 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
1909 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
1911 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
1912 DEVMETHOD(bus_set_resource, pci_set_resource),
1913 DEVMETHOD(bus_get_resource, pci_get_resource),
1914 DEVMETHOD(bus_delete_resource, pci_delete_resource),
1915 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
1916 DEVMETHOD(bus_release_resource, pci_release_resource),
1917 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
1918 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
1919 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
1920 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
1923 DEVMETHOD(pci_read_config, pci_read_config_method),
1924 DEVMETHOD(pci_write_config, pci_write_config_method),
1925 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
1926 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
1927 DEVMETHOD(pci_enable_io, pci_enable_io_method),
1928 DEVMETHOD(pci_disable_io, pci_disable_io_method),
1929 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
1930 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
1931 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
1936 static driver_t pci_driver = {
1942 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
1943 MODULE_VERSION(pci, 1);