2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_polling.h"
35 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
83 #else /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85 #endif /* IGB_RSS_DEBUG */
87 #define IGB_NAME "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
92 static struct igb_device {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
125 /* required last entry */
129 static int igb_probe(device_t);
130 static int igb_attach(device_t);
131 static int igb_detach(device_t);
132 static int igb_shutdown(device_t);
133 static int igb_suspend(device_t);
134 static int igb_resume(device_t);
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void igb_setup_ifp(struct igb_softc *);
138 static int igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
139 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
140 static void igb_add_sysctl(struct igb_softc *);
141 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
142 static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
143 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
144 static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
146 static void igb_vf_init_stats(struct igb_softc *);
147 static void igb_reset(struct igb_softc *);
148 static void igb_update_stats_counters(struct igb_softc *);
149 static void igb_update_vf_stats_counters(struct igb_softc *);
150 static void igb_update_link_status(struct igb_softc *);
151 static void igb_init_tx_unit(struct igb_softc *);
152 static void igb_init_rx_unit(struct igb_softc *);
154 static void igb_set_vlan(struct igb_softc *);
155 static void igb_set_multi(struct igb_softc *);
156 static void igb_set_promisc(struct igb_softc *);
157 static void igb_disable_promisc(struct igb_softc *);
159 static int igb_alloc_rings(struct igb_softc *);
160 static void igb_free_rings(struct igb_softc *);
161 static int igb_create_tx_ring(struct igb_tx_ring *);
162 static int igb_create_rx_ring(struct igb_rx_ring *);
163 static void igb_free_tx_ring(struct igb_tx_ring *);
164 static void igb_free_rx_ring(struct igb_rx_ring *);
165 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
166 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
167 static void igb_init_tx_ring(struct igb_tx_ring *);
168 static int igb_init_rx_ring(struct igb_rx_ring *);
169 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
170 static int igb_encap(struct igb_tx_ring *, struct mbuf **);
172 static void igb_stop(struct igb_softc *);
173 static void igb_init(void *);
174 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
175 static void igb_media_status(struct ifnet *, struct ifmediareq *);
176 static int igb_media_change(struct ifnet *);
177 static void igb_timer(void *);
178 static void igb_watchdog(struct ifnet *);
179 static void igb_start(struct ifnet *);
180 #ifdef DEVICE_POLLING
181 static void igb_poll(struct ifnet *, enum poll_cmd, int);
183 static void igb_serialize(struct ifnet *, enum ifnet_serialize);
184 static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
185 static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
187 static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
191 static void igb_intr(void *);
192 static void igb_intr_shared(void *);
193 static void igb_rxeof(struct igb_rx_ring *, int);
194 static void igb_txeof(struct igb_tx_ring *);
195 static void igb_set_eitr(struct igb_softc *, int, int);
196 static void igb_enable_intr(struct igb_softc *);
197 static void igb_disable_intr(struct igb_softc *);
198 static void igb_init_unshared_intr(struct igb_softc *);
199 static void igb_init_intr(struct igb_softc *);
200 static int igb_setup_intr(struct igb_softc *);
201 static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
202 static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
203 static void igb_set_intr_mask(struct igb_softc *);
204 static int igb_alloc_intr(struct igb_softc *);
205 static void igb_free_intr(struct igb_softc *);
206 static void igb_teardown_intr(struct igb_softc *);
207 static void igb_msix_try_alloc(struct igb_softc *);
208 static void igb_msix_free(struct igb_softc *, boolean_t);
209 static int igb_msix_setup(struct igb_softc *);
210 static void igb_msix_teardown(struct igb_softc *, int);
211 static void igb_msix_rx(void *);
212 static void igb_msix_tx(void *);
213 static void igb_msix_status(void *);
215 /* Management and WOL Support */
216 static void igb_get_mgmt(struct igb_softc *);
217 static void igb_rel_mgmt(struct igb_softc *);
218 static void igb_get_hw_control(struct igb_softc *);
219 static void igb_rel_hw_control(struct igb_softc *);
220 static void igb_enable_wol(device_t);
222 static device_method_t igb_methods[] = {
223 /* Device interface */
224 DEVMETHOD(device_probe, igb_probe),
225 DEVMETHOD(device_attach, igb_attach),
226 DEVMETHOD(device_detach, igb_detach),
227 DEVMETHOD(device_shutdown, igb_shutdown),
228 DEVMETHOD(device_suspend, igb_suspend),
229 DEVMETHOD(device_resume, igb_resume),
233 static driver_t igb_driver = {
236 sizeof(struct igb_softc),
239 static devclass_t igb_devclass;
241 DECLARE_DUMMY_MODULE(if_igb);
242 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
243 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
245 static int igb_rxd = IGB_DEFAULT_RXD;
246 static int igb_txd = IGB_DEFAULT_TXD;
247 static int igb_rxr = 0;
248 static int igb_msi_enable = 1;
249 static int igb_msix_enable = 1;
250 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
251 static int igb_fc_setting = e1000_fc_full;
254 * DMA Coalescing, only for i350 - default to off,
255 * this feature is for power savings
257 static int igb_dma_coalesce = 0;
259 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
260 TUNABLE_INT("hw.igb.txd", &igb_txd);
261 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
262 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
263 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
264 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
267 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
268 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
271 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
273 /* Ignore Checksum bit is set */
274 if (staterr & E1000_RXD_STAT_IXSM)
277 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
279 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
281 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
282 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
283 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
284 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
285 mp->m_pkthdr.csum_data = htons(0xffff);
290 static __inline struct pktinfo *
291 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
292 uint32_t hash, uint32_t hashtype, uint32_t staterr)
295 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
296 pi->pi_netisr = NETISR_IP;
298 pi->pi_l3proto = IPPROTO_TCP;
301 case E1000_RXDADV_RSSTYPE_IPV4:
302 if (staterr & E1000_RXD_STAT_IXSM)
306 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
307 E1000_RXD_STAT_TCPCS) {
308 pi->pi_netisr = NETISR_IP;
310 pi->pi_l3proto = IPPROTO_UDP;
318 m->m_flags |= M_HASH;
319 m->m_pkthdr.hash = toeplitz_hash(hash);
324 igb_probe(device_t dev)
326 const struct igb_device *d;
329 vid = pci_get_vendor(dev);
330 did = pci_get_device(dev);
332 for (d = igb_devices; d->desc != NULL; ++d) {
333 if (vid == d->vid && did == d->did) {
334 device_set_desc(dev, d->desc);
342 igb_attach(device_t dev)
344 struct igb_softc *sc = device_get_softc(dev);
345 uint16_t eeprom_data;
346 int error = 0, i, j, ring_max;
350 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
351 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
352 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
353 igb_sysctl_nvm_info, "I", "NVM Information");
355 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
356 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
357 OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
358 &igb_enable_aim, 1, "Interrupt Moderation");
360 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
361 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
362 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
363 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
366 callout_init_mp(&sc->timer);
367 lwkt_serialize_init(&sc->main_serialize);
369 sc->dev = sc->osdep.dev = dev;
372 * Determine hardware and mac type
374 sc->hw.vendor_id = pci_get_vendor(dev);
375 sc->hw.device_id = pci_get_device(dev);
376 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
377 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
378 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
380 if (e1000_set_mac_type(&sc->hw))
383 /* Are we a VF device? */
384 if (sc->hw.mac.type == e1000_vfadapt ||
385 sc->hw.mac.type == e1000_vfadapt_i350)
391 * Configure total supported RX/TX ring count
393 switch (sc->hw.mac.type) {
395 ring_max = IGB_MAX_RING_82575;
398 ring_max = IGB_MAX_RING_82580;
401 ring_max = IGB_MAX_RING_I350;
404 ring_max = IGB_MAX_RING_82576;
407 ring_max = IGB_MIN_RING;
410 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
411 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
413 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
415 sc->rx_ring_inuse = sc->rx_ring_cnt;
416 sc->tx_ring_cnt = 1; /* XXX */
418 /* Enable bus mastering */
419 pci_enable_busmaster(dev);
424 sc->mem_rid = PCIR_BAR(0);
425 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
427 if (sc->mem_res == NULL) {
428 device_printf(dev, "Unable to allocate bus resource: memory\n");
432 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
433 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
435 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
437 /* Save PCI command register for Shared Code */
438 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
439 sc->hw.back = &sc->osdep;
441 /* Do Shared Code initialization */
442 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
443 device_printf(dev, "Setup of Shared code failed\n");
448 e1000_get_bus_info(&sc->hw);
450 sc->hw.mac.autoneg = DO_AUTO_NEG;
451 sc->hw.phy.autoneg_wait_to_complete = FALSE;
452 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
455 if (sc->hw.phy.media_type == e1000_media_type_copper) {
456 sc->hw.phy.mdix = AUTO_ALL_MODES;
457 sc->hw.phy.disable_polarity_correction = FALSE;
458 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
461 /* Set the frame limits assuming standard ethernet sized frames. */
462 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
464 /* Allocate RX/TX rings */
465 error = igb_alloc_rings(sc);
469 /* Allocate interrupt */
470 error = igb_alloc_intr(sc);
478 sc->serializes[i++] = &sc->main_serialize;
480 sc->tx_serialize = i;
481 for (j = 0; j < sc->tx_ring_cnt; ++j)
482 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
484 sc->rx_serialize = i;
485 for (j = 0; j < sc->rx_ring_cnt; ++j)
486 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
488 sc->serialize_cnt = i;
489 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
491 /* Allocate the appropriate stats memory */
493 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
495 igb_vf_init_stats(sc);
497 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
501 /* Allocate multicast array memory. */
502 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
505 /* Some adapter-specific advanced features */
506 if (sc->hw.mac.type >= e1000_i350) {
508 igb_set_sysctl_value(adapter, "dma_coalesce",
509 "configure dma coalesce",
510 &adapter->dma_coalesce, igb_dma_coalesce);
511 igb_set_sysctl_value(adapter, "eee_disabled",
512 "enable Energy Efficient Ethernet",
513 &adapter->hw.dev_spec._82575.eee_disable,
516 sc->dma_coalesce = igb_dma_coalesce;
517 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
519 e1000_set_eee_i350(&sc->hw);
523 * Start from a known state, this is important in reading the nvm and
526 e1000_reset_hw(&sc->hw);
528 /* Make sure we have a good EEPROM before we read from it */
529 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
531 * Some PCI-E parts fail the first check due to
532 * the link being in sleep state, call it again,
533 * if it fails a second time its a real issue.
535 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
537 "The EEPROM Checksum Is Not Valid\n");
543 /* Copy the permanent MAC address out of the EEPROM */
544 if (e1000_read_mac_addr(&sc->hw) < 0) {
545 device_printf(dev, "EEPROM read error while reading MAC"
550 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
551 device_printf(dev, "Invalid MAC address\n");
558 ** Configure Interrupts
560 if ((adapter->msix > 1) && (igb_enable_msix))
561 error = igb_allocate_msix(adapter);
562 else /* MSI or Legacy */
563 error = igb_allocate_legacy(adapter);
568 /* Setup OS specific network interface */
571 /* Add sysctl tree, must after igb_setup_ifp() */
574 /* Now get a good starting state */
577 /* Initialize statistics */
578 igb_update_stats_counters(sc);
580 sc->hw.mac.get_link_status = 1;
581 igb_update_link_status(sc);
583 /* Indicate SOL/IDER usage */
584 if (e1000_check_reset_block(&sc->hw)) {
586 "PHY reset is blocked due to SOL/IDER session.\n");
589 /* Determine if we have to control management hardware */
590 if (e1000_enable_mng_pass_thru(&sc->hw))
591 sc->flags |= IGB_FLAG_HAS_MGMT;
596 /* APME bit in EEPROM is mapped to WUC.APME */
597 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
599 sc->wol = E1000_WUFC_MAG;
600 /* XXX disable WOL */
604 /* Register for VLAN events */
605 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
606 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
607 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
608 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
612 igb_add_hw_stats(adapter);
615 error = igb_setup_intr(sc);
617 ether_ifdetach(&sc->arpcom.ac_if);
628 igb_detach(device_t dev)
630 struct igb_softc *sc = device_get_softc(dev);
632 if (device_is_attached(dev)) {
633 struct ifnet *ifp = &sc->arpcom.ac_if;
635 ifnet_serialize_all(ifp);
639 e1000_phy_hw_reset(&sc->hw);
641 /* Give control back to firmware */
643 igb_rel_hw_control(sc);
646 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
647 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
651 igb_teardown_intr(sc);
653 ifnet_deserialize_all(ifp);
656 } else if (sc->mem_res != NULL) {
657 igb_rel_hw_control(sc);
659 bus_generic_detach(dev);
661 if (sc->sysctl_tree != NULL)
662 sysctl_ctx_free(&sc->sysctl_ctx);
666 if (sc->msix_mem_res != NULL) {
667 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
670 if (sc->mem_res != NULL) {
671 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
678 kfree(sc->mta, M_DEVBUF);
679 if (sc->stats != NULL)
680 kfree(sc->stats, M_DEVBUF);
686 igb_shutdown(device_t dev)
688 return igb_suspend(dev);
692 igb_suspend(device_t dev)
694 struct igb_softc *sc = device_get_softc(dev);
695 struct ifnet *ifp = &sc->arpcom.ac_if;
697 ifnet_serialize_all(ifp);
702 igb_rel_hw_control(sc);
705 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
706 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
710 ifnet_deserialize_all(ifp);
712 return bus_generic_suspend(dev);
716 igb_resume(device_t dev)
718 struct igb_softc *sc = device_get_softc(dev);
719 struct ifnet *ifp = &sc->arpcom.ac_if;
721 ifnet_serialize_all(ifp);
728 ifnet_deserialize_all(ifp);
730 return bus_generic_resume(dev);
734 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
736 struct igb_softc *sc = ifp->if_softc;
737 struct ifreq *ifr = (struct ifreq *)data;
738 int max_frame_size, mask, reinit;
741 ASSERT_IFNET_SERIALIZED_ALL(ifp);
745 max_frame_size = 9234;
746 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
752 ifp->if_mtu = ifr->ifr_mtu;
753 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
756 if (ifp->if_flags & IFF_RUNNING)
761 if (ifp->if_flags & IFF_UP) {
762 if (ifp->if_flags & IFF_RUNNING) {
763 if ((ifp->if_flags ^ sc->if_flags) &
764 (IFF_PROMISC | IFF_ALLMULTI)) {
765 igb_disable_promisc(sc);
771 } else if (ifp->if_flags & IFF_RUNNING) {
774 sc->if_flags = ifp->if_flags;
779 if (ifp->if_flags & IFF_RUNNING) {
780 igb_disable_intr(sc);
782 #ifdef DEVICE_POLLING
783 if (!(ifp->if_flags & IFF_POLLING))
791 * As the speed/duplex settings are being
792 * changed, we need toreset the PHY.
794 sc->hw.phy.reset_disable = FALSE;
796 /* Check SOL/IDER usage */
797 if (e1000_check_reset_block(&sc->hw)) {
798 if_printf(ifp, "Media change is "
799 "blocked due to SOL/IDER session.\n");
805 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
810 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
811 if (mask & IFCAP_HWCSUM) {
812 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
815 if (mask & IFCAP_VLAN_HWTAGGING) {
816 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
819 if (mask & IFCAP_RSS)
820 ifp->if_capenable ^= IFCAP_RSS;
821 if (reinit && (ifp->if_flags & IFF_RUNNING))
826 error = ether_ioctl(ifp, command, data);
835 struct igb_softc *sc = xsc;
836 struct ifnet *ifp = &sc->arpcom.ac_if;
840 ASSERT_IFNET_SERIALIZED_ALL(ifp);
844 /* Get the latest mac address, User can use a LAA */
845 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
847 /* Put the address into the Receive Address Array */
848 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
851 igb_update_link_status(sc);
853 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
855 /* Set hardware offload abilities */
856 if (ifp->if_capenable & IFCAP_TXCSUM)
857 ifp->if_hwassist = IGB_CSUM_FEATURES;
859 ifp->if_hwassist = 0;
861 /* Configure for OS presence */
865 #ifdef DEVICE_POLLING
866 if (ifp->if_flags & IFF_POLLING)
870 /* Configured used RX/TX rings */
871 igb_set_ring_inuse(sc, polling);
873 /* Initialize interrupt */
876 /* Prepare transmit descriptors and buffers */
877 for (i = 0; i < sc->tx_ring_cnt; ++i)
878 igb_init_tx_ring(&sc->tx_rings[i]);
879 igb_init_tx_unit(sc);
881 /* Setup Multicast table */
886 * Figure out the desired mbuf pool
887 * for doing jumbo/packetsplit
889 if (adapter->max_frame_size <= 2048)
890 adapter->rx_mbuf_sz = MCLBYTES;
891 else if (adapter->max_frame_size <= 4096)
892 adapter->rx_mbuf_sz = MJUMPAGESIZE;
894 adapter->rx_mbuf_sz = MJUM9BYTES;
897 /* Prepare receive descriptors and buffers */
898 for (i = 0; i < sc->rx_ring_inuse; ++i) {
901 error = igb_init_rx_ring(&sc->rx_rings[i]);
903 if_printf(ifp, "Could not setup receive structures\n");
908 igb_init_rx_unit(sc);
910 /* Enable VLAN support */
911 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
914 /* Don't lose promiscuous settings */
917 ifp->if_flags |= IFF_RUNNING;
918 ifp->if_flags &= ~IFF_OACTIVE;
920 callout_reset(&sc->timer, hz, igb_timer, sc);
921 e1000_clear_hw_cntrs_base_generic(&sc->hw);
924 if (adapter->msix > 1) /* Set up queue routing */
925 igb_configure_queues(adapter);
928 /* This clears any pending interrupts */
929 E1000_READ_REG(&sc->hw, E1000_ICR);
932 * Only enable interrupts if we are not polling, make sure
933 * they are off otherwise.
936 igb_disable_intr(sc);
939 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
942 /* Set Energy Efficient Ethernet */
943 e1000_set_eee_i350(&sc->hw);
945 /* Don't reset the phy next time init gets called */
946 sc->hw.phy.reset_disable = TRUE;
950 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
952 struct igb_softc *sc = ifp->if_softc;
953 u_char fiber_type = IFM_1000_SX;
955 ASSERT_IFNET_SERIALIZED_ALL(ifp);
957 igb_update_link_status(sc);
959 ifmr->ifm_status = IFM_AVALID;
960 ifmr->ifm_active = IFM_ETHER;
962 if (!sc->link_active)
965 ifmr->ifm_status |= IFM_ACTIVE;
967 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
968 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
969 ifmr->ifm_active |= fiber_type | IFM_FDX;
971 switch (sc->link_speed) {
973 ifmr->ifm_active |= IFM_10_T;
977 ifmr->ifm_active |= IFM_100_TX;
981 ifmr->ifm_active |= IFM_1000_T;
984 if (sc->link_duplex == FULL_DUPLEX)
985 ifmr->ifm_active |= IFM_FDX;
987 ifmr->ifm_active |= IFM_HDX;
992 igb_media_change(struct ifnet *ifp)
994 struct igb_softc *sc = ifp->if_softc;
995 struct ifmedia *ifm = &sc->media;
997 ASSERT_IFNET_SERIALIZED_ALL(ifp);
999 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1002 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1004 sc->hw.mac.autoneg = DO_AUTO_NEG;
1005 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1011 sc->hw.mac.autoneg = DO_AUTO_NEG;
1012 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1016 sc->hw.mac.autoneg = FALSE;
1017 sc->hw.phy.autoneg_advertised = 0;
1018 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1019 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1021 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1025 sc->hw.mac.autoneg = FALSE;
1026 sc->hw.phy.autoneg_advertised = 0;
1027 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1028 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1030 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1034 if_printf(ifp, "Unsupported media type\n");
1044 igb_set_promisc(struct igb_softc *sc)
1046 struct ifnet *ifp = &sc->arpcom.ac_if;
1047 struct e1000_hw *hw = &sc->hw;
1051 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1055 reg = E1000_READ_REG(hw, E1000_RCTL);
1056 if (ifp->if_flags & IFF_PROMISC) {
1057 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1058 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1059 } else if (ifp->if_flags & IFF_ALLMULTI) {
1060 reg |= E1000_RCTL_MPE;
1061 reg &= ~E1000_RCTL_UPE;
1062 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1067 igb_disable_promisc(struct igb_softc *sc)
1069 struct e1000_hw *hw = &sc->hw;
1073 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1076 reg = E1000_READ_REG(hw, E1000_RCTL);
1077 reg &= ~E1000_RCTL_UPE;
1078 reg &= ~E1000_RCTL_MPE;
1079 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1083 igb_set_multi(struct igb_softc *sc)
1085 struct ifnet *ifp = &sc->arpcom.ac_if;
1086 struct ifmultiaddr *ifma;
1087 uint32_t reg_rctl = 0;
1092 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1094 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1095 if (ifma->ifma_addr->sa_family != AF_LINK)
1098 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1101 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1102 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1106 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1107 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1108 reg_rctl |= E1000_RCTL_MPE;
1109 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1111 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1116 igb_timer(void *xsc)
1118 struct igb_softc *sc = xsc;
1120 lwkt_serialize_enter(&sc->main_serialize);
1122 igb_update_link_status(sc);
1123 igb_update_stats_counters(sc);
1125 callout_reset(&sc->timer, hz, igb_timer, sc);
1127 lwkt_serialize_exit(&sc->main_serialize);
1131 igb_update_link_status(struct igb_softc *sc)
1133 struct ifnet *ifp = &sc->arpcom.ac_if;
1134 struct e1000_hw *hw = &sc->hw;
1135 uint32_t link_check, thstat, ctrl;
1137 link_check = thstat = ctrl = 0;
1139 /* Get the cached link value or read for real */
1140 switch (hw->phy.media_type) {
1141 case e1000_media_type_copper:
1142 if (hw->mac.get_link_status) {
1143 /* Do the work to read phy */
1144 e1000_check_for_link(hw);
1145 link_check = !hw->mac.get_link_status;
1151 case e1000_media_type_fiber:
1152 e1000_check_for_link(hw);
1153 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1156 case e1000_media_type_internal_serdes:
1157 e1000_check_for_link(hw);
1158 link_check = hw->mac.serdes_has_link;
1161 /* VF device is type_unknown */
1162 case e1000_media_type_unknown:
1163 e1000_check_for_link(hw);
1164 link_check = !hw->mac.get_link_status;
1170 /* Check for thermal downshift or shutdown */
1171 if (hw->mac.type == e1000_i350) {
1172 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1173 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1176 /* Now we check if a transition has happened */
1177 if (link_check && sc->link_active == 0) {
1178 e1000_get_speed_and_duplex(hw,
1179 &sc->link_speed, &sc->link_duplex);
1181 if_printf(ifp, "Link is up %d Mbps %s\n",
1183 sc->link_duplex == FULL_DUPLEX ?
1184 "Full Duplex" : "Half Duplex");
1186 sc->link_active = 1;
1188 ifp->if_baudrate = sc->link_speed * 1000000;
1189 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1190 (thstat & E1000_THSTAT_LINK_THROTTLE))
1191 if_printf(ifp, "Link: thermal downshift\n");
1192 /* This can sleep */
1193 ifp->if_link_state = LINK_STATE_UP;
1194 if_link_state_change(ifp);
1195 } else if (!link_check && sc->link_active == 1) {
1196 ifp->if_baudrate = sc->link_speed = 0;
1197 sc->link_duplex = 0;
1199 if_printf(ifp, "Link is Down\n");
1200 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1201 (thstat & E1000_THSTAT_PWR_DOWN))
1202 if_printf(ifp, "Link: thermal shutdown\n");
1203 sc->link_active = 0;
1204 /* This can sleep */
1205 ifp->if_link_state = LINK_STATE_DOWN;
1206 if_link_state_change(ifp);
1211 igb_stop(struct igb_softc *sc)
1213 struct ifnet *ifp = &sc->arpcom.ac_if;
1216 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1218 igb_disable_intr(sc);
1220 callout_stop(&sc->timer);
1222 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1225 e1000_reset_hw(&sc->hw);
1226 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1228 e1000_led_off(&sc->hw);
1229 e1000_cleanup_led(&sc->hw);
1231 for (i = 0; i < sc->tx_ring_cnt; ++i)
1232 igb_free_tx_ring(&sc->tx_rings[i]);
1233 for (i = 0; i < sc->rx_ring_cnt; ++i)
1234 igb_free_rx_ring(&sc->rx_rings[i]);
1238 igb_reset(struct igb_softc *sc)
1240 struct ifnet *ifp = &sc->arpcom.ac_if;
1241 struct e1000_hw *hw = &sc->hw;
1242 struct e1000_fc_info *fc = &hw->fc;
1246 /* Let the firmware know the OS is in control */
1247 igb_get_hw_control(sc);
1250 * Packet Buffer Allocation (PBA)
1251 * Writing PBA sets the receive portion of the buffer
1252 * the remainder is used for the transmit buffer.
1254 switch (hw->mac.type) {
1256 pba = E1000_PBA_32K;
1261 pba = E1000_READ_REG(hw, E1000_RXPBS);
1262 pba &= E1000_RXPBS_SIZE_MASK_82576;
1267 case e1000_vfadapt_i350:
1268 pba = E1000_READ_REG(hw, E1000_RXPBS);
1269 pba = e1000_rxpbs_adjust_82580(pba);
1271 /* XXX pba = E1000_PBA_35K; */
1277 /* Special needs in case of Jumbo frames */
1278 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1279 uint32_t tx_space, min_tx, min_rx;
1281 pba = E1000_READ_REG(hw, E1000_PBA);
1282 tx_space = pba >> 16;
1285 min_tx = (sc->max_frame_size +
1286 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1287 min_tx = roundup2(min_tx, 1024);
1289 min_rx = sc->max_frame_size;
1290 min_rx = roundup2(min_rx, 1024);
1292 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1293 pba = pba - (min_tx - tx_space);
1295 * if short on rx space, rx wins
1296 * and must trump tx adjustment
1301 E1000_WRITE_REG(hw, E1000_PBA, pba);
1305 * These parameters control the automatic generation (Tx) and
1306 * response (Rx) to Ethernet PAUSE frames.
1307 * - High water mark should allow for at least two frames to be
1308 * received after sending an XOFF.
1309 * - Low water mark works best when it is very near the high water mark.
1310 * This allows the receiver to restart by sending XON when it has
1313 hwm = min(((pba << 10) * 9 / 10),
1314 ((pba << 10) - 2 * sc->max_frame_size));
1316 if (hw->mac.type < e1000_82576) {
1317 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1318 fc->low_water = fc->high_water - 8;
1320 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1321 fc->low_water = fc->high_water - 16;
1323 fc->pause_time = IGB_FC_PAUSE_TIME;
1324 fc->send_xon = TRUE;
1326 /* Issue a global reset */
1328 E1000_WRITE_REG(hw, E1000_WUC, 0);
1330 if (e1000_init_hw(hw) < 0)
1331 if_printf(ifp, "Hardware Initialization Failed\n");
1333 /* Setup DMA Coalescing */
1334 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1337 hwm = (pba - 4) << 10;
1338 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1339 & E1000_DMACR_DMACTHR_MASK;
1341 /* transition to L0x or L1 if available..*/
1342 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1344 /* timer = +-1000 usec in 32usec intervals */
1346 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1348 /* No lower threshold */
1349 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1351 /* set hwm to PBA - 2 * max frame size */
1352 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1354 /* Set the interval before transition */
1355 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1356 reg |= 0x800000FF; /* 255 usec */
1357 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1359 /* free space in tx packet buffer to wake from DMA coal */
1360 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1361 (20480 - (2 * sc->max_frame_size)) >> 6);
1363 /* make low power state decision controlled by DMA coal */
1364 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1365 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1366 reg | E1000_PCIEMISC_LX_DECISION);
1367 if_printf(ifp, "DMA Coalescing enabled\n");
1370 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1371 e1000_get_phy_info(hw);
1372 e1000_check_for_link(hw);
1376 igb_setup_ifp(struct igb_softc *sc)
1378 struct ifnet *ifp = &sc->arpcom.ac_if;
1380 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1382 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1383 ifp->if_init = igb_init;
1384 ifp->if_ioctl = igb_ioctl;
1385 ifp->if_start = igb_start;
1386 ifp->if_serialize = igb_serialize;
1387 ifp->if_deserialize = igb_deserialize;
1388 ifp->if_tryserialize = igb_tryserialize;
1390 ifp->if_serialize_assert = igb_serialize_assert;
1392 #ifdef DEVICE_POLLING
1393 ifp->if_poll = igb_poll;
1395 ifp->if_watchdog = igb_watchdog;
1397 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1398 ifq_set_ready(&ifp->if_snd);
1400 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1402 ifp->if_capabilities =
1403 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1404 if (IGB_ENABLE_HWRSS(sc))
1405 ifp->if_capabilities |= IFCAP_RSS;
1406 ifp->if_capenable = ifp->if_capabilities;
1407 ifp->if_hwassist = IGB_CSUM_FEATURES;
1410 * Tell the upper layer(s) we support long frames
1412 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1415 * Specify the media types supported by this adapter and register
1416 * callbacks to update media and link information
1418 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1419 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1420 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1421 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1423 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1425 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1426 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1428 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1429 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1431 if (sc->hw.phy.type != e1000_phy_ife) {
1432 ifmedia_add(&sc->media,
1433 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1434 ifmedia_add(&sc->media,
1435 IFM_ETHER | IFM_1000_T, 0, NULL);
1438 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1439 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1443 igb_add_sysctl(struct igb_softc *sc)
1448 sysctl_ctx_init(&sc->sysctl_ctx);
1449 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1450 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1451 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1452 if (sc->sysctl_tree == NULL) {
1453 device_printf(sc->dev, "can't add sysctl node\n");
1457 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1458 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1459 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1460 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1461 "# of RX rings used");
1462 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1463 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1465 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1466 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1469 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1470 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1471 SYSCTL_CHILDREN(sc->sysctl_tree),
1472 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1473 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1475 for (i = 0; i < sc->msix_cnt; ++i) {
1476 struct igb_msix_data *msix = &sc->msix_data[i];
1478 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1479 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1480 SYSCTL_CHILDREN(sc->sysctl_tree),
1481 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1482 msix, 0, igb_sysctl_msix_rate, "I",
1483 msix->msix_rate_desc);
1487 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1488 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1489 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1490 "# of segments per TX interrupt");
1492 #ifdef IGB_RSS_DEBUG
1493 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1494 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1496 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1497 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1498 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1499 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1500 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1506 igb_alloc_rings(struct igb_softc *sc)
1511 * Create top level busdma tag
1513 error = bus_dma_tag_create(NULL, 1, 0,
1514 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1515 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1518 device_printf(sc->dev, "could not create top level DMA tag\n");
1523 * Allocate TX descriptor rings and buffers
1525 sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1526 M_DEVBUF, M_WAITOK | M_ZERO);
1527 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1528 struct igb_tx_ring *txr = &sc->tx_rings[i];
1530 /* Set up some basics */
1533 lwkt_serialize_init(&txr->tx_serialize);
1535 error = igb_create_tx_ring(txr);
1541 * Allocate RX descriptor rings and buffers
1543 sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1544 M_DEVBUF, M_WAITOK | M_ZERO);
1545 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1546 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1548 /* Set up some basics */
1551 lwkt_serialize_init(&rxr->rx_serialize);
1553 error = igb_create_rx_ring(rxr);
1562 igb_free_rings(struct igb_softc *sc)
1566 if (sc->tx_rings != NULL) {
1567 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1568 struct igb_tx_ring *txr = &sc->tx_rings[i];
1570 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1572 kfree(sc->tx_rings, M_DEVBUF);
1575 if (sc->rx_rings != NULL) {
1576 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1577 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1579 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1581 kfree(sc->rx_rings, M_DEVBUF);
1586 igb_create_tx_ring(struct igb_tx_ring *txr)
1588 int tsize, error, i;
1591 * Validate number of transmit descriptors. It must not exceed
1592 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1594 if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1595 (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1596 device_printf(txr->sc->dev,
1597 "Using %d TX descriptors instead of %d!\n",
1598 IGB_DEFAULT_TXD, igb_txd);
1599 txr->num_tx_desc = IGB_DEFAULT_TXD;
1601 txr->num_tx_desc = igb_txd;
1605 * Allocate TX descriptor ring
1607 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1609 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1610 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1611 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1612 if (txr->txdma.dma_vaddr == NULL) {
1613 device_printf(txr->sc->dev,
1614 "Unable to allocate TX Descriptor memory\n");
1617 txr->tx_base = txr->txdma.dma_vaddr;
1618 bzero(txr->tx_base, tsize);
1620 txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->num_tx_desc,
1621 M_DEVBUF, M_WAITOK | M_ZERO);
1624 * Allocate TX head write-back buffer
1626 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1627 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1628 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1629 if (txr->tx_hdr == NULL) {
1630 device_printf(txr->sc->dev,
1631 "Unable to allocate TX head write-back buffer\n");
1636 * Create DMA tag for TX buffers
1638 error = bus_dma_tag_create(txr->sc->parent_tag,
1639 1, 0, /* alignment, bounds */
1640 BUS_SPACE_MAXADDR, /* lowaddr */
1641 BUS_SPACE_MAXADDR, /* highaddr */
1642 NULL, NULL, /* filter, filterarg */
1643 IGB_TSO_SIZE, /* maxsize */
1644 IGB_MAX_SCATTER, /* nsegments */
1645 PAGE_SIZE, /* maxsegsize */
1646 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1647 BUS_DMA_ONEBPAGE, /* flags */
1650 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1651 kfree(txr->tx_buf, M_DEVBUF);
1657 * Create DMA maps for TX buffers
1659 for (i = 0; i < txr->num_tx_desc; ++i) {
1660 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1662 error = bus_dmamap_create(txr->tx_tag,
1663 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1665 device_printf(txr->sc->dev,
1666 "Unable to create TX DMA map\n");
1667 igb_destroy_tx_ring(txr, i);
1673 * Initialize various watermark
1675 txr->spare_desc = IGB_TX_SPARE;
1676 txr->intr_nsegs = txr->num_tx_desc / 16;
1677 txr->oact_hi_desc = txr->num_tx_desc / 2;
1678 txr->oact_lo_desc = txr->num_tx_desc / 8;
1679 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1680 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1681 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1682 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1688 igb_free_tx_ring(struct igb_tx_ring *txr)
1692 for (i = 0; i < txr->num_tx_desc; ++i) {
1693 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1695 if (txbuf->m_head != NULL) {
1696 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1697 m_freem(txbuf->m_head);
1698 txbuf->m_head = NULL;
1704 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1708 if (txr->txdma.dma_vaddr != NULL) {
1709 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1710 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1711 txr->txdma.dma_map);
1712 bus_dma_tag_destroy(txr->txdma.dma_tag);
1713 txr->txdma.dma_vaddr = NULL;
1716 if (txr->tx_hdr != NULL) {
1717 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1718 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1720 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1724 if (txr->tx_buf == NULL)
1727 for (i = 0; i < ndesc; ++i) {
1728 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1730 KKASSERT(txbuf->m_head == NULL);
1731 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1733 bus_dma_tag_destroy(txr->tx_tag);
1735 kfree(txr->tx_buf, M_DEVBUF);
1740 igb_init_tx_ring(struct igb_tx_ring *txr)
1742 /* Clear the old descriptor contents */
1744 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1746 /* Clear TX head write-back buffer */
1750 txr->next_avail_desc = 0;
1751 txr->next_to_clean = 0;
1754 /* Set number of descriptors available */
1755 txr->tx_avail = txr->num_tx_desc;
1759 igb_init_tx_unit(struct igb_softc *sc)
1761 struct e1000_hw *hw = &sc->hw;
1765 /* Setup the Tx Descriptor Rings */
1766 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1767 struct igb_tx_ring *txr = &sc->tx_rings[i];
1768 uint64_t bus_addr = txr->txdma.dma_paddr;
1769 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1770 uint32_t txdctl = 0;
1771 uint32_t dca_txctrl;
1773 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1774 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1775 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1776 (uint32_t)(bus_addr >> 32));
1777 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1778 (uint32_t)bus_addr);
1780 /* Setup the HW Tx Head and Tail descriptor pointers */
1781 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1782 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1784 txdctl |= IGB_TX_PTHRESH;
1785 txdctl |= IGB_TX_HTHRESH << 8;
1786 txdctl |= IGB_TX_WTHRESH << 16;
1787 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1788 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1790 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1791 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1792 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1794 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1795 (uint32_t)(hdr_paddr >> 32));
1796 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1797 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1803 e1000_config_collision_dist(hw);
1805 /* Program the Transmit Control Register */
1806 tctl = E1000_READ_REG(hw, E1000_TCTL);
1807 tctl &= ~E1000_TCTL_CT;
1808 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1809 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1811 /* This write will effectively turn on the transmit unit. */
1812 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1816 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1818 struct e1000_adv_tx_context_desc *TXD;
1819 struct igb_tx_buf *txbuf;
1820 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1821 struct ether_vlan_header *eh;
1822 struct ip *ip = NULL;
1823 int ehdrlen, ctxd, ip_hlen = 0;
1824 uint16_t etype, vlantag = 0;
1825 boolean_t offload = TRUE;
1827 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1830 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1831 ctxd = txr->next_avail_desc;
1832 txbuf = &txr->tx_buf[ctxd];
1833 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1836 * In advanced descriptors the vlan tag must
1837 * be placed into the context descriptor, thus
1838 * we need to be here just for that setup.
1840 if (mp->m_flags & M_VLANTAG) {
1841 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1842 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1843 } else if (!offload) {
1848 * Determine where frame payload starts.
1849 * Jump over vlan headers if already present,
1850 * helpful for QinQ too.
1852 KASSERT(mp->m_len >= ETHER_HDR_LEN,
1853 ("igb_txctx_pullup is not called (eh)?\n"));
1854 eh = mtod(mp, struct ether_vlan_header *);
1855 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1856 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1857 ("igb_txctx_pullup is not called (evh)?\n"));
1858 etype = ntohs(eh->evl_proto);
1859 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1861 etype = ntohs(eh->evl_encap_proto);
1862 ehdrlen = ETHER_HDR_LEN;
1865 /* Set the ether header length */
1866 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1870 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1871 ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1873 /* NOTE: We could only safely access ip.ip_vhl part */
1874 ip = (struct ip *)(mp->m_data + ehdrlen);
1875 ip_hlen = ip->ip_hl << 2;
1877 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1878 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1882 case ETHERTYPE_IPV6:
1883 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1884 ip_hlen = sizeof(struct ip6_hdr);
1885 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1894 vlan_macip_lens |= ip_hlen;
1895 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1897 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1898 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1899 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1900 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1902 /* 82575 needs the queue index added */
1903 if (txr->sc->hw.mac.type == e1000_82575)
1904 mss_l4len_idx = txr->me << 4;
1906 /* Now copy bits into descriptor */
1907 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1908 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1909 TXD->seqnum_seed = htole32(0);
1910 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1912 txbuf->m_head = NULL;
1914 /* We've consumed the first desc, adjust counters */
1915 if (++ctxd == txr->num_tx_desc)
1917 txr->next_avail_desc = ctxd;
1924 igb_txeof(struct igb_tx_ring *txr)
1926 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1927 int first, hdr, avail;
1929 if (txr->tx_avail == txr->num_tx_desc)
1932 first = txr->next_to_clean;
1933 hdr = *(txr->tx_hdr);
1938 avail = txr->tx_avail;
1939 while (first != hdr) {
1940 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1943 if (txbuf->m_head) {
1944 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1945 m_freem(txbuf->m_head);
1946 txbuf->m_head = NULL;
1949 if (++first == txr->num_tx_desc)
1952 txr->next_to_clean = first;
1953 txr->tx_avail = avail;
1956 * If we have a minimum free, clear IFF_OACTIVE
1957 * to tell the stack that it is OK to send packets.
1959 if (IGB_IS_NOT_OACTIVE(txr)) {
1960 ifp->if_flags &= ~IFF_OACTIVE;
1963 * We have enough TX descriptors, turn off
1964 * the watchdog. We allow small amount of
1965 * packets (roughly intr_nsegs) pending on
1966 * the transmit ring.
1973 igb_create_rx_ring(struct igb_rx_ring *rxr)
1975 int rsize, i, error;
1978 * Validate number of receive descriptors. It must not exceed
1979 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1981 if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1982 (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1983 device_printf(rxr->sc->dev,
1984 "Using %d RX descriptors instead of %d!\n",
1985 IGB_DEFAULT_RXD, igb_rxd);
1986 rxr->num_rx_desc = IGB_DEFAULT_RXD;
1988 rxr->num_rx_desc = igb_rxd;
1992 * Allocate RX descriptor ring
1994 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1996 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1997 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1998 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1999 &rxr->rxdma.dma_paddr);
2000 if (rxr->rxdma.dma_vaddr == NULL) {
2001 device_printf(rxr->sc->dev,
2002 "Unable to allocate RxDescriptor memory\n");
2005 rxr->rx_base = rxr->rxdma.dma_vaddr;
2006 bzero(rxr->rx_base, rsize);
2008 rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->num_rx_desc,
2009 M_DEVBUF, M_WAITOK | M_ZERO);
2012 * Create DMA tag for RX buffers
2014 error = bus_dma_tag_create(rxr->sc->parent_tag,
2015 1, 0, /* alignment, bounds */
2016 BUS_SPACE_MAXADDR, /* lowaddr */
2017 BUS_SPACE_MAXADDR, /* highaddr */
2018 NULL, NULL, /* filter, filterarg */
2019 MCLBYTES, /* maxsize */
2021 MCLBYTES, /* maxsegsize */
2022 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2025 device_printf(rxr->sc->dev,
2026 "Unable to create RX payload DMA tag\n");
2027 kfree(rxr->rx_buf, M_DEVBUF);
2033 * Create spare DMA map for RX buffers
2035 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2038 device_printf(rxr->sc->dev,
2039 "Unable to create spare RX DMA maps\n");
2040 bus_dma_tag_destroy(rxr->rx_tag);
2041 kfree(rxr->rx_buf, M_DEVBUF);
2047 * Create DMA maps for RX buffers
2049 for (i = 0; i < rxr->num_rx_desc; i++) {
2050 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2052 error = bus_dmamap_create(rxr->rx_tag,
2053 BUS_DMA_WAITOK, &rxbuf->map);
2055 device_printf(rxr->sc->dev,
2056 "Unable to create RX DMA maps\n");
2057 igb_destroy_rx_ring(rxr, i);
2065 igb_free_rx_ring(struct igb_rx_ring *rxr)
2069 for (i = 0; i < rxr->num_rx_desc; ++i) {
2070 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2072 if (rxbuf->m_head != NULL) {
2073 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2074 m_freem(rxbuf->m_head);
2075 rxbuf->m_head = NULL;
2079 if (rxr->fmp != NULL)
2086 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2090 if (rxr->rxdma.dma_vaddr != NULL) {
2091 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2092 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2093 rxr->rxdma.dma_map);
2094 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2095 rxr->rxdma.dma_vaddr = NULL;
2098 if (rxr->rx_buf == NULL)
2101 for (i = 0; i < ndesc; ++i) {
2102 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2104 KKASSERT(rxbuf->m_head == NULL);
2105 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2107 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2108 bus_dma_tag_destroy(rxr->rx_tag);
2110 kfree(rxr->rx_buf, M_DEVBUF);
2115 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2117 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2118 rxd->wb.upper.status_error = 0;
2122 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2125 bus_dma_segment_t seg;
2127 struct igb_rx_buf *rxbuf;
2130 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2133 if_printf(&rxr->sc->arpcom.ac_if,
2134 "Unable to allocate RX mbuf\n");
2138 m->m_len = m->m_pkthdr.len = MCLBYTES;
2140 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2141 m_adj(m, ETHER_ALIGN);
2143 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2144 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2148 if_printf(&rxr->sc->arpcom.ac_if,
2149 "Unable to load RX mbuf\n");
2154 rxbuf = &rxr->rx_buf[i];
2155 if (rxbuf->m_head != NULL)
2156 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2159 rxbuf->map = rxr->rx_sparemap;
2160 rxr->rx_sparemap = map;
2163 rxbuf->paddr = seg.ds_addr;
2165 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2170 igb_init_rx_ring(struct igb_rx_ring *rxr)
2174 /* Clear the ring contents */
2176 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2178 /* Now replenish the ring mbufs */
2179 for (i = 0; i < rxr->num_rx_desc; ++i) {
2182 error = igb_newbuf(rxr, i, TRUE);
2187 /* Setup our descriptor indices */
2188 rxr->next_to_check = 0;
2192 rxr->discard = FALSE;
2198 igb_init_rx_unit(struct igb_softc *sc)
2200 struct ifnet *ifp = &sc->arpcom.ac_if;
2201 struct e1000_hw *hw = &sc->hw;
2202 uint32_t rctl, rxcsum, srrctl = 0;
2206 * Make sure receives are disabled while setting
2207 * up the descriptor ring
2209 rctl = E1000_READ_REG(hw, E1000_RCTL);
2210 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2214 ** Set up for header split
2216 if (igb_header_split) {
2217 /* Use a standard mbuf for the header */
2218 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2219 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2222 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2225 ** Set up for jumbo frames
2227 if (ifp->if_mtu > ETHERMTU) {
2228 rctl |= E1000_RCTL_LPE;
2230 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2231 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2232 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2233 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2234 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2235 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2237 /* Set maximum packet len */
2238 psize = adapter->max_frame_size;
2239 /* are we on a vlan? */
2240 if (adapter->ifp->if_vlantrunk != NULL)
2241 psize += VLAN_TAG_SIZE;
2242 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2244 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2245 rctl |= E1000_RCTL_SZ_2048;
2248 rctl &= ~E1000_RCTL_LPE;
2249 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2250 rctl |= E1000_RCTL_SZ_2048;
2253 /* Setup the Base and Length of the Rx Descriptor Rings */
2254 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2255 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2256 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2259 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2260 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2261 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2262 (uint32_t)(bus_addr >> 32));
2263 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2264 (uint32_t)bus_addr);
2265 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2266 /* Enable this Queue */
2267 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2268 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2269 rxdctl &= 0xFFF00000;
2270 rxdctl |= IGB_RX_PTHRESH;
2271 rxdctl |= IGB_RX_HTHRESH << 8;
2272 rxdctl |= IGB_RX_WTHRESH << 16;
2273 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2276 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2277 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2280 * Receive Checksum Offload for TCP and UDP
2282 * Checksum offloading is also enabled if multiple receive
2283 * queue is to be supported, since we need it to figure out
2286 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2289 * PCSD must be enabled to enable multiple
2292 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2295 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2298 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2300 if (IGB_ENABLE_HWRSS(sc)) {
2301 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2302 uint32_t reta_shift;
2307 * When we reach here, RSS has already been disabled
2308 * in igb_stop(), so we could safely configure RSS key
2309 * and redirect table.
2315 toeplitz_get_key(key, sizeof(key));
2316 for (i = 0; i < IGB_NRSSRK; ++i) {
2319 rssrk = IGB_RSSRK_VAL(key, i);
2320 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2322 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2326 * Configure RSS redirect table in following fashion:
2327 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2329 reta_shift = IGB_RETA_SHIFT;
2330 if (hw->mac.type == e1000_82575)
2331 reta_shift = IGB_RETA_SHIFT_82575;
2334 for (j = 0; j < IGB_NRETA; ++j) {
2337 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2340 q = (r % sc->rx_ring_inuse) << reta_shift;
2341 reta |= q << (8 * i);
2344 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2345 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2349 * Enable multiple receive queues.
2350 * Enable IPv4 RSS standard hash functions.
2351 * Disable RSS interrupt on 82575
2353 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2354 E1000_MRQC_ENABLE_RSS_4Q |
2355 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2356 E1000_MRQC_RSS_FIELD_IPV4);
2359 /* Setup the Receive Control Register */
2360 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2361 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2362 E1000_RCTL_RDMTS_HALF |
2363 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2364 /* Strip CRC bytes. */
2365 rctl |= E1000_RCTL_SECRC;
2366 /* Make sure VLAN Filters are off */
2367 rctl &= ~E1000_RCTL_VFE;
2368 /* Don't store bad packets */
2369 rctl &= ~E1000_RCTL_SBP;
2371 /* Enable Receives */
2372 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2375 * Setup the HW Rx Head and Tail Descriptor Pointers
2376 * - needs to be after enable
2378 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2379 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2381 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2382 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2387 igb_rxeof(struct igb_rx_ring *rxr, int count)
2389 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2390 union e1000_adv_rx_desc *cur;
2394 i = rxr->next_to_check;
2395 cur = &rxr->rx_base[i];
2396 staterr = le32toh(cur->wb.upper.status_error);
2398 if ((staterr & E1000_RXD_STAT_DD) == 0)
2401 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2402 struct pktinfo *pi = NULL, pi0;
2403 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2404 struct mbuf *m = NULL;
2407 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2411 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2413 struct mbuf *mp = rxbuf->m_head;
2414 uint32_t hash, hashtype;
2418 len = le16toh(cur->wb.upper.length);
2419 if (rxr->sc->hw.mac.type == e1000_i350 &&
2420 (staterr & E1000_RXDEXT_STATERR_LB))
2421 vlan = be16toh(cur->wb.upper.vlan);
2423 vlan = le16toh(cur->wb.upper.vlan);
2425 hash = le32toh(cur->wb.lower.hi_dword.rss);
2426 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2427 E1000_RXDADV_RSSTYPE_MASK;
2429 IGB_RSS_DPRINTF(rxr->sc, 10,
2430 "ring%d, hash 0x%08x, hashtype %u\n",
2431 rxr->me, hash, hashtype);
2433 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2434 BUS_DMASYNC_POSTREAD);
2436 if (igb_newbuf(rxr, i, FALSE) != 0) {
2442 if (rxr->fmp == NULL) {
2443 mp->m_pkthdr.len = len;
2447 rxr->lmp->m_next = mp;
2448 rxr->lmp = rxr->lmp->m_next;
2449 rxr->fmp->m_pkthdr.len += len;
2457 m->m_pkthdr.rcvif = ifp;
2460 if (ifp->if_capenable & IFCAP_RXCSUM)
2461 igb_rxcsum(staterr, m);
2463 if (staterr & E1000_RXD_STAT_VP) {
2464 m->m_pkthdr.ether_vlantag = vlan;
2465 m->m_flags |= M_VLANTAG;
2468 if (ifp->if_capenable & IFCAP_RSS) {
2469 pi = igb_rssinfo(m, &pi0,
2470 hash, hashtype, staterr);
2472 #ifdef IGB_RSS_DEBUG
2479 igb_setup_rxdesc(cur, rxbuf);
2481 rxr->discard = TRUE;
2483 rxr->discard = FALSE;
2484 if (rxr->fmp != NULL) {
2493 ether_input_pkt(ifp, m, pi);
2495 /* Advance our pointers to the next descriptor. */
2496 if (++i == rxr->num_rx_desc)
2499 cur = &rxr->rx_base[i];
2500 staterr = le32toh(cur->wb.upper.status_error);
2502 rxr->next_to_check = i;
2505 i = rxr->num_rx_desc - 1;
2506 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2511 igb_set_vlan(struct igb_softc *sc)
2513 struct e1000_hw *hw = &sc->hw;
2516 struct ifnet *ifp = sc->arpcom.ac_if;
2520 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2524 reg = E1000_READ_REG(hw, E1000_CTRL);
2525 reg |= E1000_CTRL_VME;
2526 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2529 /* Enable the Filter Table */
2530 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2531 reg = E1000_READ_REG(hw, E1000_RCTL);
2532 reg &= ~E1000_RCTL_CFIEN;
2533 reg |= E1000_RCTL_VFE;
2534 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2538 /* Update the frame size */
2539 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2540 sc->max_frame_size + VLAN_TAG_SIZE);
2543 /* Don't bother with table if no vlans */
2544 if ((adapter->num_vlans == 0) ||
2545 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2548 ** A soft reset zero's out the VFTA, so
2549 ** we need to repopulate it now.
2551 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2552 if (adapter->shadow_vfta[i] != 0) {
2553 if (adapter->vf_ifp)
2554 e1000_vfta_set_vf(hw,
2555 adapter->shadow_vfta[i], TRUE);
2557 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2558 i, adapter->shadow_vfta[i]);
2564 igb_enable_intr(struct igb_softc *sc)
2566 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2567 lwkt_serialize_handler_enable(&sc->main_serialize);
2571 for (i = 0; i < sc->msix_cnt; ++i) {
2572 lwkt_serialize_handler_enable(
2573 sc->msix_data[i].msix_serialize);
2577 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2578 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2579 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2581 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2582 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2583 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2584 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2586 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2588 E1000_WRITE_FLUSH(&sc->hw);
2592 igb_disable_intr(struct igb_softc *sc)
2594 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2595 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2596 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2598 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2599 E1000_WRITE_FLUSH(&sc->hw);
2601 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2602 lwkt_serialize_handler_disable(&sc->main_serialize);
2606 for (i = 0; i < sc->msix_cnt; ++i) {
2607 lwkt_serialize_handler_disable(
2608 sc->msix_data[i].msix_serialize);
2614 * Bit of a misnomer, what this really means is
2615 * to enable OS management of the system... aka
2616 * to disable special hardware management features
2619 igb_get_mgmt(struct igb_softc *sc)
2621 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2622 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2623 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2625 /* disable hardware interception of ARP */
2626 manc &= ~E1000_MANC_ARP_EN;
2628 /* enable receiving management packets to the host */
2629 manc |= E1000_MANC_EN_MNG2HOST;
2630 manc2h |= 1 << 5; /* Mng Port 623 */
2631 manc2h |= 1 << 6; /* Mng Port 664 */
2632 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2633 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2638 * Give control back to hardware management controller
2642 igb_rel_mgmt(struct igb_softc *sc)
2644 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2645 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2647 /* Re-enable hardware interception of ARP */
2648 manc |= E1000_MANC_ARP_EN;
2649 manc &= ~E1000_MANC_EN_MNG2HOST;
2651 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2656 * Sets CTRL_EXT:DRV_LOAD bit.
2658 * For ASF and Pass Through versions of f/w this means that
2659 * the driver is loaded.
2662 igb_get_hw_control(struct igb_softc *sc)
2669 /* Let firmware know the driver has taken over */
2670 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2671 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2672 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2676 * Resets CTRL_EXT:DRV_LOAD bit.
2678 * For ASF and Pass Through versions of f/w this means that the
2679 * driver is no longer loaded.
2682 igb_rel_hw_control(struct igb_softc *sc)
2689 /* Let firmware taken over control of h/w */
2690 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2691 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2692 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2696 igb_is_valid_ether_addr(const uint8_t *addr)
2698 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2700 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2706 * Enable PCI Wake On Lan capability
2709 igb_enable_wol(device_t dev)
2711 uint16_t cap, status;
2714 /* First find the capabilities pointer*/
2715 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2717 /* Read the PM Capabilities */
2718 id = pci_read_config(dev, cap, 1);
2719 if (id != PCIY_PMG) /* Something wrong */
2723 * OK, we have the power capabilities,
2724 * so now get the status register
2726 cap += PCIR_POWER_STATUS;
2727 status = pci_read_config(dev, cap, 2);
2728 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2729 pci_write_config(dev, cap, status, 2);
2733 igb_update_stats_counters(struct igb_softc *sc)
2735 struct e1000_hw *hw = &sc->hw;
2736 struct e1000_hw_stats *stats;
2737 struct ifnet *ifp = &sc->arpcom.ac_if;
2740 * The virtual function adapter has only a
2741 * small controlled set of stats, do only
2745 igb_update_vf_stats_counters(sc);
2750 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2751 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2753 E1000_READ_REG(hw,E1000_SYMERRS);
2754 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2757 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2758 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2759 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2760 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2762 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2763 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2764 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2765 stats->dc += E1000_READ_REG(hw, E1000_DC);
2766 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2767 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2768 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2771 * For watchdog management we need to know if we have been
2772 * paused during the last interval, so capture that here.
2774 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2775 stats->xoffrxc += sc->pause_frames;
2776 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2777 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2778 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2779 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2780 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2781 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2782 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2783 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2784 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2785 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2786 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2787 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2789 /* For the 64-bit byte counters the low dword must be read first. */
2790 /* Both registers clear on the read of the high dword */
2792 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2793 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2794 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2795 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2797 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2798 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2799 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2800 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2801 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2803 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2804 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2806 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2807 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2808 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2809 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2810 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2811 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2812 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2813 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2814 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2815 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2817 /* Interrupt Counts */
2819 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2820 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2821 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2822 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2823 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2824 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2825 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2826 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2827 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2829 /* Host to Card Statistics */
2831 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2832 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2833 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2834 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2835 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2836 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2837 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2838 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2839 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2840 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2841 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2842 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2843 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2844 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2846 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2847 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2848 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2849 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2850 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2851 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2853 ifp->if_collisions = stats->colc;
2856 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2857 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2860 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2862 /* Driver specific counters */
2863 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2864 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2865 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2866 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2867 sc->packet_buf_alloc_tx =
2868 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2869 sc->packet_buf_alloc_rx =
2870 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2874 igb_vf_init_stats(struct igb_softc *sc)
2876 struct e1000_hw *hw = &sc->hw;
2877 struct e1000_vf_stats *stats;
2880 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2881 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2882 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2883 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2884 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2888 igb_update_vf_stats_counters(struct igb_softc *sc)
2890 struct e1000_hw *hw = &sc->hw;
2891 struct e1000_vf_stats *stats;
2893 if (sc->link_speed == 0)
2897 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2898 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2899 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2900 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2901 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2904 #ifdef DEVICE_POLLING
2907 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2909 struct igb_softc *sc = ifp->if_softc;
2914 case POLL_DEREGISTER:
2915 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2919 case POLL_AND_CHECK_STATUS:
2920 ASSERT_SERIALIZED(&sc->main_serialize);
2921 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2922 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2923 sc->hw.mac.get_link_status = 1;
2924 igb_update_link_status(sc);
2928 ASSERT_SERIALIZED(&sc->main_serialize);
2929 if (ifp->if_flags & IFF_RUNNING) {
2930 struct igb_tx_ring *txr;
2933 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2934 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2936 lwkt_serialize_enter(&rxr->rx_serialize);
2937 igb_rxeof(rxr, count);
2938 lwkt_serialize_exit(&rxr->rx_serialize);
2941 txr = &sc->tx_rings[0];
2942 lwkt_serialize_enter(&txr->tx_serialize);
2944 if (!ifq_is_empty(&ifp->if_snd))
2946 lwkt_serialize_exit(&txr->tx_serialize);
2952 #endif /* DEVICE_POLLING */
2957 struct igb_softc *sc = xsc;
2958 struct ifnet *ifp = &sc->arpcom.ac_if;
2961 ASSERT_SERIALIZED(&sc->main_serialize);
2963 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2968 if (ifp->if_flags & IFF_RUNNING) {
2969 struct igb_tx_ring *txr;
2972 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2973 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2975 if (eicr & rxr->rx_intr_mask) {
2976 lwkt_serialize_enter(&rxr->rx_serialize);
2978 lwkt_serialize_exit(&rxr->rx_serialize);
2982 txr = &sc->tx_rings[0];
2983 if (eicr & txr->tx_intr_mask) {
2984 lwkt_serialize_enter(&txr->tx_serialize);
2986 if (!ifq_is_empty(&ifp->if_snd))
2988 lwkt_serialize_exit(&txr->tx_serialize);
2992 if (eicr & E1000_EICR_OTHER) {
2993 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2995 /* Link status change */
2996 if (icr & E1000_ICR_LSC) {
2997 sc->hw.mac.get_link_status = 1;
2998 igb_update_link_status(sc);
3003 * Reading EICR has the side effect to clear interrupt mask,
3004 * so all interrupts need to be enabled here.
3006 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3010 igb_intr_shared(void *xsc)
3012 struct igb_softc *sc = xsc;
3013 struct ifnet *ifp = &sc->arpcom.ac_if;
3016 ASSERT_SERIALIZED(&sc->main_serialize);
3018 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3021 if (reg_icr == 0xffffffff)
3024 /* Definitely not our interrupt. */
3028 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3031 if (ifp->if_flags & IFF_RUNNING) {
3033 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3036 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3037 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3039 lwkt_serialize_enter(&rxr->rx_serialize);
3041 lwkt_serialize_exit(&rxr->rx_serialize);
3045 if (reg_icr & E1000_ICR_TXDW) {
3046 struct igb_tx_ring *txr = &sc->tx_rings[0];
3048 lwkt_serialize_enter(&txr->tx_serialize);
3050 if (!ifq_is_empty(&ifp->if_snd))
3052 lwkt_serialize_exit(&txr->tx_serialize);
3056 /* Link status change */
3057 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3058 sc->hw.mac.get_link_status = 1;
3059 igb_update_link_status(sc);
3062 if (reg_icr & E1000_ICR_RXO)
3067 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
3069 struct mbuf *m = *m0;
3070 struct ether_header *eh;
3073 txr->ctx_try_pullup++;
3075 len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
3077 if (__predict_false(!M_WRITABLE(m))) {
3078 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3084 eh = mtod(m, struct ether_header *);
3086 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3087 len += EVL_ENCAPLEN;
3089 if (m->m_len < len) {
3098 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
3100 m = m_pullup(m, ETHER_HDR_LEN);
3102 txr->ctx_pullup1_failed++;
3108 eh = mtod(m, struct ether_header *);
3110 if (eh->ether_type == htons(ETHERTYPE_VLAN))
3111 len += EVL_ENCAPLEN;
3113 if (m->m_len < len) {
3115 m = m_pullup(m, len);
3117 txr->ctx_pullup2_failed++;
3127 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
3129 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3131 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3132 union e1000_adv_tx_desc *txd = NULL;
3133 struct mbuf *m_head = *m_headp;
3134 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3135 int maxsegs, nsegs, i, j, error, last = 0;
3136 uint32_t hdrlen = 0;
3138 if (m_head->m_len < IGB_TXCSUM_MINHL &&
3139 ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
3140 (m_head->m_flags & M_VLANTAG))) {
3142 * Make sure that ethernet header and ip.ip_hl are in
3143 * contiguous memory, since if TXCSUM or VLANTAG is
3144 * enabled, later TX context descriptor's setup need
3145 * to access ip.ip_hl.
3147 error = igb_txctx_pullup(txr, m_headp);
3149 KKASSERT(*m_headp == NULL);
3155 /* Set basic descriptor constants */
3156 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3157 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3158 if (m_head->m_flags & M_VLANTAG)
3159 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3162 * Map the packet for DMA.
3164 tx_buf = &txr->tx_buf[txr->next_avail_desc];
3165 tx_buf_mapped = tx_buf;
3168 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3169 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3170 if (maxsegs > IGB_MAX_SCATTER)
3171 maxsegs = IGB_MAX_SCATTER;
3173 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3174 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3176 if (error == ENOBUFS)
3177 txr->sc->mbuf_defrag_failed++;
3179 txr->sc->no_tx_dma_setup++;
3185 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3191 * Set up the context descriptor:
3192 * used when any hardware offload is done.
3193 * This includes CSUM, VLAN, and TSO. It
3194 * will use the first descriptor.
3196 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3197 if (igb_tso_setup(txr, m_head, &hdrlen)) {
3198 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3199 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3200 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3203 } else if (igb_tx_ctx_setup(txr, m_head))
3204 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3206 if (igb_txctx(txr, m_head)) {
3207 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3208 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3209 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3214 txr->tx_nsegs += nsegs;
3215 if (txr->tx_nsegs >= txr->intr_nsegs) {
3217 * Report Status (RS) is turned on every intr_nsegs
3218 * descriptors (roughly).
3221 cmd_rs = E1000_ADVTXD_DCMD_RS;
3224 /* Calculate payload length */
3225 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3226 << E1000_ADVTXD_PAYLEN_SHIFT);
3228 /* 82575 needs the queue index added */
3229 if (txr->sc->hw.mac.type == e1000_82575)
3230 olinfo_status |= txr->me << 4;
3232 /* Set up our transmit descriptors */
3233 i = txr->next_avail_desc;
3234 for (j = 0; j < nsegs; j++) {
3236 bus_addr_t seg_addr;
3238 tx_buf = &txr->tx_buf[i];
3239 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3240 seg_addr = segs[j].ds_addr;
3241 seg_len = segs[j].ds_len;
3243 txd->read.buffer_addr = htole64(seg_addr);
3244 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3245 txd->read.olinfo_status = htole32(olinfo_status);
3247 if (++i == txr->num_tx_desc)
3249 tx_buf->m_head = NULL;
3252 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3253 txr->next_avail_desc = i;
3254 txr->tx_avail -= nsegs;
3256 tx_buf->m_head = m_head;
3257 tx_buf_mapped->map = tx_buf->map;
3261 * Last Descriptor of Packet needs End Of Packet (EOP)
3263 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3266 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3267 * that this frame is available to transmit.
3269 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3276 igb_start(struct ifnet *ifp)
3278 struct igb_softc *sc = ifp->if_softc;
3279 struct igb_tx_ring *txr = &sc->tx_rings[0];
3280 struct mbuf *m_head;
3282 ASSERT_SERIALIZED(&txr->tx_serialize);
3284 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3287 if (!sc->link_active) {
3288 ifq_purge(&ifp->if_snd);
3292 if (!IGB_IS_NOT_OACTIVE(txr))
3295 while (!ifq_is_empty(&ifp->if_snd)) {
3296 if (IGB_IS_OACTIVE(txr)) {
3297 ifp->if_flags |= IFF_OACTIVE;
3298 /* Set watchdog on */
3303 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3307 if (igb_encap(txr, &m_head)) {
3312 /* Send a copy of the frame to the BPF listener */
3313 ETHER_BPF_MTAP(ifp, m_head);
3318 igb_watchdog(struct ifnet *ifp)
3320 struct igb_softc *sc = ifp->if_softc;
3321 struct igb_tx_ring *txr = &sc->tx_rings[0];
3323 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3326 * If flow control has paused us since last checking
3327 * it invalidates the watchdog timing, so dont run it.
3329 if (sc->pause_frames) {
3330 sc->pause_frames = 0;
3335 if_printf(ifp, "Watchdog timeout -- resetting\n");
3336 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3337 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3338 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3339 if_printf(ifp, "TX(%d) desc avail = %d, "
3340 "Next TX to Clean = %d\n",
3341 txr->me, txr->tx_avail, txr->next_to_clean);
3344 sc->watchdog_events++;
3347 if (!ifq_is_empty(&ifp->if_snd))
3352 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3357 if (sc->hw.mac.type == e1000_82575) {
3358 eitr = 1000000000 / 256 / rate;
3361 * Document is wrong on the 2 bits left shift
3364 eitr = 1000000 / rate;
3365 eitr <<= IGB_EITR_INTVL_SHIFT;
3369 /* Don't disable it */
3370 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3371 } else if (eitr > IGB_EITR_INTVL_MASK) {
3372 /* Don't allow it to be too large */
3373 eitr = IGB_EITR_INTVL_MASK;
3376 if (sc->hw.mac.type == e1000_82575)
3379 eitr |= E1000_EITR_CNT_IGNR;
3380 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3384 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3386 struct igb_softc *sc = (void *)arg1;
3387 struct ifnet *ifp = &sc->arpcom.ac_if;
3388 int error, intr_rate;
3390 intr_rate = sc->intr_rate;
3391 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3392 if (error || req->newptr == NULL)
3397 ifnet_serialize_all(ifp);
3399 sc->intr_rate = intr_rate;
3400 if (ifp->if_flags & IFF_RUNNING)
3401 igb_set_eitr(sc, 0, sc->intr_rate);
3404 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3406 ifnet_deserialize_all(ifp);
3412 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3414 struct igb_msix_data *msix = (void *)arg1;
3415 struct igb_softc *sc = msix->msix_sc;
3416 struct ifnet *ifp = &sc->arpcom.ac_if;
3417 int error, msix_rate;
3419 msix_rate = msix->msix_rate;
3420 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3421 if (error || req->newptr == NULL)
3426 lwkt_serialize_enter(msix->msix_serialize);
3428 msix->msix_rate = msix_rate;
3429 if (ifp->if_flags & IFF_RUNNING)
3430 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3433 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3437 lwkt_serialize_exit(msix->msix_serialize);
3443 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3445 struct igb_softc *sc = (void *)arg1;
3446 struct ifnet *ifp = &sc->arpcom.ac_if;
3447 struct igb_tx_ring *txr = &sc->tx_rings[0];
3450 nsegs = txr->intr_nsegs;
3451 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3452 if (error || req->newptr == NULL)
3457 ifnet_serialize_all(ifp);
3459 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3460 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3464 txr->intr_nsegs = nsegs;
3467 ifnet_deserialize_all(ifp);
3473 igb_init_intr(struct igb_softc *sc)
3475 igb_set_intr_mask(sc);
3477 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3478 igb_init_unshared_intr(sc);
3480 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3481 igb_set_eitr(sc, 0, sc->intr_rate);
3485 for (i = 0; i < sc->msix_cnt; ++i)
3486 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3491 igb_init_unshared_intr(struct igb_softc *sc)
3493 struct e1000_hw *hw = &sc->hw;
3494 const struct igb_rx_ring *rxr;
3495 const struct igb_tx_ring *txr;
3496 uint32_t ivar, index;
3500 * Enable extended mode
3502 if (sc->hw.mac.type != e1000_82575) {
3506 gpie = E1000_GPIE_NSICR;
3507 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3508 gpie |= E1000_GPIE_MSIX_MODE |
3512 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3517 switch (sc->hw.mac.type) {
3519 ivar_max = IGB_MAX_IVAR_82580;
3523 ivar_max = IGB_MAX_IVAR_I350;
3527 case e1000_vfadapt_i350:
3528 ivar_max = IGB_MAX_IVAR_VF;
3532 ivar_max = IGB_MAX_IVAR_82576;
3536 panic("unknown mac type %d\n", sc->hw.mac.type);
3538 for (i = 0; i < ivar_max; ++i)
3539 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3540 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3544 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3545 ("82575 w/ MSI-X"));
3546 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3547 tmp |= E1000_CTRL_EXT_IRCA;
3548 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3552 * Map TX/RX interrupts to EICR
3554 switch (sc->hw.mac.type) {
3558 case e1000_vfadapt_i350:
3560 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3561 rxr = &sc->rx_rings[i];
3564 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3569 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3573 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3575 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3578 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3579 txr = &sc->tx_rings[i];
3582 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3587 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3591 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3593 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3595 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3596 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3597 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3603 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3604 rxr = &sc->rx_rings[i];
3606 index = i & 0x7; /* Each IVAR has two entries */
3607 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3612 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3616 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3618 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3621 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3622 txr = &sc->tx_rings[i];
3624 index = i & 0x7; /* Each IVAR has two entries */
3625 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3630 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3634 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3636 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3638 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3639 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3640 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3646 * Enable necessary interrupt bits.
3648 * The name of the register is confusing; in addition to
3649 * configuring the first vector of MSI-X, it also configures
3650 * which bits of EICR could be set by the hardware even when
3651 * MSI or line interrupt is used; it thus controls interrupt
3652 * generation. It MUST be configured explicitly; the default
3653 * value mentioned in the datasheet is wrong: RX queue0 and
3654 * TX queue0 are NOT enabled by default.
3656 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3660 panic("unknown mac type %d\n", sc->hw.mac.type);
3665 igb_setup_intr(struct igb_softc *sc)
3667 struct ifnet *ifp = &sc->arpcom.ac_if;
3670 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3671 return igb_msix_setup(sc);
3673 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3676 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3678 sc->flags |= IGB_FLAG_SHARED_INTR;
3680 device_printf(sc->dev, "IRQ shared\n");
3681 } else if (bootverbose) {
3682 device_printf(sc->dev, "IRQ unshared\n");
3686 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3687 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3688 sc, &sc->intr_tag, &sc->main_serialize);
3690 device_printf(sc->dev, "Failed to register interrupt handler");
3694 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3695 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3701 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3703 if (txr->sc->hw.mac.type == e1000_82575) {
3704 txr->tx_intr_bit = 0; /* unused */
3707 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3710 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3713 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3716 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3719 panic("unsupported # of TX ring, %d\n", txr->me);
3722 int intr_bit = *intr_bit0;
3724 txr->tx_intr_bit = intr_bit % intr_bitmax;
3725 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3727 *intr_bit0 = intr_bit + 1;
3732 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3734 if (rxr->sc->hw.mac.type == e1000_82575) {
3735 rxr->rx_intr_bit = 0; /* unused */
3738 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3741 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3744 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3747 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3750 panic("unsupported # of RX ring, %d\n", rxr->me);
3753 int intr_bit = *intr_bit0;
3755 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3756 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3758 *intr_bit0 = intr_bit + 1;
3763 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3765 struct igb_softc *sc = ifp->if_softc;
3767 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3768 sc->tx_serialize, sc->rx_serialize, slz);
3772 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3774 struct igb_softc *sc = ifp->if_softc;
3776 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3777 sc->tx_serialize, sc->rx_serialize, slz);
3781 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3783 struct igb_softc *sc = ifp->if_softc;
3785 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3786 sc->tx_serialize, sc->rx_serialize, slz);
3792 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3793 boolean_t serialized)
3795 struct igb_softc *sc = ifp->if_softc;
3797 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3798 sc->tx_serialize, sc->rx_serialize, slz, serialized);
3801 #endif /* INVARIANTS */
3804 igb_set_intr_mask(struct igb_softc *sc)
3808 sc->intr_mask = sc->sts_intr_mask;
3809 for (i = 0; i < sc->rx_ring_inuse; ++i)
3810 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3811 for (i = 0; i < sc->tx_ring_cnt; ++i)
3812 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3814 device_printf(sc->dev, "intr mask 0x%08x\n", sc->intr_mask);
3818 igb_alloc_intr(struct igb_softc *sc)
3820 int i, intr_bit, intr_bitmax;
3823 igb_msix_try_alloc(sc);
3824 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3828 * Allocate MSI/legacy interrupt resource
3830 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3831 &sc->intr_rid, &intr_flags);
3833 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3834 &sc->intr_rid, intr_flags);
3835 if (sc->intr_res == NULL) {
3836 device_printf(sc->dev, "Unable to allocate bus resource: "
3842 * Setup MSI/legacy interrupt mask
3844 switch (sc->hw.mac.type) {
3846 intr_bitmax = IGB_MAX_TXRXINT_82575;
3849 intr_bitmax = IGB_MAX_TXRXINT_82580;
3852 intr_bitmax = IGB_MAX_TXRXINT_I350;
3855 intr_bitmax = IGB_MAX_TXRXINT_82576;
3858 intr_bitmax = IGB_MIN_TXRXINT;
3862 for (i = 0; i < sc->tx_ring_cnt; ++i)
3863 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3864 for (i = 0; i < sc->rx_ring_cnt; ++i)
3865 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3866 sc->sts_intr_bit = 0;
3867 sc->sts_intr_mask = E1000_EICR_OTHER;
3869 /* Initialize interrupt rate */
3870 sc->intr_rate = IGB_INTR_RATE;
3872 igb_set_ring_inuse(sc, FALSE);
3873 igb_set_intr_mask(sc);
3878 igb_free_intr(struct igb_softc *sc)
3880 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3881 if (sc->intr_res != NULL) {
3882 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3885 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3886 pci_release_msi(sc->dev);
3888 igb_msix_free(sc, TRUE);
3893 igb_teardown_intr(struct igb_softc *sc)
3895 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3896 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3898 igb_msix_teardown(sc, sc->msix_cnt);
3902 igb_msix_try_alloc(struct igb_softc *sc)
3904 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
3906 struct igb_msix_data *msix;
3907 boolean_t aggregate, setup = FALSE;
3910 * MSI-X must not be enable on 82575.
3911 * See 82575EB specification update
3913 if (sc->hw.mac.type == e1000_82575)
3916 /* Don't enable MSI-X on VF */
3920 msix_enable = device_getenv_int(sc->dev, "msix.enable",
3925 msix_cnt = pci_msix_count(sc->dev);
3926 #ifdef IGB_MSIX_DEBUG
3927 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
3929 if (msix_cnt <= 1) {
3930 /* One MSI-X model does not make sense */
3935 while ((1 << (i + 1)) <= msix_cnt)
3940 device_printf(sc->dev, "MSI-X count %d/%d\n",
3941 msix_cnt2, msix_cnt);
3944 KKASSERT(msix_cnt2 <= msix_cnt);
3945 if (msix_cnt == msix_cnt2) {
3946 /* We need at least one MSI-X for link status */
3948 if (msix_cnt2 <= 1) {
3949 /* One MSI-X for RX/TX does not make sense */
3950 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
3951 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
3954 KKASSERT(msix_cnt > msix_cnt2);
3957 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
3958 msix_cnt2, msix_cnt);
3962 sc->rx_ring_msix = sc->rx_ring_cnt;
3963 if (sc->rx_ring_msix > msix_cnt2)
3964 sc->rx_ring_msix = msix_cnt2;
3966 if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
3968 * Independent TX/RX MSI-X
3972 device_printf(sc->dev, "independent TX/RX MSI-X\n");
3973 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
3976 * Aggregate TX/RX MSI-X
3980 device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
3981 alloc_cnt = msix_cnt2;
3982 if (alloc_cnt > ncpus2)
3984 if (sc->rx_ring_msix > alloc_cnt)
3985 sc->rx_ring_msix = alloc_cnt;
3987 ++alloc_cnt; /* For link status */
3990 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
3991 alloc_cnt, sc->rx_ring_msix);
3994 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
3995 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
3996 &sc->msix_mem_rid, RF_ACTIVE);
3997 if (sc->msix_mem_res == NULL) {
3998 device_printf(sc->dev, "Unable to map MSI-X table\n");
4002 sc->msix_cnt = alloc_cnt;
4003 sc->msix_data = kmalloc(sizeof(struct igb_msix_data) * sc->msix_cnt,
4004 M_DEVBUF, M_WAITOK | M_ZERO);
4005 for (x = 0; x < sc->msix_cnt; ++x) {
4006 msix = &sc->msix_data[x];
4008 lwkt_serialize_init(&msix->msix_serialize0);
4010 msix->msix_rid = -1;
4011 msix->msix_vector = x;
4012 msix->msix_mask = 1 << msix->msix_vector;
4013 msix->msix_rate = IGB_INTR_RATE;
4018 int offset, offset_def;
4020 if (sc->rx_ring_msix == ncpus2) {
4023 offset_def = (sc->rx_ring_msix *
4024 device_get_unit(sc->dev)) % ncpus2;
4026 offset = device_getenv_int(sc->dev,
4027 "msix.rxoff", offset_def);
4028 if (offset >= ncpus2 ||
4029 offset % sc->rx_ring_msix != 0) {
4030 device_printf(sc->dev,
4031 "invalid msix.rxoff %d, use %d\n",
4032 offset, offset_def);
4033 offset = offset_def;
4038 for (i = 0; i < sc->rx_ring_msix; ++i) {
4039 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4041 KKASSERT(x < sc->msix_cnt);
4042 msix = &sc->msix_data[x++];
4043 rxr->rx_intr_bit = msix->msix_vector;
4044 rxr->rx_intr_mask = msix->msix_mask;
4046 msix->msix_serialize = &rxr->rx_serialize;
4047 msix->msix_func = igb_msix_rx;
4048 msix->msix_arg = rxr;
4049 msix->msix_cpuid = i + offset;
4050 KKASSERT(msix->msix_cpuid < ncpus2);
4051 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4052 "%s rx%d", device_get_nameunit(sc->dev), i);
4053 msix->msix_rate = IGB_MSIX_RX_RATE;
4054 ksnprintf(msix->msix_rate_desc,
4055 sizeof(msix->msix_rate_desc),
4056 "RX%d interrupt rate", i);
4059 offset_def = device_get_unit(sc->dev) % ncpus2;
4060 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4061 if (offset >= ncpus2) {
4062 device_printf(sc->dev, "invalid msix.txoff %d, "
4063 "use %d\n", offset, offset_def);
4064 offset = offset_def;
4068 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4069 struct igb_tx_ring *txr = &sc->tx_rings[i];
4071 KKASSERT(x < sc->msix_cnt);
4072 msix = &sc->msix_data[x++];
4073 txr->tx_intr_bit = msix->msix_vector;
4074 txr->tx_intr_mask = msix->msix_mask;
4076 msix->msix_serialize = &txr->tx_serialize;
4077 msix->msix_func = igb_msix_tx;
4078 msix->msix_arg = txr;
4079 msix->msix_cpuid = i + offset;
4080 sc->msix_tx_cpuid = msix->msix_cpuid; /* XXX */
4081 KKASSERT(msix->msix_cpuid < ncpus2);
4082 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4083 "%s tx%d", device_get_nameunit(sc->dev), i);
4084 msix->msix_rate = IGB_MSIX_TX_RATE;
4085 ksnprintf(msix->msix_rate_desc,
4086 sizeof(msix->msix_rate_desc),
4087 "TX%d interrupt rate", i);
4098 KKASSERT(x < sc->msix_cnt);
4099 msix = &sc->msix_data[x++];
4100 sc->sts_intr_bit = msix->msix_vector;
4101 sc->sts_intr_mask = msix->msix_mask;
4103 msix->msix_serialize = &sc->main_serialize;
4104 msix->msix_func = igb_msix_status;
4105 msix->msix_arg = sc;
4106 msix->msix_cpuid = 0; /* TODO tunable */
4107 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4108 device_get_nameunit(sc->dev));
4109 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4110 "status interrupt rate");
4112 KKASSERT(x == sc->msix_cnt);
4114 error = pci_setup_msix(sc->dev);
4116 device_printf(sc->dev, "Setup MSI-X failed\n");
4121 for (i = 0; i < sc->msix_cnt; ++i) {
4122 msix = &sc->msix_data[i];
4124 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4125 &msix->msix_rid, msix->msix_cpuid);
4127 device_printf(sc->dev,
4128 "Unable to allocate MSI-X %d on cpu%d\n",
4129 msix->msix_vector, msix->msix_cpuid);
4133 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4134 &msix->msix_rid, RF_ACTIVE);
4135 if (msix->msix_res == NULL) {
4136 device_printf(sc->dev,
4137 "Unable to allocate MSI-X %d resource\n",
4144 pci_enable_msix(sc->dev);
4145 sc->intr_type = PCI_INTR_TYPE_MSIX;
4148 igb_msix_free(sc, setup);
4152 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4156 KKASSERT(sc->msix_cnt > 1);
4158 for (i = 0; i < sc->msix_cnt; ++i) {
4159 struct igb_msix_data *msix = &sc->msix_data[i];
4161 if (msix->msix_res != NULL) {
4162 bus_release_resource(sc->dev, SYS_RES_IRQ,
4163 msix->msix_rid, msix->msix_res);
4165 if (msix->msix_rid >= 0)
4166 pci_release_msix_vector(sc->dev, msix->msix_rid);
4169 pci_teardown_msix(sc->dev);
4172 kfree(sc->msix_data, M_DEVBUF);
4173 sc->msix_data = NULL;
4177 igb_msix_setup(struct igb_softc *sc)
4179 struct ifnet *ifp = &sc->arpcom.ac_if;
4182 for (i = 0; i < sc->msix_cnt; ++i) {
4183 struct igb_msix_data *msix = &sc->msix_data[i];
4186 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4187 INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4188 &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4190 device_printf(sc->dev, "could not set up %s "
4191 "interrupt handler.\n", msix->msix_desc);
4192 igb_msix_teardown(sc, i);
4196 ifp->if_cpuid = sc->msix_tx_cpuid;
4202 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4206 for (i = 0; i < msix_cnt; ++i) {
4207 struct igb_msix_data *msix = &sc->msix_data[i];
4209 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4214 igb_msix_rx(void *arg)
4216 struct igb_rx_ring *rxr = arg;
4218 ASSERT_SERIALIZED(&rxr->rx_serialize);
4221 E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4225 igb_msix_tx(void *arg)
4227 struct igb_tx_ring *txr = arg;
4228 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
4230 ASSERT_SERIALIZED(&txr->tx_serialize);
4233 if (!ifq_is_empty(&ifp->if_snd))
4236 E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4240 igb_msix_status(void *arg)
4242 struct igb_softc *sc = arg;
4245 ASSERT_SERIALIZED(&sc->main_serialize);
4247 icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4248 if (icr & E1000_ICR_LSC) {
4249 sc->hw.mac.get_link_status = 1;
4250 igb_update_link_status(sc);
4253 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4257 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4259 if (!IGB_ENABLE_HWRSS(sc))
4262 if (sc->intr_type != PCI_INTR_TYPE_MSIX || polling)
4263 sc->rx_ring_inuse = IGB_MIN_RING_RSS;
4265 sc->rx_ring_inuse = sc->rx_ring_msix;
4267 device_printf(sc->dev, "RX rings %d/%d\n",
4268 sc->rx_ring_inuse, sc->rx_ring_cnt);