1 /******************************************************************************
4 * Project: Gigabit Ethernet Adapters, Common Modules
5 * Version: $Revision: 2.49 $
6 * Date: $Date: 2005/01/20 13:01:35 $
7 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family
9 ******************************************************************************/
11 /******************************************************************************
14 * Copyright (C) Marvell International Ltd. and/or its affiliates
16 * The computer program files contained in this folder ("Files")
17 * are provided to you under the BSD-type license terms provided
18 * below, and any use of such Files and any derivative works
19 * thereof created by you shall be governed by the following terms
22 * - Redistributions of source code must retain the above copyright
23 * notice, this list of conditions and the following disclaimer.
24 * - Redistributions in binary form must reproduce the above
25 * copyright notice, this list of conditions and the following
26 * disclaimer in the documentation and/or other materials provided
27 * with the distribution.
28 * - Neither the name of Marvell nor the names of its contributors
29 * may be used to endorse or promote products derived from this
30 * software without specific prior written permission.
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43 * OF THE POSSIBILITY OF SUCH DAMAGE.
46 ******************************************************************************/
49 * Copyright (c) 1997, 1998, 1999, 2000
50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
52 * Redistribution and use in source and binary forms, with or without
53 * modification, are permitted provided that the following conditions
55 * 1. Redistributions of source code must retain the above copyright
56 * notice, this list of conditions and the following disclaimer.
57 * 2. Redistributions in binary form must reproduce the above copyright
58 * notice, this list of conditions and the following disclaimer in the
59 * documentation and/or other materials provided with the distribution.
60 * 3. All advertising materials mentioning features or use of this software
61 * must display the following acknowledgement:
62 * This product includes software developed by Bill Paul.
63 * 4. Neither the name of the author nor the names of any co-contributors
64 * may be used to endorse or promote products derived from this software
65 * without specific prior written permission.
67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
77 * THE POSSIBILITY OF SUCH DAMAGE.
81 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
83 * Permission to use, copy, modify, and distribute this software for any
84 * purpose with or without fee is hereby granted, provided that the above
85 * copyright notice and this permission notice appear in all copies.
87 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
88 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
89 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
90 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
91 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
92 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
93 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
96 /* $FreeBSD: src/sys/dev/msk/if_mskreg.h,v 1.11 2007/12/05 09:41:58 remko Exp $ */
97 /* $DragonFly: src/sys/dev/netif/msk/if_mskreg.h,v 1.4 2008/06/17 11:00:13 sephe Exp $ */
100 * SysKonnect PCI vendor ID
102 #define VENDORID_SK 0x1148
105 * Marvell PCI vendor ID
107 #define VENDORID_MARVELL 0x11AB
110 * D-Link PCI vendor ID
112 #define VENDORID_DLINK 0x1186
115 * SysKonnect ethernet device IDs
117 #define DEVICEID_SK_YUKON2 0x9000
118 #define DEVICEID_SK_YUKON2_EXPR 0x9e00
121 * Marvell gigabit ethernet device IDs
123 #define DEVICEID_MRVL_8021CU 0x4340
124 #define DEVICEID_MRVL_8022CU 0x4341
125 #define DEVICEID_MRVL_8061CU 0x4342
126 #define DEVICEID_MRVL_8062CU 0x4343
127 #define DEVICEID_MRVL_8021X 0x4344
128 #define DEVICEID_MRVL_8022X 0x4345
129 #define DEVICEID_MRVL_8061X 0x4346
130 #define DEVICEID_MRVL_8062X 0x4347
131 #define DEVICEID_MRVL_8035 0x4350
132 #define DEVICEID_MRVL_8036 0x4351
133 #define DEVICEID_MRVL_8038 0x4352
134 #define DEVICEID_MRVL_8039 0x4353
135 #define DEVICEID_MRVL_8040 0x4354
136 #define DEVICEID_MRVL_8040T 0x4355
137 #define DEVICEID_MRVL_8048 0x435A
138 #define DEVICEID_MRVL_4360 0x4360
139 #define DEVICEID_MRVL_4361 0x4361
140 #define DEVICEID_MRVL_4362 0x4362
141 #define DEVICEID_MRVL_4363 0x4363
142 #define DEVICEID_MRVL_4364 0x4364
143 #define DEVICEID_MRVL_4365 0x4365
144 #define DEVICEID_MRVL_436A 0x436A
145 #define DEVICEID_MRVL_436B 0x436B
146 #define DEVICEID_MRVL_436C 0x436C
149 * D-Link gigabit ethernet device ID
151 #define DEVICEID_DLINK_DGE550SX 0x4001
152 #define DEVICEID_DLINK_DGE560T 0x4b00
154 #define BIT_31 (1 << 31)
155 #define BIT_30 (1 << 30)
156 #define BIT_29 (1 << 29)
157 #define BIT_28 (1 << 28)
158 #define BIT_27 (1 << 27)
159 #define BIT_26 (1 << 26)
160 #define BIT_25 (1 << 25)
161 #define BIT_24 (1 << 24)
162 #define BIT_23 (1 << 23)
163 #define BIT_22 (1 << 22)
164 #define BIT_21 (1 << 21)
165 #define BIT_20 (1 << 20)
166 #define BIT_19 (1 << 19)
167 #define BIT_18 (1 << 18)
168 #define BIT_17 (1 << 17)
169 #define BIT_16 (1 << 16)
170 #define BIT_15 (1 << 15)
171 #define BIT_14 (1 << 14)
172 #define BIT_13 (1 << 13)
173 #define BIT_12 (1 << 12)
174 #define BIT_11 (1 << 11)
175 #define BIT_10 (1 << 10)
176 #define BIT_9 (1 << 9)
177 #define BIT_8 (1 << 8)
178 #define BIT_7 (1 << 7)
179 #define BIT_6 (1 << 6)
180 #define BIT_5 (1 << 5)
181 #define BIT_4 (1 << 4)
182 #define BIT_3 (1 << 3)
183 #define BIT_2 (1 << 2)
184 #define BIT_1 (1 << 1)
185 #define BIT_0 (1 << 0)
187 #define SHIFT31(x) ((x) << 31)
188 #define SHIFT30(x) ((x) << 30)
189 #define SHIFT29(x) ((x) << 29)
190 #define SHIFT28(x) ((x) << 28)
191 #define SHIFT27(x) ((x) << 27)
192 #define SHIFT26(x) ((x) << 26)
193 #define SHIFT25(x) ((x) << 25)
194 #define SHIFT24(x) ((x) << 24)
195 #define SHIFT23(x) ((x) << 23)
196 #define SHIFT22(x) ((x) << 22)
197 #define SHIFT21(x) ((x) << 21)
198 #define SHIFT20(x) ((x) << 20)
199 #define SHIFT19(x) ((x) << 19)
200 #define SHIFT18(x) ((x) << 18)
201 #define SHIFT17(x) ((x) << 17)
202 #define SHIFT16(x) ((x) << 16)
203 #define SHIFT15(x) ((x) << 15)
204 #define SHIFT14(x) ((x) << 14)
205 #define SHIFT13(x) ((x) << 13)
206 #define SHIFT12(x) ((x) << 12)
207 #define SHIFT11(x) ((x) << 11)
208 #define SHIFT10(x) ((x) << 10)
209 #define SHIFT9(x) ((x) << 9)
210 #define SHIFT8(x) ((x) << 8)
211 #define SHIFT7(x) ((x) << 7)
212 #define SHIFT6(x) ((x) << 6)
213 #define SHIFT5(x) ((x) << 5)
214 #define SHIFT4(x) ((x) << 4)
215 #define SHIFT3(x) ((x) << 3)
216 #define SHIFT2(x) ((x) << 2)
217 #define SHIFT1(x) ((x) << 1)
218 #define SHIFT0(x) ((x) << 0)
221 * PCI Configuration Space header
223 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
224 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
225 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
226 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
227 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
228 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */
229 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */
230 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */
231 #define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */
232 #define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */
234 /* PCI Express Capability */
235 #define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
236 #define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
237 #define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
238 #define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
239 #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
240 #define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
241 #define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
242 #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
243 #define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
245 /* PCI Express Extended Capabilities */
246 #define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
247 #define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
248 #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
249 #define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
250 #define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
251 #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
252 #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */
253 #define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
255 /* PCI_OUR_REG_1 32 bit Our Register 1 */
256 #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
257 #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
258 #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
259 #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
260 #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
261 #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
262 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */
263 #define PCI_EN_IO BIT_23 /* Mapping to I/O space */
264 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */
265 /* 1 = Map Flash to memory */
266 /* 0 = Disable addr. dec */
267 #define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */
268 #define PCI_PAGE_16 (0L<<20)/* 16 k pages */
269 #define PCI_PAGE_32K (1L<<20)/* 32 k pages */
270 #define PCI_PAGE_64K (2L<<20)/* 64 k pages */
271 #define PCI_PAGE_128K (3L<<20)/* 128 k pages */
272 #define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */
273 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
274 #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */
275 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
276 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
277 #define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */
278 #define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */
279 #define PCI_BURST_DIS BIT_9 /* Burst Disable */
280 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
281 #define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */
282 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
283 #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
285 /* PCI_OUR_REG_2 32 bit Our Register 2 */
286 #define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */
287 #define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */
288 #define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */
289 /* Bit 13..12: reserved */
290 #define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
291 #define PCI_PATCH_DIR_3 BIT_11
292 #define PCI_PATCH_DIR_2 BIT_10
293 #define PCI_PATCH_DIR_1 BIT_9
294 #define PCI_PATCH_DIR_0 BIT_8
295 #define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */
296 #define PCI_EXT_PATCH_3 BIT_7
297 #define PCI_EXT_PATCH_2 BIT_6
298 #define PCI_EXT_PATCH_1 BIT_5
299 #define PCI_EXT_PATCH_0 BIT_4
300 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
301 #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
302 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
304 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
305 #define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */
306 #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
307 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
308 #define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */
309 #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
310 #define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */
311 #define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */
312 #define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */
314 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
315 /* possible values for the speed field of the register */
316 #define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */
317 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
318 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
319 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
321 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
322 #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */
323 #define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
324 #define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */
325 #define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */
326 #define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */
327 #define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
328 #define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
329 #define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */
330 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
331 #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
333 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
334 /* Bit 31..27: for A3 & later */
335 #define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */
336 #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */
337 #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */
338 #define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */
339 #define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */
340 #define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27)
341 /* Bit 26..16: Release Clock on Event */
342 #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
343 #define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
344 #define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */
345 #define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
346 #define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */
347 #define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
348 #define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */
349 #define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
350 #define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */
351 #define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
352 #define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
353 /* Bit 10.. 0: Mask for Gate Clock */
354 #define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */
355 #define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
356 #define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
357 #define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
358 #define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
359 #define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
360 #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
361 #define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
362 #define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
363 #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
364 #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
366 /* PCI_CFG_REG_1 32 bit Config Register 1 */
367 #define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */
368 /* Bit 23..21: Release Clock on Event */
369 #define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */
370 #define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */
371 #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */
372 /* Bit 20..18: Gate Clock on Event */
373 #define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */
374 #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */
375 #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */
376 #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
377 #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */
379 #define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */
380 #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */
381 #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
383 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
384 #define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
385 #define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */
386 #define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */
387 #define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */
388 #define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */
389 #define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */
390 #define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */
391 #define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */
392 #define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */
393 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */
394 #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */
396 #define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
398 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
399 #define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */
400 #define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */
401 #define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */
402 #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
403 #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
405 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
406 #define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */
407 #define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */
408 #define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */
409 #define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */
410 #define PEX_COMP_TO BIT_14 /* Completion Timeout */
411 #define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
412 #define PEX_POIS_TLP BIT_12 /* Poisoned TLP */
413 #define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */
415 #define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
417 /* Control Register File (Address Map) */
422 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
423 #define B0_CTST 0x0004 /* 16 bit Control/Status register */
424 #define B0_LED 0x0006 /* 8 Bit LED register */
425 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
426 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
427 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
428 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
429 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
430 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
432 /* Special ISR registers (Yukon-2 only) */
433 #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
434 #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
435 #define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */
436 #define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */
437 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */
441 * - completely empty (this is the RAP Block window)
442 * Note: if RAP = 1 this page is reserved
448 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
449 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
450 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
451 #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
452 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
453 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
454 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
455 #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
456 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
457 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
458 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
459 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
460 #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
461 #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */
462 #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */
463 #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */
464 #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */
465 #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/
466 #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */
467 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
468 #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */
469 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */
470 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */
471 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
472 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
473 #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */
474 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
475 #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */
476 #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */
477 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
479 #define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
480 #define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
485 /* RAM Random Registers */
486 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
487 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
488 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
490 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
492 /* RAM Interface Registers */
493 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
495 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
496 * not usable in SW. Please notice these are NOT real timeouts, these are
497 * the number of qWords transferred continuously.
499 #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */
500 #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */
501 #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */
502 #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */
503 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */
504 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */
505 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */
506 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */
507 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */
508 #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */
509 #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/
510 #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/
511 #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */
512 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */
513 #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */
518 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
519 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/
520 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */
521 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */
522 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */
523 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
524 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
525 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
527 #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs))
529 /* RSS key registers for Yukon-2 Family */
530 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
531 /* RSS key register offsets */
532 #define KEY_IDX_0 0 /* offset for location of KEY 0 */
533 #define KEY_IDX_1 4 /* offset for location of KEY 1 */
534 #define KEY_IDX_2 8 /* offset for location of KEY 2 */
535 #define KEY_IDX_3 12 /* offset for location of KEY 3 */
536 /* 0x0280 - 0x0292: MAC 2 */
537 #define RSS_KEY_ADDR(Port, KeyIndex) \
538 ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
543 /* Receive and Transmit Queue Registers, use Q_ADDR() to access */
544 #define B8_Q_REGS 0x0400
546 /* Queue Register Offsets, use Q_ADDR() to access */
547 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
548 #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
549 #define Q_DONE 0x24 /* 16 bit Done Index */
550 #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
551 #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
552 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
553 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
554 #define Q_F 0x38 /* 32 bit Flag Register */
555 #define Q_T1 0x3c /* 32 bit Test Register 1 */
556 #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */
557 #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */
558 #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */
559 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
560 #define Q_WM 0x40 /* 16 bit FIFO Watermark */
561 #define Q_AL 0x42 /* 8 bit FIFO Alignment */
562 #define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
563 #define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
564 #define Q_RP 0x48 /* 8 bit FIFO Read Pointer */
565 #define Q_RL 0x4a /* 8 bit FIFO Read Level */
566 #define Q_WP 0x4c /* 8 bit FIFO Write Pointer */
567 #define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
568 #define Q_WL 0x4e /* 8 bit FIFO Write Level */
569 #define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
571 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
573 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */
574 #define Y2_B8_PREF_REGS 0x0450
576 #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
577 #define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
578 #define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
579 #define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/
580 #define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
581 #define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
582 #define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
583 #define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
584 #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
585 #define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
587 #define PREF_UNIT_MASK_IDX 0x0fff
589 #define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs))
594 /* RAM Buffer Registers */
595 #define B16_RAM_REGS 0x0800
597 /* RAM Buffer Register Offsets, use RB_ADDR() to access */
598 #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */
599 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
600 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
601 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
602 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
603 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
604 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
605 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
606 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
607 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
608 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
609 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
610 #define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
615 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
616 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
617 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
618 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
619 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
620 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
621 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
622 #define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
623 #define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
624 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
625 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
626 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
627 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
628 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
633 /* 0x0c80 - 0x0cbf: MAC 2 */
634 /* 0x0cc0 - 0x0cff: reserved */
639 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
640 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
641 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
642 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
643 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
644 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
645 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
646 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
647 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
648 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
649 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
654 /* 0x0d80 - 0x0dbf: MAC 2 */
655 /* 0x0daa - 0x0dff: reserved */
660 /* Descriptor Poll Timer Registers */
661 #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */
662 #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */
663 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */
664 #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */
665 /* Time Stamp Timer Registers (YUKON only) */
666 #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */
667 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
668 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
669 /* Polling Unit Registers (Yukon-2 only) */
670 #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
671 #define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
672 #define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
673 #define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */
674 /* ASF Subsystem Registers (Yukon-2 only) */
675 #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
676 #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
677 #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
678 #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
679 #define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */
680 #define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
681 #define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
682 #define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
683 #define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
684 #define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
690 /* Status BMU Registers (Yukon-2 only)*/
691 #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
692 #define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
693 #define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */
694 #define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */
695 #define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */
696 #define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */
697 #define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */
698 #define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */
699 #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
700 #define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
701 /* FIFO Control/Status Registers (Yukon-2 only)*/
702 #define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */
703 #define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */
704 #define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */
705 #define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
706 #define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */
707 #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
708 #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
709 /* Level and ISR Timer Registers (Yukon-2 only)*/
710 #define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
711 #define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
712 #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
713 #define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
714 #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
715 #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
716 #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
717 #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
718 #define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
719 #define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
720 #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
721 #define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
723 #define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */
724 #define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
725 #define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
726 #define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
731 /* GMAC and GPHY Control Registers (YUKON only) */
732 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
733 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */
734 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */
735 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */
736 #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */
738 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
740 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
742 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */
743 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */
744 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
745 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
746 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
747 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
748 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
749 #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
751 /* WOL Pattern Length Registers (YUKON only) */
753 #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */
754 #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */
756 /* WOL Pattern Counter Registers (YUKON only) */
758 #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */
759 #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */
764 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
765 #define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
767 /* offset to configuration space on Yukon-2 */
768 #define Y2_CFG_SPC 0x1c00
769 #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */
770 #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */
773 * Control Register Bit Definitions:
775 /* B0_CTST 24 bit Control/Status register */
776 #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
777 #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
778 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
779 #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */
780 #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */
781 #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */
782 #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */
783 #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */
784 #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */
785 #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */
786 #define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */
787 #define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */
788 #define CS_STOP_DONE BIT_5 /* Stop Master is finished */
789 #define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */
790 #define CS_MRST_CLR BIT_3 /* Clear Master Reset */
791 #define CS_MRST_SET BIT_2 /* Set Master Reset */
792 #define CS_RST_CLR BIT_1 /* Clear Software Reset */
793 #define CS_RST_SET BIT_0 /* Set Software Reset */
795 #define LED_STAT_ON BIT_1 /* Status LED On */
796 #define LED_STAT_OFF BIT_0 /* Status LED Off */
798 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
799 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
800 #define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
801 #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
802 #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
803 #define PC_VAUX_ON BIT_3 /* Switch VAUX On */
804 #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
805 #define PC_VCC_ON BIT_1 /* Switch VCC On */
806 #define PC_VCC_OFF BIT_0 /* Switch VCC Off */
808 /* B0_ISRC 32 bit Interrupt Source Register */
809 /* B0_IMSK 32 bit Interrupt Mask Register */
810 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
811 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
812 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
813 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
814 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
815 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
816 #define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8))
817 #define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */
818 #define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */
819 #define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */
820 #define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */
821 #define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */
822 #define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */
823 #define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */
824 #define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */
825 #define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
826 #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
827 #define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */
828 #define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */
829 #define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */
830 #define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */
831 #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
832 #define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */
833 #define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
835 #define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */
837 #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */
839 #define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */
841 #define Y2_IS_PORT_A \
842 (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1)
843 #define Y2_IS_PORT_B \
844 (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2)
846 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
847 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
848 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
849 #define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */
850 #define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */
851 #define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */
852 #define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */
853 #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
854 #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */
855 #define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */
856 #define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */
857 #define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */
858 #define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
859 #define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */
860 #define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */
861 #define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */
862 #define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */
863 #define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */
864 #define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
865 #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
866 #define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
868 #define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
869 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
870 #define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
871 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
873 #define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\
874 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\
875 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
877 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
878 #define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */
879 #define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */
880 #define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
882 /* B2_CHIP_ID 8 bit Chip Identification Number */
883 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
884 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
885 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
886 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
887 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
888 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
889 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
890 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
891 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
892 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
894 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
895 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
896 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
897 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
899 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
900 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
901 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
903 #define CHIP_REV_YU_EC_U_A0 1
904 #define CHIP_REV_YU_EC_U_A1 2
906 #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
908 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */
909 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */
911 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
912 #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */
913 #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
914 #define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */
915 #define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */
916 #define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */
917 #define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */
918 #define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */
919 #define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */
921 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
922 #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */
923 #define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */
924 #define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */
926 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
927 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
929 /* B2_E_3 8 bit lower 4 bits used for HW self test result */
930 #define B2_E3_RES_MASK 0x0f
932 /* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
934 #define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */
935 #define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
937 #define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */
938 #define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */
939 #define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
940 #define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
941 #define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */
942 #define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */
944 /* B2_TI_CTRL 8 bit Timer control */
945 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
946 #define TIM_START BIT_2 /* Start Timer */
947 #define TIM_STOP BIT_1 /* Stop Timer */
948 #define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */
950 /* B2_TI_TEST 8 Bit Timer Test */
951 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
952 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
953 #define TIM_T_ON BIT_2 /* Test mode on */
954 #define TIM_T_OFF BIT_1 /* Test mode off */
955 #define TIM_T_STEP BIT_0 /* Test step */
957 /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */
958 /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */
959 #define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */
961 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
962 #define DPT_START BIT_1 /* Start Descriptor Poll Timer */
963 #define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */
965 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
966 #define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */
967 #define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */
968 #define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */
969 #define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */
970 #define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */
971 #define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */
972 #define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */
973 #define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */
976 #define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */
977 #define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */
979 #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */
980 #define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */
981 #define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */
982 #define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */
983 #define GLB_GPIO_TEST_SEL_BASE BIT_11
984 #define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */
985 #define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */
987 /* B2_I2C_CTRL 32 bit I2C HW Control Register */
988 #define I2C_FLAG BIT_31 /* Start read/write if WR */
989 #define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */
990 #define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */
991 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
992 #define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
993 #define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */
994 #define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
995 #define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
996 #define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
997 #define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
998 #define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
999 #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */
1000 #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */
1001 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
1003 /* B2_I2C_IRQ 32 bit I2C HW IRQ Register */
1004 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
1006 /* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
1007 #define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */
1008 #define I2C_DATA BIT_1 /* I2C Data Port */
1009 #define I2C_CLK BIT_0 /* I2C Clock Port */
1012 #define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */
1015 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
1016 #define BSC_START BIT_1 /* Start Blink Source Counter */
1017 #define BSC_STOP BIT_0 /* Stop Blink Source Counter */
1019 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
1020 #define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */
1022 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
1023 #define BSC_T_ON BIT_2 /* Test mode on */
1024 #define BSC_T_OFF BIT_1 /* Test mode off */
1025 #define BSC_T_STEP BIT_0 /* Test step */
1027 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
1028 #define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */
1029 #define PEX_DB_ACCESS BIT_30 /* Access to debug register */
1031 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
1032 #define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */
1034 /* RAM Interface Registers */
1035 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
1036 #define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */
1037 #define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */
1038 #define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */
1039 #define RI_RST_SET BIT_0 /* Set RAM Interface Reset */
1041 #define MSK_RI_TO_53 36 /* RAM interface timeout */
1043 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */
1044 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
1045 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
1046 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
1047 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
1048 #define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */
1050 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
1051 #define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */
1052 #define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */
1053 #define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */
1054 #define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */
1055 #define TXA_START_RC BIT_3 /* Start sync Rate Control */
1056 #define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */
1057 #define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */
1058 #define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */
1060 /* TXA_TEST 8 bit Tx Arbiter Test Register */
1061 #define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */
1062 #define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */
1063 #define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */
1064 #define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */
1065 #define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */
1066 #define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */
1068 /* TXA_STAT 8 bit Tx Arbiter Status Register */
1069 #define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */
1071 /* Q_BC 32 bit Current Byte Counter */
1072 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
1074 /* Rx BMU Control / Status Registers (Yukon-2) */
1075 #define BMU_IDLE BIT_31 /* BMU Idle State */
1076 #define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */
1077 #define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */
1078 #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
1079 #define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */
1080 #define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
1081 #define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
1082 #define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
1083 #define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
1084 #define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */
1085 #define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
1086 #define BMU_START BIT_8 /* Start Rx/Tx Queue */
1087 #define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */
1088 #define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
1089 #define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
1090 #define BMU_FIFO_RST BIT_4 /* Reset FIFO */
1091 #define BMU_OP_ON BIT_3 /* BMU Operational On */
1092 #define BMU_OP_OFF BIT_2 /* BMU Operational Off */
1093 #define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
1094 #define BMU_RST_SET BIT_0 /* Set BMU Reset */
1096 #define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
1097 #define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \
1098 BMU_START | BMU_FIFO_ENA | BMU_OP_ON)
1100 /* Tx BMU Control / Status Registers (Yukon-2) */
1101 /* Bit 31: same as for Rx */
1102 #define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
1103 #define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */
1104 #define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */
1105 /* Bit 10..0: same as for Rx */
1107 /* Q_F 32 bit Flag Register */
1108 #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
1109 #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/
1110 #define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */
1111 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
1112 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
1113 #define F_WM_REACHED BIT_25 /* Watermark reached */
1114 #define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
1115 #define F_FIFO_LEVEL (0x1f<<16)
1116 /* Bit 23..16: # of Qwords in FIFO */
1117 #define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */
1119 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
1120 /* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
1121 #define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */
1122 #define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */
1123 #define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */
1124 #define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
1126 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
1127 /* RB_START 32 bit RAM Buffer Start Address */
1128 /* RB_END 32 bit RAM Buffer End Address */
1129 /* RB_WP 32 bit RAM Buffer Write Pointer */
1130 /* RB_RP 32 bit RAM Buffer Read Pointer */
1131 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
1132 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
1133 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
1134 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
1135 /* RB_PC 32 bit RAM Buffer Packet Counter */
1136 /* RB_LEV 32 bit RAM Buffer Level Register */
1137 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
1139 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
1140 #define RB_PC_DEC BIT_3 /* Packet Counter Decrement */
1141 #define RB_PC_T_ON BIT_2 /* Packet Counter Test On */
1142 #define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */
1143 #define RB_PC_INC BIT_0 /* Packet Counter Increment */
1145 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
1146 #define RB_WP_T_ON BIT_6 /* Write Pointer Test On */
1147 #define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */
1148 #define RB_WP_INC BIT_4 /* Write Pointer Increment */
1149 #define RB_RP_T_ON BIT_2 /* Read Pointer Test On */
1150 #define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */
1151 #define RB_RP_INC BIT_0 /* Read Pointer Increment */
1153 /* RB_CTRL 8 bit RAM Buffer Control Register */
1154 #define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */
1155 #define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */
1156 #define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */
1157 #define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */
1158 #define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */
1159 #define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */
1161 /* RAM Buffer High Pause Threshold values */
1162 #define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */
1163 #define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */
1164 #define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
1166 /* Threshold values for Yukon-EC Ultra */
1167 #define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */
1168 #define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */
1169 #define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */
1170 #define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */
1171 #define MSK_ECU_JUMBO_WM 0x01
1173 #define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
1174 #define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
1175 /* performance sensitive drivers should set this define to 0x80 */
1176 #define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
1178 /* Receive and Transmit Queues */
1179 #define Q_R1 0x0000 /* Receive Queue 1 */
1180 #define Q_R2 0x0080 /* Receive Queue 2 */
1181 #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */
1182 #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */
1183 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
1184 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
1186 #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
1187 #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
1188 #define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
1189 #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
1191 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
1193 /* Minimum RAM Buffer Rx Queue Size */
1194 #define MSK_MIN_RXQ_SIZE 10
1195 /* Minimum RAM Buffer Tx Queue Size */
1196 #define MSK_MIN_TXQ_SIZE 10
1197 /* Percentage of queue size from whole memory. 80 % for receive */
1198 #define MSK_RAM_QUOTA_RX 80
1200 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1201 #define WOL_CTL_LINK_CHG_OCC BIT_15
1202 #define WOL_CTL_MAGIC_PKT_OCC BIT_14
1203 #define WOL_CTL_PATTERN_OCC BIT_13
1204 #define WOL_CTL_CLEAR_RESULT BIT_12
1205 #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11
1206 #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10
1207 #define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9
1208 #define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8
1209 #define WOL_CTL_ENA_PME_ON_PATTERN BIT_7
1210 #define WOL_CTL_DIS_PME_ON_PATTERN BIT_6
1211 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5
1212 #define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4
1213 #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3
1214 #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2
1215 #define WOL_CTL_ENA_PATTERN_UNIT BIT_1
1216 #define WOL_CTL_DIS_PATTERN_UNIT BIT_0
1218 #define WOL_CTL_DEFAULT \
1219 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
1220 WOL_CTL_DIS_PME_ON_PATTERN | \
1221 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
1222 WOL_CTL_DIS_LINK_CHG_UNIT | \
1223 WOL_CTL_DIS_PATTERN_UNIT | \
1224 WOL_CTL_DIS_MAGIC_PKT_UNIT)
1226 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1227 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
1229 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
1230 #define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */
1231 #define WOL_PATT_MATCH_PME_ALL 0x7f
1235 * Marvel-PHY Registers, indirect addressed over GMAC
1237 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */
1238 #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */
1239 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
1240 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
1241 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
1242 #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
1243 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
1244 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
1245 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
1246 /* Marvel-specific registers */
1247 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
1248 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
1249 /* 0x0b - 0x0e: reserved */
1250 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
1251 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
1252 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */
1253 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
1254 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
1255 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
1256 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
1257 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
1258 #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
1259 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
1260 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
1261 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1262 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
1263 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
1264 #define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */
1265 #define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */
1267 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1268 #define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */
1269 #define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */
1270 #define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */
1271 #define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */
1272 #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
1274 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
1275 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
1276 #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */
1277 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
1278 #define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */
1279 #define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */
1280 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
1281 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
1282 #define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */
1283 #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */
1285 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
1286 #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */
1287 #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */
1289 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
1290 #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */
1291 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
1292 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */
1293 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
1294 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
1295 #define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */
1296 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
1298 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
1299 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
1300 #define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */
1302 /* different Marvell PHY Ids */
1303 #define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */
1305 #define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */
1306 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1307 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1308 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1309 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1310 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1312 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1313 #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
1314 #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
1315 #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
1316 #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */
1317 #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
1318 #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
1319 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
1321 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1322 /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
1323 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
1324 #define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */
1325 #define PHY_M_AN_RF BIT_13 /* Remote Fault */
1326 #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
1327 #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
1328 #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */
1329 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
1330 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1331 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-T Full Duplex */
1332 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-T Half Duplex */
1333 #define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
1335 /* special defines for FIBER (88E1011S only) */
1336 #define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
1337 #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
1338 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1339 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1341 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1342 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
1343 #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */
1344 #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */
1345 #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */
1347 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1348 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
1349 #define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */
1350 #define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */
1351 #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */
1352 #define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */
1353 #define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */
1355 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1356 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
1357 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1358 #define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */
1359 #define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */
1360 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
1361 #define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */
1362 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
1363 #define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */
1364 #define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */
1365 #define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */
1366 #define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */
1367 #define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */
1369 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */
1370 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */
1372 #define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
1374 #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
1375 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
1376 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
1378 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1379 #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */
1380 #define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */
1381 #define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */
1382 /* !!! Errata in spec. (1 = disable) */
1384 #define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK)
1385 /* 000=1x; 001=2x; 010=3x; 011=4x */
1386 /* 100=5x; 101=6x; 110=7x; 111=8x */
1388 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1389 #define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */
1390 #define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */
1391 #define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */
1392 #define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */
1393 #define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */
1394 #define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */
1395 #define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */
1396 #define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */
1397 #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
1399 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1400 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
1401 #define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */
1402 #define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */
1403 #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
1404 #define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */
1405 #define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */
1406 #define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */
1407 #define PHY_M_PS_LINK_UP BIT_10 /* Link Up */
1408 #define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
1409 #define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */
1410 #define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */
1411 #define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */
1412 #define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */
1413 #define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */
1414 #define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */
1415 #define PHY_M_PS_JABBER BIT_0 /* Jabber */
1417 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1419 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1420 #define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */
1421 #define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1423 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1424 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1425 #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */
1426 #define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */
1427 #define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */
1428 #define PHY_M_IS_AN_PR BIT_12 /* Page Received */
1429 #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */
1430 #define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */
1431 #define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */
1432 #define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */
1433 #define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */
1434 #define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */
1435 #define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */
1436 #define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */
1437 #define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */
1438 #define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */
1439 #define PHY_M_IS_JABBER BIT_0 /* Jabber */
1441 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
1442 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
1444 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1445 #define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */
1446 #define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */
1447 #define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */
1448 #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */
1449 /* (88E1011 only) */
1450 #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */
1451 /* (88E1011 only) */
1452 #define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */
1453 /* (88E1111 only) */
1454 #define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */
1455 /* !!! Errata in spec. (1 = disable) */
1456 #define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/
1457 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
1458 #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */
1459 #define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */
1460 #define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */
1461 #define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */
1463 #define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
1464 /* 00=1x; 01=2x; 10=3x; 11=4x */
1465 #define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
1466 /* 00=dis; 01=1x; 10=2x; 11=3x */
1467 #define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
1468 /* 01X=0; 110=2.5; 111=25 (MHz) */
1470 #define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
1471 /* 000=1x; 001=2x; 010=3x; 011=4x */
1472 /* 100=5x; 101=6x; 110=7x; 111=8x */
1473 #define MAC_TX_CLK_0_MHZ 2
1474 #define MAC_TX_CLK_2_5_MHZ 6
1475 #define MAC_TX_CLK_25_MHZ 7
1477 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1478 #define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */
1479 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
1480 #define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */
1481 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
1482 #define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */
1483 #define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */
1484 #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
1485 /* (88E1111 only) */
1486 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
1487 /* (88E1011 only) */
1488 #define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */
1489 #define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */
1490 #define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */
1491 #define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */
1492 #define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */
1494 #define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
1496 #define PULS_NO_STR 0 /* no pulse stretching */
1497 #define PULS_21MS 1 /* 21 ms to 42 ms */
1498 #define PULS_42MS 2 /* 42 ms to 84 ms */
1499 #define PULS_84MS 3 /* 84 ms to 170 ms */
1500 #define PULS_170MS 4 /* 170 ms to 340 ms */
1501 #define PULS_340MS 5 /* 340 ms to 670 ms */
1502 #define PULS_670MS 6 /* 670 ms to 1.3 s */
1503 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */
1505 #define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
1507 #define BLINK_42MS 0 /* 42 ms */
1508 #define BLINK_84MS 1 /* 84 ms */
1509 #define BLINK_170MS 2 /* 170 ms */
1510 #define BLINK_340MS 3 /* 340 ms */
1511 #define BLINK_670MS 4 /* 670 ms */
1513 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1514 #define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */
1515 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
1516 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
1517 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
1518 #define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */
1519 #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */
1520 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */
1522 #define MO_LED_NORM 0
1523 #define MO_LED_BLINK 1
1524 #define MO_LED_OFF 2
1527 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1528 #define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */
1529 #define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */
1530 #define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */
1531 #define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */
1532 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
1534 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1535 #define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */
1536 #define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */
1537 #define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */
1538 #define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */
1539 #define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */
1540 #define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */
1541 #define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */
1542 /* (88E1111 only) */
1543 #define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */
1544 #define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */
1545 #define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1547 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1548 #define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */
1549 #define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */
1550 /* (88E1111 only) */
1551 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
1552 #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
1553 /* (88E1111 only) */
1554 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
1556 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1557 #define CABD_STAT_NORMAL 0
1558 #define CABD_STAT_SHORT 1
1559 #define CABD_STAT_OPEN 2
1560 #define CABD_STAT_FAIL 3
1562 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1563 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1564 #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
1565 #define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
1566 #define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
1568 #define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK)
1569 #define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK)
1570 #define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK)
1572 #define LED_PAR_CTRL_COLX 0x00
1573 #define LED_PAR_CTRL_ERROR 0x01
1574 #define LED_PAR_CTRL_DUPLEX 0x02
1575 #define LED_PAR_CTRL_DP_COL 0x03
1576 #define LED_PAR_CTRL_SPEED 0x04
1577 #define LED_PAR_CTRL_LINK 0x05
1578 #define LED_PAR_CTRL_TX 0x06
1579 #define LED_PAR_CTRL_RX 0x07
1580 #define LED_PAR_CTRL_ACT 0x08
1581 #define LED_PAR_CTRL_LNK_RX 0x09
1582 #define LED_PAR_CTRL_LNK_AC 0x0a
1583 #define LED_PAR_CTRL_ACT_BL 0x0b
1584 #define LED_PAR_CTRL_TX_BL 0x0c
1585 #define LED_PAR_CTRL_RX_BL 0x0d
1586 #define LED_PAR_CTRL_COL_BL 0x0e
1587 #define LED_PAR_CTRL_INACT 0x0f
1589 /***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1590 #define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */
1591 #define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */
1592 #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
1594 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1595 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1596 #define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */
1597 #define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */
1598 #define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */
1600 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1601 #define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
1602 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
1603 #define PHY_M_MAC_MD_COPPER 5 /* Copper only */
1604 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
1605 #define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK)
1607 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1608 #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
1609 #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
1610 #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1611 #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1613 #define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
1614 #define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
1615 #define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
1616 #define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
1618 /***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/
1619 #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
1620 #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1621 #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1622 #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1623 #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1624 #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1626 #define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
1627 #define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
1628 #define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK)
1629 #define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK)
1630 #define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK)
1631 #define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK)
1636 * The GMAC registers are 16 or 32 bits wide.
1637 * The GMACs host processor interface is 16 bits wide,
1638 * therefore ALL registers will be addressed with 16 bit accesses.
1640 * Note: NA reg = Network Address e.g DA, SA etc.
1643 /* Port Registers */
1644 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */
1645 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */
1646 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */
1647 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */
1648 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1649 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */
1650 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */
1652 /* Source Address Registers */
1653 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */
1654 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */
1655 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */
1656 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */
1657 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */
1658 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */
1660 /* Multicast Address Hash Registers */
1661 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */
1662 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */
1663 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */
1664 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */
1666 /* Interrupt Source Registers */
1667 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */
1668 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1669 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1671 /* Interrupt Mask Registers */
1672 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1673 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1674 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1676 /* Serial Management Interface (SMI) Registers */
1677 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */
1678 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */
1679 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */
1682 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1683 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1686 * MIB Counters base address definitions (low word) -
1687 * use offset 4 for access to high word (32 bit r/o)
1689 #define GM_RXF_UC_OK \
1690 (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */
1691 #define GM_RXF_BC_OK \
1692 (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */
1693 #define GM_RXF_MPAUSE \
1694 (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */
1695 #define GM_RXF_MC_OK \
1696 (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */
1697 #define GM_RXF_FCS_ERR \
1698 (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */
1699 #define GM_RXO_OK_LO \
1700 (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */
1701 #define GM_RXO_OK_HI \
1702 (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */
1703 #define GM_RXO_ERR_LO \
1704 (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */
1705 #define GM_RXO_ERR_HI \
1706 (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */
1707 #define GM_RXF_SHT \
1708 (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */
1709 #define GM_RXE_FRAG \
1710 (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */
1711 #define GM_RXF_64B \
1712 (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */
1713 #define GM_RXF_127B \
1714 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1715 #define GM_RXF_255B \
1716 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1717 #define GM_RXF_511B \
1718 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1719 #define GM_RXF_1023B \
1720 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1721 #define GM_RXF_1518B \
1722 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1723 #define GM_RXF_MAX_SZ \
1724 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1725 #define GM_RXF_LNG_ERR \
1726 (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */
1727 #define GM_RXF_JAB_PKT \
1728 (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */
1729 #define GM_RXE_FIFO_OV \
1730 (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */
1731 #define GM_TXF_UC_OK \
1732 (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */
1733 #define GM_TXF_BC_OK \
1734 (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */
1735 #define GM_TXF_MPAUSE \
1736 (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */
1737 #define GM_TXF_MC_OK \
1738 (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */
1739 #define GM_TXO_OK_LO \
1740 (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */
1741 #define GM_TXO_OK_HI \
1742 (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */
1743 #define GM_TXF_64B \
1744 (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */
1745 #define GM_TXF_127B \
1746 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1747 #define GM_TXF_255B \
1748 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1749 #define GM_TXF_511B \
1750 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1751 #define GM_TXF_1023B \
1752 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1753 #define GM_TXF_1518B \
1754 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1755 #define GM_TXF_MAX_SZ \
1756 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1757 #define GM_TXF_COL \
1758 (GM_MIB_CNT_BASE + 304) /* Tx Collision */
1759 #define GM_TXF_LAT_COL \
1760 (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */
1761 #define GM_TXF_ABO_COL \
1762 (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */
1763 #define GM_TXF_MUL_COL \
1764 (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */
1765 #define GM_TXF_SNG_COL \
1766 (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */
1767 #define GM_TXE_FIFO_UR \
1768 (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */
1770 /*----------------------------------------------------------------------------*/
1772 * GMAC Bit Definitions
1774 * If the bit access behaviour differs from the register access behaviour
1775 * (r/w, r/o) this is documented after the bit number.
1776 * The following bit access behaviours are used:
1777 * (sc) self clearing
1781 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1782 #define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */
1783 #define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */
1784 #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */
1785 #define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */
1786 #define GM_GPSR_PAUSE BIT_11 /* Pause State */
1787 #define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */
1788 #define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occured */
1789 #define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occured */
1790 #define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */
1791 #define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */
1792 #define GM_GPSR_PART_MODE BIT_3 /* Partition mode */
1793 #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */
1795 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1796 #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */
1797 #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */
1798 #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */
1799 #define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */
1800 #define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */
1801 #define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */
1802 #define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */
1803 #define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */
1804 #define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */
1805 #define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */
1806 #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */
1807 #define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */
1808 #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */
1809 #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */
1810 #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
1812 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1813 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
1816 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1817 #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */
1818 #define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */
1819 #define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */
1820 #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */
1821 #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
1822 /* (Yukon-2 only) */
1824 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
1825 #define TX_COL_DEF 0x04
1827 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1828 #define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */
1829 #define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */
1830 #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */
1831 #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */
1833 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1834 #define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */
1835 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
1836 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
1837 #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
1838 /* (Yukon-2 only) */
1840 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
1841 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
1842 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
1843 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1845 #define TX_JAM_LEN_DEF 0x03
1846 #define TX_JAM_IPG_DEF 0x0b
1847 #define TX_IPG_JAM_DEF 0x1c
1848 #define TX_BOF_LIM_DEF 0x04
1850 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1851 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
1852 /* r/o on Yukon, r/w on Yukon-EC */
1853 #define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */
1854 #define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */
1855 #define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */
1856 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
1858 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK)
1859 #define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK)
1861 #define DATA_BLIND_DEF 0x04
1862 #define IPG_DATA_DEF 0x1e
1864 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1865 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
1866 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
1867 #define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/
1868 #define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */
1869 #define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */
1871 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
1872 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
1874 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1875 #define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */
1876 #define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */
1878 /* Receive Frame Status Encoding */
1879 #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */
1880 #define GMR_FS_VLAN BIT_13 /* VLAN Packet */
1881 #define GMR_FS_JABBER BIT_12 /* Jabber Packet */
1882 #define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */
1883 #define GMR_FS_MC BIT_10 /* Multicast Packet */
1884 #define GMR_FS_BC BIT_9 /* Broadcast Packet */
1885 #define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */
1886 #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
1887 #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
1888 #define GMR_FS_MII_ERR BIT_5 /* MII Error */
1889 #define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */
1890 #define GMR_FS_FRAGMENT BIT_3 /* Fragment */
1891 #define GMR_FS_CRC_ERR BIT_1 /* CRC Error */
1892 #define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
1894 #define GMR_FS_LEN_SHIFT 16
1896 #define GMR_FS_ANY_ERR ( \
1906 /* Rx GMAC FIFO Flush Mask (default) */
1907 #define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR
1909 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
1911 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
1912 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
1913 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
1914 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
1915 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
1916 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
1917 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1918 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
1919 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
1920 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
1921 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
1922 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
1923 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
1924 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
1926 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1927 #define RX_TRUNC_ON BIT_27 /* enable packet truncation */
1928 #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */
1929 #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */
1930 #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */
1931 #define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */
1932 #define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */
1933 #define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */
1934 #define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */
1935 #define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
1936 #define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
1937 #define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
1938 #define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
1939 #define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
1940 #define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
1941 #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
1942 #define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
1943 #define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
1944 #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
1945 #define GMF_OPER_ON BIT_3 /* Operational Mode On */
1946 #define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
1947 #define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
1948 #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
1950 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1951 #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
1952 #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
1953 #define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */
1954 #define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */
1955 #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */
1956 #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */
1957 #define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
1958 #define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
1959 #define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
1960 /* Bits 15..8: same as for RX_GMF_CTRL_T */
1961 #define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
1962 #define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
1963 #define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
1964 /* Bits 3..0: same as for RX_GMF_CTRL_T */
1966 #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON)
1967 #define GMF_TX_CTRL_DEF GMF_OPER_ON
1969 #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
1970 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
1972 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1973 #define GMT_ST_START BIT_2 /* Start Time Stamp Timer */
1974 #define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */
1975 #define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */
1977 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
1978 #define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
1979 #define PC_POLL_RQ BIT_4 /* Poll Request Start */
1980 #define PC_POLL_OP_ON BIT_3 /* Operational Mode On */
1981 #define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */
1982 #define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
1983 #define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
1985 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1986 /* This register is used by the host driver software */
1987 #define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */
1988 #define Y2_ASF_RESET BIT_3 /* ASF system in reset state */
1989 #define Y2_ASF_RUNNING BIT_2 /* ASF system operational */
1990 #define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */
1991 #define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */
1993 #define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
1994 #define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
1996 /* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */
1997 #define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */
1998 #define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */
1999 #define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */
2000 #define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */
2001 #define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */
2002 #define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */
2003 #define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */
2004 #define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */
2005 #define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5
2006 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4
2007 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3
2008 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */
2009 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3
2010 #define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */
2011 /* Microcontroller State */
2012 #define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3
2013 #define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0
2014 #define Y2_ASF_HCU_CCSR_ASF_RESET 0
2015 #define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1
2016 #define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0
2018 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
2019 /* This register is used by the ASF firmware */
2020 #define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
2021 #define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
2023 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2024 #define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */
2025 #define SC_STAT_OP_ON BIT_3 /* Operational Mode On */
2026 #define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */
2027 #define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
2028 #define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
2030 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2031 #define GMC_SEC_RST BIT_15 /* MAC SEC RST */
2032 #define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */
2033 #define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */
2034 #define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */
2035 #define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */
2036 #define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */
2037 #define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */
2038 #define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */
2039 #define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
2040 #define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
2041 #define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
2042 #define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
2043 #define GMC_PAUSE_ON BIT_3 /* Pause On */
2044 #define GMC_PAUSE_OFF BIT_2 /* Pause Off */
2045 #define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
2046 #define GMC_RST_SET BIT_0 /* Set GMAC Reset */
2048 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2049 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
2050 #define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */
2051 #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */
2052 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */
2053 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */
2054 #define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */
2055 #define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */
2056 #define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */
2057 #define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */
2058 #define GPC_ANEG_0 BIT_19 /* ANEG[0] */
2059 #define GPC_ENA_XC BIT_18 /* Enable MDI crossover */
2060 #define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */
2061 #define GPC_ANEG_3 BIT_16 /* ANEG[3] */
2062 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */
2063 #define GPC_ANEG_1 BIT_14 /* ANEG[1] */
2064 #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
2065 #define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */
2066 #define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
2067 #define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */
2068 #define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */
2069 #define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
2070 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
2071 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
2073 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
2074 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2075 #define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */
2076 #define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */
2077 #define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */
2078 #define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */
2079 #define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
2080 #define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
2082 #define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR)
2084 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2085 #define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */
2086 #define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */
2088 #define MSK_PORT_A 0
2089 #define MSK_PORT_B 1
2091 /* Register access macros */
2092 #define CSR_WRITE_4(sc, reg, val) \
2093 bus_space_write_4((sc)->msk_res_bt, (sc)->msk_res_bh, (reg), (val))
2094 #define CSR_WRITE_2(sc, reg, val) \
2095 bus_space_write_2((sc)->msk_res_bt, (sc)->msk_res_bh, (reg), (val))
2096 #define CSR_WRITE_1(sc, reg, val) \
2097 bus_space_write_1((sc)->msk_res_bt, (sc)->msk_res_bh, (reg), (val))
2099 #define CSR_READ_4(sc, reg) \
2100 bus_space_read_4((sc)->msk_res_bt, (sc)->msk_res_bh, (reg))
2101 #define CSR_READ_2(sc, reg) \
2102 bus_space_read_2((sc)->msk_res_bt, (sc)->msk_res_bh, (reg))
2103 #define CSR_READ_1(sc, reg) \
2104 bus_space_read_1((sc)->msk_res_bt, (sc)->msk_res_bh, (reg))
2106 #define CSR_PCI_WRITE_4(sc, reg, val) \
2107 bus_space_write_4((sc)->msk_res_bt, (sc)->msk_res_bh, \
2108 Y2_CFG_SPC + (reg), (val))
2109 #define CSR_PCI_WRITE_2(sc, reg, val) \
2110 bus_space_write_2((sc)->msk_res_bt, (sc)->msk_res_bh, \
2111 Y2_CFG_SPC + (reg), (val))
2112 #define CSR_PCI_WRITE_1(sc, reg, val) \
2113 bus_space_write_1((sc)->msk_res_bt, (sc)->msk_res_bh, \
2114 Y2_CFG_SPC + (reg), (val))
2116 #define CSR_PCI_READ_4(sc, reg) \
2117 bus_space_read_4((sc)->msk_res_bt, (sc)->msk_res_bh, Y2_CFG_SPC + (reg))
2118 #define CSR_PCI_READ_2(sc, reg) \
2119 bus_space_read_2((sc)->msk_res_bt, (sc)->msk_res_bh, Y2_CFG_SPC + (reg))
2120 #define CSR_PCI_READ_1(sc, reg) \
2121 bus_space_read_1((sc)->msk_res_bt, (sc)->msk_res_bh, Y2_CFG_SPC + (reg))
2123 #define MSK_IF_READ_4(sc_if, reg) \
2124 CSR_READ_4((sc_if)->msk_softc, (reg))
2125 #define MSK_IF_READ_2(sc_if, reg) \
2126 CSR_READ_2((sc_if)->msk_softc, (reg))
2127 #define MSK_IF_READ_1(sc_if, reg) \
2128 CSR_READ_1((sc_if)->msk_softc, (reg))
2130 #define MSK_IF_WRITE_4(sc_if, reg, val) \
2131 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))
2132 #define MSK_IF_WRITE_2(sc_if, reg, val) \
2133 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
2134 #define MSK_IF_WRITE_1(sc_if, reg, val) \
2135 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
2137 #define GMAC_REG(port, reg) \
2138 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
2139 #define GMAC_WRITE_2(sc, port, reg, val) \
2140 CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))
2141 #define GMAC_READ_2(sc, port, reg) \
2142 CSR_READ_2((sc), GMAC_REG((port), (reg)))
2144 /* GPHY address (bits 15..11 of SMI control reg) */
2145 #define PHY_ADDR_MARV 0
2147 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL)
2148 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32)
2151 * At first I guessed 8 bytes, the size of a single descriptor, would be
2152 * required alignment constraints. But, it seems that Yukon II have 4096
2153 * bytes boundary alignment constraints.
2155 #define MSK_RING_ALIGN 4096
2156 #define MSK_STAT_ALIGN 4096
2158 /* Rx descriptor data structure */
2159 struct msk_rx_desc {
2161 uint32_t msk_control;
2164 /* Tx descriptor data structure */
2165 struct msk_tx_desc {
2167 uint32_t msk_control;
2170 /* Status descriptor data structure */
2171 struct msk_stat_desc {
2172 uint32_t msk_status;
2173 uint32_t msk_control;
2176 /* mask and shift value to get Tx async queue status for port 1 */
2177 #define STLE_TXA1_MSKL 0x00000fff
2178 #define STLE_TXA1_SHIFTL 0
2180 /* mask and shift value to get Tx sync queue status for port 1 */
2181 #define STLE_TXS1_MSKL 0x00fff000
2182 #define STLE_TXS1_SHIFTL 12
2184 /* mask and shift value to get Tx async queue status for port 2 */
2185 #define STLE_TXA2_MSKL 0xff000000
2186 #define STLE_TXA2_SHIFTL 24
2187 #define STLE_TXA2_MSKH 0x000f
2188 /* this one shifts up */
2189 #define STLE_TXA2_SHIFTH 8
2191 /* mask and shift value to get Tx sync queue status for port 2 */
2192 #define STLE_TXS2_MSKL 0x00000000
2193 #define STLE_TXS2_SHIFTL 0
2194 #define STLE_TXS2_MSKH 0xfff0
2195 #define STLE_TXS2_SHIFTH 4
2197 /* YUKON-2 bit values */
2198 #define HW_OWNER 0x80000000
2199 #define SW_OWNER 0x00000000
2201 #define PU_PUTIDX_VALID 0x10000000
2203 /* YUKON-2 Control flags */
2204 #define UDPTCP 0x00010000
2205 #define CALSUM 0x00020000
2206 #define WR_SUM 0x00040000
2207 #define INIT_SUM 0x00080000
2208 #define LOCK_SUM 0x00100000
2209 #define INS_VLAN 0x00200000
2210 #define FRC_STAT 0x00400000
2211 #define EOP 0x00800000
2213 #define TX_LOCK 0x01000000
2214 #define BUF_SEND 0x02000000
2215 #define PACKET_SEND 0x04000000
2217 #define NO_WARNING 0x40000000
2218 #define NO_UPDATE 0x80000000
2220 /* YUKON-2 Rx/Tx opcodes defines */
2221 #define OP_TCPWRITE 0x11000000
2222 #define OP_TCPSTART 0x12000000
2223 #define OP_TCPINIT 0x14000000
2224 #define OP_TCPLCK 0x18000000
2225 #define OP_TCPCHKSUM OP_TCPSTART
2226 #define OP_TCPIS (OP_TCPINIT | OP_TCPSTART)
2227 #define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE)
2228 #define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
2229 #define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
2230 #define OP_ADDR64 0x21000000
2231 #define OP_VLAN 0x22000000
2232 #define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN)
2233 #define OP_LRGLEN 0x24000000
2234 #define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN)
2235 #define OP_BUFFER 0x40000000
2236 #define OP_PACKET 0x41000000
2237 #define OP_LARGESEND 0x43000000
2239 /* YUKON-2 STATUS opcodes defines */
2240 #define OP_RXSTAT 0x60000000
2241 #define OP_RXTIMESTAMP 0x61000000
2242 #define OP_RXVLAN 0x62000000
2243 #define OP_RXCHKS 0x64000000
2244 #define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN)
2245 #define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN)
2246 #define OP_RSS_HASH 0x65000000
2247 #define OP_TXINDEXLE 0x68000000
2249 /* YUKON-2 SPECIAL opcodes defines */
2250 #define OP_PUTIDX 0x70000000
2252 #define STLE_OP_MASK 0xff000000
2253 #define STLE_CSS_MASK 0x00ff0000
2254 #define STLE_LEN_MASK 0x0000ffff
2256 /* CSS defined in status LE(valid for descriptor V2 format). */
2257 #define CSS_TCPUDP_CSUM_OK 0x00800000
2258 #define CSS_UDP 0x00400000
2259 #define CSS_TCP 0x00200000
2260 #define CSS_IPFRAG 0x00100000
2261 #define CSS_IPV6 0x00080000
2262 #define CSS_IPV4_CSUM_OK 0x00040000
2263 #define CSS_IPV4 0x00020000
2264 #define CSS_PORT 0x00010000
2266 /* Descriptor Bit Definition */
2267 /* TxCtrl Transmit Buffer Control Field */
2268 /* RxCtrl Receive Buffer Control Field */
2269 #define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */
2270 #define BMU_STF BIT_30 /* Start of Frame */
2271 #define BMU_EOF BIT_29 /* End of Frame */
2272 #define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */
2273 #define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */
2274 /* TxCtrl specific bits */
2275 #define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */
2276 #define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */
2277 #define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */
2278 /* RxCtrl specific bits */
2279 #define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */
2280 #define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */
2281 #define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */
2282 /* Bit 23..16: BMU Check Opcodes */
2283 #define BMU_CHECK (0x55<<16) /* Default BMU check */
2284 #define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */
2285 #define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */
2286 #define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */
2288 #define MSK_TX_RING_CNT 256
2289 #define MSK_RX_RING_CNT 256
2290 #define MSK_RX_BUF_ALIGN 8
2291 #define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT
2292 #define MSK_STAT_RING_CNT ((1 + 3) * (MSK_TX_RING_CNT + MSK_RX_RING_CNT))
2293 #define MSK_MAXTXSEGS 32
2294 #define MSK_MAXSGSIZE 4096
2295 #define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header))
2296 #define MSK_MAXRXSEGS 32
2299 * It seems that the hardware requires extra decriptors(LEs) to offload
2300 * TCP/UDP checksum, VLAN hardware tag inserstion and TSO.
2302 * 1 descriptor for TCP/UDP checksum offload.
2303 * 1 descriptor VLAN hardware tag insertion.
2304 * 1 descriptor for TSO(TCP Segmentation Offload)
2305 * 1 descriptor for 64bits DMA : Not applicatable due to the use of
2306 * BUS_SPACE_MAXADDR_32BIT in parent DMA tag creation.
2308 #define MSK_RESERVED_TX_DESC_CNT 3
2311 * Jumbo buffer stuff. Note that we must allocate more jumbo
2312 * buffers than there are descriptors in the receive ring. This
2313 * is because we don't know how long it will take for a packet
2314 * to be released after we hand it off to the upper protocol
2315 * layers. To be safe, we allocate 1.5 times the number of
2316 * receive descriptors.
2318 #define MSK_JUMBO_FRAMELEN 9022
2319 #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2320 #define MSK_MAX_FRAMELEN \
2321 (ETHER_MAX_LEN + EVL_ENCAPLEN - ETHER_CRC_LEN)
2322 #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
2323 #define MSK_JSLOTS ((MSK_RX_RING_CNT * 3) / 2)
2325 #define MSK_JRAWLEN (MSK_JUMBO_FRAMELEN + ETHER_ALIGN)
2326 #define MSK_JLEN (MSK_JRAWLEN + (sizeof(uint64_t) - \
2327 (MSK_JRAWLEN % sizeof(uint64_t))))
2328 #define MSK_JPAGESZ PAGE_SIZE
2330 (MSK_JPAGESZ - (MSK_JLEN * MSK_JSLOTS) % MSK_JPAGESZ)
2331 #define MSK_JMEM ((MSK_JLEN * MSK_JSLOTS) + MSK_RESID)
2333 struct msk_jpool_entry {
2335 SLIST_ENTRY(msk_jpool_entry) jpool_entries;
2340 bus_dmamap_t tx_dmamap;
2341 struct msk_tx_desc *tx_le;
2346 bus_dmamap_t rx_dmamap;
2347 struct msk_rx_desc *rx_le;
2350 struct msk_chain_data {
2351 bus_dma_tag_t msk_parent_tag;
2352 bus_dma_tag_t msk_tx_tag;
2353 struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT];
2354 bus_dma_tag_t msk_rx_tag;
2355 struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT];
2356 bus_dma_tag_t msk_tx_ring_tag;
2357 bus_dma_tag_t msk_rx_ring_tag;
2358 bus_dmamap_t msk_tx_ring_map;
2359 bus_dmamap_t msk_rx_ring_map;
2360 bus_dmamap_t msk_rx_sparemap;
2362 bus_dma_tag_t msk_jumbo_rx_tag;
2363 bus_dma_tag_t msk_jumbo_tag;
2364 bus_dmamap_t msk_jumbo_map;
2365 bus_dma_tag_t msk_jumbo_mtag;
2366 caddr_t msk_jslots[MSK_JSLOTS];
2367 struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT];
2368 bus_dma_tag_t msk_jumbo_rx_ring_tag;
2369 bus_dmamap_t msk_jumbo_rx_ring_map;
2370 bus_dmamap_t msk_jumbo_rx_sparemap;
2381 struct msk_ring_data {
2382 struct msk_tx_desc *msk_tx_ring;
2383 bus_addr_t msk_tx_ring_paddr;
2384 struct msk_rx_desc *msk_rx_ring;
2385 bus_addr_t msk_rx_ring_paddr;
2386 struct msk_rx_desc *msk_jumbo_rx_ring;
2387 bus_addr_t msk_jumbo_rx_ring_paddr;
2388 void *msk_jumbo_buf;
2389 bus_addr_t msk_jumbo_buf_paddr;
2392 #define MSK_TX_RING_ADDR(sc, i) \
2393 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i))
2394 #define MSK_RX_RING_ADDR(sc, i) \
2395 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2396 #define MSK_JUMBO_RX_RING_ADDR(sc, i) \
2397 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2399 #define MSK_TX_RING_SZ \
2400 (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT)
2401 #define MSK_RX_RING_SZ \
2402 (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT)
2403 #define MSK_JUMBO_RX_RING_SZ \
2404 (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT)
2405 #define MSK_STAT_RING_SZ \
2406 (sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT)
2408 #define MSK_INC(x, y) (x) = (x + 1) % y
2410 #define MSK_PCI_BUS 0
2411 #define MSK_PCIX_BUS 1
2412 #define MSK_PEX_BUS 2
2414 #define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2)
2415 #define MSK_PROC_MIN 30
2416 #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1)
2418 #define MSK_TX_TIMEOUT 5
2419 #define MSK_PUT_WM 10
2422 struct msk_if_softc;
2424 /* Softc for the Marvell Yukon II controller. */
2430 struct resource *msk_res; /* I/O port/mem resource */
2431 bus_space_tag_t msk_res_bt;
2432 bus_space_handle_t msk_res_bh;
2435 struct resource *msk_irq; /* IRQ resources */
2436 void *msk_intrhand; /* irq handler handle */
2440 uint8_t msk_bustype;
2441 uint8_t msk_num_port;
2442 int msk_ramsize; /* amount of SRAM on NIC */
2443 uint32_t msk_pmd; /* physical media type */
2444 uint32_t msk_coppertype;
2445 uint32_t msk_intrmask;
2446 uint32_t msk_intrhwemask;
2447 uint32_t msk_pflags;
2450 struct msk_if_softc *msk_if[2];
2451 device_t msk_devs[2];
2454 int msk_txqstart[2];
2456 int msk_rxqstart[2];
2458 bus_dma_tag_t msk_stat_tag;
2459 bus_dmamap_t msk_stat_map;
2460 struct msk_stat_desc *msk_stat_ring;
2461 bus_addr_t msk_stat_ring_paddr;
2463 struct lwkt_serialize msk_serializer;
2465 struct sysctl_ctx_list msk_sysctl_ctx;
2466 struct sysctl_oid *msk_sysctl_tree;
2471 int msk_process_limit;
2473 int msk_defrag_avoided;
2474 int msk_leading_copied;
2475 int msk_trailing_copied;
2478 #define MSK_USECS(sc, us) ((sc)->msk_clock * (us))
2480 /* Softc for each logical interface. */
2481 struct msk_if_softc {
2482 struct arpcom arpcom;
2483 struct ifnet *msk_ifp; /* interface info */
2484 device_t msk_miibus;
2485 device_t msk_if_dev;
2486 int32_t msk_port; /* port # on controller */
2492 #define MSK_FLAG_FASTETHER 0x0004
2493 #define MSK_FLAG_RAMBUF 0x0010
2494 #define MSK_FLAG_NORXCHK 0x0100
2495 struct callout msk_tick_ch;
2496 uint32_t msk_txq; /* Tx. Async Queue offset */
2497 uint32_t msk_txsq; /* Tx. Syn Queue offset */
2498 uint32_t msk_rxq; /* Rx. Qeueue offset */
2499 struct msk_chain_data msk_cdata;
2500 struct msk_ring_data msk_rdata;
2501 struct msk_softc *msk_softc; /* parent controller */
2504 uint16_t msk_vtag; /* VLAN tag id. */
2506 SLIST_HEAD(__msk_jfreehead, msk_jpool_entry) msk_jfree_listhead;
2507 SLIST_HEAD(__msk_jinusehead, msk_jpool_entry) msk_jinuse_listhead;
2508 struct mtx msk_jlist_mtx;
2512 #define MSK_TIMEOUT 1000
2513 #define MSK_PHY_POWERUP 1
2514 #define MSK_PHY_POWERDOWN 0
2516 #define MSK_SPARE_TX_DESC_CNT 5
2517 #define MSK_IS_OACTIVE(sc_if) \
2518 ((sc_if)->msk_cdata.msk_tx_cnt + \
2519 MSK_RESERVED_TX_DESC_CNT + MSK_SPARE_TX_DESC_CNT > MSK_TX_RING_CNT)