sys/dev/drm/i915/i915_drv.c

   1 /* i915_drv.c -- Intel i915 driver -*- linux-c -*-
   2  * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
   3  */
   4 /*-
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  31  */
  32
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include <drm/drm_pciids.h>
  37 #include "intel_drv.h"
  38
  39 /*               "Specify LVDS channel mode "
  40                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)" */
  41 int i915_lvds_channel_mode __read_mostly = 0;
  42 TUNABLE_INT("drm.i915.lvds_channel_mode", &i915_lvds_channel_mode);
  43
  44 static struct drm_driver driver;
  45
  46 #define INTEL_VGA_DEVICE(id, info_) {           \
  47         .device = id,                           \
  48         .info = info_,                          \
  49 }
  50
  51 static const struct intel_device_info intel_i830_info = {
  52         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
  53         .has_overlay = 1, .overlay_needs_physical = 1,
  54 };
  55
  56 static const struct intel_device_info intel_845g_info = {
  57         .gen = 2,
  58         .has_overlay = 1, .overlay_needs_physical = 1,
  59 };
  60
  61 static const struct intel_device_info intel_i85x_info = {
  62         .gen = 2, .is_i85x = 1, .is_mobile = 1,
  63         .cursor_needs_physical = 1,
  64         .has_overlay = 1, .overlay_needs_physical = 1,
  65 };
  66
  67 static const struct intel_device_info intel_i865g_info = {
  68         .gen = 2,
  69         .has_overlay = 1, .overlay_needs_physical = 1,
  70 };
  71
  72 static const struct intel_device_info intel_i915g_info = {
  73         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
  74         .has_overlay = 1, .overlay_needs_physical = 1,
  75 };
  76 static const struct intel_device_info intel_i915gm_info = {
  77         .gen = 3, .is_mobile = 1,
  78         .cursor_needs_physical = 1,
  79         .has_overlay = 1, .overlay_needs_physical = 1,
  80         .supports_tv = 1,
  81 };
  82 static const struct intel_device_info intel_i945g_info = {
  83         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
  84         .has_overlay = 1, .overlay_needs_physical = 1,
  85 };
  86 static const struct intel_device_info intel_i945gm_info = {
  87         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
  88         .has_hotplug = 1, .cursor_needs_physical = 1,
  89         .has_overlay = 1, .overlay_needs_physical = 1,
  90         .supports_tv = 1,
  91 };
  92
  93 static const struct intel_device_info intel_i965g_info = {
  94         .gen = 4, .is_broadwater = 1,
  95         .has_hotplug = 1,
  96         .has_overlay = 1,
  97 };
  98
  99 static const struct intel_device_info intel_i965gm_info = {
 100         .gen = 4, .is_crestline = 1,
 101         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 102         .has_overlay = 1,
 103         .supports_tv = 1,
 104 };
 105
 106 static const struct intel_device_info intel_g33_info = {
 107         .gen = 3, .is_g33 = 1,
 108         .need_gfx_hws = 1, .has_hotplug = 1,
 109         .has_overlay = 1,
 110 };
 111
 112 static const struct intel_device_info intel_g45_info = {
 113         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 114         .has_pipe_cxsr = 1, .has_hotplug = 1,
 115         .has_bsd_ring = 1,
 116 };
 117
 118 static const struct intel_device_info intel_gm45_info = {
 119         .gen = 4, .is_g4x = 1,
 120         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 121         .has_pipe_cxsr = 1, .has_hotplug = 1,
 122         .supports_tv = 1,
 123         .has_bsd_ring = 1,
 124 };
 125
 126 static const struct intel_device_info intel_pineview_info = {
 127         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 128         .need_gfx_hws = 1, .has_hotplug = 1,
 129         .has_overlay = 1,
 130 };
 131
 132 static const struct intel_device_info intel_ironlake_d_info = {
 133         .gen = 5,
 134         .need_gfx_hws = 1, .has_hotplug = 1,
 135         .has_bsd_ring = 1,
 136 };
 137
 138 static const struct intel_device_info intel_ironlake_m_info = {
 139         .gen = 5, .is_mobile = 1,
 140         .need_gfx_hws = 1, .has_hotplug = 1,
 141         .has_fbc = 1,
 142         .has_bsd_ring = 1,
 143 };
 144
 145 static const struct intel_device_info intel_sandybridge_d_info = {
 146         .gen = 6,
 147         .need_gfx_hws = 1, .has_hotplug = 1,
 148         .has_bsd_ring = 1,
 149         .has_blt_ring = 1,
 150         .has_llc = 1,
 151         .has_force_wake = 1,
 152 };
 153
 154 static const struct intel_device_info intel_sandybridge_m_info = {
 155         .gen = 6, .is_mobile = 1,
 156         .need_gfx_hws = 1, .has_hotplug = 1,
 157         .has_fbc = 1,
 158         .has_bsd_ring = 1,
 159         .has_blt_ring = 1,
 160         .has_llc = 1,
 161         .has_force_wake = 1,
 162 };
 163
 164 static const struct intel_device_info intel_ivybridge_d_info = {
 165         .is_ivybridge = 1, .gen = 7,
 166         .need_gfx_hws = 1, .has_hotplug = 1,
 167         .has_bsd_ring = 1,
 168         .has_blt_ring = 1,
 169         .has_llc = 1,
 170         .has_force_wake = 1,
 171 };
 172
 173 static const struct intel_device_info intel_ivybridge_m_info = {
 174         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 175         .need_gfx_hws = 1, .has_hotplug = 1,
 176         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 177         .has_bsd_ring = 1,
 178         .has_blt_ring = 1,
 179         .has_llc = 1,
 180         .has_force_wake = 1,
 181 };
 182
 183 static const struct intel_device_info intel_valleyview_m_info = {
 184         .gen = 7, .is_mobile = 1,
 185         .need_gfx_hws = 1, .has_hotplug = 1,
 186         .has_fbc = 0,
 187         .has_bsd_ring = 1,
 188         .has_blt_ring = 1,
 189         .is_valleyview = 1,
 190 };
 191
 192 static const struct intel_device_info intel_valleyview_d_info = {
 193         .gen = 7,
 194         .need_gfx_hws = 1, .has_hotplug = 1,
 195         .has_fbc = 0,
 196         .has_bsd_ring = 1,
 197         .has_blt_ring = 1,
 198         .is_valleyview = 1,
 199 };
 200
 201 static const struct intel_device_info intel_haswell_d_info = {
 202         .is_haswell = 1, .gen = 7,
 203         .need_gfx_hws = 1, .has_hotplug = 1,
 204         .has_bsd_ring = 1,
 205         .has_blt_ring = 1,
 206         .has_llc = 1,
 207         .has_force_wake = 1,
 208 };
 209
 210 static const struct intel_device_info intel_haswell_m_info = {
 211         .is_haswell = 1, .gen = 7, .is_mobile = 1,
 212         .need_gfx_hws = 1, .has_hotplug = 1,
 213         .has_bsd_ring = 1,
 214         .has_blt_ring = 1,
 215         .has_llc = 1,
 216         .has_force_wake = 1,
 217 };
 218
 219 static const struct intel_gfx_device_id {
 220         int device;
 221         const struct intel_device_info *info;
 222 } pciidlist[] = {               /* aka */
 223         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 224         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 225         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 226         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 227         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 228         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 229         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 230         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 231         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 232         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 233         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 234         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 235         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 236         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 237         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 238         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 239         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 240         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 241         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 242         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 243         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 244         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 245         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 246         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 247         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 248         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 249         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 250         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 251         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 252         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 253         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 254         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 255         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 256         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 257         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 258         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 259         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 260         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 261         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 262         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 263         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 264         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 265         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 266         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
 267         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
 268         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
 269         INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
 270         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
 271         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
 272         INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
 273         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
 274         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
 275         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
 276         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
 277         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
 278         INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
 279         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
 280         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
 281         INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
 282         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
 283         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
 284         INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
 285         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
 286         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
 287         INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
 288         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
 289         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
 290         INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
 291         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
 292         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
 293         INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
 294         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
 295         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
 296         INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
 297         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
 298         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
 299         INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
 300         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
 301         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
 302         INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
 303         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
 304         INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
 305         INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
 306         {0, 0}
 307 };
 308
 309 #define PCI_VENDOR_INTEL        0x8086
 310
 311 void intel_detect_pch(struct drm_device *dev)
 312 {
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314         device_t pch;
 315
 316         /*
 317          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 318          * make graphics device passthrough work easy for VMM, that only
 319          * need to expose ISA bridge to let driver know the real hardware
 320          * underneath. This is a requirement from virtualization team.
 321          */
 322         pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
 323         if (pch) {
 324                 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
 325                         unsigned short id;
 326                         id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
 327                         dev_priv->pch_id = id;
 328
 329                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 330                                 dev_priv->pch_type = PCH_IBX;
 331                                 dev_priv->num_pch_pll = 2;
 332                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 333                                 WARN_ON(!IS_GEN5(dev));
 334                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 335                                 dev_priv->pch_type = PCH_CPT;
 336                                 dev_priv->num_pch_pll = 2;
 337                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 338                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 339                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 340                                 /* PantherPoint is CPT compatible */
 341                                 dev_priv->pch_type = PCH_CPT;
 342                                 dev_priv->num_pch_pll = 2;
 343                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 344                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 345                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 346                                 dev_priv->pch_type = PCH_LPT;
 347                                 dev_priv->num_pch_pll = 0;
 348                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 349                                 WARN_ON(!IS_HASWELL(dev));
 350                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 351                                 dev_priv->pch_type = PCH_LPT;
 352                                 dev_priv->num_pch_pll = 0;
 353                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 354                                 WARN_ON(!IS_HASWELL(dev));
 355                         }
 356                         BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
 357                 }
 358 #if 0
 359                 pci_dev_put(pch);
 360 #endif
 361         }
 362 }
 363
 364 bool i915_semaphore_is_enabled(struct drm_device *dev)
 365 {
 366         if (INTEL_INFO(dev)->gen < 6)
 367                 return 0;
 368
 369         if (i915_semaphores >= 0)
 370                 return i915_semaphores;
 371
 372 #ifdef CONFIG_INTEL_IOMMU
 373         /* Enable semaphores on SNB when IO remapping is off */
 374         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 375                 return false;
 376 #endif
 377
 378         return 1;
 379 }
 380
 381 static int i915_drm_freeze(struct drm_device *dev)
 382 {
 383         struct drm_i915_private *dev_priv = dev->dev_private;
 384
 385         drm_kms_helper_poll_disable(dev);
 386
 387 #if 0
 388         pci_save_state(dev->pdev);
 389 #endif
 390
 391         /* If KMS is active, we do the leavevt stuff here */
 392         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 393                 int error = i915_gem_idle(dev);
 394                 if (error) {
 395                         device_printf(dev->dev,
 396                                 "GEM idle failed, resume might fail");
 397                         return error;
 398                 }
 399                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
 400
 401 #if 0
 402                 intel_modeset_disable(dev);
 403 #endif
 404
 405                 drm_irq_uninstall(dev);
 406         }
 407
 408         i915_save_state(dev);
 409
 410         intel_opregion_fini(dev);
 411
 412         /* Modeset on resume, not lid events */
 413         dev_priv->modeset_on_lid = 0;
 414
 415         return 0;
 416 }
 417
 418 static int
 419 i915_suspend(device_t kdev)
 420 {
 421         struct drm_device *dev;
 422         int error;
 423
 424         dev = device_get_softc(kdev);
 425         if (dev == NULL || dev->dev_private == NULL) {
 426                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 427                 return -ENODEV;
 428         }
 429
 430         DRM_DEBUG_KMS("starting suspend\n");
 431         error = i915_drm_freeze(dev);
 432         if (error)
 433                 return (error);
 434
 435         error = bus_generic_suspend(kdev);
 436         DRM_DEBUG_KMS("finished suspend %d\n", error);
 437         return (error);
 438 }
 439
 440 static int i915_drm_thaw(struct drm_device *dev)
 441 {
 442         struct drm_i915_private *dev_priv = dev->dev_private;
 443         int error = 0;
 444
 445         intel_gt_reset(dev);
 446
 447         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 448                 DRM_LOCK(dev);
 449                 i915_gem_restore_gtt_mappings(dev);
 450                 DRM_UNLOCK(dev);
 451         }
 452
 453         i915_restore_state(dev);
 454         intel_opregion_setup(dev);
 455
 456         /* KMS EnterVT equivalent */
 457         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 458                 intel_init_pch_refclk(dev);
 459
 460                 DRM_LOCK(dev);
 461                 dev_priv->mm.suspended = 0;
 462
 463                 error = i915_gem_init_hw(dev);
 464                 DRM_UNLOCK(dev);
 465
 466                 intel_modeset_init_hw(dev);
 467                 intel_modeset_setup_hw_state(dev, false);
 468                 drm_irq_install(dev);
 469         }
 470
 471         intel_opregion_init(dev);
 472
 473         dev_priv->modeset_on_lid = 0;
 474
 475 #if 0
 476         console_lock();
 477         intel_fbdev_set_suspend(dev, 0);
 478         console_unlock();
 479 #endif
 480         return error;
 481 }
 482
 483 static int
 484 i915_resume(device_t kdev)
 485 {
 486         struct drm_device *dev;
 487         int ret;
 488
 489         dev = device_get_softc(kdev);
 490         DRM_DEBUG_KMS("starting resume\n");
 491 #if 0
 492         if (pci_enable_device(dev->pdev))
 493                 return -EIO;
 494
 495         pci_set_master(dev->pdev);
 496 #endif
 497
 498         ret = -i915_drm_thaw(dev);
 499         if (ret != 0)
 500                 return (ret);
 501
 502         drm_kms_helper_poll_enable(dev);
 503         ret = bus_generic_resume(kdev);
 504         DRM_DEBUG_KMS("finished resume %d\n", ret);
 505         return (ret);
 506 }
 507
 508 /* XXX Hack for the old *BSD drm code base
 509  * The device id field is set at probe time */
 510 static drm_pci_id_list_t i915_attach_list[] = {
 511         {0x8086, 0, 0, "Intel i915 GPU"},
 512         {0, 0, 0, NULL}
 513 };
 514
 515 static int
 516 i915_probe(device_t kdev)
 517 {
 518         int device, i = 0;
 519
 520         if (pci_get_class(kdev) != PCIC_DISPLAY)
 521                 return ENXIO;
 522
 523         if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL)
 524                 return ENXIO;
 525
 526         device = pci_get_device(kdev);
 527
 528         for (i = 0; pciidlist[i].device != 0; i++) {
 529                 if (pciidlist[i].device == device) {
 530                         i915_attach_list[0].device = device;
 531                         return 0;
 532                 }
 533         }
 534
 535         return ENXIO;
 536 }
 537
 538 int i915_modeset;
 539
 540 /* static int __init i915_init(void) */
 541 static int
 542 i915_attach(device_t kdev)
 543 {
 544         struct drm_device *dev;
 545
 546         dev = device_get_softc(kdev);
 547
 548         driver.num_ioctls = i915_max_ioctl;
 549
 550         if (i915_modeset == 1)
 551                 driver.driver_features |= DRIVER_MODESET;
 552
 553         dev->driver = &driver;
 554         return (drm_attach(kdev, i915_attach_list));
 555 }
 556
 557 const struct intel_device_info *
 558 i915_get_device_id(int device)
 559 {
 560         const struct intel_gfx_device_id *did;
 561
 562         for (did = &pciidlist[0]; did->device != 0; did++) {
 563                 if (did->device != device)
 564                         continue;
 565                 return (did->info);
 566         }
 567         return (NULL);
 568 }
 569
 570 static device_method_t i915_methods[] = {
 571         /* Device interface */
 572         DEVMETHOD(device_probe,         i915_probe),
 573         DEVMETHOD(device_attach,        i915_attach),
 574         DEVMETHOD(device_suspend,       i915_suspend),
 575         DEVMETHOD(device_resume,        i915_resume),
 576         DEVMETHOD(device_detach,        drm_detach),
 577         DEVMETHOD_END
 578 };
 579
 580 static driver_t i915_driver = {
 581         "drm",
 582         i915_methods,
 583         sizeof(struct drm_device)
 584 };
 585
 586 extern devclass_t drm_devclass;
 587 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
 588     SI_ORDER_ANY);
 589 MODULE_DEPEND(i915kms, drm, 1, 1, 1);
 590 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
 591 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
 592 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
 593 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
 594
 595 int intel_iommu_enabled = 0;
 596 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
 597
 598 int i915_semaphores = -1;
 599 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
 600 static int i915_try_reset = 1;
 601 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
 602 unsigned int i915_lvds_downclock = 0;
 603 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
 604 int i915_vbt_sdvo_panel_type = -1;
 605 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
 606 unsigned int i915_powersave = 1;
 607 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
 608 int i915_enable_fbc = 0;
 609 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
 610 int i915_enable_rc6 = 0;
 611 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
 612 int i915_panel_use_ssc = -1;
 613 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
 614 int i915_panel_ignore_lid = 0;
 615 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
 616 int i915_modeset = 1;
 617 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
 618 int i915_enable_ppgtt = -1;
 619 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
 620 int i915_enable_hangcheck = 1;
 621 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
 622
 623 static int i8xx_do_reset(struct drm_device *dev)
 624 {
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626
 627         if (IS_I85X(dev))
 628                 return -ENODEV;
 629
 630         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 631         POSTING_READ(D_STATE);
 632
 633         if (IS_I830(dev) || IS_845G(dev)) {
 634                 I915_WRITE(DEBUG_RESET_I830,
 635                            DEBUG_RESET_DISPLAY |
 636                            DEBUG_RESET_RENDER |
 637                            DEBUG_RESET_FULL);
 638                 POSTING_READ(DEBUG_RESET_I830);
 639                 msleep(1);
 640
 641                 I915_WRITE(DEBUG_RESET_I830, 0);
 642                 POSTING_READ(DEBUG_RESET_I830);
 643         }
 644
 645         msleep(1);
 646
 647         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 648         POSTING_READ(D_STATE);
 649
 650         return 0;
 651 }
 652
 653 static int i965_reset_complete(struct drm_device *dev)
 654 {
 655         u8 gdrst;
 656         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 657         return (gdrst & 0x1);
 658 }
 659
 660 static int i965_do_reset(struct drm_device *dev)
 661 {
 662         int ret;
 663         u8 gdrst;
 664
 665         /*
 666          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 667          * well as the reset bit (GR/bit 0).  Setting the GR bit
 668          * triggers the reset; when done, the hardware will clear it.
 669          */
 670         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 671         pci_write_config(dev->dev, I965_GDRST,
 672                               gdrst | GRDOM_RENDER |
 673                               GRDOM_RESET_ENABLE, 1);
 674         ret =  wait_for(i965_reset_complete(dev), 500);
 675         if (ret)
 676                 return ret;
 677
 678         /* We can't reset render&media without also resetting display ... */
 679         gdrst = pci_read_config(dev->dev, I965_GDRST, 1);
 680         pci_write_config(dev->dev, I965_GDRST,
 681                               gdrst | GRDOM_MEDIA |
 682                               GRDOM_RESET_ENABLE, 1);
 683
 684         return wait_for(i965_reset_complete(dev), 500);
 685 }
 686
 687 static int ironlake_do_reset(struct drm_device *dev)
 688 {
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         u32 gdrst;
 691         int ret;
 692
 693         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 694         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 695                    gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
 696         ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 697         if (ret)
 698                 return ret;
 699
 700         /* We can't reset render&media without also resetting display ... */
 701         gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 702         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
 703                    gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 704         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 705 }
 706
 707 static int gen6_do_reset(struct drm_device *dev)
 708 {
 709         struct drm_i915_private *dev_priv = dev->dev_private;
 710         int ret;
 711
 712         dev_priv = dev->dev_private;
 713
 714         /* Hold gt_lock across reset to prevent any register access
 715          * with forcewake not set correctly
 716          */
 717         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
 718
 719         /* Reset the chip */
 720
 721         /* GEN6_GDRST is not in the gt power well, no need to check
 722          * for fifo space for the write or forcewake the chip for
 723          * the read
 724          */
 725         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 726
 727         /* Spin waiting for the device to ack the reset request */
 728         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 729
 730         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 731         if (dev_priv->forcewake_count)
 732                 dev_priv->gt.force_wake_get(dev_priv);
 733         else
 734                 dev_priv->gt.force_wake_put(dev_priv);
 735
 736         /* Restore fifo count */
 737         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 738
 739         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
 740         return ret;
 741 }
 742
 743 int intel_gpu_reset(struct drm_device *dev)
 744 {
 745         struct drm_i915_private *dev_priv = dev->dev_private;
 746         int ret = -ENODEV;
 747
 748         switch (INTEL_INFO(dev)->gen) {
 749         case 7:
 750         case 6:
 751                 ret = gen6_do_reset(dev);
 752                 break;
 753         case 5:
 754                 ret = ironlake_do_reset(dev);
 755                 break;
 756         case 4:
 757                 ret = i965_do_reset(dev);
 758                 break;
 759         case 2:
 760                 ret = i8xx_do_reset(dev);
 761                 break;
 762         }
 763
 764         /* Also reset the gpu hangman. */
 765         if (dev_priv->stop_rings) {
 766                 DRM_DEBUG("Simulated gpu hang, resetting stop_rings\n");
 767                 dev_priv->stop_rings = 0;
 768                 if (ret == -ENODEV) {
 769                         DRM_ERROR("Reset not implemented, but ignoring "
 770                                   "error for simulated gpu hangs\n");
 771                         ret = 0;
 772                 }
 773         }
 774
 775         return ret;
 776 }
 777
 778 /**
 779  * i915_reset - reset chip after a hang
 780  * @dev: drm device to reset
 781  *
 782  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 783  * reset or otherwise an error code.
 784  *
 785  * Procedure is fairly simple:
 786  *   - reset the chip using the reset reg
 787  *   - re-init context state
 788  *   - re-init hardware status page
 789  *   - re-init ring buffer
 790  *   - re-init interrupt state
 791  *   - re-init display
 792  */
 793 int i915_reset(struct drm_device *dev)
 794 {
 795         drm_i915_private_t *dev_priv = dev->dev_private;
 796         int ret;
 797
 798         if (!i915_try_reset)
 799                 return 0;
 800
 801         DRM_LOCK(dev);
 802
 803         i915_gem_reset(dev);
 804
 805         ret = -ENODEV;
 806         if (time_uptime - dev_priv->last_gpu_reset < 5)
 807                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 808         else
 809                 ret = intel_gpu_reset(dev);
 810
 811         dev_priv->last_gpu_reset = time_uptime;
 812         if (ret) {
 813                 DRM_ERROR("Failed to reset chip.\n");
 814                 DRM_UNLOCK(dev);
 815                 return ret;
 816         }
 817
 818         /* Ok, now get things going again... */
 819
 820         /*
 821          * Everything depends on having the GTT running, so we need to start
 822          * there.  Fortunately we don't need to do this unless we reset the
 823          * chip at a PCI level.
 824          *
 825          * Next we need to restore the context, but we don't use those
 826          * yet either...
 827          *
 828          * Ring buffer needs to be re-initialized in the KMS case, or if X
 829          * was running at the time of the reset (i.e. we weren't VT
 830          * switched away).
 831          */
 832         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 833                         !dev_priv->mm.suspended) {
 834                 struct intel_ring_buffer *ring;
 835                 int i;
 836
 837                 dev_priv->mm.suspended = 0;
 838
 839                 i915_gem_init_swizzling(dev);
 840
 841                 for_each_ring(ring, dev_priv, i)
 842                         ring->init(ring);
 843
 844 #if 0   /* XXX: HW context support */
 845                 i915_gem_context_init(dev);
 846 #endif
 847                 i915_gem_init_ppgtt(dev);
 848
 849                 /*
 850                  * It would make sense to re-init all the other hw state, at
 851                  * least the rps/rc6/emon init done within modeset_init_hw. For
 852                  * some unknown reason, this blows up my ilk, so don't.
 853                  */
 854
 855                 DRM_UNLOCK(dev);
 856
 857                 drm_irq_uninstall(dev);
 858                 drm_irq_install(dev);
 859         } else {
 860                 DRM_UNLOCK(dev);
 861         }
 862
 863         return 0;
 864 }
 865
 866 static struct drm_driver driver = {
 867         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
 868             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
 869             DRIVER_GEM /*| DRIVER_MODESET*/,
 870
 871         .buf_priv_size  = sizeof(drm_i915_private_t),
 872         .load           = i915_driver_load,
 873         .open           = i915_driver_open,
 874         .unload         = i915_driver_unload,
 875         .preclose       = i915_driver_preclose,
 876         .lastclose      = i915_driver_lastclose,
 877         .postclose      = i915_driver_postclose,
 878         .device_is_agp  = i915_driver_device_is_agp,
 879         .gem_init_object = i915_gem_init_object,
 880         .gem_free_object = i915_gem_free_object,
 881         .gem_pager_ops  = &i915_gem_pager_ops,
 882         .dumb_create    = i915_gem_dumb_create,
 883         .dumb_map_offset = i915_gem_mmap_gtt,
 884         .dumb_destroy   = i915_gem_dumb_destroy,
 885
 886         .ioctls         = i915_ioctls,
 887
 888         .name           = DRIVER_NAME,
 889         .desc           = DRIVER_DESC,
 890         .date           = DRIVER_DATE,
 891         .major          = DRIVER_MAJOR,
 892         .minor          = DRIVER_MINOR,
 893         .patchlevel     = DRIVER_PATCHLEVEL,
 894 };
 895
 896 /* We give fast paths for the really cool registers */
 897 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
 898         ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
 899          ((reg) < 0x40000) &&            \
 900          ((reg) != FORCEWAKE))
 901
 902 static bool IS_DISPLAYREG(u32 reg)
 903 {
 904         /*
 905          * This should make it easier to transition modules over to the
 906          * new register block scheme, since we can do it incrementally.
 907          */
 908         if (reg >= VLV_DISPLAY_BASE)
 909                 return false;
 910
 911         if (reg >= RENDER_RING_BASE &&
 912             reg < RENDER_RING_BASE + 0xff)
 913                 return false;
 914         if (reg >= GEN6_BSD_RING_BASE &&
 915             reg < GEN6_BSD_RING_BASE + 0xff)
 916                 return false;
 917         if (reg >= BLT_RING_BASE &&
 918             reg < BLT_RING_BASE + 0xff)
 919                 return false;
 920
 921         if (reg == PGTBL_ER)
 922                 return false;
 923
 924         if (reg >= IPEIR_I965 &&
 925             reg < HWSTAM)
 926                 return false;
 927
 928         if (reg == MI_MODE)
 929                 return false;
 930
 931         if (reg == GFX_MODE_GEN7)
 932                 return false;
 933
 934         if (reg == RENDER_HWS_PGA_GEN7 ||
 935             reg == BSD_HWS_PGA_GEN7 ||
 936             reg == BLT_HWS_PGA_GEN7)
 937                 return false;
 938
 939         if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL ||
 940             reg == GEN6_BSD_RNCID)
 941                 return false;
 942
 943         if (reg == GEN6_BLITTER_ECOSKPD)
 944                 return false;
 945
 946         if (reg >= 0x4000c &&
 947             reg <= 0x4002c)
 948                 return false;
 949
 950         if (reg >= 0x4f000 &&
 951             reg <= 0x4f08f)
 952                 return false;
 953
 954         if (reg >= 0x4f100 &&
 955             reg <= 0x4f11f)
 956                 return false;
 957
 958         if (reg >= VLV_MASTER_IER &&
 959             reg <= GEN6_PMIER)
 960                 return false;
 961
 962         if (reg >= FENCE_REG_SANDYBRIDGE_0 &&
 963             reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8)))
 964                 return false;
 965
 966         if (reg >= VLV_IIR_RW &&
 967             reg <= VLV_ISR)
 968                 return false;
 969
 970         if (reg == FORCEWAKE_VLV ||
 971             reg == FORCEWAKE_ACK_VLV)
 972                 return false;
 973
 974         if (reg == GEN6_GDRST)
 975                 return false;
 976
 977         switch (reg) {
 978         case _3D_CHICKEN3:
 979         case IVB_CHICKEN3:
 980         case GEN7_COMMON_SLICE_CHICKEN1:
 981         case GEN7_L3CNTLREG1:
 982         case GEN7_L3_CHICKEN_MODE_REGISTER:
 983         case GEN7_ROW_CHICKEN2:
 984         case GEN7_L3SQCREG4:
 985         case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG:
 986         case GEN7_HALF_SLICE_CHICKEN1:
 987         case GEN6_MBCTL:
 988         case GEN6_UCGCTL2:
 989                 return false;
 990         default:
 991                 break;
 992         }
 993
 994         return true;
 995 }
 996
 997 static void
 998 ilk_dummy_write(struct drm_i915_private *dev_priv)
 999 {
1000         /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1001          * chip from rc6 before touching it for real. MI_MODE is masked, hence
1002          * harmless to write 0 into. */
1003         I915_WRITE_NOTRACE(MI_MODE, 0);
1004 }
1005
1006 #define __i915_read(x, y) \
1007 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1008         u##x val = 0; \
1009         if (IS_GEN5(dev_priv->dev)) \
1010                 ilk_dummy_write(dev_priv); \
1011         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1012                 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); \
1013                 if (dev_priv->forcewake_count == 0) \
1014                         dev_priv->gt.force_wake_get(dev_priv); \
1015                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
1016                 if (dev_priv->forcewake_count == 0) \
1017                         dev_priv->gt.force_wake_put(dev_priv); \
1018                 lockmgr(&dev_priv->gt_lock, LK_RELEASE); \
1019         } else if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1020                 val = DRM_READ##y(dev_priv->mmio_map, reg + 0x180000);  \
1021         } else { \
1022                 val = DRM_READ##y(dev_priv->mmio_map, reg);     \
1023         } \
1024         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1025         return val; \
1026 }
1027
1028 __i915_read(8, 8)
1029 __i915_read(16, 16)
1030 __i915_read(32, 32)
1031 __i915_read(64, 64)
1032 #undef __i915_read
1033
1034 #define __i915_write(x, y) \
1035 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1036         u32 __fifo_ret = 0; \
1037         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1038         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1039                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1040         } \
1041         if (IS_GEN5(dev_priv->dev)) \
1042                 ilk_dummy_write(dev_priv); \
1043         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1044                 DRM_ERROR("Unknown unclaimed register before writing to %x\n", reg); \
1045                 I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
1046         } \
1047         if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \
1048                 DRM_WRITE##y(dev_priv->mmio_map, reg + 0x180000, val);  \
1049         } else {                                                        \
1050                 DRM_WRITE##y(dev_priv->mmio_map, reg, val);             \
1051         }                                                               \
1052         if (unlikely(__fifo_ret)) { \
1053                 gen6_gt_check_fifodbg(dev_priv); \
1054         } \
1055         if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
1056                 DRM_ERROR("Unclaimed write to %x\n", reg); \
1057                 DRM_WRITE32(dev_priv->mmio_map, GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED);  \
1058         } \
1059 }
1060
1061 __i915_write(8, 8)
1062 __i915_write(16, 16)
1063 __i915_write(32, 32)
1064 __i915_write(64, 64)
1065 #undef __i915_write