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38 * EMX_TXD: Maximum number of Transmit Descriptors
39 * Valid Range: 256-4096 for others
41 * This value is the number of transmit descriptors allocated by the driver.
42 * Increasing this value allows the driver to queue more transmits. Each
43 * descriptor is 16 bytes.
44 * Since TDLEN should be multiple of 128bytes, the number of transmit
45 * desscriptors should meet the following condition.
46 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
48 #define EMX_MIN_TXD 256
49 #define EMX_MAX_TXD 4096
50 #define EMX_DEFAULT_TXD 512
53 * EMX_RXD - Maximum number of receive Descriptors
54 * Valid Range: 256-4096 for others
56 * This value is the number of receive descriptors allocated by the driver.
57 * Increasing this value allows the driver to buffer more incoming packets.
58 * Each descriptor is 16 bytes. A receive buffer is also allocated for each
59 * descriptor. The maximum MTU size is 16110.
60 * Since TDLEN should be multiple of 128bytes, the number of transmit
61 * desscriptors should meet the following condition.
62 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
64 #define EMX_MIN_RXD 256
65 #define EMX_MAX_RXD 4096
66 #define EMX_DEFAULT_RXD 512
69 * Receive Interrupt Delay Timer (Packet Timer)
72 * RDTR and RADV are deprecated; use ITR instead. They are only used to
73 * workaround hardware bug on certain 82573 based NICs.
75 #define EMX_RDTR_82573 32
78 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
81 * RDTR and RADV are deprecated; use ITR instead. They are only used to
82 * workaround hardware bug on certain 82573 based NICs.
84 #define EMX_RADV_82573 64
87 * This parameter controls the duration of transmit watchdog timer.
89 #define EMX_TX_TIMEOUT 5
91 /* One for TX csum offloading desc, the other 2 are reserved */
92 #define EMX_TX_RESERVED 3
94 /* Large enough for 64K TSO segment */
95 #define EMX_TX_SPARE 33
97 #define EMX_TX_OACTIVE_MAX 64
99 /* Interrupt throttle rate */
100 #define EMX_DEFAULT_ITR 6000
103 * This parameter controls whether or not autonegotation is enabled.
104 * 0 - Disable autonegotiation
105 * 1 - Enable autonegotiation
107 #define EMX_DO_AUTO_NEG 1
109 /* Tunables -- End */
111 #define EMX_AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | \
112 ADVERTISE_10_FULL | \
113 ADVERTISE_100_HALF | \
114 ADVERTISE_100_FULL | \
117 #define EMX_AUTO_ALL_MODES 0
119 /* PHY master/slave setting */
120 #define EMX_MASTER_SLAVE e1000_ms_hw_default
123 * Micellaneous constants
125 #define EMX_VENDOR_ID 0x8086
127 #define EMX_BAR_MEM PCIR_BAR(0)
129 #define EMX_JUMBO_PBA 0x00000028
130 #define EMX_DEFAULT_PBA 0x00000030
131 #define EMX_SMARTSPEED_DOWNSHIFT 3
132 #define EMX_SMARTSPEED_MAX 15
133 #define EMX_MAX_INTR 10
135 #define EMX_MCAST_ADDR_MAX 128
136 #define EMX_FC_PAUSE_TIME 1000
137 #define EMX_EEPROM_APME 0x400;
140 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
141 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
142 * also optimize cache line size effect. H/W supports up to cache line size 128.
144 #define EMX_DBA_ALIGN 128
147 * Speed mode bit in TARC0/TARC1.
148 * 82571EB/82572EI only, used to improve small packet transmit performance.
150 #define EMX_TARC_SPEED_MODE (1 << 21)
152 #define EMX_MAX_SCATTER 64
153 #define EMX_TSO_SIZE (IP_MAXPACKET + \
154 sizeof(struct ether_vlan_header))
155 #define EMX_MAX_SEGSIZE PAGE_SIZE
156 #define EMX_MSIX_MASK 0x01F00000 /* For 82574 use */
158 #define EMX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
161 * 82574 has a nonstandard address for EIAC
162 * and since its only used in MSIX, and in
163 * the em driver only 82574 uses MSIX we can
164 * solve it just using this define.
166 #define EMX_EIAC 0x000DC
168 #define EMX_NRSSRK 10
169 #define EMX_RSSRK_SIZE 4
170 #define EMX_RSSRK_VAL(key, i) (key[(i) * EMX_RSSRK_SIZE] | \
171 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \
172 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \
173 key[(i) * EMX_RSSRK_SIZE + 3] << 24)
176 #define EMX_RETA_SIZE 4
177 #define EMX_RETA_RINGIDX_SHIFT 7
179 #define EMX_NRX_RING 2
180 #define EMX_NSERIALIZE 4
182 typedef union e1000_rx_desc_extended emx_rxdesc_t;
184 #define rxd_bufaddr read.buffer_addr /* 64bits */
185 #define rxd_length wb.upper.length /* 16bits */
186 #define rxd_vlan wb.upper.vlan /* 16bits */
187 #define rxd_staterr wb.upper.status_error /* 32bits */
188 #define rxd_mrq wb.lower.mrq /* 32bits */
189 #define rxd_rss wb.lower.hi_dword.rss /* 32bits */
191 #define EMX_RXDMRQ_RSSTYPE_MASK 0xf
192 #define EMX_RXDMRQ_NO_HASH 0
193 #define EMX_RXDMRQ_IPV4_TCP 1
194 #define EMX_RXDMRQ_IPV4 2
195 #define EMX_RXDMRQ_IPV6_TCP 3
196 #define EMX_RXDMRQ_IPV6 5
201 struct lwkt_serialize rx_serialize;
202 struct emx_softc *sc;
206 * Receive definitions
208 * we have an array of num_rx_desc rx_desc (handled by the
209 * controller), and paired with an array of rx_buffers
210 * (at rx_buffer_area).
211 * The next pair to check on receive is at offset next_rx_desc_to_check
213 emx_rxdesc_t *rx_desc;
214 uint32_t next_rx_desc_to_check;
216 struct emx_rxbuf *rx_buf;
218 bus_dmamap_t rx_sparemap;
221 * First/last mbuf pointers, for
222 * collecting multisegment RX packets.
228 unsigned long rx_pkts;
230 bus_dma_tag_t rx_desc_dtag;
231 bus_dmamap_t rx_desc_dmap;
232 bus_addr_t rx_desc_paddr;
236 struct lwkt_serialize tx_serialize;
237 struct emx_softc *sc;
241 * Transmit definitions
243 * We have an array of num_tx_desc descriptors (handled
244 * by the controller) paired with an array of tx_buffers
245 * (at tx_buffer_area).
246 * The index of the next available descriptor is next_avail_tx_desc.
247 * The number of remaining tx_desc is num_tx_desc_avail.
249 struct e1000_tx_desc *tx_desc_base;
250 struct emx_txbuf *tx_buf;
251 uint32_t next_avail_tx_desc;
252 uint32_t next_tx_to_clean;
253 int num_tx_desc_avail;
255 bus_dma_tag_t txtag; /* dma tag for tx */
259 /* Saved csum offloading context information */
264 int csum_thlen; /* TSO */
265 int csum_mss; /* TSO */
266 int csum_pktlen; /* TSO */
268 uint32_t csum_txd_upper;
269 uint32_t csum_txd_lower;
272 * Variables used to reduce TX interrupt rate and
273 * number of device's TX ring write requests.
276 * Number of TX descriptors setup so far.
279 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
280 * in the last TX descriptor of the packet, and
281 * tx_nsegs will be reset to 0. So TX interrupt and
282 * TX ring write request should be generated roughly
283 * every tx_int_nsegs TX descriptors.
286 * Index of the TX descriptors which have RS bit set,
287 * i.e. DD bit will be set on this TX descriptor after
288 * the data of the TX descriptor are transfered to
289 * hardware's internal packet buffer. Only the TX
290 * descriptors listed in tx_dd[] will be checked upon
291 * TX interrupt. This array is used as circular ring.
293 * tx_dd_tail, tx_dd_head:
294 * Tail and head index of valid elements in tx_dd[].
295 * tx_dd_tail == tx_dd_head means there is no valid
296 * elements in tx_dd[]. tx_dd_tail points to the position
297 * which is one beyond the last valid element in tx_dd[].
298 * tx_dd_head points to the first valid element in
305 #define EMX_TXDD_MAX 64
306 #define EMX_TXDD_SAFE 48 /* 48 <= val < EMX_TXDD_MAX */
307 int tx_dd[EMX_TXDD_MAX];
310 unsigned long tso_segments;
311 unsigned long tso_ctx_reused;
313 bus_dma_tag_t tx_desc_dtag;
314 bus_dmamap_t tx_desc_dmap;
315 bus_addr_t tx_desc_paddr;
319 struct arpcom arpcom;
322 #define EMX_FLAG_SHARED_INTR 0x0001
323 #define EMX_FLAG_TSO_PULLEX 0x0002
324 #define EMX_FLAG_HAS_MGMT 0x0004
325 #define EMX_FLAG_HAS_AMT 0x0008
326 #define EMX_FLAG_HW_CTRL 0x0010
328 /* DragonFly operating-system-specific structures. */
329 struct e1000_osdep osdep;
332 bus_dma_tag_t parent_dtag;
334 struct resource *memory;
337 struct resource *intr_res;
342 struct ifmedia media;
343 struct callout timer;
348 /* WOL register value */
351 /* Multicast array memory */
354 /* Info about the board itself */
357 uint16_t link_duplex;
359 int int_throttle_ceil;
364 struct lwkt_serialize main_serialize;
365 struct lwkt_serialize *serializes[EMX_NSERIALIZE];
367 struct emx_txdata tx_data;
371 struct emx_rxdata rx_data[EMX_NRX_RING];
373 /* Misc stats maintained by the driver */
374 unsigned long rx_overruns;
376 /* sysctl tree glue */
377 struct sysctl_ctx_list sysctl_ctx;
378 struct sysctl_oid *sysctl_tree;
380 struct e1000_hw_stats stats;
394 #define EMX_IS_OACTIVE(tdata) \
395 ((tdata)->num_tx_desc_avail <= (tdata)->oact_tx_desc)
397 #define EMX_INC_TXDD_IDX(idx) \
399 if (++(idx) == EMX_TXDD_MAX) \
403 #endif /* !_IF_EMX_H_ */