1 @c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2 @c 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
3 @c This is part of the GAS manual.
4 @c For copying conditions, see the file as.texinfo.
9 @chapter ARM Dependent Features
13 @node Machine Dependencies
14 @chapter ARM Dependent Features
20 * ARM Options:: Options
22 * ARM Floating Point:: Floating Point
23 * ARM Directives:: ARM Machine Directives
24 * ARM Opcodes:: Opcodes
25 * ARM Mapping Symbols:: Mapping Symbols
26 * ARM Unwinding Tutorial:: Unwinding
31 @cindex ARM options (none)
32 @cindex options for ARM (none)
36 @cindex @code{-mcpu=} command line option, ARM
37 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
38 This option specifies the target processor. The assembler will issue an
39 error message if an attempt is made to assemble an instruction which
40 will not execute on the target processor. The following processor names are
85 @code{fa526} (Faraday FA526 processor),
86 @code{fa626} (Faraday FA626 processor),
105 @code{fa606te} (Faraday FA606TE processor),
106 @code{fa616te} (Faraday FA616TE processor),
107 @code{fa626te} (Faraday FA626TE processor),
108 @code{fmp626} (Faraday FMP626 processor),
109 @code{fa726te} (Faraday FA726TE processor),
129 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
130 @code{i80200} (Intel XScale processor)
131 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
134 The special name @code{all} may be used to allow the
135 assembler to accept instructions valid for any ARM processor.
137 In addition to the basic instruction set, the assembler can be told to
138 accept various extension mnemonics that extend the processor using the
139 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
140 is equivalent to specifying @code{-mcpu=ep9312}.
142 Multiple extensions may be specified, separated by a @code{+}. The
143 extensions should be specified in ascending alphabetical order.
145 Some extensions may be restricted to particular architectures; this is
146 documented in the list of extensions below.
148 Extension mnemonics may also be removed from those the assembler accepts.
149 This is done be prepending @code{no} to the option that adds the extension.
150 Extensions that are removed should be listed after all extensions which have
151 been added, again in ascending alphabetical order. For example,
152 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
155 The following extensions are currently supported:
156 @code{idiv}, (Integer Divide Extensions for v7-A and v7-R architectures),
160 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
161 @code{os} (Operating System for v6M architecture),
162 @code{sec} (Security Extensions for v6K and v7-A architectures),
163 @code{virt} (Virtualization Extensions for v7-A architecture, implies
168 @cindex @code{-march=} command line option, ARM
169 @item -march=@var{architecture}[+@var{extension}@dots{}]
170 This option specifies the target architecture. The assembler will issue
171 an error message if an attempt is made to assemble an instruction which
172 will not execute on the target architecture. The following architecture
173 names are recognized:
204 If both @code{-mcpu} and
205 @code{-march} are specified, the assembler will use
206 the setting for @code{-mcpu}.
208 The architecture option can be extended with the same instruction set
209 extension options as the @code{-mcpu} option.
211 @cindex @code{-mfpu=} command line option, ARM
212 @item -mfpu=@var{floating-point-format}
214 This option specifies the floating point format to assemble for. The
215 assembler will issue an error message if an attempt is made to assemble
216 an instruction which will not execute on the target floating point unit.
217 The following format options are recognized:
237 @code{vfpv3-d16-fp16},
251 In addition to determining which instructions are assembled, this option
252 also affects the way in which the @code{.double} assembler directive behaves
253 when assembling little-endian code.
255 The default is dependent on the processor selected. For Architecture 5 or
256 later, the default is to assembler for VFP instructions; for earlier
257 architectures the default is to assemble for FPA instructions.
259 @cindex @code{-mthumb} command line option, ARM
261 This option specifies that the assembler should start assembling Thumb
262 instructions; that is, it should behave as though the file starts with a
263 @code{.code 16} directive.
265 @cindex @code{-mthumb-interwork} command line option, ARM
266 @item -mthumb-interwork
267 This option specifies that the output generated by the assembler should
268 be marked as supporting interworking.
270 @cindex @code{-mimplicit-it} command line option, ARM
271 @item -mimplicit-it=never
272 @itemx -mimplicit-it=always
273 @itemx -mimplicit-it=arm
274 @itemx -mimplicit-it=thumb
275 The @code{-mimplicit-it} option controls the behavior of the assembler when
276 conditional instructions are not enclosed in IT blocks.
277 There are four possible behaviors.
278 If @code{never} is specified, such constructs cause a warning in ARM
279 code and an error in Thumb-2 code.
280 If @code{always} is specified, such constructs are accepted in both
281 ARM and Thumb-2 code, where the IT instruction is added implicitly.
282 If @code{arm} is specified, such constructs are accepted in ARM code
283 and cause an error in Thumb-2 code.
284 If @code{thumb} is specified, such constructs cause a warning in ARM
285 code and are accepted in Thumb-2 code. If you omit this option, the
286 behavior is equivalent to @code{-mimplicit-it=arm}.
288 @cindex @code{-mapcs-26} command line option, ARM
289 @cindex @code{-mapcs-32} command line option, ARM
292 These options specify that the output generated by the assembler should
293 be marked as supporting the indicated version of the Arm Procedure.
296 @cindex @code{-matpcs} command line option, ARM
298 This option specifies that the output generated by the assembler should
299 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
300 enabled this option will cause the assembler to create an empty
301 debugging section in the object file called .arm.atpcs. Debuggers can
302 use this to determine the ABI being used by.
304 @cindex @code{-mapcs-float} command line option, ARM
306 This indicates the floating point variant of the APCS should be
307 used. In this variant floating point arguments are passed in FP
308 registers rather than integer registers.
310 @cindex @code{-mapcs-reentrant} command line option, ARM
311 @item -mapcs-reentrant
312 This indicates that the reentrant variant of the APCS should be used.
313 This variant supports position independent code.
315 @cindex @code{-mfloat-abi=} command line option, ARM
316 @item -mfloat-abi=@var{abi}
317 This option specifies that the output generated by the assembler should be
318 marked as using specified floating point ABI.
319 The following values are recognized:
325 @cindex @code{-eabi=} command line option, ARM
326 @item -meabi=@var{ver}
327 This option specifies which EABI version the produced object files should
329 The following values are recognized:
335 @cindex @code{-EB} command line option, ARM
337 This option specifies that the output generated by the assembler should
338 be marked as being encoded for a big-endian processor.
340 @cindex @code{-EL} command line option, ARM
342 This option specifies that the output generated by the assembler should
343 be marked as being encoded for a little-endian processor.
345 @cindex @code{-k} command line option, ARM
346 @cindex PIC code generation for ARM
348 This option specifies that the output of the assembler should be marked
349 as position-independent code (PIC).
351 @cindex @code{--fix-v4bx} command line option, ARM
353 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
354 the linker option of the same name.
356 @cindex @code{-mwarn-deprecated} command line option, ARM
357 @item -mwarn-deprecated
358 @itemx -mno-warn-deprecated
359 Enable or disable warnings about using deprecated options or
360 features. The default is to warn.
368 * ARM-Instruction-Set:: Instruction Set
369 * ARM-Chars:: Special Characters
370 * ARM-Regs:: Register Names
371 * ARM-Relocations:: Relocations
372 * ARM-Neon-Alignment:: NEON Alignment Specifiers
375 @node ARM-Instruction-Set
376 @subsection Instruction Set Syntax
377 Two slightly different syntaxes are support for ARM and THUMB
378 instructions. The default, @code{divided}, uses the old style where
379 ARM and THUMB instructions had their own, separate syntaxes. The new,
380 @code{unified} syntax, which can be selected via the @code{.syntax}
381 directive, and has the following main features:
385 Immediate operands do not require a @code{#} prefix.
388 The @code{IT} instruction may appear, and if it does it is validated
389 against subsequent conditional affixes. In ARM mode it does not
390 generate machine code, in THUMB mode it does.
393 For ARM instructions the conditional affixes always appear at the end
394 of the instruction. For THUMB instructions conditional affixes can be
395 used, but only inside the scope of an @code{IT} instruction.
398 All of the instructions new to the V6T2 architecture (and later) are
399 available. (Only a few such instructions can be written in the
400 @code{divided} syntax).
403 The @code{.N} and @code{.W} suffixes are recognized and honored.
406 All instructions set the flags if and only if they have an @code{s}
411 @subsection Special Characters
413 @cindex line comment character, ARM
414 @cindex ARM line comment character
415 The presence of a @samp{@@} anywhere on a line indicates the start of
416 a comment that extends to the end of that line.
418 If a @samp{#} appears as the first character of a line then the whole
419 line is treated as a comment, but in this case the line could also be
420 a logical line number directive (@pxref{Comments}) or a preprocessor
421 control command (@pxref{Preprocessing}).
423 @cindex line separator, ARM
424 @cindex statement separator, ARM
425 @cindex ARM line separator
426 The @samp{;} character can be used instead of a newline to separate
429 @cindex immediate character, ARM
430 @cindex ARM immediate character
431 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
433 @cindex identifiers, ARM
434 @cindex ARM identifiers
435 *TODO* Explain about /data modifier on symbols.
438 @subsection Register Names
440 @cindex ARM register names
441 @cindex register names, ARM
442 *TODO* Explain about ARM register naming, and the predefined names.
444 @node ARM-Neon-Alignment
445 @subsection NEON Alignment Specifiers
447 @cindex alignment for NEON instructions
448 Some NEON load/store instructions allow an optional address
450 The ARM documentation specifies that this is indicated by
451 @samp{@@ @var{align}}. However GAS already interprets
452 the @samp{@@} character as a "line comment" start,
453 so @samp{: @var{align}} is used instead. For example:
456 vld1.8 @{q0@}, [r0, :128]
459 @node ARM Floating Point
460 @section Floating Point
462 @cindex floating point, ARM (@sc{ieee})
463 @cindex ARM floating point (@sc{ieee})
464 The ARM family uses @sc{ieee} floating-point numbers.
466 @node ARM-Relocations
467 @subsection ARM relocation generation
469 @cindex data relocations, ARM
470 @cindex ARM data relocations
471 Specific data relocations can be generated by putting the relocation name
472 in parentheses after the symbol name. For example:
478 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
480 The following relocations are supported:
496 For compatibility with older toolchains the assembler also accepts
497 @code{(PLT)} after branch targets. This will generate the deprecated
498 @samp{R_ARM_PLT32} relocation.
500 @cindex MOVW and MOVT relocations, ARM
501 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
502 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
503 respectively. For example to load the 32-bit address of foo into r0:
506 MOVW r0, #:lower16:foo
507 MOVT r0, #:upper16:foo
511 @section ARM Machine Directives
513 @cindex machine directives, ARM
514 @cindex ARM machine directives
517 @c AAAAAAAAAAAAAAAAAAAAAAAAA
519 @cindex @code{.2byte} directive, ARM
520 @cindex @code{.4byte} directive, ARM
521 @cindex @code{.8byte} directive, ARM
522 @item .2byte @var{expression} [, @var{expression}]*
523 @itemx .4byte @var{expression} [, @var{expression}]*
524 @itemx .8byte @var{expression} [, @var{expression}]*
525 These directives write 2, 4 or 8 byte values to the output section.
527 @cindex @code{.align} directive, ARM
528 @item .align @var{expression} [, @var{expression}]
529 This is the generic @var{.align} directive. For the ARM however if the
530 first argument is zero (ie no alignment is needed) the assembler will
531 behave as if the argument had been 2 (ie pad to the next four byte
532 boundary). This is for compatibility with ARM's own assembler.
534 @cindex @code{.arch} directive, ARM
535 @item .arch @var{name}
536 Select the target architecture. Valid values for @var{name} are the same as
537 for the @option{-march} commandline option.
539 Specifying @code{.arch} clears any previously selected architecture
542 @cindex @code{.arch_extension} directive, ARM
543 @item .arch_extension @var{name}
544 Add or remove an architecture extension to the target architecture. Valid
545 values for @var{name} are the same as those accepted as architectural
546 extensions by the @option{-mcpu} commandline option.
548 @code{.arch_extension} may be used multiple times to add or remove extensions
549 incrementally to the architecture being compiled for.
551 @cindex @code{.arm} directive, ARM
553 This performs the same action as @var{.code 32}.
556 @cindex @code{.pad} directive, ARM
557 @item .pad #@var{count}
558 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
559 A positive value indicates the function prologue allocated stack space by
560 decrementing the stack pointer.
562 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
564 @cindex @code{.bss} directive, ARM
566 This directive switches to the @code{.bss} section.
568 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
570 @cindex @code{.cantunwind} directive, ARM
572 Prevents unwinding through the current function. No personality routine
573 or exception table data is required or permitted.
575 @cindex @code{.code} directive, ARM
576 @item .code @code{[16|32]}
577 This directive selects the instruction set being generated. The value 16
578 selects Thumb, with the value 32 selecting ARM.
580 @cindex @code{.cpu} directive, ARM
581 @item .cpu @var{name}
582 Select the target processor. Valid values for @var{name} are the same as
583 for the @option{-mcpu} commandline option.
585 Specifying @code{.cpu} clears any previously selected architecture
588 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
590 @cindex @code{.dn} and @code{.qn} directives, ARM
591 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
592 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
594 The @code{dn} and @code{qn} directives are used to create typed
595 and/or indexed register aliases for use in Advanced SIMD Extension
596 (Neon) instructions. The former should be used to create aliases
597 of double-precision registers, and the latter to create aliases of
598 quad-precision registers.
600 If these directives are used to create typed aliases, those aliases can
601 be used in Neon instructions instead of writing types after the mnemonic
602 or after each operand. For example:
611 This is equivalent to writing the following:
617 Aliases created using @code{dn} or @code{qn} can be destroyed using
620 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
622 @cindex @code{.eabi_attribute} directive, ARM
623 @item .eabi_attribute @var{tag}, @var{value}
624 Set the EABI object attribute @var{tag} to @var{value}.
626 The @var{tag} is either an attribute number, or one of the following:
627 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
628 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
629 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
630 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
631 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
632 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
633 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
634 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
635 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
636 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
637 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
638 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
639 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
640 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
641 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
642 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
643 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
644 @code{Tag_conformance}, @code{Tag_T2EE_use},
645 @code{Tag_Virtualization_use}
647 The @var{value} is either a @code{number}, @code{"string"}, or
648 @code{number, "string"} depending on the tag.
650 Note - the following legacy values are also accepted by @var{tag}:
651 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
652 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
654 @cindex @code{.even} directive, ARM
656 This directive aligns to an even-numbered address.
658 @cindex @code{.extend} directive, ARM
659 @cindex @code{.ldouble} directive, ARM
660 @item .extend @var{expression} [, @var{expression}]*
661 @itemx .ldouble @var{expression} [, @var{expression}]*
662 These directives write 12byte long double floating-point values to the
663 output section. These are not compatible with current ARM processors
666 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
669 @cindex @code{.fnend} directive, ARM
671 Marks the end of a function with an unwind table entry. The unwind index
672 table entry is created when this directive is processed.
674 If no personality routine has been specified then standard personality
675 routine 0 or 1 will be used, depending on the number of unwind opcodes
679 @cindex @code{.fnstart} directive, ARM
681 Marks the start of a function with an unwind table entry.
683 @cindex @code{.force_thumb} directive, ARM
685 This directive forces the selection of Thumb instructions, even if the
686 target processor does not support those instructions
688 @cindex @code{.fpu} directive, ARM
689 @item .fpu @var{name}
690 Select the floating-point unit to assemble for. Valid values for @var{name}
691 are the same as for the @option{-mfpu} commandline option.
693 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
694 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
696 @cindex @code{.handlerdata} directive, ARM
698 Marks the end of the current function, and the start of the exception table
699 entry for that function. Anything between this directive and the
700 @code{.fnend} directive will be added to the exception table entry.
702 Must be preceded by a @code{.personality} or @code{.personalityindex}
705 @c IIIIIIIIIIIIIIIIIIIIIIIIII
707 @cindex @code{.inst} directive, ARM
708 @item .inst @var{opcode} [ , @dots{} ]
709 @itemx .inst.n @var{opcode} [ , @dots{} ]
710 @itemx .inst.w @var{opcode} [ , @dots{} ]
711 Generates the instruction corresponding to the numerical value @var{opcode}.
712 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
713 specified explicitly, overriding the normal encoding rules.
715 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
716 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
717 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
719 @item .ldouble @var{expression} [, @var{expression}]*
722 @cindex @code{.ltorg} directive, ARM
724 This directive causes the current contents of the literal pool to be
725 dumped into the current section (which is assumed to be the .text
726 section) at the current location (aligned to a word boundary).
727 @code{GAS} maintains a separate literal pool for each section and each
728 sub-section. The @code{.ltorg} directive will only affect the literal
729 pool of the current section and sub-section. At the end of assembly
730 all remaining, un-empty literal pools will automatically be dumped.
732 Note - older versions of @code{GAS} would dump the current literal
733 pool any time a section change occurred. This is no longer done, since
734 it prevents accurate control of the placement of literal pools.
736 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
738 @cindex @code{.movsp} directive, ARM
739 @item .movsp @var{reg} [, #@var{offset}]
740 Tell the unwinder that @var{reg} contains an offset from the current
741 stack pointer. If @var{offset} is not specified then it is assumed to be
744 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
745 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
747 @cindex @code{.object_arch} directive, ARM
748 @item .object_arch @var{name}
749 Override the architecture recorded in the EABI object attribute section.
750 Valid values for @var{name} are the same as for the @code{.arch} directive.
751 Typically this is useful when code uses runtime detection of CPU features.
753 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
755 @cindex @code{.packed} directive, ARM
756 @item .packed @var{expression} [, @var{expression}]*
757 This directive writes 12-byte packed floating-point values to the
758 output section. These are not compatible with current ARM processors
761 @cindex @code{.pad} directive, ARM
762 @item .pad #@var{count}
763 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
764 A positive value indicates the function prologue allocated stack space by
765 decrementing the stack pointer.
767 @cindex @code{.personality} directive, ARM
768 @item .personality @var{name}
769 Sets the personality routine for the current function to @var{name}.
771 @cindex @code{.personalityindex} directive, ARM
772 @item .personalityindex @var{index}
773 Sets the personality routine for the current function to the EABI standard
774 routine number @var{index}
776 @cindex @code{.pool} directive, ARM
778 This is a synonym for .ltorg.
780 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
781 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
783 @cindex @code{.req} directive, ARM
784 @item @var{name} .req @var{register name}
785 This creates an alias for @var{register name} called @var{name}. For
792 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
795 @cindex @code{.save} directive, ARM
796 @item .save @var{reglist}
797 Generate unwinder annotations to restore the registers in @var{reglist}.
798 The format of @var{reglist} is the same as the corresponding store-multiple
802 @exdent @emph{core registers}
803 .save @{r4, r5, r6, lr@}
804 stmfd sp!, @{r4, r5, r6, lr@}
805 @exdent @emph{FPA registers}
808 @exdent @emph{VFP registers}
809 .save @{d8, d9, d10@}
810 fstmdx sp!, @{d8, d9, d10@}
811 @exdent @emph{iWMMXt registers}
813 wstrd wr11, [sp, #-8]!
814 wstrd wr10, [sp, #-8]!
817 wstrd wr11, [sp, #-8]!
819 wstrd wr10, [sp, #-8]!
823 @cindex @code{.setfp} directive, ARM
824 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
825 Make all unwinder annotations relative to a frame pointer. Without this
826 the unwinder will use offsets from the stack pointer.
828 The syntax of this directive is the same as the @code{add} or @code{mov}
829 instruction used to set the frame pointer. @var{spreg} must be either
830 @code{sp} or mentioned in a previous @code{.movsp} directive.
840 @cindex @code{.secrel32} directive, ARM
841 @item .secrel32 @var{expression} [, @var{expression}]*
842 This directive emits relocations that evaluate to the section-relative
843 offset of each expression's symbol. This directive is only supported
846 @cindex @code{.syntax} directive, ARM
847 @item .syntax [@code{unified} | @code{divided}]
848 This directive sets the Instruction Set Syntax as described in the
849 @ref{ARM-Instruction-Set} section.
851 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
853 @cindex @code{.thumb} directive, ARM
855 This performs the same action as @var{.code 16}.
857 @cindex @code{.thumb_func} directive, ARM
859 This directive specifies that the following symbol is the name of a
860 Thumb encoded function. This information is necessary in order to allow
861 the assembler and linker to generate correct code for interworking
862 between Arm and Thumb instructions and should be used even if
863 interworking is not going to be performed. The presence of this
864 directive also implies @code{.thumb}
866 This directive is not neccessary when generating EABI objects. On these
867 targets the encoding is implicit when generating Thumb code.
869 @cindex @code{.thumb_set} directive, ARM
871 This performs the equivalent of a @code{.set} directive in that it
872 creates a symbol which is an alias for another symbol (possibly not yet
873 defined). This directive also has the added property in that it marks
874 the aliased symbol as being a thumb function entry point, in the same
875 way that the @code{.thumb_func} directive does.
877 @cindex @code{.tlsdescseq} directive, ARM
878 @item .tlsdescseq @var{tls-variable}
879 This directive is used to annotate parts of an inlined TLS descriptor
880 trampoline. Normally the trampoline is provided by the linker, and
881 this directive is not needed.
883 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
885 @cindex @code{.unreq} directive, ARM
886 @item .unreq @var{alias-name}
887 This undefines a register alias which was previously defined using the
888 @code{req}, @code{dn} or @code{qn} directives. For example:
895 An error occurs if the name is undefined. Note - this pseudo op can
896 be used to delete builtin in register name aliases (eg 'r0'). This
897 should only be done if it is really necessary.
899 @cindex @code{.unwind_raw} directive, ARM
900 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
901 Insert one of more arbitary unwind opcode bytes, which are known to adjust
902 the stack pointer by @var{offset} bytes.
904 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
907 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
909 @cindex @code{.vsave} directive, ARM
910 @item .vsave @var{vfp-reglist}
911 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
912 using FLDMD. Also works for VFPv3 registers
913 that are to be restored using VLDM.
914 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
918 @exdent @emph{VFP registers}
919 .vsave @{d8, d9, d10@}
920 fstmdd sp!, @{d8, d9, d10@}
921 @exdent @emph{VFPv3 registers}
922 .vsave @{d15, d16, d17@}
923 vstm sp!, @{d15, d16, d17@}
926 Since FLDMX and FSTMX are now deprecated, this directive should be
927 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
929 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
930 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
931 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
932 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
940 @cindex opcodes for ARM
941 @code{@value{AS}} implements all the standard ARM opcodes. It also
942 implements several pseudo opcodes, including several synthetic load
947 @cindex @code{NOP} pseudo op, ARM
953 This pseudo op will always evaluate to a legal ARM instruction that does
954 nothing. Currently it will evaluate to MOV r0, r0.
956 @cindex @code{LDR reg,=<label>} pseudo op, ARM
959 ldr <register> , = <expression>
962 If expression evaluates to a numeric constant then a MOV or MVN
963 instruction will be used in place of the LDR instruction, if the
964 constant can be generated by either of these instructions. Otherwise
965 the constant will be placed into the nearest literal pool (if it not
966 already there) and a PC relative LDR instruction will be generated.
968 @cindex @code{ADR reg,<label>} pseudo op, ARM
971 adr <register> <label>
974 This instruction will load the address of @var{label} into the indicated
975 register. The instruction will evaluate to a PC relative ADD or SUB
976 instruction depending upon where the label is located. If the label is
977 out of range, or if it is not defined in the same file (and section) as
978 the ADR instruction, then an error will be generated. This instruction
979 will not make use of the literal pool.
981 @cindex @code{ADRL reg,<label>} pseudo op, ARM
984 adrl <register> <label>
987 This instruction will load the address of @var{label} into the indicated
988 register. The instruction will evaluate to one or two PC relative ADD
989 or SUB instructions depending upon where the label is located. If a
990 second instruction is not needed a NOP instruction will be generated in
991 its place, so that this instruction is always 8 bytes long.
993 If the label is out of range, or if it is not defined in the same file
994 (and section) as the ADRL instruction, then an error will be generated.
995 This instruction will not make use of the literal pool.
999 For information on the ARM or Thumb instruction sets, see @cite{ARM
1000 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1003 @node ARM Mapping Symbols
1004 @section Mapping Symbols
1006 The ARM ELF specification requires that special symbols be inserted
1007 into object files to mark certain features:
1013 At the start of a region of code containing ARM instructions.
1017 At the start of a region of code containing THUMB instructions.
1021 At the start of a region of data.
1025 The assembler will automatically insert these symbols for you - there
1026 is no need to code them yourself. Support for tagging symbols ($b,
1027 $f, $p and $m) which is also mentioned in the current ARM ELF
1028 specification is not implemented. This is because they have been
1029 dropped from the new EABI and so tools cannot rely upon their
1032 @node ARM Unwinding Tutorial
1035 The ABI for the ARM Architecture specifies a standard format for
1036 exception unwind information. This information is used when an
1037 exception is thrown to determine where control should be transferred.
1038 In particular, the unwind information is used to determine which
1039 function called the function that threw the exception, and which
1040 function called that one, and so forth. This information is also used
1041 to restore the values of callee-saved registers in the function
1042 catching the exception.
1044 If you are writing functions in assembly code, and those functions
1045 call other functions that throw exceptions, you must use assembly
1046 pseudo ops to ensure that appropriate exception unwind information is
1047 generated. Otherwise, if one of the functions called by your assembly
1048 code throws an exception, the run-time library will be unable to
1049 unwind the stack through your assembly code and your program will not
1052 To illustrate the use of these pseudo ops, we will examine the code
1053 that G++ generates for the following C++ input:
1056 void callee (int *);
1067 This example does not show how to throw or catch an exception from
1068 assembly code. That is a much more complex operation and should
1069 always be done in a high-level language, such as C++, that directly
1070 supports exceptions.
1072 The code generated by one particular version of G++ when compiling the
1079 @ Function supports interworking.
1080 @ args = 0, pretend = 0, frame = 8
1081 @ frame_needed = 1, uses_anonymous_args = 0
1103 Of course, the sequence of instructions varies based on the options
1104 you pass to GCC and on the version of GCC in use. The exact
1105 instructions are not important since we are focusing on the pseudo ops
1106 that are used to generate unwind information.
1108 An important assumption made by the unwinder is that the stack frame
1109 does not change during the body of the function. In particular, since
1110 we assume that the assembly code does not itself throw an exception,
1111 the only point where an exception can be thrown is from a call, such
1112 as the @code{bl} instruction above. At each call site, the same saved
1113 registers (including @code{lr}, which indicates the return address)
1114 must be located in the same locations relative to the frame pointer.
1116 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1117 op appears immediately before the first instruction of the function
1118 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1119 op appears immediately after the last instruction of the function.
1120 These pseudo ops specify the range of the function.
1122 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1123 @code{.pad}) matters; their exact locations are irrelevant. In the
1124 example above, the compiler emits the pseudo ops with particular
1125 instructions. That makes it easier to understand the code, but it is
1126 not required for correctness. It would work just as well to emit all
1127 of the pseudo ops other than @code{.fnend} in the same order, but
1128 immediately after @code{.fnstart}.
1130 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1131 indicates registers that have been saved to the stack so that they can
1132 be restored before the function returns. The argument to the
1133 @code{.save} pseudo op is a list of registers to save. If a register
1134 is ``callee-saved'' (as specified by the ABI) and is modified by the
1135 function you are writing, then your code must save the value before it
1136 is modified and restore the original value before the function
1137 returns. If an exception is thrown, the run-time library restores the
1138 values of these registers from their locations on the stack before
1139 returning control to the exception handler. (Of course, if an
1140 exception is not thrown, the function that contains the @code{.save}
1141 pseudo op restores these registers in the function epilogue, as is
1142 done with the @code{ldmfd} instruction above.)
1144 You do not have to save callee-saved registers at the very beginning
1145 of the function and you do not need to use the @code{.save} pseudo op
1146 immediately following the point at which the registers are saved.
1147 However, if you modify a callee-saved register, you must save it on
1148 the stack before modifying it and before calling any functions which
1149 might throw an exception. And, you must use the @code{.save} pseudo
1150 op to indicate that you have done so.
1152 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1153 modification of the stack pointer that does not save any registers.
1154 The argument is the number of bytes (in decimal) that are subtracted
1155 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1156 subtracting from the stack pointer increases the size of the stack.)
1158 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1159 indicates the register that contains the frame pointer. The first
1160 argument is the register that is set, which is typically @code{fp}.
1161 The second argument indicates the register from which the frame
1162 pointer takes its value. The third argument, if present, is the value
1163 (in decimal) added to the register specified by the second argument to
1164 compute the value of the frame pointer. You should not modify the
1165 frame pointer in the body of the function.
1167 If you do not use a frame pointer, then you should not use the
1168 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1169 should avoid modifying the stack pointer outside of the function
1170 prologue. Otherwise, the run-time library will be unable to find
1171 saved registers when it is unwinding the stack.
1173 The pseudo ops described above are sufficient for writing assembly
1174 code that calls functions which may throw exceptions. If you need to
1175 know more about the object-file format used to represent unwind
1176 information, you may consult the @cite{Exception Handling ABI for the
1177 ARM Architecture} available from @uref{http://infocenter.arm.com}.