sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35
  36 static struct drm_i915_private *i915_mch_dev;
  37 /*
  38  * Lock protecting IPS related data structures
  39  *   - i915_mch_dev
  40  *   - dev_priv->max_delay
  41  *   - dev_priv->min_delay
  42  *   - dev_priv->fmax
  43  *   - dev_priv->gpu_busy
  44  */
  45 static struct lock mchdev_lock;
  46 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE);
  47
  48 static void i915_pineview_get_mem_freq(struct drm_device *dev);
  49 static void i915_ironlake_get_mem_freq(struct drm_device *dev);
  50 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
  51
  52 static void i915_write_hws_pga(struct drm_device *dev)
  53 {
  54         drm_i915_private_t *dev_priv = dev->dev_private;
  55         u32 addr;
  56
  57         addr = dev_priv->status_page_dmah->busaddr;
  58         if (INTEL_INFO(dev)->gen >= 4)
  59                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  60         I915_WRITE(HWS_PGA, addr);
  61 }
  62
  63 /**
  64  * Sets up the hardware status page for devices that need a physical address
  65  * in the register.
  66  */
  67 static int i915_init_phys_hws(struct drm_device *dev)
  68 {
  69         drm_i915_private_t *dev_priv = dev->dev_private;
  70         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  71
  72         /*
  73          * Program Hardware Status Page
  74          * XXXKIB Keep 4GB limit for allocation for now.  This method
  75          * of allocation is used on <= 965 hardware, that has several
  76          * erratas regarding the use of physical memory > 4 GB.
  77          */
  78         DRM_UNLOCK(dev);
  79         dev_priv->status_page_dmah =
  80                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  81         DRM_LOCK(dev);
  82         if (!dev_priv->status_page_dmah) {
  83                 DRM_ERROR("Can not allocate hardware status page\n");
  84                 return -ENOMEM;
  85         }
  86         ring->status_page.page_addr = dev_priv->hw_status_page =
  87             dev_priv->status_page_dmah->vaddr;
  88         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  89
  90         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  91
  92         i915_write_hws_pga(dev);
  93         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  94             (uintmax_t)dev_priv->dma_status_page);
  95         return 0;
  96 }
  97
  98 /**
  99  * Frees the hardware status page, whether it's a physical address or a virtual
 100  * address set up by the X Server.
 101  */
 102 static void i915_free_hws(struct drm_device *dev)
 103 {
 104         drm_i915_private_t *dev_priv = dev->dev_private;
 105         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 106
 107         if (dev_priv->status_page_dmah) {
 108                 drm_pci_free(dev, dev_priv->status_page_dmah);
 109                 dev_priv->status_page_dmah = NULL;
 110         }
 111
 112         if (dev_priv->status_gfx_addr) {
 113                 dev_priv->status_gfx_addr = 0;
 114                 ring->status_page.gfx_addr = 0;
 115                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 116         }
 117
 118         /* Need to rewrite hardware status page */
 119         I915_WRITE(HWS_PGA, 0x1ffff000);
 120 }
 121
 122 void i915_kernel_lost_context(struct drm_device * dev)
 123 {
 124         drm_i915_private_t *dev_priv = dev->dev_private;
 125         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 126
 127         /*
 128          * We should never lose context on the ring with modesetting
 129          * as we don't expose it to userspace
 130          */
 131         if (drm_core_check_feature(dev, DRIVER_MODESET))
 132                 return;
 133
 134         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 135         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 136         ring->space = ring->head - (ring->tail + 8);
 137         if (ring->space < 0)
 138                 ring->space += ring->size;
 139
 140 #if 1
 141         KIB_NOTYET();
 142 #else
 143         if (!dev->primary->master)
 144                 return;
 145 #endif
 146
 147         if (ring->head == ring->tail && dev_priv->sarea_priv)
 148                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 149 }
 150
 151 static int i915_dma_cleanup(struct drm_device * dev)
 152 {
 153         drm_i915_private_t *dev_priv = dev->dev_private;
 154         int i;
 155
 156
 157         /* Make sure interrupts are disabled here because the uninstall ioctl
 158          * may not have been called from userspace and after dev_private
 159          * is freed, it's too late.
 160          */
 161         if (dev->irq_enabled)
 162                 drm_irq_uninstall(dev);
 163
 164         for (i = 0; i < I915_NUM_RINGS; i++)
 165                 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
 166
 167         /* Clear the HWS virtual address at teardown */
 168         if (I915_NEED_GFX_HWS(dev))
 169                 i915_free_hws(dev);
 170
 171         return 0;
 172 }
 173
 174 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 175 {
 176         drm_i915_private_t *dev_priv = dev->dev_private;
 177         int ret;
 178
 179         dev_priv->sarea = drm_getsarea(dev);
 180         if (!dev_priv->sarea) {
 181                 DRM_ERROR("can not find sarea!\n");
 182                 i915_dma_cleanup(dev);
 183                 return -EINVAL;
 184         }
 185
 186         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 187             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 188
 189         if (init->ring_size != 0) {
 190                 if (LP_RING(dev_priv)->obj != NULL) {
 191                         i915_dma_cleanup(dev);
 192                         DRM_ERROR("Client tried to initialize ringbuffer in "
 193                                   "GEM mode\n");
 194                         return -EINVAL;
 195                 }
 196
 197                 ret = intel_render_ring_init_dri(dev,
 198                                                  init->ring_start,
 199                                                  init->ring_size);
 200                 if (ret) {
 201                         i915_dma_cleanup(dev);
 202                         return ret;
 203                 }
 204         }
 205
 206         dev_priv->cpp = init->cpp;
 207         dev_priv->back_offset = init->back_offset;
 208         dev_priv->front_offset = init->front_offset;
 209         dev_priv->current_page = 0;
 210         dev_priv->sarea_priv->pf_current_page = 0;
 211
 212         /* Allow hardware batchbuffers unless told otherwise.
 213          */
 214         dev_priv->allow_batchbuffer = 1;
 215
 216         return 0;
 217 }
 218
 219 static int i915_dma_resume(struct drm_device * dev)
 220 {
 221         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 222         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 223
 224         DRM_DEBUG("\n");
 225
 226         if (ring->map.handle == NULL) {
 227                 DRM_ERROR("can not ioremap virtual address for"
 228                           " ring buffer\n");
 229                 return -ENOMEM;
 230         }
 231
 232         /* Program Hardware Status Page */
 233         if (!ring->status_page.page_addr) {
 234                 DRM_ERROR("Can not find hardware status page\n");
 235                 return -EINVAL;
 236         }
 237         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 238         if (ring->status_page.gfx_addr != 0)
 239                 intel_ring_setup_status_page(ring);
 240         else
 241                 i915_write_hws_pga(dev);
 242
 243         DRM_DEBUG("Enabled hardware status page\n");
 244
 245         return 0;
 246 }
 247
 248 static int i915_dma_init(struct drm_device *dev, void *data,
 249                          struct drm_file *file_priv)
 250 {
 251         drm_i915_init_t *init = data;
 252         int retcode = 0;
 253
 254         switch (init->func) {
 255         case I915_INIT_DMA:
 256                 retcode = i915_initialize(dev, init);
 257                 break;
 258         case I915_CLEANUP_DMA:
 259                 retcode = i915_dma_cleanup(dev);
 260                 break;
 261         case I915_RESUME_DMA:
 262                 retcode = i915_dma_resume(dev);
 263                 break;
 264         default:
 265                 retcode = -EINVAL;
 266                 break;
 267         }
 268
 269         return retcode;
 270 }
 271
 272 /* Implement basically the same security restrictions as hardware does
 273  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 274  *
 275  * Most of the calculations below involve calculating the size of a
 276  * particular instruction.  It's important to get the size right as
 277  * that tells us where the next instruction to check is.  Any illegal
 278  * instruction detected will be given a size of zero, which is a
 279  * signal to abort the rest of the buffer.
 280  */
 281 static int do_validate_cmd(int cmd)
 282 {
 283         switch (((cmd >> 29) & 0x7)) {
 284         case 0x0:
 285                 switch ((cmd >> 23) & 0x3f) {
 286                 case 0x0:
 287                         return 1;       /* MI_NOOP */
 288                 case 0x4:
 289                         return 1;       /* MI_FLUSH */
 290                 default:
 291                         return 0;       /* disallow everything else */
 292                 }
 293                 break;
 294         case 0x1:
 295                 return 0;       /* reserved */
 296         case 0x2:
 297                 return (cmd & 0xff) + 2;        /* 2d commands */
 298         case 0x3:
 299                 if (((cmd >> 24) & 0x1f) <= 0x18)
 300                         return 1;
 301
 302                 switch ((cmd >> 24) & 0x1f) {
 303                 case 0x1c:
 304                         return 1;
 305                 case 0x1d:
 306                         switch ((cmd >> 16) & 0xff) {
 307                         case 0x3:
 308                                 return (cmd & 0x1f) + 2;
 309                         case 0x4:
 310                                 return (cmd & 0xf) + 2;
 311                         default:
 312                                 return (cmd & 0xffff) + 2;
 313                         }
 314                 case 0x1e:
 315                         if (cmd & (1 << 23))
 316                                 return (cmd & 0xffff) + 1;
 317                         else
 318                                 return 1;
 319                 case 0x1f:
 320                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 321                                 return (cmd & 0x1ffff) + 2;
 322                         else if (cmd & (1 << 17))       /* indirect random */
 323                                 if ((cmd & 0xffff) == 0)
 324                                         return 0;       /* unknown length, too hard */
 325                                 else
 326                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 327                         else
 328                                 return 2;       /* indirect sequential */
 329                 default:
 330                         return 0;
 331                 }
 332         default:
 333                 return 0;
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int validate_cmd(int cmd)
 340 {
 341         int ret = do_validate_cmd(cmd);
 342
 343 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 344
 345         return ret;
 346 }
 347
 348 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 349                           int dwords)
 350 {
 351         drm_i915_private_t *dev_priv = dev->dev_private;
 352         int i;
 353
 354         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 355                 return -EINVAL;
 356
 357         BEGIN_LP_RING((dwords+1)&~1);
 358
 359         for (i = 0; i < dwords;) {
 360                 int cmd, sz;
 361
 362                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 363                         return -EINVAL;
 364
 365                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 366                         return -EINVAL;
 367
 368                 OUT_RING(cmd);
 369
 370                 while (++i, --sz) {
 371                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 372                                                          sizeof(cmd))) {
 373                                 return -EINVAL;
 374                         }
 375                         OUT_RING(cmd);
 376                 }
 377         }
 378
 379         if (dwords & 1)
 380                 OUT_RING(0);
 381
 382         ADVANCE_LP_RING();
 383
 384         return 0;
 385 }
 386
 387 int i915_emit_box(struct drm_device * dev,
 388                   struct drm_clip_rect *boxes,
 389                   int i, int DR1, int DR4)
 390 {
 391         struct drm_clip_rect box;
 392
 393         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 394                 return -EFAULT;
 395         }
 396
 397         return (i915_emit_box_p(dev, &box, DR1, DR4));
 398 }
 399
 400 int
 401 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
 402     int DR1, int DR4)
 403 {
 404         drm_i915_private_t *dev_priv = dev->dev_private;
 405         int ret;
 406
 407         if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
 408             box->x2 <= 0) {
 409                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 410                           box->x1, box->y1, box->x2, box->y2);
 411                 return -EINVAL;
 412         }
 413
 414         if (INTEL_INFO(dev)->gen >= 4) {
 415                 ret = BEGIN_LP_RING(4);
 416                 if (ret != 0)
 417                         return (ret);
 418
 419                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 420                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 421                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 422                 OUT_RING(DR4);
 423         } else {
 424                 ret = BEGIN_LP_RING(6);
 425                 if (ret != 0)
 426                         return (ret);
 427
 428                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 429                 OUT_RING(DR1);
 430                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 431                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 432                 OUT_RING(DR4);
 433                 OUT_RING(0);
 434         }
 435         ADVANCE_LP_RING();
 436
 437         return 0;
 438 }
 439
 440 /* XXX: Emitting the counter should really be moved to part of the IRQ
 441  * emit. For now, do it in both places:
 442  */
 443
 444 static void i915_emit_breadcrumb(struct drm_device *dev)
 445 {
 446         drm_i915_private_t *dev_priv = dev->dev_private;
 447
 448         if (++dev_priv->counter > 0x7FFFFFFFUL)
 449                 dev_priv->counter = 0;
 450         if (dev_priv->sarea_priv)
 451                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 452
 453         if (BEGIN_LP_RING(4) == 0) {
 454                 OUT_RING(MI_STORE_DWORD_INDEX);
 455                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 456                 OUT_RING(dev_priv->counter);
 457                 OUT_RING(0);
 458                 ADVANCE_LP_RING();
 459         }
 460 }
 461
 462 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 463     drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
 464 {
 465         int nbox = cmd->num_cliprects;
 466         int i = 0, count, ret;
 467
 468         if (cmd->sz & 0x3) {
 469                 DRM_ERROR("alignment\n");
 470                 return -EINVAL;
 471         }
 472
 473         i915_kernel_lost_context(dev);
 474
 475         count = nbox ? nbox : 1;
 476
 477         for (i = 0; i < count; i++) {
 478                 if (i < nbox) {
 479                         ret = i915_emit_box_p(dev, &cmd->cliprects[i],
 480                             cmd->DR1, cmd->DR4);
 481                         if (ret)
 482                                 return ret;
 483                 }
 484
 485                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 486                 if (ret)
 487                         return ret;
 488         }
 489
 490         i915_emit_breadcrumb(dev);
 491         return 0;
 492 }
 493
 494 static int
 495 i915_dispatch_batchbuffer(struct drm_device * dev,
 496     drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
 497 {
 498         drm_i915_private_t *dev_priv = dev->dev_private;
 499         int nbox = batch->num_cliprects;
 500         int i, count, ret;
 501
 502         if ((batch->start | batch->used) & 0x7) {
 503                 DRM_ERROR("alignment\n");
 504                 return -EINVAL;
 505         }
 506
 507         i915_kernel_lost_context(dev);
 508
 509         count = nbox ? nbox : 1;
 510
 511         for (i = 0; i < count; i++) {
 512                 if (i < nbox) {
 513                         int ret = i915_emit_box_p(dev, &cliprects[i],
 514                             batch->DR1, batch->DR4);
 515                         if (ret)
 516                                 return ret;
 517                 }
 518
 519                 if (!IS_I830(dev) && !IS_845G(dev)) {
 520                         ret = BEGIN_LP_RING(2);
 521                         if (ret != 0)
 522                                 return (ret);
 523
 524                         if (INTEL_INFO(dev)->gen >= 4) {
 525                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
 526                                     MI_BATCH_NON_SECURE_I965);
 527                                 OUT_RING(batch->start);
 528                         } else {
 529                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 530                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 531                         }
 532                 } else {
 533                         ret = BEGIN_LP_RING(4);
 534                         if (ret != 0)
 535                                 return (ret);
 536
 537                         OUT_RING(MI_BATCH_BUFFER);
 538                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 539                         OUT_RING(batch->start + batch->used - 4);
 540                         OUT_RING(0);
 541                 }
 542                 ADVANCE_LP_RING();
 543         }
 544
 545         i915_emit_breadcrumb(dev);
 546
 547         return 0;
 548 }
 549
 550 static int i915_dispatch_flip(struct drm_device * dev)
 551 {
 552         drm_i915_private_t *dev_priv = dev->dev_private;
 553         int ret;
 554
 555         if (!dev_priv->sarea_priv)
 556                 return -EINVAL;
 557
 558         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 559                   __func__,
 560                   dev_priv->current_page,
 561                   dev_priv->sarea_priv->pf_current_page);
 562
 563         i915_kernel_lost_context(dev);
 564
 565         ret = BEGIN_LP_RING(10);
 566         if (ret)
 567                 return ret;
 568         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 569         OUT_RING(0);
 570
 571         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 572         OUT_RING(0);
 573         if (dev_priv->current_page == 0) {
 574                 OUT_RING(dev_priv->back_offset);
 575                 dev_priv->current_page = 1;
 576         } else {
 577                 OUT_RING(dev_priv->front_offset);
 578                 dev_priv->current_page = 0;
 579         }
 580         OUT_RING(0);
 581
 582         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 583         OUT_RING(0);
 584
 585         ADVANCE_LP_RING();
 586
 587         if (++dev_priv->counter > 0x7FFFFFFFUL)
 588                 dev_priv->counter = 0;
 589         if (dev_priv->sarea_priv)
 590                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 591
 592         if (BEGIN_LP_RING(4) == 0) {
 593                 OUT_RING(MI_STORE_DWORD_INDEX);
 594                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 595                 OUT_RING(dev_priv->counter);
 596                 OUT_RING(0);
 597                 ADVANCE_LP_RING();
 598         }
 599
 600         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 601         return 0;
 602 }
 603
 604 static int
 605 i915_quiescent(struct drm_device *dev)
 606 {
 607         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 608
 609         i915_kernel_lost_context(dev);
 610         return (intel_wait_ring_idle(ring));
 611 }
 612
 613 static int
 614 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 615 {
 616         int ret;
 617
 618         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 619
 620         DRM_LOCK(dev);
 621         ret = i915_quiescent(dev);
 622         DRM_UNLOCK(dev);
 623
 624         return (ret);
 625 }
 626
 627 static int i915_batchbuffer(struct drm_device *dev, void *data,
 628                             struct drm_file *file_priv)
 629 {
 630         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 631         drm_i915_sarea_t *sarea_priv;
 632         drm_i915_batchbuffer_t *batch = data;
 633         struct drm_clip_rect *cliprects;
 634         size_t cliplen;
 635         int ret;
 636
 637         if (!dev_priv->allow_batchbuffer) {
 638                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 639                 return -EINVAL;
 640         }
 641         DRM_UNLOCK(dev);
 642
 643         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 644                   batch->start, batch->used, batch->num_cliprects);
 645
 646         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 647         if (batch->num_cliprects < 0)
 648                 return -EFAULT;
 649         if (batch->num_cliprects != 0) {
 650                 cliprects = kmalloc(batch->num_cliprects *
 651                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 652                     M_WAITOK | M_ZERO);
 653
 654                 ret = -copyin(batch->cliprects, cliprects,
 655                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 656                 if (ret != 0) {
 657                         DRM_LOCK(dev);
 658                         goto fail_free;
 659                 }
 660         } else
 661                 cliprects = NULL;
 662
 663         DRM_LOCK(dev);
 664         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 665         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 666
 667         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 668         if (sarea_priv)
 669                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 670
 671 fail_free:
 672         drm_free(cliprects, DRM_MEM_DMA);
 673         return ret;
 674 }
 675
 676 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 677                           struct drm_file *file_priv)
 678 {
 679         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 680         drm_i915_sarea_t *sarea_priv;
 681         drm_i915_cmdbuffer_t *cmdbuf = data;
 682         struct drm_clip_rect *cliprects = NULL;
 683         void *batch_data;
 684         int ret;
 685
 686         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 687                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 688
 689         if (cmdbuf->num_cliprects < 0)
 690                 return -EINVAL;
 691
 692         DRM_UNLOCK(dev);
 693
 694         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 695
 696         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 697         if (ret != 0) {
 698                 DRM_LOCK(dev);
 699                 goto fail_batch_free;
 700         }
 701
 702         if (cmdbuf->num_cliprects) {
 703                 cliprects = kmalloc(cmdbuf->num_cliprects *
 704                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 705                     M_WAITOK | M_ZERO);
 706                 ret = -copyin(cmdbuf->cliprects, cliprects,
 707                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 708                 if (ret != 0) {
 709                         DRM_LOCK(dev);
 710                         goto fail_clip_free;
 711                 }
 712         }
 713
 714         DRM_LOCK(dev);
 715         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 716         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 717         if (ret) {
 718                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 719                 goto fail_clip_free;
 720         }
 721
 722         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 723         if (sarea_priv)
 724                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 725
 726 fail_clip_free:
 727         drm_free(cliprects, DRM_MEM_DMA);
 728 fail_batch_free:
 729         drm_free(batch_data, DRM_MEM_DMA);
 730         return ret;
 731 }
 732
 733 static int i915_flip_bufs(struct drm_device *dev, void *data,
 734                           struct drm_file *file_priv)
 735 {
 736         int ret;
 737
 738         DRM_DEBUG("%s\n", __func__);
 739
 740         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 741
 742         ret = i915_dispatch_flip(dev);
 743
 744         return ret;
 745 }
 746
 747 static int i915_getparam(struct drm_device *dev, void *data,
 748                          struct drm_file *file_priv)
 749 {
 750         drm_i915_private_t *dev_priv = dev->dev_private;
 751         drm_i915_getparam_t *param = data;
 752         int value;
 753
 754         if (!dev_priv) {
 755                 DRM_ERROR("called with no initialization\n");
 756                 return -EINVAL;
 757         }
 758
 759         switch (param->param) {
 760         case I915_PARAM_IRQ_ACTIVE:
 761                 value = dev->irq_enabled ? 1 : 0;
 762                 break;
 763         case I915_PARAM_ALLOW_BATCHBUFFER:
 764                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 765                 break;
 766         case I915_PARAM_LAST_DISPATCH:
 767                 value = READ_BREADCRUMB(dev_priv);
 768                 break;
 769         case I915_PARAM_CHIPSET_ID:
 770                 value = dev->pci_device;
 771                 break;
 772         case I915_PARAM_HAS_GEM:
 773                 value = 1;
 774                 break;
 775         case I915_PARAM_NUM_FENCES_AVAIL:
 776                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 777                 break;
 778         case I915_PARAM_HAS_OVERLAY:
 779                 value = dev_priv->overlay ? 1 : 0;
 780                 break;
 781         case I915_PARAM_HAS_PAGEFLIPPING:
 782                 value = 1;
 783                 break;
 784         case I915_PARAM_HAS_EXECBUF2:
 785                 value = 1;
 786                 break;
 787         case I915_PARAM_HAS_BSD:
 788                 value = HAS_BSD(dev);
 789                 break;
 790         case I915_PARAM_HAS_BLT:
 791                 value = HAS_BLT(dev);
 792                 break;
 793         case I915_PARAM_HAS_RELAXED_FENCING:
 794                 value = 1;
 795                 break;
 796         case I915_PARAM_HAS_COHERENT_RINGS:
 797                 value = 1;
 798                 break;
 799         case I915_PARAM_HAS_EXEC_CONSTANTS:
 800                 value = INTEL_INFO(dev)->gen >= 4;
 801                 break;
 802         case I915_PARAM_HAS_RELAXED_DELTA:
 803                 value = 1;
 804                 break;
 805         case I915_PARAM_HAS_GEN7_SOL_RESET:
 806                 value = 1;
 807                 break;
 808         case I915_PARAM_HAS_LLC:
 809                 value = HAS_LLC(dev);
 810                 break;
 811         default:
 812                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 813                                  param->param);
 814                 return -EINVAL;
 815         }
 816
 817         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 818                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 819                 return -EFAULT;
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int i915_setparam(struct drm_device *dev, void *data,
 826                          struct drm_file *file_priv)
 827 {
 828         drm_i915_private_t *dev_priv = dev->dev_private;
 829         drm_i915_setparam_t *param = data;
 830
 831         if (!dev_priv) {
 832                 DRM_ERROR("called with no initialization\n");
 833                 return -EINVAL;
 834         }
 835
 836         switch (param->param) {
 837         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 838                 break;
 839         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 840                 dev_priv->tex_lru_log_granularity = param->value;
 841                 break;
 842         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 843                 dev_priv->allow_batchbuffer = param->value;
 844                 break;
 845         case I915_SETPARAM_NUM_USED_FENCES:
 846                 if (param->value > dev_priv->num_fence_regs ||
 847                     param->value < 0)
 848                         return -EINVAL;
 849                 /* Userspace can use first N regs */
 850                 dev_priv->fence_reg_start = param->value;
 851                 break;
 852         default:
 853                 DRM_DEBUG("unknown parameter %d\n", param->param);
 854                 return -EINVAL;
 855         }
 856
 857         return 0;
 858 }
 859
 860 static int i915_set_status_page(struct drm_device *dev, void *data,
 861                                 struct drm_file *file_priv)
 862 {
 863         drm_i915_private_t *dev_priv = dev->dev_private;
 864         drm_i915_hws_addr_t *hws = data;
 865         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 866
 867         if (!I915_NEED_GFX_HWS(dev))
 868                 return -EINVAL;
 869
 870         if (!dev_priv) {
 871                 DRM_ERROR("called with no initialization\n");
 872                 return -EINVAL;
 873         }
 874
 875         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
 876         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 877                 DRM_ERROR("tried to set status page when mode setting active\n");
 878                 return 0;
 879         }
 880
 881         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
 882             hws->addr & (0x1ffff<<12);
 883
 884         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 885         dev_priv->hws_map.size = 4*1024;
 886         dev_priv->hws_map.type = 0;
 887         dev_priv->hws_map.flags = 0;
 888         dev_priv->hws_map.mtrr = 0;
 889
 890         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 891         if (dev_priv->hws_map.virtual == NULL) {
 892                 i915_dma_cleanup(dev);
 893                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
 894                 DRM_ERROR("can not ioremap virtual address for"
 895                                 " G33 hw status page\n");
 896                 return -ENOMEM;
 897         }
 898         ring->status_page.page_addr = dev_priv->hw_status_page =
 899             dev_priv->hws_map.virtual;
 900
 901         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 902         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 903         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 904                         dev_priv->status_gfx_addr);
 905         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 906         return 0;
 907 }
 908
 909 static bool
 910 intel_enable_ppgtt(struct drm_device *dev)
 911 {
 912         if (i915_enable_ppgtt >= 0)
 913                 return i915_enable_ppgtt;
 914
 915         /* Disable ppgtt on SNB if VT-d is on. */
 916         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
 917                 return false;
 918
 919         return true;
 920 }
 921
 922 static int
 923 i915_load_gem_init(struct drm_device *dev)
 924 {
 925         struct drm_i915_private *dev_priv = dev->dev_private;
 926         unsigned long prealloc_size, gtt_size, mappable_size;
 927         int ret;
 928
 929         prealloc_size = dev_priv->mm.gtt->stolen_size;
 930         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
 931         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
 932
 933         /* Basic memrange allocator for stolen space */
 934         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
 935
 936         DRM_LOCK(dev);
 937         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 938                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 939                  * aperture accordingly when using aliasing ppgtt. */
 940                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 941                 /* For paranoia keep the guard page in between. */
 942                 gtt_size -= PAGE_SIZE;
 943
 944                 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
 945
 946                 ret = i915_gem_init_aliasing_ppgtt(dev);
 947                 if (ret) {
 948                         DRM_UNLOCK(dev);
 949                         return ret;
 950                 }
 951         } else {
 952                 /* Let GEM Manage all of the aperture.
 953                  *
 954                  * However, leave one page at the end still bound to the scratch
 955                  * page.  There are a number of places where the hardware
 956                  * apparently prefetches past the end of the object, and we've
 957                  * seen multiple hangs with the GPU head pointer stuck in a
 958                  * batchbuffer bound at the last page of the aperture.  One page
 959                  * should be enough to keep any prefetching inside of the
 960                  * aperture.
 961                  */
 962                 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
 963         }
 964
 965         ret = i915_gem_init_hw(dev);
 966         DRM_UNLOCK(dev);
 967         if (ret != 0) {
 968                 i915_gem_cleanup_aliasing_ppgtt(dev);
 969                 return (ret);
 970         }
 971
 972 #if 0
 973         /* Try to set up FBC with a reasonable compressed buffer size */
 974         if (I915_HAS_FBC(dev) && i915_powersave) {
 975                 int cfb_size;
 976
 977                 /* Leave 1M for line length buffer & misc. */
 978
 979                 /* Try to get a 32M buffer... */
 980                 if (prealloc_size > (36*1024*1024))
 981                         cfb_size = 32*1024*1024;
 982                 else /* fall back to 7/8 of the stolen space */
 983                         cfb_size = prealloc_size * 7 / 8;
 984                 i915_setup_compression(dev, cfb_size);
 985         }
 986 #endif
 987
 988         /* Allow hardware batchbuffers unless told otherwise. */
 989         dev_priv->allow_batchbuffer = 1;
 990         return 0;
 991 }
 992
 993 static int
 994 i915_load_modeset_init(struct drm_device *dev)
 995 {
 996         struct drm_i915_private *dev_priv = dev->dev_private;
 997         int ret;
 998
 999         ret = intel_parse_bios(dev);
1000         if (ret)
1001                 DRM_INFO("failed to find VBIOS tables\n");
1002
1003 #if 0
1004         intel_register_dsm_handler();
1005 #endif
1006
1007         /* IIR "flip pending" bit means done if this bit is set */
1008         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1009                 dev_priv->flip_pending_is_done = true;
1010
1011         intel_modeset_init(dev);
1012
1013         ret = i915_load_gem_init(dev);
1014         if (ret != 0)
1015                 goto cleanup_gem;
1016
1017         intel_modeset_gem_init(dev);
1018
1019         ret = drm_irq_install(dev);
1020         if (ret)
1021                 goto cleanup_gem;
1022
1023         dev->vblank_disable_allowed = 1;
1024
1025         ret = intel_fbdev_init(dev);
1026         if (ret)
1027                 goto cleanup_gem;
1028
1029         drm_kms_helper_poll_init(dev);
1030
1031         /* We're off and running w/KMS */
1032         dev_priv->mm.suspended = 0;
1033
1034         return (0);
1035
1036 cleanup_gem:
1037         DRM_LOCK(dev);
1038         i915_gem_cleanup_ringbuffer(dev);
1039         DRM_UNLOCK(dev);
1040         i915_gem_cleanup_aliasing_ppgtt(dev);
1041         return (ret);
1042 }
1043
1044 static int
1045 i915_get_bridge_dev(struct drm_device *dev)
1046 {
1047         struct drm_i915_private *dev_priv;
1048
1049         dev_priv = dev->dev_private;
1050
1051         dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1052         if (dev_priv->bridge_dev == NULL) {
1053                 DRM_ERROR("bridge device not found\n");
1054                 return (-1);
1055         }
1056         return (0);
1057 }
1058
1059 #define MCHBAR_I915 0x44
1060 #define MCHBAR_I965 0x48
1061 #define MCHBAR_SIZE (4*4096)
1062
1063 #define DEVEN_REG 0x54
1064 #define   DEVEN_MCHBAR_EN (1 << 28)
1065
1066 /* Allocate space for the MCH regs if needed, return nonzero on error */
1067 static int
1068 intel_alloc_mchbar_resource(struct drm_device *dev)
1069 {
1070         drm_i915_private_t *dev_priv;
1071         device_t vga;
1072         int reg;
1073         u32 temp_lo, temp_hi;
1074         u64 mchbar_addr, temp;
1075
1076         dev_priv = dev->dev_private;
1077         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1078
1079         if (INTEL_INFO(dev)->gen >= 4)
1080                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1081         else
1082                 temp_hi = 0;
1083         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1084         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1085
1086         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1087 #ifdef XXX_CONFIG_PNP
1088         if (mchbar_addr &&
1089             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1090                 return 0;
1091 #endif
1092
1093         /* Get some space for it */
1094         vga = device_get_parent(dev->device);
1095         dev_priv->mch_res_rid = 0x100;
1096         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1097             dev->device, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1098             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1099         if (dev_priv->mch_res == NULL) {
1100                 DRM_ERROR("failed mchbar resource alloc\n");
1101                 return (-ENOMEM);
1102         }
1103
1104         if (INTEL_INFO(dev)->gen >= 4) {
1105                 temp = rman_get_start(dev_priv->mch_res);
1106                 temp >>= 32;
1107                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1108         }
1109         pci_write_config(dev_priv->bridge_dev, reg,
1110             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1111         return (0);
1112 }
1113
1114 static void
1115 intel_setup_mchbar(struct drm_device *dev)
1116 {
1117         drm_i915_private_t *dev_priv;
1118         int mchbar_reg;
1119         u32 temp;
1120         bool enabled;
1121
1122         dev_priv = dev->dev_private;
1123         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1124
1125         dev_priv->mchbar_need_disable = false;
1126
1127         if (IS_I915G(dev) || IS_I915GM(dev)) {
1128                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1129                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1130         } else {
1131                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1132                 enabled = temp & 1;
1133         }
1134
1135         /* If it's already enabled, don't have to do anything */
1136         if (enabled) {
1137                 DRM_DEBUG("mchbar already enabled\n");
1138                 return;
1139         }
1140
1141         if (intel_alloc_mchbar_resource(dev))
1142                 return;
1143
1144         dev_priv->mchbar_need_disable = true;
1145
1146         /* Space is allocated or reserved, so enable it. */
1147         if (IS_I915G(dev) || IS_I915GM(dev)) {
1148                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1149                     temp | DEVEN_MCHBAR_EN, 4);
1150         } else {
1151                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1152                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1153         }
1154 }
1155
1156 static void
1157 intel_teardown_mchbar(struct drm_device *dev)
1158 {
1159         drm_i915_private_t *dev_priv;
1160         device_t vga;
1161         int mchbar_reg;
1162         u32 temp;
1163
1164         dev_priv = dev->dev_private;
1165         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1166
1167         if (dev_priv->mchbar_need_disable) {
1168                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1169                         temp = pci_read_config(dev_priv->bridge_dev,
1170                             DEVEN_REG, 4);
1171                         temp &= ~DEVEN_MCHBAR_EN;
1172                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1173                             temp, 4);
1174                 } else {
1175                         temp = pci_read_config(dev_priv->bridge_dev,
1176                             mchbar_reg, 4);
1177                         temp &= ~1;
1178                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1179                             temp, 4);
1180                 }
1181         }
1182
1183         if (dev_priv->mch_res != NULL) {
1184                 vga = device_get_parent(dev->device);
1185                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->device,
1186                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1187                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->device,
1188                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1189                 dev_priv->mch_res = NULL;
1190         }
1191 }
1192
1193 int
1194 i915_driver_load(struct drm_device *dev, unsigned long flags)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         unsigned long base, size;
1198         int mmio_bar, ret;
1199
1200         ret = 0;
1201
1202         /* i915 has 4 more counters */
1203         dev->counters += 4;
1204         dev->types[6] = _DRM_STAT_IRQ;
1205         dev->types[7] = _DRM_STAT_PRIMARY;
1206         dev->types[8] = _DRM_STAT_SECONDARY;
1207         dev->types[9] = _DRM_STAT_DMA;
1208
1209         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1210             M_ZERO | M_WAITOK);
1211         if (dev_priv == NULL)
1212                 return -ENOMEM;
1213
1214         dev->dev_private = (void *)dev_priv;
1215         dev_priv->dev = dev;
1216         dev_priv->info = i915_get_device_id(dev->pci_device);
1217
1218         if (i915_get_bridge_dev(dev)) {
1219                 drm_free(dev_priv, DRM_MEM_DRIVER);
1220                 return (-EIO);
1221         }
1222         dev_priv->mm.gtt = intel_gtt_get();
1223
1224         /* Add register map (needed for suspend/resume) */
1225         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1226         base = drm_get_resource_start(dev, mmio_bar);
1227         size = drm_get_resource_len(dev, mmio_bar);
1228
1229         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1230             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1231
1232         dev_priv->tq = taskqueue_create("915", M_WAITOK,
1233             taskqueue_thread_enqueue, &dev_priv->tq);
1234         taskqueue_start_threads(&dev_priv->tq, 1, 0, -1, "i915 taskq");
1235         lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE);
1236         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1237         lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1238         lockinit(&dev_priv->rps_lock, "915rps", 0, LK_CANRECURSE);
1239
1240         dev_priv->has_gem = 1;
1241         intel_irq_init(dev);
1242
1243         intel_setup_mchbar(dev);
1244         intel_setup_gmbus(dev);
1245         intel_opregion_setup(dev);
1246
1247         intel_setup_bios(dev);
1248
1249         i915_gem_load(dev);
1250
1251         /* Init HWS */
1252         if (!I915_NEED_GFX_HWS(dev)) {
1253                 ret = i915_init_phys_hws(dev);
1254                 if (ret != 0) {
1255                         drm_rmmap(dev, dev_priv->mmio_map);
1256                         drm_free(dev_priv, DRM_MEM_DRIVER);
1257                         return ret;
1258                 }
1259         }
1260
1261         if (IS_PINEVIEW(dev))
1262                 i915_pineview_get_mem_freq(dev);
1263         else if (IS_GEN5(dev))
1264                 i915_ironlake_get_mem_freq(dev);
1265
1266         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1267
1268         if (IS_IVYBRIDGE(dev))
1269                 dev_priv->num_pipe = 3;
1270         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1271                 dev_priv->num_pipe = 2;
1272         else
1273                 dev_priv->num_pipe = 1;
1274
1275         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1276         if (ret)
1277                 goto out_gem_unload;
1278
1279         /* Start out suspended */
1280         dev_priv->mm.suspended = 1;
1281
1282         intel_detect_pch(dev);
1283
1284         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1285                 DRM_UNLOCK(dev);
1286                 ret = i915_load_modeset_init(dev);
1287                 DRM_LOCK(dev);
1288                 if (ret < 0) {
1289                         DRM_ERROR("failed to init modeset\n");
1290                         goto out_gem_unload;
1291                 }
1292         }
1293
1294         intel_opregion_init(dev);
1295
1296         callout_init_mp(&dev_priv->hangcheck_timer);
1297         callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1298             i915_hangcheck_elapsed, dev);
1299
1300         if (IS_GEN5(dev)) {
1301                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1302                 i915_mch_dev = dev_priv;
1303                 dev_priv->mchdev_lock = &mchdev_lock;
1304                 lockmgr(&mchdev_lock, LK_RELEASE);
1305         }
1306
1307         return (0);
1308
1309 out_gem_unload:
1310         /* XXXKIB */
1311         (void) i915_driver_unload_int(dev, true);
1312         return (ret);
1313 }
1314
1315 static int
1316 i915_driver_unload_int(struct drm_device *dev, bool locked)
1317 {
1318         struct drm_i915_private *dev_priv = dev->dev_private;
1319         int ret;
1320
1321         if (!locked)
1322                 DRM_LOCK(dev);
1323         ret = i915_gpu_idle(dev, true);
1324         if (ret)
1325                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1326         if (!locked)
1327                 DRM_UNLOCK(dev);
1328
1329         i915_free_hws(dev);
1330
1331         intel_teardown_mchbar(dev);
1332
1333         if (locked)
1334                 DRM_UNLOCK(dev);
1335         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1336                 intel_fbdev_fini(dev);
1337                 intel_modeset_cleanup(dev);
1338         }
1339
1340         /* Free error state after interrupts are fully disabled. */
1341         callout_stop(&dev_priv->hangcheck_timer);
1342
1343         i915_destroy_error_state(dev);
1344
1345         intel_opregion_fini(dev);
1346
1347         if (locked)
1348                 DRM_LOCK(dev);
1349
1350         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1351                 if (!locked)
1352                         DRM_LOCK(dev);
1353                 i915_gem_free_all_phys_object(dev);
1354                 i915_gem_cleanup_ringbuffer(dev);
1355                 if (!locked)
1356                         DRM_UNLOCK(dev);
1357                 i915_gem_cleanup_aliasing_ppgtt(dev);
1358 #if 1
1359                 KIB_NOTYET();
1360 #else
1361                 if (I915_HAS_FBC(dev) && i915_powersave)
1362                         i915_cleanup_compression(dev);
1363 #endif
1364                 drm_mm_takedown(&dev_priv->mm.stolen);
1365
1366                 intel_cleanup_overlay(dev);
1367
1368                 if (!I915_NEED_GFX_HWS(dev))
1369                         i915_free_hws(dev);
1370         }
1371
1372         i915_gem_unload(dev);
1373
1374         lockuninit(&dev_priv->irq_lock);
1375
1376         if (dev_priv->tq != NULL)
1377                 taskqueue_free(dev_priv->tq);
1378
1379         bus_generic_detach(dev->device);
1380         drm_rmmap(dev, dev_priv->mmio_map);
1381         intel_teardown_gmbus(dev);
1382
1383         lockuninit(&dev_priv->error_lock);
1384         lockuninit(&dev_priv->error_completion_lock);
1385         lockuninit(&dev_priv->rps_lock);
1386         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1387
1388         return (0);
1389 }
1390
1391 int
1392 i915_driver_unload(struct drm_device *dev)
1393 {
1394
1395         return (i915_driver_unload_int(dev, true));
1396 }
1397
1398 int
1399 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1400 {
1401         struct drm_i915_file_private *i915_file_priv;
1402
1403         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1404             M_WAITOK | M_ZERO);
1405
1406         spin_init(&i915_file_priv->mm.lock);
1407         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1408         file_priv->driver_priv = i915_file_priv;
1409
1410         return (0);
1411 }
1412
1413 void
1414 i915_driver_lastclose(struct drm_device * dev)
1415 {
1416         drm_i915_private_t *dev_priv = dev->dev_private;
1417
1418         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1419 #if 1
1420                 KIB_NOTYET();
1421 #else
1422                 drm_fb_helper_restore();
1423                 vga_switcheroo_process_delayed_switch();
1424 #endif
1425                 return;
1426         }
1427         i915_gem_lastclose(dev);
1428         i915_dma_cleanup(dev);
1429 }
1430
1431 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1432 {
1433
1434         i915_gem_release(dev, file_priv);
1435 }
1436
1437 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1438 {
1439         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1440
1441         spin_uninit(&i915_file_priv->mm.lock);
1442         drm_free(i915_file_priv, DRM_MEM_FILES);
1443 }
1444
1445 struct drm_ioctl_desc i915_ioctls[] = {
1446         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1447         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1448         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1449         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1450         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1451         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1452         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1453         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1454         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1455         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1456         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1457         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1458         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1459         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1460         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1461         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1462         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1463         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1464         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1465         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1466         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1467         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1468         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1469         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1470         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1471         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1472         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1473         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1474         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1475         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1476         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1477         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1478         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1479         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1480         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1481         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1482         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1483         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1484         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1485         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1486         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1487         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1488 };
1489
1490 struct drm_driver i915_driver_info = {
1491         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1492             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1493             DRIVER_GEM /*| DRIVER_MODESET*/,
1494
1495         .buf_priv_size  = sizeof(drm_i915_private_t),
1496         .load           = i915_driver_load,
1497         .open           = i915_driver_open,
1498         .unload         = i915_driver_unload,
1499         .preclose       = i915_driver_preclose,
1500         .lastclose      = i915_driver_lastclose,
1501         .postclose      = i915_driver_postclose,
1502         .device_is_agp  = i915_driver_device_is_agp,
1503         .gem_init_object = i915_gem_init_object,
1504         .gem_free_object = i915_gem_free_object,
1505         .gem_pager_ops  = &i915_gem_pager_ops,
1506         .dumb_create    = i915_gem_dumb_create,
1507         .dumb_map_offset = i915_gem_mmap_gtt,
1508         .dumb_destroy   = i915_gem_dumb_destroy,
1509         .sysctl_init    = i915_sysctl_init,
1510         .sysctl_cleanup = i915_sysctl_cleanup,
1511
1512         .ioctls         = i915_ioctls,
1513         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1514
1515         .name           = DRIVER_NAME,
1516         .desc           = DRIVER_DESC,
1517         .date           = DRIVER_DATE,
1518         .major          = DRIVER_MAJOR,
1519         .minor          = DRIVER_MINOR,
1520         .patchlevel     = DRIVER_PATCHLEVEL,
1521 };
1522
1523 /**
1524  * Determine if the device really is AGP or not.
1525  *
1526  * All Intel graphics chipsets are treated as AGP, even if they are really
1527  * built-in.
1528  *
1529  * \param dev   The device to be tested.
1530  *
1531  * \returns
1532  * A value of 1 is always retured to indictate every i9x5 is AGP.
1533  */
1534 int i915_driver_device_is_agp(struct drm_device * dev)
1535 {
1536         return 1;
1537 }
1538
1539 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1540 {
1541         drm_i915_private_t *dev_priv = dev->dev_private;
1542         u32 tmp;
1543
1544         tmp = I915_READ(CLKCFG);
1545
1546         switch (tmp & CLKCFG_FSB_MASK) {
1547         case CLKCFG_FSB_533:
1548                 dev_priv->fsb_freq = 533; /* 133*4 */
1549                 break;
1550         case CLKCFG_FSB_800:
1551                 dev_priv->fsb_freq = 800; /* 200*4 */
1552                 break;
1553         case CLKCFG_FSB_667:
1554                 dev_priv->fsb_freq =  667; /* 167*4 */
1555                 break;
1556         case CLKCFG_FSB_400:
1557                 dev_priv->fsb_freq = 400; /* 100*4 */
1558                 break;
1559         }
1560
1561         switch (tmp & CLKCFG_MEM_MASK) {
1562         case CLKCFG_MEM_533:
1563                 dev_priv->mem_freq = 533;
1564                 break;
1565         case CLKCFG_MEM_667:
1566                 dev_priv->mem_freq = 667;
1567                 break;
1568         case CLKCFG_MEM_800:
1569                 dev_priv->mem_freq = 800;
1570                 break;
1571         }
1572
1573         /* detect pineview DDR3 setting */
1574         tmp = I915_READ(CSHRDDR3CTL);
1575         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1576 }
1577
1578 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1579 {
1580         drm_i915_private_t *dev_priv = dev->dev_private;
1581         u16 ddrpll, csipll;
1582
1583         ddrpll = I915_READ16(DDRMPLL1);
1584         csipll = I915_READ16(CSIPLL0);
1585
1586         switch (ddrpll & 0xff) {
1587         case 0xc:
1588                 dev_priv->mem_freq = 800;
1589                 break;
1590         case 0x10:
1591                 dev_priv->mem_freq = 1066;
1592                 break;
1593         case 0x14:
1594                 dev_priv->mem_freq = 1333;
1595                 break;
1596         case 0x18:
1597                 dev_priv->mem_freq = 1600;
1598                 break;
1599         default:
1600                 DRM_DEBUG("unknown memory frequency 0x%02x\n",
1601                                  ddrpll & 0xff);
1602                 dev_priv->mem_freq = 0;
1603                 break;
1604         }
1605
1606         dev_priv->r_t = dev_priv->mem_freq;
1607
1608         switch (csipll & 0x3ff) {
1609         case 0x00c:
1610                 dev_priv->fsb_freq = 3200;
1611                 break;
1612         case 0x00e:
1613                 dev_priv->fsb_freq = 3733;
1614                 break;
1615         case 0x010:
1616                 dev_priv->fsb_freq = 4266;
1617                 break;
1618         case 0x012:
1619                 dev_priv->fsb_freq = 4800;
1620                 break;
1621         case 0x014:
1622                 dev_priv->fsb_freq = 5333;
1623                 break;
1624         case 0x016:
1625                 dev_priv->fsb_freq = 5866;
1626                 break;
1627         case 0x018:
1628                 dev_priv->fsb_freq = 6400;
1629                 break;
1630         default:
1631                 DRM_DEBUG("unknown fsb frequency 0x%04x\n",
1632                                  csipll & 0x3ff);
1633                 dev_priv->fsb_freq = 0;
1634                 break;
1635         }
1636
1637         if (dev_priv->fsb_freq == 3200) {
1638                 dev_priv->c_m = 0;
1639         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1640                 dev_priv->c_m = 1;
1641         } else {
1642                 dev_priv->c_m = 2;
1643         }
1644 }
1645
1646 static const struct cparams {
1647         u16 i;
1648         u16 t;
1649         u16 m;
1650         u16 c;
1651 } cparams[] = {
1652         { 1, 1333, 301, 28664 },
1653         { 1, 1066, 294, 24460 },
1654         { 1, 800, 294, 25192 },
1655         { 0, 1333, 276, 27605 },
1656         { 0, 1066, 276, 27605 },
1657         { 0, 800, 231, 23784 },
1658 };
1659
1660 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1661 {
1662         u64 total_count, diff, ret;
1663         u32 count1, count2, count3, m = 0, c = 0;
1664         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1665         int i;
1666
1667         diff1 = now - dev_priv->last_time1;
1668         /*
1669          * sysctl(8) reads the value of sysctl twice in rapid
1670          * succession.  There is high chance that it happens in the
1671          * same timer tick.  Use the cached value to not divide by
1672          * zero and give the hw a chance to gather more samples.
1673          */
1674         if (diff1 <= 10)
1675                 return (dev_priv->chipset_power);
1676
1677         count1 = I915_READ(DMIEC);
1678         count2 = I915_READ(DDREC);
1679         count3 = I915_READ(CSIEC);
1680
1681         total_count = count1 + count2 + count3;
1682
1683         /* FIXME: handle per-counter overflow */
1684         if (total_count < dev_priv->last_count1) {
1685                 diff = ~0UL - dev_priv->last_count1;
1686                 diff += total_count;
1687         } else {
1688                 diff = total_count - dev_priv->last_count1;
1689         }
1690
1691         for (i = 0; i < DRM_ARRAY_SIZE(cparams); i++) {
1692                 if (cparams[i].i == dev_priv->c_m &&
1693                     cparams[i].t == dev_priv->r_t) {
1694                         m = cparams[i].m;
1695                         c = cparams[i].c;
1696                         break;
1697                 }
1698         }
1699
1700         diff = diff / diff1;
1701         ret = ((m * diff) + c);
1702         ret = ret / 10;
1703
1704         dev_priv->last_count1 = total_count;
1705         dev_priv->last_time1 = now;
1706
1707         dev_priv->chipset_power = ret;
1708         return (ret);
1709 }
1710
1711 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1712 {
1713         unsigned long m, x, b;
1714         u32 tsfs;
1715
1716         tsfs = I915_READ(TSFS);
1717
1718         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1719         x = I915_READ8(I915_TR1);
1720
1721         b = tsfs & TSFS_INTR_MASK;
1722
1723         return ((m * x) / 127) - b;
1724 }
1725
1726 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1727 {
1728         static const struct v_table {
1729                 u16 vd; /* in .1 mil */
1730                 u16 vm; /* in .1 mil */
1731         } v_table[] = {
1732                 { 0, 0, },
1733                 { 375, 0, },
1734                 { 500, 0, },
1735                 { 625, 0, },
1736                 { 750, 0, },
1737                 { 875, 0, },
1738                 { 1000, 0, },
1739                 { 1125, 0, },
1740                 { 4125, 3000, },
1741                 { 4125, 3000, },
1742                 { 4125, 3000, },
1743                 { 4125, 3000, },
1744                 { 4125, 3000, },
1745                 { 4125, 3000, },
1746                 { 4125, 3000, },
1747                 { 4125, 3000, },
1748                 { 4125, 3000, },
1749                 { 4125, 3000, },
1750                 { 4125, 3000, },
1751                 { 4125, 3000, },
1752                 { 4125, 3000, },
1753                 { 4125, 3000, },
1754                 { 4125, 3000, },
1755                 { 4125, 3000, },
1756                 { 4125, 3000, },
1757                 { 4125, 3000, },
1758                 { 4125, 3000, },
1759                 { 4125, 3000, },
1760                 { 4125, 3000, },
1761                 { 4125, 3000, },
1762                 { 4125, 3000, },
1763                 { 4125, 3000, },
1764                 { 4250, 3125, },
1765                 { 4375, 3250, },
1766                 { 4500, 3375, },
1767                 { 4625, 3500, },
1768                 { 4750, 3625, },
1769                 { 4875, 3750, },
1770                 { 5000, 3875, },
1771                 { 5125, 4000, },
1772                 { 5250, 4125, },
1773                 { 5375, 4250, },
1774                 { 5500, 4375, },
1775                 { 5625, 4500, },
1776                 { 5750, 4625, },
1777                 { 5875, 4750, },
1778                 { 6000, 4875, },
1779                 { 6125, 5000, },
1780                 { 6250, 5125, },
1781                 { 6375, 5250, },
1782                 { 6500, 5375, },
1783                 { 6625, 5500, },
1784                 { 6750, 5625, },
1785                 { 6875, 5750, },
1786                 { 7000, 5875, },
1787                 { 7125, 6000, },
1788                 { 7250, 6125, },
1789                 { 7375, 6250, },
1790                 { 7500, 6375, },
1791                 { 7625, 6500, },
1792                 { 7750, 6625, },
1793                 { 7875, 6750, },
1794                 { 8000, 6875, },
1795                 { 8125, 7000, },
1796                 { 8250, 7125, },
1797                 { 8375, 7250, },
1798                 { 8500, 7375, },
1799                 { 8625, 7500, },
1800                 { 8750, 7625, },
1801                 { 8875, 7750, },
1802                 { 9000, 7875, },
1803                 { 9125, 8000, },
1804                 { 9250, 8125, },
1805                 { 9375, 8250, },
1806                 { 9500, 8375, },
1807                 { 9625, 8500, },
1808                 { 9750, 8625, },
1809                 { 9875, 8750, },
1810                 { 10000, 8875, },
1811                 { 10125, 9000, },
1812                 { 10250, 9125, },
1813                 { 10375, 9250, },
1814                 { 10500, 9375, },
1815                 { 10625, 9500, },
1816                 { 10750, 9625, },
1817                 { 10875, 9750, },
1818                 { 11000, 9875, },
1819                 { 11125, 10000, },
1820                 { 11250, 10125, },
1821                 { 11375, 10250, },
1822                 { 11500, 10375, },
1823                 { 11625, 10500, },
1824                 { 11750, 10625, },
1825                 { 11875, 10750, },
1826                 { 12000, 10875, },
1827                 { 12125, 11000, },
1828                 { 12250, 11125, },
1829                 { 12375, 11250, },
1830                 { 12500, 11375, },
1831                 { 12625, 11500, },
1832                 { 12750, 11625, },
1833                 { 12875, 11750, },
1834                 { 13000, 11875, },
1835                 { 13125, 12000, },
1836                 { 13250, 12125, },
1837                 { 13375, 12250, },
1838                 { 13500, 12375, },
1839                 { 13625, 12500, },
1840                 { 13750, 12625, },
1841                 { 13875, 12750, },
1842                 { 14000, 12875, },
1843                 { 14125, 13000, },
1844                 { 14250, 13125, },
1845                 { 14375, 13250, },
1846                 { 14500, 13375, },
1847                 { 14625, 13500, },
1848                 { 14750, 13625, },
1849                 { 14875, 13750, },
1850                 { 15000, 13875, },
1851                 { 15125, 14000, },
1852                 { 15250, 14125, },
1853                 { 15375, 14250, },
1854                 { 15500, 14375, },
1855                 { 15625, 14500, },
1856                 { 15750, 14625, },
1857                 { 15875, 14750, },
1858                 { 16000, 14875, },
1859                 { 16125, 15000, },
1860         };
1861         if (dev_priv->info->is_mobile)
1862                 return v_table[pxvid].vm;
1863         else
1864                 return v_table[pxvid].vd;
1865 }
1866
1867 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1868 {
1869         struct timespec now, diff1;
1870         u64 diff;
1871         unsigned long diffms;
1872         u32 count;
1873
1874         if (dev_priv->info->gen != 5)
1875                 return;
1876
1877         nanotime(&now);
1878         diff1 = now;
1879         timespecsub(&diff1, &dev_priv->last_time2);
1880
1881         /* Don't divide by 0 */
1882         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1883         if (!diffms)
1884                 return;
1885
1886         count = I915_READ(GFXEC);
1887
1888         if (count < dev_priv->last_count2) {
1889                 diff = ~0UL - dev_priv->last_count2;
1890                 diff += count;
1891         } else {
1892                 diff = count - dev_priv->last_count2;
1893         }
1894
1895         dev_priv->last_count2 = count;
1896         dev_priv->last_time2 = now;
1897
1898         /* More magic constants... */
1899         diff = diff * 1181;
1900         diff = diff / (diffms * 10);
1901         dev_priv->gfx_power = diff;
1902 }
1903
1904 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1905 {
1906         unsigned long t, corr, state1, corr2, state2;
1907         u32 pxvid, ext_v;
1908
1909         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1910         pxvid = (pxvid >> 24) & 0x7f;
1911         ext_v = pvid_to_extvid(dev_priv, pxvid);
1912
1913         state1 = ext_v;
1914
1915         t = i915_mch_val(dev_priv);
1916
1917         /* Revel in the empirically derived constants */
1918
1919         /* Correction factor in 1/100000 units */
1920         if (t > 80)
1921                 corr = ((t * 2349) + 135940);
1922         else if (t >= 50)
1923                 corr = ((t * 964) + 29317);
1924         else /* < 50 */
1925                 corr = ((t * 301) + 1004);
1926
1927         corr = corr * ((150142 * state1) / 10000 - 78642);
1928         corr /= 100000;
1929         corr2 = (corr * dev_priv->corr);
1930
1931         state2 = (corr2 * state1) / 10000;
1932         state2 /= 100; /* convert to mW */
1933
1934         i915_update_gfx_val(dev_priv);
1935
1936         return dev_priv->gfx_power + state2;
1937 }
1938
1939 /**
1940  * i915_read_mch_val - return value for IPS use
1941  *
1942  * Calculate and return a value for the IPS driver to use when deciding whether
1943  * we have thermal and power headroom to increase CPU or GPU power budget.
1944  */
1945 unsigned long i915_read_mch_val(void)
1946 {
1947         struct drm_i915_private *dev_priv;
1948         unsigned long chipset_val, graphics_val, ret = 0;
1949
1950         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1951         if (!i915_mch_dev)
1952                 goto out_unlock;
1953         dev_priv = i915_mch_dev;
1954
1955         chipset_val = i915_chipset_val(dev_priv);
1956         graphics_val = i915_gfx_val(dev_priv);
1957
1958         ret = chipset_val + graphics_val;
1959
1960 out_unlock:
1961         lockmgr(&mchdev_lock, LK_RELEASE);
1962
1963         return ret;
1964 }
1965
1966 /**
1967  * i915_gpu_raise - raise GPU frequency limit
1968  *
1969  * Raise the limit; IPS indicates we have thermal headroom.
1970  */
1971 bool i915_gpu_raise(void)
1972 {
1973         struct drm_i915_private *dev_priv;
1974         bool ret = true;
1975
1976         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1977         if (!i915_mch_dev) {
1978                 ret = false;
1979                 goto out_unlock;
1980         }
1981         dev_priv = i915_mch_dev;
1982
1983         if (dev_priv->max_delay > dev_priv->fmax)
1984                 dev_priv->max_delay--;
1985
1986 out_unlock:
1987         lockmgr(&mchdev_lock, LK_RELEASE);
1988
1989         return ret;
1990 }
1991
1992 /**
1993  * i915_gpu_lower - lower GPU frequency limit
1994  *
1995  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1996  * frequency maximum.
1997  */
1998 bool i915_gpu_lower(void)
1999 {
2000         struct drm_i915_private *dev_priv;
2001         bool ret = true;
2002
2003         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2004         if (!i915_mch_dev) {
2005                 ret = false;
2006                 goto out_unlock;
2007         }
2008         dev_priv = i915_mch_dev;
2009
2010         if (dev_priv->max_delay < dev_priv->min_delay)
2011                 dev_priv->max_delay++;
2012
2013 out_unlock:
2014         lockmgr(&mchdev_lock, LK_RELEASE);
2015
2016         return ret;
2017 }
2018
2019 /**
2020  * i915_gpu_busy - indicate GPU business to IPS
2021  *
2022  * Tell the IPS driver whether or not the GPU is busy.
2023  */
2024 bool i915_gpu_busy(void)
2025 {
2026         struct drm_i915_private *dev_priv;
2027         bool ret = false;
2028
2029         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2030         if (!i915_mch_dev)
2031                 goto out_unlock;
2032         dev_priv = i915_mch_dev;
2033
2034         ret = dev_priv->busy;
2035
2036 out_unlock:
2037         lockmgr(&mchdev_lock, LK_RELEASE);
2038
2039         return ret;
2040 }
2041
2042 /**
2043  * i915_gpu_turbo_disable - disable graphics turbo
2044  *
2045  * Disable graphics turbo by resetting the max frequency and setting the
2046  * current frequency to the default.
2047  */
2048 bool i915_gpu_turbo_disable(void)
2049 {
2050         struct drm_i915_private *dev_priv;
2051         bool ret = true;
2052
2053         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2054         if (!i915_mch_dev) {
2055                 ret = false;
2056                 goto out_unlock;
2057         }
2058         dev_priv = i915_mch_dev;
2059
2060         dev_priv->max_delay = dev_priv->fstart;
2061
2062         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2063                 ret = false;
2064
2065 out_unlock:
2066         lockmgr(&mchdev_lock, LK_RELEASE);
2067
2068         return ret;
2069 }