2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
73 #include "opt_ifpoll.h"
75 #include <sys/param.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
80 #include <sys/interrupt.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
90 #include <netinet/ip.h>
91 #include <netinet/tcp.h>
94 #include <net/ethernet.h>
96 #include <net/if_arp.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_poll.h>
100 #include <net/if_types.h>
101 #include <net/ifq_var.h>
102 #include <net/vlan/if_vlan_var.h>
103 #include <net/vlan/if_vlan_ether.h>
105 #include <dev/netif/mii_layer/mii.h>
106 #include <dev/netif/mii_layer/miivar.h>
107 #include <dev/netif/mii_layer/brgphyreg.h>
110 #include <bus/pci/pcireg.h>
111 #include <bus/pci/pcivar.h>
113 #include <dev/netif/bge/if_bgereg.h>
114 #include <dev/netif/bge/if_bgevar.h>
116 /* "device miibus" required. See GENERIC if you get errors here. */
117 #include "miibus_if.h"
119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
121 #define BGE_RESET_SHUTDOWN 0
122 #define BGE_RESET_START 1
123 #define BGE_RESET_SUSPEND 2
125 static const struct bge_type {
130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
131 "3COM 3C996 Gigabit Ethernet" },
133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
134 "Alteon BCM5700 Gigabit Ethernet" },
135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
136 "Alteon BCM5701 Gigabit Ethernet" },
138 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
139 "Altima AC1000 Gigabit Ethernet" },
140 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
141 "Altima AC1002 Gigabit Ethernet" },
142 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
143 "Altima AC9100 Gigabit Ethernet" },
145 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
146 "Apple BCM5701 Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
149 "Broadcom BCM5700 Gigabit Ethernet" },
150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
151 "Broadcom BCM5701 Gigabit Ethernet" },
152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
153 "Broadcom BCM5702 Gigabit Ethernet" },
154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
155 "Broadcom BCM5702X Gigabit Ethernet" },
156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
157 "Broadcom BCM5702 Gigabit Ethernet" },
158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
159 "Broadcom BCM5703 Gigabit Ethernet" },
160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
161 "Broadcom BCM5703X Gigabit Ethernet" },
162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
163 "Broadcom BCM5703 Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
165 "Broadcom BCM5704C Dual Gigabit Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
167 "Broadcom BCM5704S Dual Gigabit Ethernet" },
168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
169 "Broadcom BCM5704S Dual Gigabit Ethernet" },
170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
171 "Broadcom BCM5705 Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
173 "Broadcom BCM5705F Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
175 "Broadcom BCM5705K Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
177 "Broadcom BCM5705M Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
179 "Broadcom BCM5705M Gigabit Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
181 "Broadcom BCM5714C Gigabit Ethernet" },
182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
183 "Broadcom BCM5714S Gigabit Ethernet" },
184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
185 "Broadcom BCM5715 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
187 "Broadcom BCM5715S Gigabit Ethernet" },
188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
189 "Broadcom BCM5720 Gigabit Ethernet" },
190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
191 "Broadcom BCM5721 Gigabit Ethernet" },
192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
193 "Broadcom BCM5722 Gigabit Ethernet" },
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
195 "Broadcom BCM5723 Gigabit Ethernet" },
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
197 "Broadcom BCM5750 Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
199 "Broadcom BCM5750M Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
201 "Broadcom BCM5751 Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
203 "Broadcom BCM5751F Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
205 "Broadcom BCM5751M Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
207 "Broadcom BCM5752 Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
209 "Broadcom BCM5752M Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
211 "Broadcom BCM5753 Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
213 "Broadcom BCM5753F Gigabit Ethernet" },
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
215 "Broadcom BCM5753M Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
217 "Broadcom BCM5754 Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
219 "Broadcom BCM5754M Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
221 "Broadcom BCM5755 Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
223 "Broadcom BCM5755M Gigabit Ethernet" },
224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
225 "Broadcom BCM5756 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
227 "Broadcom BCM5761 Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
229 "Broadcom BCM5761E Gigabit Ethernet" },
230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
231 "Broadcom BCM5761S Gigabit Ethernet" },
232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
233 "Broadcom BCM5761SE Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
235 "Broadcom BCM5764 Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
237 "Broadcom BCM5780 Gigabit Ethernet" },
238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
239 "Broadcom BCM5780S Gigabit Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
241 "Broadcom BCM5781 Gigabit Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
243 "Broadcom BCM5782 Gigabit Ethernet" },
244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
245 "Broadcom BCM5784 Gigabit Ethernet" },
246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
247 "Broadcom BCM5785F Gigabit Ethernet" },
248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
249 "Broadcom BCM5785G Gigabit Ethernet" },
250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
251 "Broadcom BCM5786 Gigabit Ethernet" },
252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
253 "Broadcom BCM5787 Gigabit Ethernet" },
254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
255 "Broadcom BCM5787F Gigabit Ethernet" },
256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
257 "Broadcom BCM5787M Gigabit Ethernet" },
258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
259 "Broadcom BCM5788 Gigabit Ethernet" },
260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
261 "Broadcom BCM5789 Gigabit Ethernet" },
262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
263 "Broadcom BCM5901 Fast Ethernet" },
264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
265 "Broadcom BCM5901A2 Fast Ethernet" },
266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
267 "Broadcom BCM5903M Fast Ethernet" },
268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
269 "Broadcom BCM5906 Fast Ethernet"},
270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
271 "Broadcom BCM5906M Fast Ethernet"},
272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
273 "Broadcom BCM57760 Gigabit Ethernet"},
274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
275 "Broadcom BCM57780 Gigabit Ethernet"},
276 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
277 "Broadcom BCM57788 Gigabit Ethernet"},
278 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
279 "Broadcom BCM57790 Gigabit Ethernet"},
280 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
281 "SysKonnect Gigabit Ethernet" },
286 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
287 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
288 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
289 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
290 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
291 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
292 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788)
294 #define BGE_IS_CRIPPLED(sc) \
295 (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
297 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
299 static int bge_probe(device_t);
300 static int bge_attach(device_t);
301 static int bge_detach(device_t);
302 static void bge_txeof(struct bge_softc *, uint16_t);
303 static void bge_rxeof(struct bge_softc *, uint16_t, int);
305 static void bge_tick(void *);
306 static void bge_stats_update(struct bge_softc *);
307 static void bge_stats_update_regs(struct bge_softc *);
309 bge_defrag_shortdma(struct mbuf *);
310 static int bge_encap(struct bge_softc *, struct mbuf **,
312 static void bge_xmit(struct bge_softc *, uint32_t);
313 static int bge_setup_tso(struct bge_softc *, struct mbuf **,
314 uint16_t *, uint16_t *);
317 static void bge_npoll(struct ifnet *, struct ifpoll_info *);
318 static void bge_npoll_compat(struct ifnet *, void *, int );
320 static void bge_intr_crippled(void *);
321 static void bge_intr_legacy(void *);
322 static void bge_msi(void *);
323 static void bge_msi_oneshot(void *);
324 static void bge_intr(struct bge_softc *);
325 static void bge_enable_intr(struct bge_softc *);
326 static void bge_disable_intr(struct bge_softc *);
327 static void bge_start(struct ifnet *, struct ifaltq_subque *);
328 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
329 static void bge_init(void *);
330 static void bge_stop(struct bge_softc *);
331 static void bge_watchdog(struct ifnet *);
332 static void bge_shutdown(device_t);
333 static int bge_suspend(device_t);
334 static int bge_resume(device_t);
335 static int bge_ifmedia_upd(struct ifnet *);
336 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
338 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
339 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
341 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
342 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
344 static void bge_setmulti(struct bge_softc *);
345 static void bge_setpromisc(struct bge_softc *);
346 static void bge_enable_msi(struct bge_softc *sc);
348 static int bge_alloc_jumbo_mem(struct bge_softc *);
349 static void bge_free_jumbo_mem(struct bge_softc *);
350 static struct bge_jslot
351 *bge_jalloc(struct bge_softc *);
352 static void bge_jfree(void *);
353 static void bge_jref(void *);
354 static int bge_newbuf_std(struct bge_softc *, int, int);
355 static int bge_newbuf_jumbo(struct bge_softc *, int, int);
356 static void bge_setup_rxdesc_std(struct bge_softc *, int);
357 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int);
358 static int bge_init_rx_ring_std(struct bge_softc *);
359 static void bge_free_rx_ring_std(struct bge_softc *);
360 static int bge_init_rx_ring_jumbo(struct bge_softc *);
361 static void bge_free_rx_ring_jumbo(struct bge_softc *);
362 static void bge_free_tx_ring(struct bge_softc *);
363 static int bge_init_tx_ring(struct bge_softc *);
365 static int bge_chipinit(struct bge_softc *);
366 static int bge_blockinit(struct bge_softc *);
367 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
369 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
370 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
372 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
374 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
375 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
376 static void bge_writembx(struct bge_softc *, int, int);
378 static int bge_miibus_readreg(device_t, int, int);
379 static int bge_miibus_writereg(device_t, int, int, int);
380 static void bge_miibus_statchg(device_t);
381 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
382 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
383 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
384 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t);
385 static void bge_link_poll(struct bge_softc *);
387 static void bge_reset(struct bge_softc *);
389 static int bge_dma_alloc(struct bge_softc *);
390 static void bge_dma_free(struct bge_softc *);
391 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
392 bus_dma_tag_t *, bus_dmamap_t *,
393 void **, bus_addr_t *);
394 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
396 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
397 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
398 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
399 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
401 static void bge_coal_change(struct bge_softc *);
402 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
403 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
404 static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
405 static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
406 static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
407 static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
408 static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
409 static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
410 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
413 static void bge_sig_post_reset(struct bge_softc *, int);
414 static void bge_sig_legacy(struct bge_softc *, int);
415 static void bge_sig_pre_reset(struct bge_softc *, int);
416 static void bge_stop_fw(struct bge_softc *);
417 static void bge_asf_driver_up(struct bge_softc *);
420 * Set following tunable to 1 for some IBM blade servers with the DNLK
421 * switch module. Auto negotiation is broken for those configurations.
423 static int bge_fake_autoneg = 0;
424 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
426 static int bge_msi_enable = 1;
427 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable);
429 static int bge_allow_asf = 1;
430 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
432 #if !defined(KTR_IF_BGE)
433 #define KTR_IF_BGE KTR_ALL
435 KTR_INFO_MASTER(if_bge);
436 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
437 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
438 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
439 #define logif(name) KTR_LOG(if_bge_ ## name)
441 static device_method_t bge_methods[] = {
442 /* Device interface */
443 DEVMETHOD(device_probe, bge_probe),
444 DEVMETHOD(device_attach, bge_attach),
445 DEVMETHOD(device_detach, bge_detach),
446 DEVMETHOD(device_shutdown, bge_shutdown),
447 DEVMETHOD(device_suspend, bge_suspend),
448 DEVMETHOD(device_resume, bge_resume),
451 DEVMETHOD(bus_print_child, bus_generic_print_child),
452 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
455 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
456 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
457 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
462 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
463 static devclass_t bge_devclass;
465 DECLARE_DUMMY_MODULE(if_bge);
466 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
467 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
470 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
472 device_t dev = sc->bge_dev;
475 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
476 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
479 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
480 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
481 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
486 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
488 device_t dev = sc->bge_dev;
490 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
491 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
494 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
495 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
496 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
501 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
503 device_t dev = sc->bge_dev;
505 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
506 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
511 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
513 device_t dev = sc->bge_dev;
515 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
516 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
520 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
522 CSR_WRITE_4(sc, off, val);
526 bge_writembx(struct bge_softc *sc, int off, int val)
528 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
529 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
531 CSR_WRITE_4(sc, off, val);
532 if (sc->bge_mbox_reorder)
537 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
539 uint32_t access, byte = 0;
543 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
544 for (i = 0; i < 8000; i++) {
545 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
553 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
554 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
556 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
557 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
558 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
560 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
566 if (i == BGE_TIMEOUT * 10) {
567 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
572 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
574 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
576 /* Disable access. */
577 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
580 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
581 CSR_READ_4(sc, BGE_NVRAM_SWARB);
587 * Read a sequence of bytes from NVRAM.
590 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
595 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
598 for (i = 0; i < cnt; i++) {
599 err = bge_nvram_getbyte(sc, off + i, &byte);
605 return (err ? 1 : 0);
609 * Read a byte of data stored in the EEPROM at address 'addr.' The
610 * BCM570x supports both the traditional bitbang interface and an
611 * auto access interface for reading the EEPROM. We use the auto
615 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
621 * Enable use of auto EEPROM access so we can avoid
622 * having to use the bitbang method.
624 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
626 /* Reset the EEPROM, load the clock period. */
627 CSR_WRITE_4(sc, BGE_EE_ADDR,
628 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
631 /* Issue the read EEPROM command. */
632 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
634 /* Wait for completion */
635 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
637 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
641 if (i == BGE_TIMEOUT) {
642 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
647 byte = CSR_READ_4(sc, BGE_EE_DATA);
649 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
655 * Read a sequence of bytes from the EEPROM.
658 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
664 for (byte = 0, err = 0, i = 0; i < len; i++) {
665 err = bge_eeprom_getbyte(sc, off + i, &byte);
675 bge_miibus_readreg(device_t dev, int phy, int reg)
677 struct bge_softc *sc = device_get_softc(dev);
681 KASSERT(phy == sc->bge_phyno,
682 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
684 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
685 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
686 CSR_WRITE_4(sc, BGE_MI_MODE,
687 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
691 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
692 BGE_MIPHY(phy) | BGE_MIREG(reg));
694 /* Poll for the PHY register access to complete. */
695 for (i = 0; i < BGE_TIMEOUT; i++) {
697 val = CSR_READ_4(sc, BGE_MI_COMM);
698 if ((val & BGE_MICOMM_BUSY) == 0) {
700 val = CSR_READ_4(sc, BGE_MI_COMM);
704 if (i == BGE_TIMEOUT) {
705 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
706 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
710 /* Restore the autopoll bit if necessary. */
711 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
712 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
716 if (val & BGE_MICOMM_READFAIL)
719 return (val & 0xFFFF);
723 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
725 struct bge_softc *sc = device_get_softc(dev);
728 KASSERT(phy == sc->bge_phyno,
729 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
731 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
732 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
735 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
736 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
737 CSR_WRITE_4(sc, BGE_MI_MODE,
738 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
742 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
743 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
745 for (i = 0; i < BGE_TIMEOUT; i++) {
747 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
749 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
753 if (i == BGE_TIMEOUT) {
754 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
755 "(phy %d, reg %d, val %d)\n", phy, reg, val);
758 /* Restore the autopoll bit if necessary. */
759 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
760 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
768 bge_miibus_statchg(device_t dev)
770 struct bge_softc *sc;
771 struct mii_data *mii;
774 sc = device_get_softc(dev);
775 if ((sc->arpcom.ac_if.if_flags & IFF_RUNNING) == 0)
778 mii = device_get_softc(sc->bge_miibus);
780 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
781 (IFM_ACTIVE | IFM_AVALID)) {
782 switch (IFM_SUBTYPE(mii->mii_media_active)) {
790 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
802 if (sc->bge_link == 0)
806 * APE firmware touches these registers to keep the MAC
807 * connected to the outside world. Try to keep the
811 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
812 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
814 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
815 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
816 mac_mode |= BGE_PORTMODE_GMII;
818 mac_mode |= BGE_PORTMODE_MII;
820 if ((mii->mii_media_active & IFM_GMASK) != IFM_FDX)
821 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
823 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
827 * Memory management for jumbo frames.
830 bge_alloc_jumbo_mem(struct bge_softc *sc)
832 struct ifnet *ifp = &sc->arpcom.ac_if;
833 struct bge_jslot *entry;
839 * Create tag for jumbo mbufs.
840 * This is really a bit of a kludge. We allocate a special
841 * jumbo buffer pool which (thanks to the way our DMA
842 * memory allocation works) will consist of contiguous
843 * pages. This means that even though a jumbo buffer might
844 * be larger than a page size, we don't really need to
845 * map it into more than one DMA segment. However, the
846 * default mbuf tag will result in multi-segment mappings,
847 * so we have to create a special jumbo mbuf tag that
848 * lets us get away with mapping the jumbo buffers as
849 * a single segment. I think eventually the driver should
850 * be changed so that it uses ordinary mbufs and cluster
851 * buffers, i.e. jumbo frames can span multiple DMA
852 * descriptors. But that's a project for another day.
856 * Create DMA stuffs for jumbo RX ring.
858 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
859 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
860 &sc->bge_cdata.bge_rx_jumbo_ring_map,
861 (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
862 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
864 if_printf(ifp, "could not create jumbo RX ring\n");
869 * Create DMA stuffs for jumbo buffer block.
871 error = bge_dma_block_alloc(sc, BGE_JMEM,
872 &sc->bge_cdata.bge_jumbo_tag,
873 &sc->bge_cdata.bge_jumbo_map,
874 (void **)&sc->bge_ldata.bge_jumbo_buf,
877 if_printf(ifp, "could not create jumbo buffer\n");
881 SLIST_INIT(&sc->bge_jfree_listhead);
884 * Now divide it up into 9K pieces and save the addresses
885 * in an array. Note that we play an evil trick here by using
886 * the first few bytes in the buffer to hold the the address
887 * of the softc structure for this interface. This is because
888 * bge_jfree() needs it, but it is called by the mbuf management
889 * code which will not pass it to us explicitly.
891 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
892 entry = &sc->bge_cdata.bge_jslots[i];
894 entry->bge_buf = ptr;
895 entry->bge_paddr = paddr;
896 entry->bge_inuse = 0;
898 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
907 bge_free_jumbo_mem(struct bge_softc *sc)
909 /* Destroy jumbo RX ring. */
910 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
911 sc->bge_cdata.bge_rx_jumbo_ring_map,
912 sc->bge_ldata.bge_rx_jumbo_ring);
914 /* Destroy jumbo buffer block. */
915 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
916 sc->bge_cdata.bge_jumbo_map,
917 sc->bge_ldata.bge_jumbo_buf);
921 * Allocate a jumbo buffer.
923 static struct bge_jslot *
924 bge_jalloc(struct bge_softc *sc)
926 struct bge_jslot *entry;
928 lwkt_serialize_enter(&sc->bge_jslot_serializer);
929 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
931 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
932 entry->bge_inuse = 1;
934 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
936 lwkt_serialize_exit(&sc->bge_jslot_serializer);
941 * Adjust usage count on a jumbo buffer.
946 struct bge_jslot *entry = (struct bge_jslot *)arg;
947 struct bge_softc *sc = entry->bge_sc;
950 panic("bge_jref: can't find softc pointer!");
952 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
953 panic("bge_jref: asked to reference buffer "
954 "that we don't manage!");
955 } else if (entry->bge_inuse == 0) {
956 panic("bge_jref: buffer already free!");
958 atomic_add_int(&entry->bge_inuse, 1);
963 * Release a jumbo buffer.
968 struct bge_jslot *entry = (struct bge_jslot *)arg;
969 struct bge_softc *sc = entry->bge_sc;
972 panic("bge_jfree: can't find softc pointer!");
974 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
975 panic("bge_jfree: asked to free buffer that we don't manage!");
976 } else if (entry->bge_inuse == 0) {
977 panic("bge_jfree: buffer already free!");
980 * Possible MP race to 0, use the serializer. The atomic insn
981 * is still needed for races against bge_jref().
983 lwkt_serialize_enter(&sc->bge_jslot_serializer);
984 atomic_subtract_int(&entry->bge_inuse, 1);
985 if (entry->bge_inuse == 0) {
986 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
989 lwkt_serialize_exit(&sc->bge_jslot_serializer);
995 * Intialize a standard receive ring descriptor.
998 bge_newbuf_std(struct bge_softc *sc, int i, int init)
1000 struct mbuf *m_new = NULL;
1001 bus_dma_segment_t seg;
1005 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1008 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1010 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1011 m_adj(m_new, ETHER_ALIGN);
1013 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
1014 sc->bge_cdata.bge_rx_tmpmap, m_new,
1015 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1022 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1023 sc->bge_cdata.bge_rx_std_dmamap[i],
1024 BUS_DMASYNC_POSTREAD);
1025 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1026 sc->bge_cdata.bge_rx_std_dmamap[i]);
1029 map = sc->bge_cdata.bge_rx_tmpmap;
1030 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
1031 sc->bge_cdata.bge_rx_std_dmamap[i] = map;
1033 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
1034 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1036 bge_setup_rxdesc_std(sc, i);
1041 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1043 struct bge_rxchain *rc;
1044 struct bge_rx_bd *r;
1046 rc = &sc->bge_cdata.bge_rx_std_chain[i];
1047 r = &sc->bge_ldata.bge_rx_std_ring[i];
1049 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1050 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1051 r->bge_len = rc->bge_mbuf->m_len;
1053 r->bge_flags = BGE_RXBDFLAG_END;
1057 * Initialize a jumbo receive ring descriptor. This allocates
1058 * a jumbo buffer from the pool managed internally by the driver.
1061 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1063 struct mbuf *m_new = NULL;
1064 struct bge_jslot *buf;
1067 /* Allocate the mbuf. */
1068 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1072 /* Allocate the jumbo buffer */
1073 buf = bge_jalloc(sc);
1079 /* Attach the buffer to the mbuf. */
1080 m_new->m_ext.ext_arg = buf;
1081 m_new->m_ext.ext_buf = buf->bge_buf;
1082 m_new->m_ext.ext_free = bge_jfree;
1083 m_new->m_ext.ext_ref = bge_jref;
1084 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1086 m_new->m_flags |= M_EXT;
1088 m_new->m_data = m_new->m_ext.ext_buf;
1089 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1091 paddr = buf->bge_paddr;
1092 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1093 m_adj(m_new, ETHER_ALIGN);
1094 paddr += ETHER_ALIGN;
1097 /* Save necessary information */
1098 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1099 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1101 /* Set up the descriptor. */
1102 bge_setup_rxdesc_jumbo(sc, i);
1107 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1109 struct bge_rx_bd *r;
1110 struct bge_rxchain *rc;
1112 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1113 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1115 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1116 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1117 r->bge_len = rc->bge_mbuf->m_len;
1119 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1123 bge_init_rx_ring_std(struct bge_softc *sc)
1127 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1128 error = bge_newbuf_std(sc, i, 1);
1133 sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1134 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1140 bge_free_rx_ring_std(struct bge_softc *sc)
1144 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1145 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1147 if (rc->bge_mbuf != NULL) {
1148 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1149 sc->bge_cdata.bge_rx_std_dmamap[i]);
1150 m_freem(rc->bge_mbuf);
1151 rc->bge_mbuf = NULL;
1153 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1154 sizeof(struct bge_rx_bd));
1159 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1161 struct bge_rcb *rcb;
1164 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1165 error = bge_newbuf_jumbo(sc, i, 1);
1170 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1172 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1173 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1174 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1176 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1182 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1186 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1187 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1189 if (rc->bge_mbuf != NULL) {
1190 m_freem(rc->bge_mbuf);
1191 rc->bge_mbuf = NULL;
1193 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1194 sizeof(struct bge_rx_bd));
1199 bge_free_tx_ring(struct bge_softc *sc)
1203 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1204 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1205 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1206 sc->bge_cdata.bge_tx_dmamap[i]);
1207 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1208 sc->bge_cdata.bge_tx_chain[i] = NULL;
1210 bzero(&sc->bge_ldata.bge_tx_ring[i],
1211 sizeof(struct bge_tx_bd));
1216 bge_init_tx_ring(struct bge_softc *sc)
1219 sc->bge_tx_saved_considx = 0;
1220 sc->bge_tx_prodidx = 0;
1222 /* Initialize transmit producer index for host-memory send ring. */
1223 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1225 /* 5700 b2 errata */
1226 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1227 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1229 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1230 /* 5700 b2 errata */
1231 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1232 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1238 bge_setmulti(struct bge_softc *sc)
1241 struct ifmultiaddr *ifma;
1242 uint32_t hashes[4] = { 0, 0, 0, 0 };
1245 ifp = &sc->arpcom.ac_if;
1247 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1248 for (i = 0; i < 4; i++)
1249 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1253 /* First, zot all the existing filters. */
1254 for (i = 0; i < 4; i++)
1255 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1257 /* Now program new ones. */
1258 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1259 if (ifma->ifma_addr->sa_family != AF_LINK)
1262 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1263 ETHER_ADDR_LEN) & 0x7f;
1264 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1267 for (i = 0; i < 4; i++)
1268 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1272 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1273 * self-test results.
1276 bge_chipinit(struct bge_softc *sc)
1279 uint32_t dma_rw_ctl, mode_ctl;
1282 /* Set endian type before we access any non-PCI registers. */
1283 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1284 BGE_INIT | sc->bge_pci_miscctl, 4);
1286 /* Clear the MAC control register */
1287 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1290 * Clear the MAC statistics block in the NIC's
1293 for (i = BGE_STATS_BLOCK;
1294 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1295 BGE_MEMWIN_WRITE(sc, i, 0);
1297 for (i = BGE_STATUS_BLOCK;
1298 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1299 BGE_MEMWIN_WRITE(sc, i, 0);
1301 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1303 * Fix data corruption caused by non-qword write with WB.
1304 * Fix master abort in PCI mode.
1305 * Fix PCI latency timer.
1307 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1308 val |= (1 << 10) | (1 << 12) | (1 << 13);
1309 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1312 /* Set up the PCI DMA control register. */
1313 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
1314 if (sc->bge_flags & BGE_FLAG_PCIE) {
1316 /* DMA read watermark not used on PCI-E */
1317 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1318 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1320 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1321 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1322 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1323 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1324 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) {
1325 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1326 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1327 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1328 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1329 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1330 uint32_t rd_wat = 0x7;
1333 clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1334 if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) &&
1335 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1337 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1338 } else if (clkctl == 0x6 || clkctl == 0x7) {
1340 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1342 if (sc->bge_asicrev == BGE_ASICREV_BCM5703)
1345 dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1346 (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1347 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1349 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1350 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1354 /* Conventional PCI bus */
1355 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1356 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1357 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1358 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1362 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1363 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1364 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1365 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1366 sc->bge_asicrev == BGE_ASICREV_BCM5701) {
1367 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1368 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1370 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1373 * Set up general mode register.
1375 mode_ctl = BGE_DMA_SWAP_OPTIONS|
1376 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1377 BGE_MODECTL_TX_NO_PHDR_CSUM;
1380 * BCM5701 B5 have a bug causing data corruption when using
1381 * 64-bit DMA reads, which can be terminated early and then
1382 * completed later as 32-bit accesses, in combination with
1385 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1386 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1387 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1390 * Tell the firmware the driver is running
1392 if (sc->bge_asf_mode & ASF_STACKUP)
1393 mode_ctl |= BGE_MODECTL_STACKUP;
1395 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1398 * Disable memory write invalidate. Apparently it is not supported
1399 * properly by these devices. Also ensure that INTx isn't disabled,
1400 * as these chips need it even when using MSI.
1402 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1403 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1405 /* Set the timer prescaler (always 66Mhz) */
1406 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1408 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1409 DELAY(40); /* XXX */
1411 /* Put PHY into ready state */
1412 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1413 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1421 bge_blockinit(struct bge_softc *sc)
1423 struct bge_rcb *rcb;
1430 * Initialize the memory window pointer register so that
1431 * we can access the first 32K of internal NIC RAM. This will
1432 * allow us to set up the TX send ring RCBs and the RX return
1433 * ring RCBs, plus other things which live in NIC memory.
1435 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1437 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1439 if (!BGE_IS_5705_PLUS(sc)) {
1440 /* Configure mbuf memory pool */
1441 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1442 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1443 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1445 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1447 /* Configure DMA resource pool */
1448 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1449 BGE_DMA_DESCRIPTORS);
1450 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1453 /* Configure mbuf pool watermarks */
1454 if (!BGE_IS_5705_PLUS(sc)) {
1455 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1456 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1457 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1458 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1459 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1460 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1461 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1463 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1464 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1465 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1468 /* Configure DMA resource watermarks */
1469 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1470 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1472 /* Enable buffer manager */
1473 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1474 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1476 /* Poll for buffer manager start indication */
1477 for (i = 0; i < BGE_TIMEOUT; i++) {
1478 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1483 if (i == BGE_TIMEOUT) {
1484 if_printf(&sc->arpcom.ac_if,
1485 "buffer manager failed to start\n");
1489 /* Enable flow-through queues */
1490 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1491 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1493 /* Wait until queue initialization is complete */
1494 for (i = 0; i < BGE_TIMEOUT; i++) {
1495 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1500 if (i == BGE_TIMEOUT) {
1501 if_printf(&sc->arpcom.ac_if,
1502 "flow-through queue init failed\n");
1507 * Summary of rings supported by the controller:
1509 * Standard Receive Producer Ring
1510 * - This ring is used to feed receive buffers for "standard"
1511 * sized frames (typically 1536 bytes) to the controller.
1513 * Jumbo Receive Producer Ring
1514 * - This ring is used to feed receive buffers for jumbo sized
1515 * frames (i.e. anything bigger than the "standard" frames)
1516 * to the controller.
1518 * Mini Receive Producer Ring
1519 * - This ring is used to feed receive buffers for "mini"
1520 * sized frames to the controller.
1521 * - This feature required external memory for the controller
1522 * but was never used in a production system. Should always
1525 * Receive Return Ring
1526 * - After the controller has placed an incoming frame into a
1527 * receive buffer that buffer is moved into a receive return
1528 * ring. The driver is then responsible to passing the
1529 * buffer up to the stack. Many versions of the controller
1530 * support multiple RR rings.
1533 * - This ring is used for outgoing frames. Many versions of
1534 * the controller support multiple send rings.
1537 /* Initialize the standard receive producer ring control block. */
1538 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1539 rcb->bge_hostaddr.bge_addr_lo =
1540 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1541 rcb->bge_hostaddr.bge_addr_hi =
1542 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1543 if (BGE_IS_5705_PLUS(sc)) {
1545 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1546 * Bits 15-2 : Reserved (should be 0)
1547 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1550 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1553 * Ring size is always XXX entries
1554 * Bits 31-16: Maximum RX frame size
1555 * Bits 15-2 : Reserved (should be 0)
1556 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1559 rcb->bge_maxlen_flags =
1560 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1562 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1563 /* Write the standard receive producer ring control block. */
1564 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1565 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1566 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1567 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1568 /* Reset the standard receive producer ring producer index. */
1569 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1572 * Initialize the jumbo RX producer ring control
1573 * block. We set the 'ring disabled' bit in the
1574 * flags field until we're actually ready to start
1575 * using this ring (i.e. once we set the MTU
1576 * high enough to require it).
1578 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1579 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1580 /* Get the jumbo receive producer ring RCB parameters. */
1581 rcb->bge_hostaddr.bge_addr_lo =
1582 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1583 rcb->bge_hostaddr.bge_addr_hi =
1584 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1585 rcb->bge_maxlen_flags =
1586 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1587 BGE_RCB_FLAG_RING_DISABLED);
1588 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1589 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1590 rcb->bge_hostaddr.bge_addr_hi);
1591 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1592 rcb->bge_hostaddr.bge_addr_lo);
1593 /* Program the jumbo receive producer ring RCB parameters. */
1594 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1595 rcb->bge_maxlen_flags);
1596 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1597 /* Reset the jumbo receive producer ring producer index. */
1598 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1601 /* Disable the mini receive producer ring RCB. */
1602 if (BGE_IS_5700_FAMILY(sc)) {
1603 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1604 rcb->bge_maxlen_flags =
1605 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1606 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1607 rcb->bge_maxlen_flags);
1608 /* Reset the mini receive producer ring producer index. */
1609 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1612 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1613 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1614 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1615 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1616 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1617 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1618 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1622 * The BD ring replenish thresholds control how often the
1623 * hardware fetches new BD's from the producer rings in host
1624 * memory. Setting the value too low on a busy system can
1625 * starve the hardware and recue the throughpout.
1627 * Set the BD ring replentish thresholds. The recommended
1628 * values are 1/8th the number of descriptors allocated to
1631 if (BGE_IS_5705_PLUS(sc))
1634 val = BGE_STD_RX_RING_CNT / 8;
1635 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1636 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1637 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1638 BGE_JUMBO_RX_RING_CNT/8);
1642 * Disable all send rings by setting the 'ring disabled' bit
1643 * in the flags field of all the TX send ring control blocks,
1644 * located in NIC memory.
1646 if (!BGE_IS_5705_PLUS(sc)) {
1647 /* 5700 to 5704 had 16 send rings. */
1648 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1652 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1653 for (i = 0; i < limit; i++) {
1654 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1655 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1656 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1657 vrcb += sizeof(struct bge_rcb);
1660 /* Configure send ring RCB 0 (we use only the first ring) */
1661 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1662 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1663 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1664 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1665 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1666 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1667 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1668 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1671 * Disable all receive return rings by setting the
1672 * 'ring diabled' bit in the flags field of all the receive
1673 * return ring control blocks, located in NIC memory.
1675 if (!BGE_IS_5705_PLUS(sc))
1676 limit = BGE_RX_RINGS_MAX;
1677 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1681 /* Disable all receive return rings. */
1682 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1683 for (i = 0; i < limit; i++) {
1684 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1685 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1686 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1687 BGE_RCB_FLAG_RING_DISABLED);
1688 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1689 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1690 (i * (sizeof(uint64_t))), 0);
1691 vrcb += sizeof(struct bge_rcb);
1695 * Set up receive return ring 0. Note that the NIC address
1696 * for RX return rings is 0x0. The return rings live entirely
1697 * within the host, so the nicaddr field in the RCB isn't used.
1699 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1700 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1701 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1702 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1703 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1704 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1705 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1707 /* Set random backoff seed for TX */
1708 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1709 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1710 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1711 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1712 BGE_TX_BACKOFF_SEED_MASK);
1714 /* Set inter-packet gap */
1715 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1718 * Specify which ring to use for packets that don't match
1721 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1724 * Configure number of RX lists. One interrupt distribution
1725 * list, sixteen active lists, one bad frames class.
1727 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1729 /* Inialize RX list placement stats mask. */
1730 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1731 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1733 /* Disable host coalescing until we get it set up */
1734 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1736 /* Poll to make sure it's shut down. */
1737 for (i = 0; i < BGE_TIMEOUT; i++) {
1738 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1743 if (i == BGE_TIMEOUT) {
1744 if_printf(&sc->arpcom.ac_if,
1745 "host coalescing engine failed to idle\n");
1749 /* Set up host coalescing defaults */
1750 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1751 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1752 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1753 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1754 if (!BGE_IS_5705_PLUS(sc)) {
1755 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1756 sc->bge_rx_coal_ticks_int);
1757 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1758 sc->bge_tx_coal_ticks_int);
1762 * The datasheet (57XX-PG105-R) says BCM5705+ do not
1763 * have following two registers; obviously it is wrong.
1765 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1766 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1768 /* Set up address of statistics block */
1769 if (!BGE_IS_5705_PLUS(sc)) {
1770 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1771 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1772 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1773 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1775 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1776 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1777 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1780 /* Set up address of status block */
1781 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1782 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1783 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1784 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1785 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1788 * Set up status block partail update size.
1790 * Because only single TX ring, RX produce ring and Rx return ring
1791 * are used, ask device to update only minimum part of status block
1792 * except for BCM5700 AX/BX, whose status block partial update size
1793 * can't be configured.
1795 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1796 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1797 /* XXX Actually reserved on BCM5700 AX/BX */
1798 val = BGE_STATBLKSZ_FULL;
1800 val = BGE_STATBLKSZ_32BYTE;
1804 * Does not seem to have visible effect in both
1805 * bulk data (1472B UDP datagram) and tiny data
1806 * (18B UDP datagram) TX tests.
1808 if (!BGE_IS_CRIPPLED(sc))
1809 val |= BGE_HCCMODE_CLRTICK_TX;
1812 /* Turn on host coalescing state machine */
1813 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1815 /* Turn on RX BD completion state machine and enable attentions */
1816 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1817 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1819 /* Turn on RX list placement state machine */
1820 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1822 /* Turn on RX list selector state machine. */
1823 if (!BGE_IS_5705_PLUS(sc))
1824 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1826 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1827 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1828 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1829 BGE_MACMODE_FRMHDR_DMA_ENB;
1831 if (sc->bge_flags & BGE_FLAG_TBI)
1832 val |= BGE_PORTMODE_TBI;
1833 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1834 val |= BGE_PORTMODE_GMII;
1836 val |= BGE_PORTMODE_MII;
1838 /* Turn on DMA, clear stats */
1839 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1841 /* Set misc. local control, enable interrupts on attentions */
1842 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1845 /* Assert GPIO pins for PHY reset */
1846 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1847 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1848 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1849 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1852 /* Turn on DMA completion state machine */
1853 if (!BGE_IS_5705_PLUS(sc))
1854 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1856 /* Turn on write DMA state machine */
1857 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1858 if (BGE_IS_5755_PLUS(sc)) {
1859 /* Enable host coalescing bug fix. */
1860 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1862 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1863 /* Request larger DMA burst size to get better performance. */
1864 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1866 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1869 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1870 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1871 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1872 sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1874 * Enable fix for read DMA FIFO overruns.
1875 * The fix is to limit the number of RX BDs
1876 * the hardware would fetch at a fime.
1878 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1879 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1880 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1883 /* Turn on read DMA state machine */
1884 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1885 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1886 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1887 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1888 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1889 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1890 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1891 if (sc->bge_flags & BGE_FLAG_PCIE)
1892 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1893 if (sc->bge_flags & BGE_FLAG_TSO)
1894 val |= BGE_RDMAMODE_TSO4_ENABLE;
1895 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1898 /* Turn on RX data completion state machine */
1899 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1901 /* Turn on RX BD initiator state machine */
1902 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1904 /* Turn on RX data and RX BD initiator state machine */
1905 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1907 /* Turn on Mbuf cluster free state machine */
1908 if (!BGE_IS_5705_PLUS(sc))
1909 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1911 /* Turn on send BD completion state machine */
1912 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1914 /* Turn on send data completion state machine */
1915 val = BGE_SDCMODE_ENABLE;
1916 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1917 val |= BGE_SDCMODE_CDELAY;
1918 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1920 /* Turn on send data initiator state machine */
1921 if (sc->bge_flags & BGE_FLAG_TSO)
1922 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1923 BGE_SDIMODE_HW_LSO_PRE_DMA);
1925 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1927 /* Turn on send BD initiator state machine */
1928 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1930 /* Turn on send BD selector state machine */
1931 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1933 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1934 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1935 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1937 /* ack/clear link change events */
1938 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1939 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1940 BGE_MACSTAT_LINK_CHANGED);
1941 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1944 * Enable attention when the link has changed state for
1945 * devices that use auto polling.
1947 if (sc->bge_flags & BGE_FLAG_TBI) {
1948 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1950 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1951 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1954 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1955 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1956 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1957 BGE_EVTENB_MI_INTERRUPT);
1962 * Clear any pending link state attention.
1963 * Otherwise some link state change events may be lost until attention
1964 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1965 * It's not necessary on newer BCM chips - perhaps enabling link
1966 * state change attentions implies clearing pending attention.
1968 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1969 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1970 BGE_MACSTAT_LINK_CHANGED);
1972 /* Enable link state change attentions. */
1973 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1979 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1980 * against our list and return its name if we find a match. Note
1981 * that since the Broadcom controller contains VPD support, we
1982 * can get the device name string from the controller itself instead
1983 * of the compiled-in string. This is a little slow, but it guarantees
1984 * we'll always announce the right product name.
1987 bge_probe(device_t dev)
1989 const struct bge_type *t;
1990 uint16_t product, vendor;
1992 product = pci_get_device(dev);
1993 vendor = pci_get_vendor(dev);
1995 for (t = bge_devs; t->bge_name != NULL; t++) {
1996 if (vendor == t->bge_vid && product == t->bge_did)
1999 if (t->bge_name == NULL)
2002 device_set_desc(dev, t->bge_name);
2007 bge_attach(device_t dev)
2010 struct bge_softc *sc;
2011 uint32_t hwcfg = 0, misccfg;
2012 int error = 0, rid, capmask;
2013 uint8_t ether_addr[ETHER_ADDR_LEN];
2014 uint16_t product, vendor;
2015 driver_intr_t *intr_func;
2016 uintptr_t mii_priv = 0;
2020 sc = device_get_softc(dev);
2022 callout_init_mp(&sc->bge_stat_timer);
2023 lwkt_serialize_init(&sc->bge_jslot_serializer);
2025 product = pci_get_device(dev);
2026 vendor = pci_get_vendor(dev);
2028 #ifndef BURN_BRIDGES
2029 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2032 irq = pci_read_config(dev, PCIR_INTLINE, 4);
2033 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
2035 device_printf(dev, "chip is in D%d power mode "
2036 "-- setting to D0\n", pci_get_powerstate(dev));
2038 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2040 pci_write_config(dev, PCIR_INTLINE, irq, 4);
2041 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
2043 #endif /* !BURN_BRIDGE */
2046 * Map control/status registers.
2048 pci_enable_busmaster(dev);
2051 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2054 if (sc->bge_res == NULL) {
2055 device_printf(dev, "couldn't map memory\n");
2059 sc->bge_btag = rman_get_bustag(sc->bge_res);
2060 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2062 /* Save various chip information */
2064 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2065 BGE_PCIMISCCTL_ASICREV_SHIFT;
2066 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2067 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */
2068 sc->bge_flags |= BGE_FLAG_CPMU;
2069 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2071 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2072 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2074 /* Save chipset family. */
2075 switch (sc->bge_asicrev) {
2076 case BGE_ASICREV_BCM5755:
2077 case BGE_ASICREV_BCM5761:
2078 case BGE_ASICREV_BCM5784:
2079 case BGE_ASICREV_BCM5785:
2080 case BGE_ASICREV_BCM5787:
2081 case BGE_ASICREV_BCM57780:
2082 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2086 case BGE_ASICREV_BCM5700:
2087 case BGE_ASICREV_BCM5701:
2088 case BGE_ASICREV_BCM5703:
2089 case BGE_ASICREV_BCM5704:
2090 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2093 case BGE_ASICREV_BCM5714_A0:
2094 case BGE_ASICREV_BCM5780:
2095 case BGE_ASICREV_BCM5714:
2096 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2099 case BGE_ASICREV_BCM5750:
2100 case BGE_ASICREV_BCM5752:
2101 case BGE_ASICREV_BCM5906:
2102 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2105 case BGE_ASICREV_BCM5705:
2106 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2110 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2111 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2113 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2114 sc->bge_flags |= BGE_FLAG_APE;
2116 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2117 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2118 (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2119 misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2120 sc->bge_flags |= BGE_FLAG_5788;
2122 /* BCM5755 or higher and BCM5906 have short DMA bug. */
2123 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2124 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2127 * Increase STD RX ring prod index by at most 8 for BCM5750,
2128 * BCM5752 and BCM5755 to workaround hardware errata.
2130 if (sc->bge_asicrev == BGE_ASICREV_BCM5750 ||
2131 sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2132 sc->bge_asicrev == BGE_ASICREV_BCM5755)
2133 sc->bge_rx_wreg = 8;
2136 * Check if this is a PCI-X or PCI Express device.
2138 if (BGE_IS_5705_PLUS(sc)) {
2139 if (pci_is_pcie(dev)) {
2140 sc->bge_flags |= BGE_FLAG_PCIE;
2141 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2142 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2146 * Check if the device is in PCI-X Mode.
2147 * (This bit is not valid on PCI Express controllers.)
2149 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2150 BGE_PCISTATE_PCI_BUSMODE) == 0) {
2151 sc->bge_flags |= BGE_FLAG_PCIX;
2152 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2153 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2157 device_printf(dev, "CHIP ID 0x%08x; "
2158 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2159 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2160 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2161 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2165 * The 40bit DMA bug applies to the 5714/5715 controllers and is
2166 * not actually a MAC controller bug but an issue with the embedded
2167 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2169 if ((sc->bge_flags & BGE_FLAG_PCIX) &&
2170 (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0)))
2171 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2174 * When using the BCM5701 in PCI-X mode, data corruption has
2175 * been observed in the first few bytes of some received packets.
2176 * Aligning the packet buffer in memory eliminates the corruption.
2177 * Unfortunately, this misaligns the packet payloads. On platforms
2178 * which do not support unaligned accesses, we will realign the
2179 * payloads by copying the received packets.
2181 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2182 (sc->bge_flags & BGE_FLAG_PCIX))
2183 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2185 if (!BGE_IS_CRIPPLED(sc)) {
2186 if (device_getenv_int(dev, "status_tag", 1)) {
2187 sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2188 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2190 device_printf(dev, "enable status tag\n");
2194 if (BGE_IS_5755_PLUS(sc)) {
2196 * BCM5754 and BCM5787 shares the same ASIC id so
2197 * explicit device id check is required.
2198 * Due to unknown reason TSO does not work on BCM5755M.
2200 if (product != PCI_PRODUCT_BROADCOM_BCM5754 &&
2201 product != PCI_PRODUCT_BROADCOM_BCM5754M &&
2202 product != PCI_PRODUCT_BROADCOM_BCM5755M)
2203 sc->bge_flags |= BGE_FLAG_TSO;
2207 * Set various PHY quirk flags.
2210 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2211 sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2212 pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2213 mii_priv |= BRGPHY_FLAG_NO_3LED;
2215 capmask = MII_CAPMASK_DEFAULT;
2216 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2217 (misccfg == 0x4000 || misccfg == 0x8000)) ||
2218 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2219 vendor == PCI_VENDOR_BROADCOM &&
2220 (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2221 product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2222 product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2223 (vendor == PCI_VENDOR_BROADCOM &&
2224 (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2225 product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2226 product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2227 product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2228 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2230 capmask &= ~BMSR_EXTSTAT;
2233 mii_priv |= BRGPHY_FLAG_WIRESPEED;
2234 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2235 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2236 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2237 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2238 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2239 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
2241 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2242 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2243 mii_priv |= BRGPHY_FLAG_CRC_BUG;
2245 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2246 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2247 mii_priv |= BRGPHY_FLAG_ADC_BUG;
2249 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2250 mii_priv |= BRGPHY_FLAG_5704_A0;
2252 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2253 mii_priv |= BRGPHY_FLAG_5906;
2255 if (BGE_IS_5705_PLUS(sc) &&
2256 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2257 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2258 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2259 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2260 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2261 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2262 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2263 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2264 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2265 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2266 product != PCI_PRODUCT_BROADCOM_BCM5756)
2267 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
2268 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2269 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
2271 mii_priv |= BRGPHY_FLAG_BER_BUG;
2276 * Allocate interrupt
2278 msi_enable = bge_msi_enable;
2279 if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) {
2280 /* If "tagged status" is disabled, don't enable MSI */
2282 } else if (msi_enable) {
2283 msi_enable = 0; /* Disable by default */
2284 if (BGE_IS_575X_PLUS(sc)) {
2286 /* XXX we filter all 5714 chips */
2287 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
2288 (sc->bge_asicrev == BGE_ASICREV_BCM5750 &&
2289 (sc->bge_chiprev == BGE_CHIPREV_5750_AX ||
2290 sc->bge_chiprev == BGE_CHIPREV_5750_BX)))
2292 else if (BGE_IS_5755_PLUS(sc) ||
2293 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2294 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI;
2298 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) {
2299 device_printf(dev, "no MSI capability\n");
2304 sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid,
2307 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid,
2309 if (sc->bge_irq == NULL) {
2310 device_printf(dev, "couldn't map interrupt\n");
2315 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2318 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI;
2320 /* Initialize if_name earlier, so if_printf could be used */
2321 ifp = &sc->arpcom.ac_if;
2322 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2324 sc->bge_asf_mode = 0;
2325 /* No ASF if APE present. */
2326 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
2327 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
2328 BGE_SRAM_DATA_SIG_MAGIC)) {
2329 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
2331 sc->bge_asf_mode |= ASF_ENABLE;
2332 sc->bge_asf_mode |= ASF_STACKUP;
2333 if (BGE_IS_575X_PLUS(sc))
2334 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2340 * Try to reset the chip.
2343 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
2345 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
2346 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
2348 if (bge_chipinit(sc)) {
2349 device_printf(dev, "chip initialization failed\n");
2355 * Get station address
2357 error = bge_get_eaddr(sc, ether_addr);
2359 device_printf(dev, "failed to read station address\n");
2363 /* 5705/5750 limits RX return ring to 512 entries. */
2364 if (BGE_IS_5705_PLUS(sc))
2365 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2367 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2369 error = bge_dma_alloc(sc);
2373 /* Set default tuneable values. */
2374 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2375 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2376 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2377 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2378 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2379 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2380 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2381 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2382 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2383 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2385 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2386 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2387 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2388 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2390 sc->bge_tx_wreg = BGE_TX_WREG_NSEGS;
2392 /* Set up TX spare and reserved descriptor count */
2393 if (sc->bge_flags & BGE_FLAG_TSO) {
2394 sc->bge_txspare = BGE_NSEG_SPARE_TSO;
2395 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO;
2397 sc->bge_txspare = BGE_NSEG_SPARE;
2398 sc->bge_txrsvd = BGE_NSEG_RSVD;
2401 /* Set up ifnet structure */
2403 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2404 ifp->if_ioctl = bge_ioctl;
2405 ifp->if_start = bge_start;
2406 #ifdef IFPOLL_ENABLE
2407 ifp->if_npoll = bge_npoll;
2409 ifp->if_watchdog = bge_watchdog;
2410 ifp->if_init = bge_init;
2411 ifp->if_mtu = ETHERMTU;
2412 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2413 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2414 ifq_set_ready(&ifp->if_snd);
2417 * 5700 B0 chips do not support checksumming correctly due
2420 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2421 ifp->if_capabilities |= IFCAP_HWCSUM;
2422 ifp->if_hwassist |= BGE_CSUM_FEATURES;
2424 if (sc->bge_flags & BGE_FLAG_TSO) {
2425 ifp->if_capabilities |= IFCAP_TSO;
2426 ifp->if_hwassist |= CSUM_TSO;
2428 ifp->if_capenable = ifp->if_capabilities;
2431 * Figure out what sort of media we have by checking the
2432 * hardware config word in the first 32k of NIC internal memory,
2433 * or fall back to examining the EEPROM if necessary.
2434 * Note: on some BCM5700 cards, this value appears to be unset.
2435 * If that's the case, we have to rely on identifying the NIC
2436 * by its PCI subsystem ID, as we do below for the SysKonnect
2439 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) {
2440 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
2442 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2444 device_printf(dev, "failed to read EEPROM\n");
2448 hwcfg = ntohl(hwcfg);
2451 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2452 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2453 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2454 if (BGE_IS_5714_FAMILY(sc))
2455 sc->bge_flags |= BGE_FLAG_MII_SERDES;
2457 sc->bge_flags |= BGE_FLAG_TBI;
2461 if (sc->bge_flags & BGE_FLAG_CPMU)
2462 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2464 sc->bge_mi_mode = BGE_MIMODE_BASE;
2465 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2466 /* Enable auto polling for BCM570[0-5]. */
2467 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2470 /* Setup link status update stuffs */
2471 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2472 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2473 sc->bge_link_upd = bge_bcm5700_link_upd;
2474 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2475 } else if (sc->bge_flags & BGE_FLAG_TBI) {
2476 sc->bge_link_upd = bge_tbi_link_upd;
2477 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2478 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2479 sc->bge_link_upd = bge_autopoll_link_upd;
2480 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2482 sc->bge_link_upd = bge_copper_link_upd;
2483 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2487 * Broadcom's own driver always assumes the internal
2488 * PHY is at GMII address 1. On some chips, the PHY responds
2489 * to accesses at all addresses, which could cause us to
2490 * bogusly attach the PHY 32 times at probe type. Always
2491 * restricting the lookup to address 1 is simpler than
2492 * trying to figure out which chips revisions should be
2497 if (sc->bge_flags & BGE_FLAG_TBI) {
2498 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2499 bge_ifmedia_upd, bge_ifmedia_sts);
2500 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2501 ifmedia_add(&sc->bge_ifmedia,
2502 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2503 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2504 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2505 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2507 struct mii_probe_args mii_args;
2511 * Do transceiver setup and tell the firmware the
2512 * driver is down so we can try to get access the
2513 * probe if ASF is running. Retry a couple of times
2514 * if we get a conflict with the ASF firmware accessing
2518 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2520 bge_asf_driver_up(sc);
2522 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2523 mii_args.mii_probemask = 1 << sc->bge_phyno;
2524 mii_args.mii_capmask = capmask;
2525 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2526 mii_args.mii_priv = mii_priv;
2528 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2531 device_printf(sc->bge_dev, "Probe MII again\n");
2532 bge_miibus_writereg(sc->bge_dev,
2533 sc->bge_phyno, MII_BMCR, BMCR_RESET);
2536 device_printf(dev, "MII without any PHY!\n");
2541 * Now tell the firmware we are going up after probing the PHY
2543 if (sc->bge_asf_mode & ASF_STACKUP)
2544 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2548 * Create sysctl nodes.
2550 sysctl_ctx_init(&sc->bge_sysctl_ctx);
2551 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
2552 SYSCTL_STATIC_CHILDREN(_hw),
2554 device_get_nameunit(dev),
2556 if (sc->bge_sysctl_tree == NULL) {
2557 device_printf(dev, "can't add sysctl node\n");
2562 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2563 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2564 OID_AUTO, "rx_coal_ticks",
2565 CTLTYPE_INT | CTLFLAG_RW,
2566 sc, 0, bge_sysctl_rx_coal_ticks, "I",
2567 "Receive coalescing ticks (usec).");
2568 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2569 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2570 OID_AUTO, "tx_coal_ticks",
2571 CTLTYPE_INT | CTLFLAG_RW,
2572 sc, 0, bge_sysctl_tx_coal_ticks, "I",
2573 "Transmit coalescing ticks (usec).");
2574 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2575 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2576 OID_AUTO, "rx_coal_bds",
2577 CTLTYPE_INT | CTLFLAG_RW,
2578 sc, 0, bge_sysctl_rx_coal_bds, "I",
2579 "Receive max coalesced BD count.");
2580 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2581 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2582 OID_AUTO, "tx_coal_bds",
2583 CTLTYPE_INT | CTLFLAG_RW,
2584 sc, 0, bge_sysctl_tx_coal_bds, "I",
2585 "Transmit max coalesced BD count.");
2587 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2588 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2589 OID_AUTO, "tx_wreg", CTLFLAG_RW,
2590 &sc->bge_tx_wreg, 0,
2591 "# of segments before writing to hardware register");
2593 if (sc->bge_flags & BGE_FLAG_PCIE) {
2595 * A common design characteristic for many Broadcom
2596 * client controllers is that they only support a
2597 * single outstanding DMA read operation on the PCIe
2598 * bus. This means that it will take twice as long to
2599 * fetch a TX frame that is split into header and
2600 * payload buffers as it does to fetch a single,
2601 * contiguous TX frame (2 reads vs. 1 read). For these
2602 * controllers, coalescing buffers to reduce the number
2603 * of memory reads is effective way to get maximum
2604 * performance(about 940Mbps). Without collapsing TX
2605 * buffers the maximum TCP bulk transfer performance
2606 * is about 850Mbps. However forcing coalescing mbufs
2607 * consumes a lot of CPU cycles, so leave it off by
2610 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
2611 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
2612 OID_AUTO, "force_defrag", CTLFLAG_RW,
2613 &sc->bge_force_defrag, 0,
2614 "Force defragment on TX path");
2616 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2617 if (!BGE_IS_5705_PLUS(sc)) {
2618 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2619 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2620 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2621 sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2622 "Receive coalescing ticks "
2623 "during interrupt (usec).");
2624 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2625 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2626 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2627 sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2628 "Transmit coalescing ticks "
2629 "during interrupt (usec).");
2631 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2632 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2633 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2634 sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2635 "Receive max coalesced BD count during interrupt.");
2636 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
2637 SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
2638 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2639 sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2640 "Transmit max coalesced BD count during interrupt.");
2644 * Call MI attach routine.
2646 ether_ifattach(ifp, ether_addr, NULL);
2648 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
2650 #ifdef IFPOLL_ENABLE
2652 ifpoll_compat_setup(&sc->bge_npoll,
2653 &sc->bge_sysctl_ctx, sc->bge_sysctl_tree, device_get_unit(dev),
2654 ifp->if_serializer);
2657 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2658 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
2659 intr_func = bge_msi_oneshot;
2661 device_printf(dev, "oneshot MSI\n");
2663 intr_func = bge_msi;
2665 } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2666 intr_func = bge_intr_legacy;
2668 intr_func = bge_intr_crippled;
2670 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2671 &sc->bge_intrhand, ifp->if_serializer);
2673 ether_ifdetach(ifp);
2674 device_printf(dev, "couldn't set up irq\n");
2685 bge_detach(device_t dev)
2687 struct bge_softc *sc = device_get_softc(dev);
2689 if (device_is_attached(dev)) {
2690 struct ifnet *ifp = &sc->arpcom.ac_if;
2692 lwkt_serialize_enter(ifp->if_serializer);
2694 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2695 lwkt_serialize_exit(ifp->if_serializer);
2697 ether_ifdetach(ifp);
2700 if (sc->bge_flags & BGE_FLAG_TBI)
2701 ifmedia_removeall(&sc->bge_ifmedia);
2703 device_delete_child(dev, sc->bge_miibus);
2704 bus_generic_detach(dev);
2706 if (sc->bge_irq != NULL) {
2707 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid,
2710 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2711 pci_release_msi(dev);
2713 if (sc->bge_res != NULL) {
2714 bus_release_resource(dev, SYS_RES_MEMORY,
2715 BGE_PCI_BAR0, sc->bge_res);
2718 if (sc->bge_sysctl_tree != NULL)
2719 sysctl_ctx_free(&sc->bge_sysctl_ctx);
2727 bge_reset(struct bge_softc *sc)
2730 uint32_t cachesize, command, pcistate, reset;
2731 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2736 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2737 sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2738 if (sc->bge_flags & BGE_FLAG_PCIE)
2739 write_op = bge_writemem_direct;
2741 write_op = bge_writemem_ind;
2743 write_op = bge_writereg_ind;
2746 /* Save some important PCI state. */
2747 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2748 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2749 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2751 pci_write_config(dev, BGE_PCI_MISC_CTL,
2752 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2753 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2754 sc->bge_pci_miscctl, 4);
2756 /* Disable fastboot on controllers that support it. */
2757 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2758 BGE_IS_5755_PLUS(sc)) {
2760 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2761 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2765 * Write the magic number to SRAM at offset 0xB50.
2766 * When firmware finishes its initialization it will
2767 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
2769 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
2771 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2773 /* XXX: Broadcom Linux driver. */
2774 if (sc->bge_flags & BGE_FLAG_PCIE) {
2775 /* Force PCI-E 1.0a mode */
2776 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2777 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2778 (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2779 BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2780 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2781 BGE_PCIE_PHY_TSTCTL_PSCRAM);
2783 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2784 /* Prevent PCIE link training during global reset */
2785 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2791 * Set GPHY Power Down Override to leave GPHY
2792 * powered up in D0 uninitialized.
2794 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2795 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2797 /* Issue global reset */
2798 write_op(sc, BGE_MISC_CFG, reset);
2800 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2801 uint32_t status, ctrl;
2803 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2804 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2805 status | BGE_VCPU_STATUS_DRV_RESET);
2806 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2807 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2808 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2813 /* XXX: Broadcom Linux driver. */
2814 if (sc->bge_flags & BGE_FLAG_PCIE) {
2817 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2820 DELAY(500000); /* wait for link training to complete */
2821 v = pci_read_config(dev, 0xc4, 4);
2822 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2825 devctl = pci_read_config(dev,
2826 sc->bge_pciecap + PCIER_DEVCTRL, 2);
2828 /* Disable no snoop and disable relaxed ordering. */
2829 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2831 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2832 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) {
2833 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2834 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2837 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2840 /* Clear error status. */
2841 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2842 PCIEM_DEVSTS_CORR_ERR |
2843 PCIEM_DEVSTS_NFATAL_ERR |
2844 PCIEM_DEVSTS_FATAL_ERR |
2845 PCIEM_DEVSTS_UNSUPP_REQ, 2);
2848 /* Reset some of the PCI state that got zapped by reset */
2849 pci_write_config(dev, BGE_PCI_MISC_CTL,
2850 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2851 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2852 sc->bge_pci_miscctl, 4);
2853 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2854 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2855 write_op(sc, BGE_MISC_CFG, (65 << 1));
2858 * Disable PCI-X relaxed ordering to ensure status block update
2859 * comes first then packet buffer DMA. Otherwise driver may
2860 * read stale status block.
2862 if (sc->bge_flags & BGE_FLAG_PCIX) {
2865 devctl = pci_read_config(dev,
2866 sc->bge_pcixcap + PCIXR_COMMAND, 2);
2867 devctl &= ~PCIXM_COMMAND_ERO;
2868 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2869 devctl &= ~PCIXM_COMMAND_MAX_READ;
2870 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2871 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2872 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2873 PCIXM_COMMAND_MAX_READ);
2874 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2876 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2881 * Enable memory arbiter and re-enable MSI if necessary.
2883 if (BGE_IS_5714_FAMILY(sc)) {
2886 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2888 * Resetting BCM5714 family will clear MSI
2889 * enable bit; restore it after resetting.
2891 PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL,
2892 PCIM_MSICTRL_MSI_ENABLE, 2);
2893 BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE);
2895 val = CSR_READ_4(sc, BGE_MARB_MODE);
2896 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2898 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2901 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2902 for (i = 0; i < BGE_TIMEOUT; i++) {
2903 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2904 if (val & BGE_VCPU_STATUS_INIT_DONE)
2908 if (i == BGE_TIMEOUT) {
2909 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2914 * Poll until we see the 1's complement of the magic number.
2915 * This indicates that the firmware initialization
2918 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2919 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
2920 if (val == ~BGE_SRAM_FW_MB_MAGIC)
2924 if (i == BGE_FIRMWARE_TIMEOUT) {
2925 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2926 "timed out, found 0x%08x\n", val);
2931 * XXX Wait for the value of the PCISTATE register to
2932 * return to its original pre-reset state. This is a
2933 * fairly good indicator of reset completion. If we don't
2934 * wait for the reset to fully complete, trying to read
2935 * from the device's non-PCI registers may yield garbage
2938 for (i = 0; i < BGE_TIMEOUT; i++) {
2939 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2944 /* Fix up byte swapping */
2945 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2946 BGE_MODECTL_BYTESWAP_DATA);
2948 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2951 * The 5704 in TBI mode apparently needs some special
2952 * adjustment to insure the SERDES drive level is set
2955 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2956 (sc->bge_flags & BGE_FLAG_TBI)) {
2959 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2960 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2961 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2964 /* XXX: Broadcom Linux driver. */
2965 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2966 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
2967 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
2970 /* Enable Data FIFO protection. */
2971 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2972 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2979 * Frame reception handling. This is called if there's a frame
2980 * on the receive return list.
2982 * Note: we have to be able to handle two possibilities here:
2983 * 1) the frame is from the jumbo recieve ring
2984 * 2) the frame is from the standard receive ring
2988 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count)
2991 int stdcnt = 0, jumbocnt = 0;
2993 ifp = &sc->arpcom.ac_if;
2995 while (sc->bge_rx_saved_considx != rx_prod && count != 0) {
2996 struct bge_rx_bd *cur_rx;
2998 struct mbuf *m = NULL;
2999 uint16_t vlan_tag = 0;
3005 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
3007 rxidx = cur_rx->bge_idx;
3008 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
3011 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3013 vlan_tag = cur_rx->bge_vlan_tag;
3016 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3017 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3020 if (rxidx != sc->bge_jumbo) {
3021 IFNET_STAT_INC(ifp, ierrors, 1);
3022 if_printf(ifp, "sw jumbo index(%d) "
3023 "and hw jumbo index(%d) mismatch, drop!\n",
3024 sc->bge_jumbo, rxidx);
3025 bge_setup_rxdesc_jumbo(sc, rxidx);
3029 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
3030 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3031 IFNET_STAT_INC(ifp, ierrors, 1);
3032 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
3035 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
3036 IFNET_STAT_INC(ifp, ierrors, 1);
3037 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
3043 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3046 if (rxidx != sc->bge_std) {
3047 IFNET_STAT_INC(ifp, ierrors, 1);
3048 if_printf(ifp, "sw std index(%d) "
3049 "and hw std index(%d) mismatch, drop!\n",
3050 sc->bge_std, rxidx);
3051 bge_setup_rxdesc_std(sc, rxidx);
3056 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
3057 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3058 IFNET_STAT_INC(ifp, ierrors, 1);
3059 bge_setup_rxdesc_std(sc, sc->bge_std);
3063 if (bge_newbuf_std(sc, sc->bge_std, 0)) {
3064 IFNET_STAT_INC(ifp, ierrors, 1);
3065 bge_setup_rxdesc_std(sc, sc->bge_std);
3069 if (sc->bge_rx_wreg > 0 && stdcnt >= sc->bge_rx_wreg) {
3070 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO,
3078 IFNET_STAT_INC(ifp, ipackets, 1);
3079 #if !defined(__i386__) && !defined(__x86_64__)
3081 * The x86 allows unaligned accesses, but for other
3082 * platforms we must make sure the payload is aligned.
3084 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3085 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3087 m->m_data += ETHER_ALIGN;
3090 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3091 m->m_pkthdr.rcvif = ifp;
3093 if (ifp->if_capenable & IFCAP_RXCSUM) {
3094 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3095 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3096 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
3097 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3099 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
3100 m->m_pkthdr.len >= BGE_MIN_FRAMELEN) {
3101 m->m_pkthdr.csum_data =
3102 cur_rx->bge_tcp_udp_csum;
3103 m->m_pkthdr.csum_flags |=
3104 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3109 * If we received a packet with a vlan tag, pass it
3110 * to vlan_input() instead of ether_input().
3113 m->m_flags |= M_VLANTAG;
3114 m->m_pkthdr.ether_vlantag = vlan_tag;
3116 ifp->if_input(ifp, m);
3119 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3121 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3123 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3127 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3131 ifp = &sc->arpcom.ac_if;
3134 * Go through our tx ring and free mbufs for those
3135 * frames that have been sent.
3137 while (sc->bge_tx_saved_considx != tx_cons) {
3140 idx = sc->bge_tx_saved_considx;
3141 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3142 IFNET_STAT_INC(ifp, opackets, 1);
3143 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3144 sc->bge_cdata.bge_tx_dmamap[idx]);
3145 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3146 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3149 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3153 if ((BGE_TX_RING_CNT - sc->bge_txcnt) >=
3154 (sc->bge_txrsvd + sc->bge_txspare))
3155 ifq_clr_oactive(&ifp->if_snd);
3157 if (sc->bge_txcnt == 0)
3160 if (!ifq_is_empty(&ifp->if_snd))
3164 #ifdef IFPOLL_ENABLE
3167 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles)
3169 struct bge_softc *sc = ifp->if_softc;
3170 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3171 uint16_t rx_prod, tx_cons;
3173 ASSERT_SERIALIZED(ifp->if_serializer);
3175 if (sc->bge_npoll.ifpc_stcount-- == 0) {
3176 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac;
3178 * Process link state changes.
3183 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
3184 sc->bge_status_tag = sblk->bge_status_tag;
3186 * Use a load fence to ensure that status_tag
3187 * is saved before rx_prod and tx_cons.
3192 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3193 if (sc->bge_rx_saved_considx != rx_prod)
3194 bge_rxeof(sc, rx_prod, cycles);
3196 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3197 if (sc->bge_tx_saved_considx != tx_cons)
3198 bge_txeof(sc, tx_cons);
3200 if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
3201 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3203 if (sc->bge_coal_chg)
3204 bge_coal_change(sc);
3208 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3210 struct bge_softc *sc = ifp->if_softc;
3212 ASSERT_SERIALIZED(ifp->if_serializer);
3215 int cpuid = sc->bge_npoll.ifpc_cpuid;
3217 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat;
3218 info->ifpi_rx[cpuid].arg = NULL;
3219 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
3221 if (ifp->if_flags & IFF_RUNNING)
3222 bge_disable_intr(sc);
3223 ifq_set_cpuid(&ifp->if_snd, cpuid);
3225 if (ifp->if_flags & IFF_RUNNING)
3226 bge_enable_intr(sc);
3227 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
3231 #endif /* IFPOLL_ENABLE */
3234 bge_intr_crippled(void *xsc)
3236 struct bge_softc *sc = xsc;
3237 struct ifnet *ifp = &sc->arpcom.ac_if;
3242 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3243 * disable interrupts by writing nonzero like we used to, since with
3244 * our current organization this just gives complications and
3245 * pessimizations for re-enabling interrupts. We used to have races
3246 * instead of the necessary complications. Disabling interrupts
3247 * would just reduce the chance of a status update while we are
3248 * running (by switching to the interrupt-mode coalescence
3249 * parameters), but this chance is already very low so it is more
3250 * efficient to get another interrupt than prevent it.
3252 * We do the ack first to ensure another interrupt if there is a
3253 * status update after the ack. We don't check for the status
3254 * changing later because it is more efficient to get another
3255 * interrupt than prevent it, not quite as above (not checking is
3256 * a smaller optimization than not toggling the interrupt enable,
3257 * since checking doesn't involve PCI accesses and toggling require
3258 * the status check). So toggling would probably be a pessimization
3259 * even with MSI. It would only be needed for using a task queue.
3261 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3264 * Process link state changes.
3268 if (ifp->if_flags & IFF_RUNNING) {
3269 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3270 uint16_t rx_prod, tx_cons;
3272 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3273 if (sc->bge_rx_saved_considx != rx_prod)
3274 bge_rxeof(sc, rx_prod, -1);
3276 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3277 if (sc->bge_tx_saved_considx != tx_cons)
3278 bge_txeof(sc, tx_cons);
3281 if (sc->bge_coal_chg)
3282 bge_coal_change(sc);
3286 bge_intr_legacy(void *xsc)
3288 struct bge_softc *sc = xsc;
3289 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3291 if (sc->bge_status_tag == sblk->bge_status_tag) {
3294 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3295 if (val & BGE_PCISTAT_INTR_NOTACT)
3301 * Interrupt will have to be disabled if tagged status
3302 * is used, else interrupt will always be asserted on
3303 * certain chips (at least on BCM5750 AX/BX).
3305 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3313 struct bge_softc *sc = xsc;
3315 /* Disable interrupt first */
3316 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3321 bge_msi_oneshot(void *xsc)
3327 bge_intr(struct bge_softc *sc)
3329 struct ifnet *ifp = &sc->arpcom.ac_if;
3330 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3331 uint16_t rx_prod, tx_cons;
3334 sc->bge_status_tag = sblk->bge_status_tag;
3336 * Use a load fence to ensure that status_tag is saved
3337 * before rx_prod, tx_cons and status.
3341 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3342 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3343 status = sblk->bge_status;
3345 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
3348 if (ifp->if_flags & IFF_RUNNING) {
3349 if (sc->bge_rx_saved_considx != rx_prod)
3350 bge_rxeof(sc, rx_prod, -1);
3352 if (sc->bge_tx_saved_considx != tx_cons)
3353 bge_txeof(sc, tx_cons);
3356 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3358 if (sc->bge_coal_chg)
3359 bge_coal_change(sc);
3365 struct bge_softc *sc = xsc;
3366 struct ifnet *ifp = &sc->arpcom.ac_if;
3368 lwkt_serialize_enter(ifp->if_serializer);
3370 if (BGE_IS_5705_PLUS(sc))
3371 bge_stats_update_regs(sc);
3373 bge_stats_update(sc);
3375 if (sc->bge_flags & BGE_FLAG_TBI) {
3377 * Since in TBI mode auto-polling can't be used we should poll
3378 * link status manually. Here we register pending link event
3379 * and trigger interrupt.
3382 if (BGE_IS_CRIPPLED(sc))
3383 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3385 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3386 } else if (!sc->bge_link) {
3387 mii_tick(device_get_softc(sc->bge_miibus));
3390 bge_asf_driver_up(sc);
3392 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3394 lwkt_serialize_exit(ifp->if_serializer);
3398 bge_stats_update_regs(struct bge_softc *sc)
3400 struct ifnet *ifp = &sc->arpcom.ac_if;
3401 struct bge_mac_stats_regs stats;
3405 s = (uint32_t *)&stats;
3406 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3407 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3411 IFNET_STAT_SET(ifp, collisions,
3412 (stats.dot3StatsSingleCollisionFrames +
3413 stats.dot3StatsMultipleCollisionFrames +
3414 stats.dot3StatsExcessiveCollisions +
3415 stats.dot3StatsLateCollisions));
3419 bge_stats_update(struct bge_softc *sc)
3421 struct ifnet *ifp = &sc->arpcom.ac_if;
3424 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3426 #define READ_STAT(sc, stats, stat) \
3427 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3429 IFNET_STAT_SET(ifp, collisions,
3430 (READ_STAT(sc, stats,
3431 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3432 READ_STAT(sc, stats,
3433 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3434 READ_STAT(sc, stats,
3435 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3436 READ_STAT(sc, stats,
3437 txstats.dot3StatsLateCollisions.bge_addr_lo)));
3442 IFNET_STAT_SET(ifp, collisions,
3443 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3444 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3445 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3446 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions));
3451 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3452 * pointers to descriptors.
3455 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
3458 struct bge_tx_bd *d = NULL, *last_d;
3459 uint16_t csum_flags = 0, mss = 0;
3460 bus_dma_segment_t segs[BGE_NSEG_NEW];
3462 int error, maxsegs, nsegs, idx, i;
3463 struct mbuf *m_head = *m_head0, *m_new;
3465 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3466 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags);
3470 } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) {
3471 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3472 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3473 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3474 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3475 if (m_head->m_flags & M_LASTFRAG)
3476 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3477 else if (m_head->m_flags & M_FRAG)
3478 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3482 map = sc->bge_cdata.bge_tx_dmamap[idx];
3484 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd;
3485 KASSERT(maxsegs >= sc->bge_txspare,
3486 ("not enough segments %d", maxsegs));
3488 if (maxsegs > BGE_NSEG_NEW)
3489 maxsegs = BGE_NSEG_NEW;
3492 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3493 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3494 * but when such padded frames employ the bge IP/TCP checksum
3495 * offload, the hardware checksum assist gives incorrect results
3496 * (possibly from incorporating its own padding into the UDP/TCP
3497 * checksum; who knows). If we pad such runts with zeros, the
3498 * onboard checksum comes out correct.
3500 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3501 m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) {
3502 error = m_devpad(m_head, BGE_MIN_FRAMELEN);
3507 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3508 m_new = bge_defrag_shortdma(m_head);
3509 if (m_new == NULL) {
3513 *m_head0 = m_head = m_new;
3515 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3516 sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3517 m_head->m_next != NULL) {
3519 * Forcefully defragment mbuf chain to overcome hardware
3520 * limitation which only support a single outstanding
3521 * DMA read operation. If it fails, keep moving on using
3522 * the original mbuf chain.
3524 m_new = m_defrag(m_head, MB_DONTWAIT);
3526 *m_head0 = m_head = m_new;
3529 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3530 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3533 *segs_used += nsegs;
3536 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3538 for (i = 0; ; i++) {
3539 d = &sc->bge_ldata.bge_tx_ring[idx];
3541 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3542 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3543 d->bge_len = segs[i].ds_len;
3544 d->bge_flags = csum_flags;
3549 BGE_INC(idx, BGE_TX_RING_CNT);
3553 /* Set vlan tag to the first segment of the packet. */
3554 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3555 if (m_head->m_flags & M_VLANTAG) {
3556 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3557 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3559 d->bge_vlan_tag = 0;
3562 /* Mark the last segment as end of packet... */
3563 last_d->bge_flags |= BGE_TXBDFLAG_END;
3566 * Insure that the map for this transmission is placed at
3567 * the array index of the last descriptor in this chain.
3569 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3570 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3571 sc->bge_cdata.bge_tx_chain[idx] = m_head;
3572 sc->bge_txcnt += nsegs;
3574 BGE_INC(idx, BGE_TX_RING_CNT);
3585 bge_xmit(struct bge_softc *sc, uint32_t prodidx)
3588 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3589 /* 5700 b2 errata */
3590 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3591 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3595 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3596 * to the mbuf data regions directly in the transmit descriptors.
3599 bge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3601 struct bge_softc *sc = ifp->if_softc;
3602 struct mbuf *m_head = NULL;
3606 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
3608 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
3611 prodidx = sc->bge_tx_prodidx;
3613 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3614 m_head = ifq_dequeue(&ifp->if_snd);
3620 * The code inside the if() block is never reached since we
3621 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3622 * requests to checksum TCP/UDP in a fragmented packet.
3625 * safety overkill. If this is a fragmented packet chain
3626 * with delayed TCP/UDP checksums, then only encapsulate
3627 * it if we have enough descriptors to handle the entire
3629 * (paranoia -- may not actually be needed)
3631 if ((m_head->m_flags & M_FIRSTFRAG) &&
3632 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3633 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3634 m_head->m_pkthdr.csum_data + sc->bge_txrsvd) {
3635 ifq_set_oactive(&ifp->if_snd);
3636 ifq_prepend(&ifp->if_snd, m_head);
3642 * Sanity check: avoid coming within bge_txrsvd
3643 * descriptors of the end of the ring. Also make
3644 * sure there are bge_txspare descriptors for
3645 * jumbo buffers' defragmentation.
3647 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3648 (sc->bge_txrsvd + sc->bge_txspare)) {
3649 ifq_set_oactive(&ifp->if_snd);
3650 ifq_prepend(&ifp->if_snd, m_head);
3655 * Pack the data into the transmit ring. If we
3656 * don't have room, set the OACTIVE flag and wait
3657 * for the NIC to drain the ring.
3659 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) {
3660 ifq_set_oactive(&ifp->if_snd);
3661 IFNET_STAT_INC(ifp, oerrors, 1);
3665 if (nsegs >= sc->bge_tx_wreg) {
3666 bge_xmit(sc, prodidx);
3670 ETHER_BPF_MTAP(ifp, m_head);
3673 * Set a timeout in case the chip goes out to lunch.
3679 bge_xmit(sc, prodidx);
3680 sc->bge_tx_prodidx = prodidx;
3686 struct bge_softc *sc = xsc;
3687 struct ifnet *ifp = &sc->arpcom.ac_if;
3691 ASSERT_SERIALIZED(ifp->if_serializer);
3693 /* Cancel pending I/O and flush buffers. */
3697 bge_sig_pre_reset(sc, BGE_RESET_START);
3699 bge_sig_legacy(sc, BGE_RESET_START);
3700 bge_sig_post_reset(sc, BGE_RESET_START);
3705 * Init the various state machines, ring
3706 * control blocks and firmware.
3708 if (bge_blockinit(sc)) {
3709 if_printf(ifp, "initialization failure\n");
3715 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3716 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3718 /* Load our MAC address. */
3719 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3720 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3721 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3723 /* Enable or disable promiscuous mode as needed. */
3726 /* Program multicast filter. */
3730 if (bge_init_rx_ring_std(sc)) {
3731 if_printf(ifp, "RX ring initialization failed\n");
3737 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3738 * memory to insure that the chip has in fact read the first
3739 * entry of the ring.
3741 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3743 for (i = 0; i < 10; i++) {
3745 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3746 if (v == (MCLBYTES - ETHER_ALIGN))
3750 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3753 /* Init jumbo RX ring. */
3754 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3755 if (bge_init_rx_ring_jumbo(sc)) {
3756 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3762 /* Init our RX return ring index */
3763 sc->bge_rx_saved_considx = 0;
3766 bge_init_tx_ring(sc);
3768 /* Enable TX MAC state machine lockup fix. */
3769 mode = CSR_READ_4(sc, BGE_TX_MODE);
3770 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3771 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3772 /* Turn on transmitter */
3773 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3775 /* Turn on receiver */
3776 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3779 * Set the number of good frames to receive after RX MBUF
3780 * Low Watermark has been reached. After the RX MAC receives
3781 * this number of frames, it will drop subsequent incoming
3782 * frames until the MBUF High Watermark is reached.
3784 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3786 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
3788 if_printf(ifp, "MSI_MODE: %#x\n",
3789 CSR_READ_4(sc, BGE_MSI_MODE));
3794 * Linux driver turns it on for all chips supporting MSI?!
3796 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
3799 * According to 5722-PG101-R,
3800 * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to
3803 BGE_SETBIT(sc, BGE_PCIE_TRANSACT,
3804 BGE_PCIE_TRANSACT_ONESHOT_MSI);
3808 /* Tell firmware we're alive. */
3809 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3811 /* Enable host interrupts if polling(4) is not enabled. */
3812 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3813 #ifdef IFPOLL_ENABLE
3814 if (ifp->if_flags & IFF_NPOLLING)
3815 bge_disable_intr(sc);
3818 bge_enable_intr(sc);
3820 ifp->if_flags |= IFF_RUNNING;
3821 ifq_clr_oactive(&ifp->if_snd);
3823 bge_ifmedia_upd(ifp);
3825 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3829 * Set media options.
3832 bge_ifmedia_upd(struct ifnet *ifp)
3834 struct bge_softc *sc = ifp->if_softc;
3836 /* If this is a 1000baseX NIC, enable the TBI port. */
3837 if (sc->bge_flags & BGE_FLAG_TBI) {
3838 struct ifmedia *ifm = &sc->bge_ifmedia;
3840 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3843 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3846 * The BCM5704 ASIC appears to have a special
3847 * mechanism for programming the autoneg
3848 * advertisement registers in TBI mode.
3850 if (!bge_fake_autoneg &&
3851 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3854 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3855 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3856 sgdig |= BGE_SGDIGCFG_AUTO |
3857 BGE_SGDIGCFG_PAUSE_CAP |
3858 BGE_SGDIGCFG_ASYM_PAUSE;
3859 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3860 sgdig | BGE_SGDIGCFG_SEND);
3862 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3866 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3867 BGE_CLRBIT(sc, BGE_MAC_MODE,
3868 BGE_MACMODE_HALF_DUPLEX);
3870 BGE_SETBIT(sc, BGE_MAC_MODE,
3871 BGE_MACMODE_HALF_DUPLEX);
3878 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3882 if (mii->mii_instance) {
3883 struct mii_softc *miisc;
3885 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3886 mii_phy_reset(miisc);
3891 * Force an interrupt so that we will call bge_link_upd
3892 * if needed and clear any pending link state attention.
3893 * Without this we are not getting any further interrupts
3894 * for link state changes and thus will not UP the link and
3895 * not be able to send in bge_start. The only way to get
3896 * things working was to receive a packet and get an RX
3899 * bge_tick should help for fiber cards and we might not
3900 * need to do this here if BGE_FLAG_TBI is set but as
3901 * we poll for fiber anyway it should not harm.
3903 if (BGE_IS_CRIPPLED(sc))
3904 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3906 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3912 * Report current media status.
3915 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3917 struct bge_softc *sc = ifp->if_softc;
3919 if ((ifp->if_flags & IFF_RUNNING) == 0)
3922 if (sc->bge_flags & BGE_FLAG_TBI) {
3923 ifmr->ifm_status = IFM_AVALID;
3924 ifmr->ifm_active = IFM_ETHER;
3925 if (CSR_READ_4(sc, BGE_MAC_STS) &
3926 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3927 ifmr->ifm_status |= IFM_ACTIVE;
3929 ifmr->ifm_active |= IFM_NONE;
3933 ifmr->ifm_active |= IFM_1000_SX;
3934 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3935 ifmr->ifm_active |= IFM_HDX;
3937 ifmr->ifm_active |= IFM_FDX;
3939 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3942 ifmr->ifm_active = mii->mii_media_active;
3943 ifmr->ifm_status = mii->mii_media_status;
3948 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3950 struct bge_softc *sc = ifp->if_softc;
3951 struct ifreq *ifr = (struct ifreq *)data;
3952 int mask, error = 0;
3954 ASSERT_SERIALIZED(ifp->if_serializer);
3958 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3959 (BGE_IS_JUMBO_CAPABLE(sc) &&
3960 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3962 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3963 ifp->if_mtu = ifr->ifr_mtu;
3964 if (ifp->if_flags & IFF_RUNNING)
3969 if (ifp->if_flags & IFF_UP) {
3970 if (ifp->if_flags & IFF_RUNNING) {
3971 mask = ifp->if_flags ^ sc->bge_if_flags;
3974 * If only the state of the PROMISC flag
3975 * changed, then just use the 'set promisc
3976 * mode' command instead of reinitializing
3977 * the entire NIC. Doing a full re-init
3978 * means reloading the firmware and waiting
3979 * for it to start up, which may take a
3980 * second or two. Similarly for ALLMULTI.
3982 if (mask & IFF_PROMISC)
3984 if (mask & IFF_ALLMULTI)
3989 } else if (ifp->if_flags & IFF_RUNNING) {
3992 sc->bge_if_flags = ifp->if_flags;
3996 if (ifp->if_flags & IFF_RUNNING)
4001 if (sc->bge_flags & BGE_FLAG_TBI) {
4002 error = ifmedia_ioctl(ifp, ifr,
4003 &sc->bge_ifmedia, command);
4005 struct mii_data *mii;
4007 mii = device_get_softc(sc->bge_miibus);
4008 error = ifmedia_ioctl(ifp, ifr,
4009 &mii->mii_media, command);
4013 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4014 if (mask & IFCAP_HWCSUM) {
4015 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
4016 if (ifp->if_capenable & IFCAP_TXCSUM)
4017 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4019 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4021 if (mask & IFCAP_TSO) {
4022 ifp->if_capenable ^= IFCAP_TSO;
4023 if (ifp->if_capenable & IFCAP_TSO)
4024 ifp->if_hwassist |= CSUM_TSO;
4026 ifp->if_hwassist &= ~CSUM_TSO;
4030 error = ether_ioctl(ifp, command, data);
4037 bge_watchdog(struct ifnet *ifp)
4039 struct bge_softc *sc = ifp->if_softc;
4041 if_printf(ifp, "watchdog timeout -- resetting\n");
4045 IFNET_STAT_INC(ifp, oerrors, 1);
4047 if (!ifq_is_empty(&ifp->if_snd))
4052 * Stop the adapter and free any mbufs allocated to the
4056 bge_stop(struct bge_softc *sc)
4058 struct ifnet *ifp = &sc->arpcom.ac_if;
4060 ASSERT_SERIALIZED(ifp->if_serializer);
4062 callout_stop(&sc->bge_stat_timer);
4064 /* Disable host interrupts. */
4065 bge_disable_intr(sc);
4068 * Tell firmware we're shutting down.
4071 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
4074 * Disable all of the receiver blocks
4076 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4077 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4078 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4079 if (BGE_IS_5700_FAMILY(sc))
4080 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4081 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4082 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4083 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4086 * Disable all of the transmit blocks
4088 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4089 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4090 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4091 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4092 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4093 if (BGE_IS_5700_FAMILY(sc))
4094 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4095 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4098 * Shut down all of the memory managers and related
4101 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4102 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4103 if (BGE_IS_5700_FAMILY(sc))
4104 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4105 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4106 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4107 if (!BGE_IS_5705_PLUS(sc)) {
4108 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4109 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4113 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
4114 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
4117 * Keep the ASF firmware running if up.
4119 if (sc->bge_asf_mode & ASF_STACKUP)
4120 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4122 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4124 /* Free the RX lists. */
4125 bge_free_rx_ring_std(sc);
4127 /* Free jumbo RX list. */
4128 if (BGE_IS_JUMBO_CAPABLE(sc))
4129 bge_free_rx_ring_jumbo(sc);
4131 /* Free TX buffers. */
4132 bge_free_tx_ring(sc);
4134 sc->bge_status_tag = 0;
4136 sc->bge_coal_chg = 0;
4138 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4140 ifp->if_flags &= ~IFF_RUNNING;
4141 ifq_clr_oactive(&ifp->if_snd);
4146 * Stop all chip I/O so that the kernel's probe routines don't
4147 * get confused by errant DMAs when rebooting.
4150 bge_shutdown(device_t dev)
4152 struct bge_softc *sc = device_get_softc(dev);
4153 struct ifnet *ifp = &sc->arpcom.ac_if;
4155 lwkt_serialize_enter(ifp->if_serializer);
4157 lwkt_serialize_exit(ifp->if_serializer);
4161 bge_suspend(device_t dev)
4163 struct bge_softc *sc = device_get_softc(dev);
4164 struct ifnet *ifp = &sc->arpcom.ac_if;
4166 lwkt_serialize_enter(ifp->if_serializer);
4168 lwkt_serialize_exit(ifp->if_serializer);
4174 bge_resume(device_t dev)
4176 struct bge_softc *sc = device_get_softc(dev);
4177 struct ifnet *ifp = &sc->arpcom.ac_if;
4179 lwkt_serialize_enter(ifp->if_serializer);
4181 if (ifp->if_flags & IFF_UP) {
4184 if (!ifq_is_empty(&ifp->if_snd))
4188 lwkt_serialize_exit(ifp->if_serializer);
4194 bge_setpromisc(struct bge_softc *sc)
4196 struct ifnet *ifp = &sc->arpcom.ac_if;
4198 if (ifp->if_flags & IFF_PROMISC)
4199 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4201 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4205 bge_dma_free(struct bge_softc *sc)
4209 /* Destroy RX mbuf DMA stuffs. */
4210 if (sc->bge_cdata.bge_rx_mtag != NULL) {
4211 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4212 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4213 sc->bge_cdata.bge_rx_std_dmamap[i]);
4215 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4216 sc->bge_cdata.bge_rx_tmpmap);
4217 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4220 /* Destroy TX mbuf DMA stuffs. */
4221 if (sc->bge_cdata.bge_tx_mtag != NULL) {
4222 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4223 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4224 sc->bge_cdata.bge_tx_dmamap[i]);
4226 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4229 /* Destroy standard RX ring */
4230 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
4231 sc->bge_cdata.bge_rx_std_ring_map,
4232 sc->bge_ldata.bge_rx_std_ring);
4234 if (BGE_IS_JUMBO_CAPABLE(sc))
4235 bge_free_jumbo_mem(sc);
4237 /* Destroy RX return ring */
4238 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
4239 sc->bge_cdata.bge_rx_return_ring_map,
4240 sc->bge_ldata.bge_rx_return_ring);
4242 /* Destroy TX ring */
4243 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
4244 sc->bge_cdata.bge_tx_ring_map,
4245 sc->bge_ldata.bge_tx_ring);
4247 /* Destroy status block */
4248 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
4249 sc->bge_cdata.bge_status_map,
4250 sc->bge_ldata.bge_status_block);
4252 /* Destroy statistics block */
4253 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
4254 sc->bge_cdata.bge_stats_map,
4255 sc->bge_ldata.bge_stats);
4257 /* Destroy the parent tag */
4258 if (sc->bge_cdata.bge_parent_tag != NULL)
4259 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
4263 bge_dma_alloc(struct bge_softc *sc)
4265 struct ifnet *ifp = &sc->arpcom.ac_if;
4270 lowaddr = BUS_SPACE_MAXADDR;
4271 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
4272 lowaddr = BGE_DMA_MAXADDR_40BIT;
4275 * Allocate the parent bus DMA tag appropriate for PCI.
4277 * All of the NetExtreme/NetLink controllers have 4GB boundary
4279 * Whenever an address crosses a multiple of the 4GB boundary
4280 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
4281 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
4282 * state machine will lockup and cause the device to hang.
4284 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
4285 lowaddr, BUS_SPACE_MAXADDR,
4287 BUS_SPACE_MAXSIZE_32BIT, 0,
4288 BUS_SPACE_MAXSIZE_32BIT,
4289 0, &sc->bge_cdata.bge_parent_tag);
4291 if_printf(ifp, "could not allocate parent dma tag\n");
4296 * Create DMA tag and maps for RX mbufs.
4298 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4299 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4300 NULL, NULL, MCLBYTES, 1, MCLBYTES,
4301 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
4302 &sc->bge_cdata.bge_rx_mtag);
4304 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
4308 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4309 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
4311 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4312 sc->bge_cdata.bge_rx_mtag = NULL;
4316 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4317 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4319 &sc->bge_cdata.bge_rx_std_dmamap[i]);
4323 for (j = 0; j < i; ++j) {
4324 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4325 sc->bge_cdata.bge_rx_std_dmamap[j]);
4327 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4328 sc->bge_cdata.bge_rx_mtag = NULL;
4330 if_printf(ifp, "could not create DMA map for RX\n");
4336 * Create DMA tag and maps for TX mbufs.
4338 if (sc->bge_flags & BGE_FLAG_TSO)
4339 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4341 txmaxsz = BGE_JUMBO_FRAMELEN;
4342 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4343 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4345 txmaxsz, BGE_NSEG_NEW, PAGE_SIZE,
4346 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
4348 &sc->bge_cdata.bge_tx_mtag);
4350 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
4354 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4355 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
4356 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4357 &sc->bge_cdata.bge_tx_dmamap[i]);
4361 for (j = 0; j < i; ++j) {
4362 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4363 sc->bge_cdata.bge_tx_dmamap[j]);
4365 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4366 sc->bge_cdata.bge_tx_mtag = NULL;
4368 if_printf(ifp, "could not create DMA map for TX\n");
4374 * Create DMA stuffs for standard RX ring.
4376 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4377 &sc->bge_cdata.bge_rx_std_ring_tag,
4378 &sc->bge_cdata.bge_rx_std_ring_map,
4379 (void *)&sc->bge_ldata.bge_rx_std_ring,
4380 &sc->bge_ldata.bge_rx_std_ring_paddr);
4382 if_printf(ifp, "could not create std RX ring\n");
4387 * Create jumbo buffer pool.
4389 if (BGE_IS_JUMBO_CAPABLE(sc)) {
4390 error = bge_alloc_jumbo_mem(sc);
4392 if_printf(ifp, "could not create jumbo buffer pool\n");
4398 * Create DMA stuffs for RX return ring.
4400 error = bge_dma_block_alloc(sc,
4401 BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt),
4402 &sc->bge_cdata.bge_rx_return_ring_tag,
4403 &sc->bge_cdata.bge_rx_return_ring_map,
4404 (void *)&sc->bge_ldata.bge_rx_return_ring,
4405 &sc->bge_ldata.bge_rx_return_ring_paddr);
4407 if_printf(ifp, "could not create RX ret ring\n");
4412 * Create DMA stuffs for TX ring.
4414 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
4415 &sc->bge_cdata.bge_tx_ring_tag,
4416 &sc->bge_cdata.bge_tx_ring_map,
4417 (void *)&sc->bge_ldata.bge_tx_ring,
4418 &sc->bge_ldata.bge_tx_ring_paddr);
4420 if_printf(ifp, "could not create TX ring\n");
4425 * Create DMA stuffs for status block.
4427 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
4428 &sc->bge_cdata.bge_status_tag,
4429 &sc->bge_cdata.bge_status_map,
4430 (void *)&sc->bge_ldata.bge_status_block,
4431 &sc->bge_ldata.bge_status_block_paddr);
4433 if_printf(ifp, "could not create status block\n");
4438 * Create DMA stuffs for statistics block.
4440 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
4441 &sc->bge_cdata.bge_stats_tag,
4442 &sc->bge_cdata.bge_stats_map,
4443 (void *)&sc->bge_ldata.bge_stats,
4444 &sc->bge_ldata.bge_stats_paddr);
4446 if_printf(ifp, "could not create stats block\n");
4453 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4454 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4459 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
4460 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4461 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4465 *tag = dmem.dmem_tag;
4466 *map = dmem.dmem_map;
4467 *addr = dmem.dmem_addr;
4468 *paddr = dmem.dmem_busaddr;
4474 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4477 bus_dmamap_unload(tag, map);
4478 bus_dmamem_free(tag, addr, map);
4479 bus_dma_tag_destroy(tag);
4484 * Grrr. The link status word in the status block does
4485 * not work correctly on the BCM5700 rev AX and BX chips,
4486 * according to all available information. Hence, we have
4487 * to enable MII interrupts in order to properly obtain
4488 * async link changes. Unfortunately, this also means that
4489 * we have to read the MAC status register to detect link
4490 * changes, thereby adding an additional register access to
4491 * the interrupt handler.
4493 * XXX: perhaps link state detection procedure used for
4494 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4497 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
4499 struct ifnet *ifp = &sc->arpcom.ac_if;
4500 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4504 if (!sc->bge_link &&
4505 (mii->mii_media_status & IFM_ACTIVE) &&
4506 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4509 if_printf(ifp, "link UP\n");
4510 } else if (sc->bge_link &&
4511 (!(mii->mii_media_status & IFM_ACTIVE) ||
4512 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4515 if_printf(ifp, "link DOWN\n");
4518 /* Clear the interrupt. */
4519 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4520 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4521 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4525 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4527 struct ifnet *ifp = &sc->arpcom.ac_if;
4529 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4532 * Sometimes PCS encoding errors are detected in
4533 * TBI mode (on fiber NICs), and for some reason
4534 * the chip will signal them as link changes.
4535 * If we get a link change event, but the 'PCS
4536 * encoding error' bit in the MAC status register
4537 * is set, don't bother doing a link check.
4538 * This avoids spurious "gigabit link up" messages
4539 * that sometimes appear on fiber NICs during
4540 * periods of heavy traffic.
4542 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4543 if (!sc->bge_link) {
4545 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4546 BGE_CLRBIT(sc, BGE_MAC_MODE,
4547 BGE_MACMODE_TBI_SEND_CFGS);
4549 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4552 if_printf(ifp, "link UP\n");
4554 ifp->if_link_state = LINK_STATE_UP;
4555 if_link_state_change(ifp);
4557 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4562 if_printf(ifp, "link DOWN\n");
4564 ifp->if_link_state = LINK_STATE_DOWN;
4565 if_link_state_change(ifp);
4569 #undef PCS_ENCODE_ERR
4571 /* Clear the attention. */
4572 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4573 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4574 BGE_MACSTAT_LINK_CHANGED);
4578 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4580 struct ifnet *ifp = &sc->arpcom.ac_if;
4581 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4584 bge_miibus_statchg(sc->bge_dev);
4588 if_printf(ifp, "link UP\n");
4590 if_printf(ifp, "link DOWN\n");
4593 /* Clear the attention. */
4594 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4595 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4596 BGE_MACSTAT_LINK_CHANGED);
4600 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4602 struct ifnet *ifp = &sc->arpcom.ac_if;
4603 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4607 if (!sc->bge_link &&
4608 (mii->mii_media_status & IFM_ACTIVE) &&
4609 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4612 if_printf(ifp, "link UP\n");
4613 } else if (sc->bge_link &&
4614 (!(mii->mii_media_status & IFM_ACTIVE) ||
4615 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4618 if_printf(ifp, "link DOWN\n");
4621 /* Clear the attention. */
4622 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4623 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4624 BGE_MACSTAT_LINK_CHANGED);
4628 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4630 struct bge_softc *sc = arg1;
4632 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4633 &sc->bge_rx_coal_ticks,
4634 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4635 BGE_RX_COAL_TICKS_CHG);
4639 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4641 struct bge_softc *sc = arg1;
4643 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4644 &sc->bge_tx_coal_ticks,
4645 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4646 BGE_TX_COAL_TICKS_CHG);
4650 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4652 struct bge_softc *sc = arg1;
4654 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4655 &sc->bge_rx_coal_bds,
4656 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4657 BGE_RX_COAL_BDS_CHG);
4661 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4663 struct bge_softc *sc = arg1;
4665 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4666 &sc->bge_tx_coal_bds,
4667 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4668 BGE_TX_COAL_BDS_CHG);
4672 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4674 struct bge_softc *sc = arg1;
4676 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4677 &sc->bge_rx_coal_ticks_int,
4678 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4679 BGE_RX_COAL_TICKS_INT_CHG);
4683 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4685 struct bge_softc *sc = arg1;
4687 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4688 &sc->bge_tx_coal_ticks_int,
4689 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4690 BGE_TX_COAL_TICKS_INT_CHG);
4694 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4696 struct bge_softc *sc = arg1;
4698 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4699 &sc->bge_rx_coal_bds_int,
4700 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4701 BGE_RX_COAL_BDS_INT_CHG);
4705 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4707 struct bge_softc *sc = arg1;
4709 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4710 &sc->bge_tx_coal_bds_int,
4711 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4712 BGE_TX_COAL_BDS_INT_CHG);
4716 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4717 int coal_min, int coal_max, uint32_t coal_chg_mask)
4719 struct bge_softc *sc = arg1;
4720 struct ifnet *ifp = &sc->arpcom.ac_if;
4723 lwkt_serialize_enter(ifp->if_serializer);
4726 error = sysctl_handle_int(oidp, &v, 0, req);
4727 if (!error && req->newptr != NULL) {
4728 if (v < coal_min || v > coal_max) {
4732 sc->bge_coal_chg |= coal_chg_mask;
4736 lwkt_serialize_exit(ifp->if_serializer);
4741 bge_coal_change(struct bge_softc *sc)
4743 struct ifnet *ifp = &sc->arpcom.ac_if;
4745 ASSERT_SERIALIZED(ifp->if_serializer);
4747 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4748 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4749 sc->bge_rx_coal_ticks);
4751 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4754 if_printf(ifp, "rx_coal_ticks -> %u\n",
4755 sc->bge_rx_coal_ticks);
4759 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4760 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4761 sc->bge_tx_coal_ticks);
4763 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4766 if_printf(ifp, "tx_coal_ticks -> %u\n",
4767 sc->bge_tx_coal_ticks);
4771 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) {
4772 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4773 sc->bge_rx_coal_bds);
4775 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4778 if_printf(ifp, "rx_coal_bds -> %u\n",
4779 sc->bge_rx_coal_bds);
4783 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) {
4784 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4785 sc->bge_tx_coal_bds);
4787 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4790 if_printf(ifp, "tx_max_coal_bds -> %u\n",
4791 sc->bge_tx_coal_bds);
4795 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) {
4796 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
4797 sc->bge_rx_coal_ticks_int);
4799 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT);
4802 if_printf(ifp, "rx_coal_ticks_int -> %u\n",
4803 sc->bge_rx_coal_ticks_int);
4807 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) {
4808 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
4809 sc->bge_tx_coal_ticks_int);
4811 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT);
4814 if_printf(ifp, "tx_coal_ticks_int -> %u\n",
4815 sc->bge_tx_coal_ticks_int);
4819 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) {
4820 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4821 sc->bge_rx_coal_bds_int);
4823 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4826 if_printf(ifp, "rx_coal_bds_int -> %u\n",
4827 sc->bge_rx_coal_bds_int);
4831 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) {
4832 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4833 sc->bge_tx_coal_bds_int);
4835 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4838 if_printf(ifp, "tx_coal_bds_int -> %u\n",
4839 sc->bge_tx_coal_bds_int);
4843 sc->bge_coal_chg = 0;
4847 bge_enable_intr(struct bge_softc *sc)
4849 struct ifnet *ifp = &sc->arpcom.ac_if;
4851 lwkt_serialize_handler_enable(ifp->if_serializer);
4856 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4857 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
4858 /* XXX Linux driver */
4859 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4863 * Unmask the interrupt when we stop polling.
4865 PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4866 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4869 * Trigger another interrupt, since above writing
4870 * to interrupt mailbox0 may acknowledge pending
4873 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4877 bge_disable_intr(struct bge_softc *sc)
4879 struct ifnet *ifp = &sc->arpcom.ac_if;
4882 * Mask the interrupt when we start polling.
4884 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4885 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4888 * Acknowledge possible asserted interrupt.
4890 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4892 sc->bge_npoll.ifpc_stcount = 0;
4894 lwkt_serialize_handler_disable(ifp->if_serializer);
4898 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4903 mac_addr = bge_readmem_ind(sc, 0x0c14);
4904 if ((mac_addr >> 16) == 0x484b) {
4905 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4906 ether_addr[1] = (uint8_t)mac_addr;
4907 mac_addr = bge_readmem_ind(sc, 0x0c18);
4908 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4909 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4910 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4911 ether_addr[5] = (uint8_t)mac_addr;
4918 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4920 int mac_offset = BGE_EE_MAC_OFFSET;
4922 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4923 mac_offset = BGE_EE_MAC_OFFSET_5906;
4925 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4929 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4931 if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4934 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4939 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
4941 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
4942 /* NOTE: Order is critical */
4944 bge_get_eaddr_nvram,
4945 bge_get_eaddr_eeprom,
4948 const bge_eaddr_fcn_t *func;
4950 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
4951 if ((*func)(sc, eaddr) == 0)
4954 return (*func == NULL ? ENXIO : 0);
4958 * NOTE: 'm' is not freed upon failure
4961 bge_defrag_shortdma(struct mbuf *m)
4967 * If device receive two back-to-back send BDs with less than
4968 * or equal to 8 total bytes then the device may hang. The two
4969 * back-to-back send BDs must in the same frame for this failure
4970 * to occur. Scan mbuf chains and see whether two back-to-back
4971 * send BDs are there. If this is the case, allocate new mbuf
4972 * and copy the frame to workaround the silicon bug.
4974 for (n = m, found = 0; n != NULL; n = n->m_next) {
4985 n = m_defrag(m, MB_DONTWAIT);
4992 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
4996 BGE_CLRBIT(sc, reg, bit);
4997 for (i = 0; i < BGE_TIMEOUT; i++) {
4998 if ((CSR_READ_4(sc, reg) & bit) == 0)
5005 bge_link_poll(struct bge_softc *sc)
5009 status = CSR_READ_4(sc, BGE_MAC_STS);
5010 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
5011 sc->bge_link_evt = 0;
5012 sc->bge_link_upd(sc, status);
5017 bge_enable_msi(struct bge_softc *sc)
5021 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
5022 msi_mode |= BGE_MSIMODE_ENABLE;
5023 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
5025 * According to all of the datasheets that are publicly
5026 * available, bit 5 of the MSI_MODE is defined to be
5027 * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on
5028 * which "oneshot MSI" is enabled. However, it is always
5029 * safe to clear it here.
5031 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
5033 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
5037 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp,
5038 uint16_t *mss0, uint16_t *flags0)
5043 int thoff, iphlen, hoff, hlen;
5044 uint16_t flags, mss;
5047 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
5049 hoff = m->m_pkthdr.csum_lhlen;
5050 iphlen = m->m_pkthdr.csum_iphlen;
5051 thoff = m->m_pkthdr.csum_thlen;
5053 KASSERT(hoff > 0, ("invalid ether header len"));
5054 KASSERT(iphlen > 0, ("invalid ip header len"));
5055 KASSERT(thoff > 0, ("invalid tcp header len"));
5057 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
5058 m = m_pullup(m, hoff + iphlen + thoff);
5065 ip = mtodoff(m, struct ip *, hoff);
5066 th = mtodoff(m, struct tcphdr *, hoff + iphlen);
5068 mss = m->m_pkthdr.tso_segsz;
5069 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
5071 ip->ip_len = htons(mss + iphlen + thoff);
5074 hlen = (iphlen + thoff) >> 2;
5075 mss |= (hlen << 11);
5084 bge_stop_fw(struct bge_softc *sc)
5088 if (sc->bge_asf_mode) {
5089 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
5090 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
5091 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
5093 for (i = 0; i < 100; i++ ) {
5094 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
5095 BGE_RX_CPU_DRV_EVENT))
5103 bge_sig_pre_reset(struct bge_softc *sc, int type)
5106 * Some chips don't like this so only do this if ASF is enabled
5108 if (sc->bge_asf_mode)
5109 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
5111 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
5113 case BGE_RESET_START:
5114 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5115 BGE_FW_DRV_STATE_START);
5117 case BGE_RESET_SHUTDOWN:
5118 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5119 BGE_FW_DRV_STATE_UNLOAD);
5121 case BGE_RESET_SUSPEND:
5122 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5123 BGE_FW_DRV_STATE_SUSPEND);
5129 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
5130 bge_ape_driver_state_change(sc, type);
5135 bge_sig_legacy(struct bge_softc *sc, int type)
5137 if (sc->bge_asf_mode) {
5139 case BGE_RESET_START:
5140 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5141 BGE_FW_DRV_STATE_START);
5143 case BGE_RESET_SHUTDOWN:
5144 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5145 BGE_FW_DRV_STATE_UNLOAD);
5152 bge_sig_post_reset(struct bge_softc *sc, int type)
5154 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
5156 case BGE_RESET_START:
5157 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5158 BGE_FW_DRV_STATE_START_DONE);
5161 case BGE_RESET_SHUTDOWN:
5162 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5163 BGE_FW_DRV_STATE_UNLOAD_DONE);
5168 if (type == BGE_RESET_SHUTDOWN)
5169 bge_ape_driver_state_change(sc, type);
5174 bge_asf_driver_up(struct bge_softc *sc)
5176 if (sc->bge_asf_mode & ASF_STACKUP) {
5177 /* Send ASF heartbeat aprox. every 2s */
5178 if (sc->bge_asf_count)
5179 sc->bge_asf_count --;
5181 sc->bge_asf_count = 2;
5182 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
5183 BGE_FW_CMD_DRV_ALIVE);
5184 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
5185 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
5186 BGE_FW_HB_TIMEOUT_SEC);
5187 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
5188 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
5189 BGE_RX_CPU_DRV_EVENT);