2 * Copyright (c) 2005 David Young. All rights reserved.
4 * This code was written by David Young.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
19 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
20 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
21 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
22 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * $NetBSD: sa2400reg.h,v 1.6 2006/03/08 08:26:50 dyoung Exp $
32 * $DragonFly: src/sys/dev/netif/rtw/sa2400reg.h,v 1.3 2007/10/14 04:15:17 sephe Exp $
35 #ifndef _DEV_IC_SA2400REG_H_
36 #define _DEV_IC_SA2400REG_H_
39 * Serial bus format for Philips SA2400 Single-chip Transceiver.
41 #define SA2400_TWI_DATA_MASK __BITS(31,8)
42 #define SA2400_TWI_WREN __BIT(7) /* enable write */
43 #define SA2400_TWI_ADDR_MASK __BITS(6,0)
46 * Registers for Philips SA2400 Single-chip Transceiver.
48 #define SA2400_SYNA 0 /* Synthesizer Register A */
49 #define SA2400_SYNA_FM __BIT(21) /* fractional modulus select,
53 #define SA2400_SYNA_NF_MASK __BITS(20,18) /* fractional increment value,
56 #define SA2400_SYNA_N_MASK __BITS(17,2) /* main divider division ratio,
57 * 512 to 65535, default 615
60 #define SA2400_SYNB 1 /* Synthesizer Register B */
61 #define SA2400_SYNB_R_MASK __BITS(21,12) /* reference divider ratio,
62 * 4 to 1023, default 11
64 #define SA2400_SYNB_L_MASK __BITS(11,10) /* lock detect mode */
65 #define SA2400_SYNB_L_INACTIVE0 __SHIFTIN(0, SA2400_SYNB_L_MASK)
66 #define SA2400_SYNB_L_INACTIVE1 __SHIFTIN(1, SA2400_SYNB_L_MASK)
67 #define SA2400_SYNB_L_NORMAL __SHIFTIN(2, SA2400_SYNB_L_MASK)
68 #define SA2400_SYNB_L_INACTIVE2 __SHIFTIN(3, SA2400_SYNB_L_MASK)
70 #define SA2400_SYNB_ON __BIT(9) /* power on/off,
71 * 0: inverted chip mode control
72 * 1: as defined by chip mode
75 #define SA2400_SYNB_ONE __BIT(8) /* always 1 */
76 #define SA2400_SYNB_FC_MASK __BITS(7,0) /* fractional compensation
77 * charge pump current DAC,
78 * 0 to 255, default 80.
81 #define SA2400_SYNC 2 /* Synthesizer Register C */
82 #define SA2400_SYNC_CP_MASK __BITS(7,6) /* charge pump current
85 #define SA2400_SYNC_CP_NORMAL_ __SHIFTIN(0, SA2400_SYNC_CP_MASK)
86 #define SA2400_SYNC_CP_THIRD_ __SHIFTIN(1, SA2400_SYNC_CP_MASK)
87 #define SA2400_SYNC_CP_NORMAL __SHIFTIN(2, SA2400_SYNC_CP_MASK) /* recommended */
88 #define SA2400_SYNC_CP_THIRD __SHIFTIN(3, SA2400_SYNC_CP_MASK)
90 #define SA2400_SYNC_SM_MASK __BITS(5,3) /* comparison divider select,
91 * 0 to 4, extra division
94 #define SA2400_SYNC_ZERO __BIT(2) /* always 0 */
96 #define SA2400_SYND 3 /* Synthesizer Register D */
97 #define SA2400_SYND_ZERO1_MASK __BITS(21,17) /* always 0 */
98 #define SA2400_SYND_TPHPSU __BIT(16) /* T[phpsu], 1: disable
100 * overrides SA2400_SYND_TSPU
102 #define SA2400_SYND_TPSU __BIT(15) /* T[spu], 1: speedup on,
105 #define SA2400_SYND_ZERO2_MASK __BITS(14,3) /* always 0 */
107 #define SA2400_OPMODE 4 /* Operating mode, filter tuner,
110 /* 1: in Rx mode, RSSI-ADC always on 0: RSSI-ADC only on during AGC */
111 #define SA2400_OPMODE_ADC __BIT(19)
112 /* read-only filter tuner error: 1 if tuner out of range */
113 #define SA2400_OPMODE_FTERR __BIT(18)
114 /* Rx & Tx filter tuning, write tuning value (test mode only) or
115 * read tuner setting (in normal mode).
117 #define SA2400_OPMODE_FILTTUNE_MASK __BITS(17,15)
119 /* external reference voltage (pad v2p5) on */
120 #define SA2400_OPMODE_V2P5 __BIT(14)
121 /* external reference current ... */
122 #define SA2400_OPMODE_I1M __BIT(13)
123 /* external reference current ... */
124 #define SA2400_OPMODE_I0P3 __BIT(12)
125 #define SA2400_OPMODE_IN22 __BIT(10) /* xtal input frequency,
129 #define SA2400_OPMODE_CLK __BIT(9) /* reference clock output on */
130 #define SA2400_OPMODE_XO __BIT(8) /* xtal oscillator on */
131 #define SA2400_OPMODE_DIGIN __BIT(7) /* use digital Tx inputs
134 #define SA2400_OPMODE_RXLV __BIT(6) /* Rx output common mode
139 #define SA2400_OPMODE_VEO __BIT(5) /* make internal vco
140 * available at vco pads
143 #define SA2400_OPMODE_VEI __BIT(4) /* use external vco input
146 /* main operating mode */
147 #define SA2400_OPMODE_MODE_MASK __BITS(3,0)
148 #define SA2400_OPMODE_MODE_SLEEP __SHIFTIN(0, SA2400_OPMODE_MODE_MASK)
149 #define SA2400_OPMODE_MODE_TXRX __SHIFTIN(1, SA2400_OPMODE_MODE_MASK)
150 #define SA2400_OPMODE_MODE_WAIT __SHIFTIN(2, SA2400_OPMODE_MODE_MASK)
151 #define SA2400_OPMODE_MODE_RXMGC __SHIFTIN(3, SA2400_OPMODE_MODE_MASK)
152 #define SA2400_OPMODE_MODE_FCALIB __SHIFTIN(4, SA2400_OPMODE_MODE_MASK)
153 #define SA2400_OPMODE_MODE_DCALIB __SHIFTIN(5, SA2400_OPMODE_MODE_MASK)
154 #define SA2400_OPMODE_MODE_FASTTXRXMGC __SHIFTIN(6, SA2400_OPMODE_MODE_MASK)
155 #define SA2400_OPMODE_MODE_RESET __SHIFTIN(7, SA2400_OPMODE_MODE_MASK)
156 #define SA2400_OPMODE_MODE_VCOCALIB __SHIFTIN(8, SA2400_OPMODE_MODE_MASK)
158 #define SA2400_OPMODE_DEFAULTS \
159 (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK | \
160 SA2400_OPMODE_I0P3 | __SHIFTIN(3, SA2400_OPMODE_FILTTUNE_MASK))
162 #define SA2400_AGC 5 /* AGC adjustment */
163 #define SA2400_AGC_TARGETSIGN __BIT(23) /* fine-tune AGC target:
164 * -7dB to 7dB, sign bit ... */
165 #define SA2400_AGC_TARGET_MASK __BITS(22,20) /* ... plus 0dB - 7dB */
166 #define SA2400_AGC_MAXGAIN_MASK __BITS(19,15) /* maximum AGC gain, 0 to 31,
167 * (yields 54dB to 85dB)
169 /* write: settling time after baseband gain switching, units of
171 * read: output of RSSI/Tx-peak detector's ADC in 5-bit Gray code.
173 #define SA2400_AGC_BBPDELAY_MASK __BITS(14,10)
174 #define SA2400_AGC_ADCVAL_MASK SA2400_AGC_BBPDELAY_MASK
176 /* write: settling time after LNA gain switching, units of
178 * read: 2nd sample of RSSI in AGC cycle
180 #define SA2400_AGC_LNADELAY_MASK __BITS(9,5)
181 #define SA2400_AGC_SAMPLE2_MASK SA2400_AGC_LNADELAY_MASK
183 /* write: time between turning on Rx and AGCSET, units of
185 * read: 1st sample of RSSI in AGC cycle
187 #define SA2400_AGC_RXONDELAY_MASK __BITS(4,0)
188 #define SA2400_AGC_SAMPLE1_MASK SA2400_AGC_RXONDELAY_MASK
190 #define SA2400_MANRX 6 /* Manual receiver control settings */
191 #define SA2400_MANRX_AHSN __BIT(23) /* 1: AGC w/ high S/N---switch
194 * 0: switch LNA at step 60
197 /* If _RXOSQON, Q offset is
198 * (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts,
199 * otherwise, Q offset is 0.
203 #define SA2400_MANRX_RXOSQON __BIT(22) /* Rx Q-channel correction. */
204 #define SA2400_MANRX_RXOSQSIGN __BIT(21)
205 #define SA2400_MANRX_RXOSQ_MASK __BITS(20,18)
207 #define SA2400_MANRX_RXOSION __BIT(17) /* Rx I-channel correction. */
208 #define SA2400_MANRX_RXOSISIGN __BIT(16)
209 #define SA2400_MANRX_RXOSI_MASK __BITS(15,13)
210 #define SA2400_MANRX_TEN __BIT(12) /* use 10MHz offset cancellation
211 * cornerpoint for brief period
212 * after each gain change
215 /* DC offset cancellation cornerpoint select
216 * write: in RXMGC, set the cornerpoint
217 * read: in other modes, read AGC-controlled cornerpoint
219 #define SA2400_MANRX_CORNERFREQ_MASK __BITS(11,10)
221 /* write: in RXMGC mode, sets receiver gain
222 * read: in other modes, read AGC-controlled gain
224 #define SA2400_MANRX_RXGAIN_MASK __BITS(9,0)
226 #define SA2400_TX 7 /* Transmitter settings */
229 * write: in test mode, sets the offsets
230 * read: in normal mode, returns automatic settings
232 #define SA2400_TX_TXOSQON __BIT(19)
233 #define SA2400_TX_TXOSQSIGN __BIT(18)
234 #define SA2400_TX_TXOSQ_MASK __BITS(17,15)
235 #define SA2400_TX_TXOSION __BIT(14)
236 #define SA2400_TX_TXOSISIGN __BIT(13)
237 #define SA2400_TX_TXOSI_MASK __BITS(12,10)
239 #define SA2400_TX_RAMP_MASK __BITS(9,8) /* Ramp-up delay,
244 * datasheet says, "ramp-up
245 * time always 1us". huh?
247 #define SA2400_TX_HIGAIN_MASK __BITS(7,4) /* Transmitter gain settings
250 #define SA2400_TX_LOGAIN_MASK __BITS(3,0) /* Transmitter gain settings
254 #define SA2400_VCO 8 /* VCO settings */
255 #define SA2400_VCO_ZERO __BITS(6,5) /* always zero */
256 #define SA2400_VCO_VCERR __BIT(4)/* VCO calibration error flag---no
257 * band with low enough frequency
260 #define SA2400_VCO_VCOBAND_MASK __BITS(3,0) /* VCO band,
261 * write: in test mode, sets
263 * read: in normal mode,
265 * calibration (VCOCAL).
270 #define SA2400_SQ_RSSI_MAP \
271 0x64, 0x64, 0x63, 0x62, 0x61, 0x60, 0x5f, 0x5e, \
272 0x5d, 0x5c, 0x5b, 0x5a, 0x57, 0x54, 0x52, 0x50, \
273 0x4e, 0x4c, 0x4a, 0x48, 0x46, 0x44, 0x41, 0x3f, \
274 0x3c, 0x3a, 0x37, 0x36, 0x36, 0x1c, 0x1c, 0x1b, \
275 0x1b, 0x1a, 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17, \
276 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13, \
277 0x13, 0x12, 0x12, 0x11, 0x11, 0x10, 0x10, 0x0f, \
278 0x0f, 0x0e, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b, \
279 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07, \
280 0x07, 0x06, 0x06, 0x05, 0x04, 0x03, 0x02, 0x00
282 #define SA2400_SQ_RSSI_MAP_MAX 80
284 #endif /* _DEV_IC_SA2400REG_H_ */