2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
85 #include <bus/pci/pcireg.h>
86 #include <bus/pci/pcivar.h>
88 #include "miibus_if.h"
90 #include <dev/netif/bce/if_bcereg.h>
91 #include <dev/netif/bce/if_bcefw.h>
93 /****************************************************************************/
94 /* BCE Debug Options */
95 /****************************************************************************/
98 static uint32_t bce_debug = BCE_WARN;
102 * 1 = 1 in 2,147,483,648
103 * 256 = 1 in 8,388,608
104 * 2048 = 1 in 1,048,576
105 * 65536 = 1 in 32,768
106 * 1048576 = 1 in 2,048
109 * 1073741824 = 1 in 2
111 * bce_debug_l2fhdr_status_check:
112 * How often the l2_fhdr frame error check will fail.
114 * bce_debug_unexpected_attention:
115 * How often the unexpected attention check will fail.
117 * bce_debug_mbuf_allocation_failure:
118 * How often to simulate an mbuf allocation failure.
120 * bce_debug_dma_map_addr_failure:
121 * How often to simulate a DMA mapping failure.
123 * bce_debug_bootcode_running_failure:
124 * How often to simulate a bootcode failure.
126 static int bce_debug_l2fhdr_status_check = 0;
127 static int bce_debug_unexpected_attention = 0;
128 static int bce_debug_mbuf_allocation_failure = 0;
129 static int bce_debug_dma_map_addr_failure = 0;
130 static int bce_debug_bootcode_running_failure = 0;
132 #endif /* BCE_DEBUG */
135 /****************************************************************************/
136 /* PCI Device ID Table */
138 /* Used by bce_probe() to identify the devices supported by this driver. */
139 /****************************************************************************/
140 #define BCE_DEVDESC_MAX 64
142 static struct bce_type bce_devs[] = {
143 /* BCM5706C Controllers and OEM boards. */
144 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
145 "HP NC370T Multifunction Gigabit Server Adapter" },
146 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
147 "HP NC370i Multifunction Gigabit Server Adapter" },
148 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
149 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
150 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
151 "HP NC371i Multifunction Gigabit Server Adapter" },
152 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
153 "Broadcom NetXtreme II BCM5706 1000Base-T" },
155 /* BCM5706S controllers and OEM boards. */
156 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
157 "HP NC370F Multifunction Gigabit Server Adapter" },
158 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
159 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
161 /* BCM5708C controllers and OEM boards. */
162 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
163 "HP NC373T PCIe Multifunction Gig Server Adapter" },
164 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
165 "HP NC373i Multifunction Gigabit Server Adapter" },
166 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
167 "HP NC374m PCIe Multifunction Adapter" },
168 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
169 "Broadcom NetXtreme II BCM5708 1000Base-T" },
171 /* BCM5708S controllers and OEM boards. */
172 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
173 "HP NC373m Multifunction Gigabit Server Adapter" },
174 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
175 "HP NC373i Multifunction Gigabit Server Adapter" },
176 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
177 "HP NC373F PCIe Multifunc Giga Server Adapter" },
178 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
179 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
181 /* BCM5709C controllers and OEM boards. */
182 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
183 "HP NC382i DP Multifunction Gigabit Server Adapter" },
184 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
185 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
186 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
187 "Broadcom NetXtreme II BCM5709 1000Base-T" },
189 /* BCM5709S controllers and OEM boards. */
190 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
191 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
192 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
193 "HP NC382i DP Multifunction Gigabit Server Adapter" },
194 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
195 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
197 /* BCM5716 controllers and OEM boards. */
198 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
199 "Broadcom NetXtreme II BCM5716 1000Base-T" },
205 /****************************************************************************/
206 /* Supported Flash NVRAM device data. */
207 /****************************************************************************/
208 static const struct flash_spec flash_table[] =
210 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
211 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
214 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
215 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
216 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
218 /* Expansion entry 0001 */
219 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
223 /* Saifun SA25F010 (non-buffered flash) */
224 /* strap, cfg1, & write1 need updates */
225 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
226 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
227 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
228 "Non-buffered flash (128kB)"},
229 /* Saifun SA25F020 (non-buffered flash) */
230 /* strap, cfg1, & write1 need updates */
231 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
232 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
233 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
234 "Non-buffered flash (256kB)"},
235 /* Expansion entry 0100 */
236 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
237 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
238 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
240 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
241 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
242 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
243 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
244 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
245 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
246 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
247 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
248 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
249 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
250 /* Saifun SA25F005 (non-buffered flash) */
251 /* strap, cfg1, & write1 need updates */
252 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
253 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
254 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
255 "Non-buffered flash (64kB)"},
257 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
258 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
259 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
261 /* Expansion entry 1001 */
262 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
263 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
264 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
266 /* Expansion entry 1010 */
267 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
268 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
269 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
271 /* ATMEL AT45DB011B (buffered flash) */
272 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
273 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
274 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
275 "Buffered flash (128kB)"},
276 /* Expansion entry 1100 */
277 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
278 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
279 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
281 /* Expansion entry 1101 */
282 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
283 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
284 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
286 /* Ateml Expansion entry 1110 */
287 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
288 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
289 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
290 "Entry 1110 (Atmel)"},
291 /* ATMEL AT45DB021B (buffered flash) */
292 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
293 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
294 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
295 "Buffered flash (256kB)"},
299 * The BCM5709 controllers transparently handle the
300 * differences between Atmel 264 byte pages and all
301 * flash devices which use 256 byte pages, so no
302 * logical-to-physical mapping is required in the
305 static struct flash_spec flash_5709 = {
306 .flags = BCE_NV_BUFFERED,
307 .page_bits = BCM5709_FLASH_PAGE_BITS,
308 .page_size = BCM5709_FLASH_PAGE_SIZE,
309 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
310 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
311 .name = "5709/5716 buffered flash (256kB)",
315 /****************************************************************************/
316 /* DragonFly device entry points. */
317 /****************************************************************************/
318 static int bce_probe(device_t);
319 static int bce_attach(device_t);
320 static int bce_detach(device_t);
321 static void bce_shutdown(device_t);
323 /****************************************************************************/
324 /* BCE Debug Data Structure Dump Routines */
325 /****************************************************************************/
327 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
328 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
329 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
330 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
331 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
332 static void bce_dump_l2fhdr(struct bce_softc *, int,
333 struct l2_fhdr *) __unused;
334 static void bce_dump_tx_chain(struct bce_softc *, int, int);
335 static void bce_dump_rx_chain(struct bce_softc *, int, int);
336 static void bce_dump_status_block(struct bce_softc *);
337 static void bce_dump_driver_state(struct bce_softc *);
338 static void bce_dump_stats_block(struct bce_softc *) __unused;
339 static void bce_dump_hw_state(struct bce_softc *);
340 static void bce_dump_txp_state(struct bce_softc *);
341 static void bce_dump_rxp_state(struct bce_softc *) __unused;
342 static void bce_dump_tpat_state(struct bce_softc *) __unused;
343 static void bce_freeze_controller(struct bce_softc *) __unused;
344 static void bce_unfreeze_controller(struct bce_softc *) __unused;
345 static void bce_breakpoint(struct bce_softc *);
346 #endif /* BCE_DEBUG */
349 /****************************************************************************/
350 /* BCE Register/Memory Access Routines */
351 /****************************************************************************/
352 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
353 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
354 static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
355 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
356 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
357 static int bce_miibus_read_reg(device_t, int, int);
358 static int bce_miibus_write_reg(device_t, int, int, int);
359 static void bce_miibus_statchg(device_t);
362 /****************************************************************************/
363 /* BCE NVRAM Access Routines */
364 /****************************************************************************/
365 static int bce_acquire_nvram_lock(struct bce_softc *);
366 static int bce_release_nvram_lock(struct bce_softc *);
367 static void bce_enable_nvram_access(struct bce_softc *);
368 static void bce_disable_nvram_access(struct bce_softc *);
369 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
371 static int bce_init_nvram(struct bce_softc *);
372 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
373 static int bce_nvram_test(struct bce_softc *);
375 /****************************************************************************/
376 /* BCE DMA Allocate/Free Routines */
377 /****************************************************************************/
378 static int bce_dma_alloc(struct bce_softc *);
379 static void bce_dma_free(struct bce_softc *);
380 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
382 /****************************************************************************/
383 /* BCE Firmware Synchronization and Load */
384 /****************************************************************************/
385 static int bce_fw_sync(struct bce_softc *, uint32_t);
386 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
388 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
390 static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
391 static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
392 static void bce_start_rxp_cpu(struct bce_softc *);
393 static void bce_init_rxp_cpu(struct bce_softc *);
394 static void bce_init_txp_cpu(struct bce_softc *);
395 static void bce_init_tpat_cpu(struct bce_softc *);
396 static void bce_init_cp_cpu(struct bce_softc *);
397 static void bce_init_com_cpu(struct bce_softc *);
398 static void bce_init_cpus(struct bce_softc *);
400 static void bce_stop(struct bce_softc *);
401 static int bce_reset(struct bce_softc *, uint32_t);
402 static int bce_chipinit(struct bce_softc *);
403 static int bce_blockinit(struct bce_softc *);
404 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
406 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
407 static void bce_probe_pci_caps(struct bce_softc *);
408 static void bce_print_adapter_info(struct bce_softc *);
409 static void bce_get_media(struct bce_softc *);
411 static void bce_init_tx_context(struct bce_softc *);
412 static int bce_init_tx_chain(struct bce_softc *);
413 static void bce_init_rx_context(struct bce_softc *);
414 static int bce_init_rx_chain(struct bce_softc *);
415 static void bce_free_rx_chain(struct bce_softc *);
416 static void bce_free_tx_chain(struct bce_softc *);
418 static int bce_encap(struct bce_softc *, struct mbuf **);
419 static void bce_start(struct ifnet *);
420 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
421 static void bce_watchdog(struct ifnet *);
422 static int bce_ifmedia_upd(struct ifnet *);
423 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
424 static void bce_init(void *);
425 static void bce_mgmt_init(struct bce_softc *);
427 static int bce_init_ctx(struct bce_softc *);
428 static void bce_get_mac_addr(struct bce_softc *);
429 static void bce_set_mac_addr(struct bce_softc *);
430 static void bce_phy_intr(struct bce_softc *);
431 static void bce_rx_intr(struct bce_softc *, int);
432 static void bce_tx_intr(struct bce_softc *);
433 static void bce_disable_intr(struct bce_softc *);
434 static void bce_enable_intr(struct bce_softc *, int);
436 #ifdef DEVICE_POLLING
437 static void bce_poll(struct ifnet *, enum poll_cmd, int);
439 static void bce_intr(struct bce_softc *);
440 static void bce_intr_legacy(void *);
441 static void bce_intr_msi(void *);
442 static void bce_intr_msi_oneshot(void *);
443 static void bce_set_rx_mode(struct bce_softc *);
444 static void bce_stats_update(struct bce_softc *);
445 static void bce_tick(void *);
446 static void bce_tick_serialized(struct bce_softc *);
447 static void bce_pulse(void *);
448 static void bce_pulse_check_msi(struct bce_softc *);
449 static void bce_add_sysctls(struct bce_softc *);
451 static void bce_coal_change(struct bce_softc *);
452 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
453 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
454 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
455 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
456 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
457 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
458 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
459 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
460 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
461 uint32_t *, uint32_t);
465 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
466 * takes 1023 as the TX ticks limit. However, using 1023 will
467 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
468 * there is _no_ network activity on the NIC.
470 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
471 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
472 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
473 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
474 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
475 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
476 static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
477 static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
479 static int bce_msi_enable = 1;
481 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
482 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
483 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
484 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
485 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
486 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
487 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
488 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
489 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
491 /****************************************************************************/
492 /* DragonFly device dispatch table. */
493 /****************************************************************************/
494 static device_method_t bce_methods[] = {
495 /* Device interface */
496 DEVMETHOD(device_probe, bce_probe),
497 DEVMETHOD(device_attach, bce_attach),
498 DEVMETHOD(device_detach, bce_detach),
499 DEVMETHOD(device_shutdown, bce_shutdown),
502 DEVMETHOD(bus_print_child, bus_generic_print_child),
503 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
506 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
507 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
508 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
513 static driver_t bce_driver = {
516 sizeof(struct bce_softc)
519 static devclass_t bce_devclass;
522 DECLARE_DUMMY_MODULE(if_bce);
523 MODULE_DEPEND(bce, miibus, 1, 1, 1);
524 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
525 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
528 /****************************************************************************/
529 /* Device probe function. */
531 /* Compares the device to the driver's list of supported devices and */
532 /* reports back to the OS whether this is the right driver for the device. */
535 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
536 /****************************************************************************/
538 bce_probe(device_t dev)
541 uint16_t vid, did, svid, sdid;
543 /* Get the data for the device to be probed. */
544 vid = pci_get_vendor(dev);
545 did = pci_get_device(dev);
546 svid = pci_get_subvendor(dev);
547 sdid = pci_get_subdevice(dev);
549 /* Look through the list of known devices for a match. */
550 for (t = bce_devs; t->bce_name != NULL; ++t) {
551 if (vid == t->bce_vid && did == t->bce_did &&
552 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
553 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
554 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
557 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
559 /* Print out the device identity. */
560 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
562 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
564 device_set_desc_copy(dev, descbuf);
565 kfree(descbuf, M_TEMP);
573 /****************************************************************************/
574 /* PCI Capabilities Probe Function. */
576 /* Walks the PCI capabiites list for the device to find what features are */
581 /****************************************************************************/
583 bce_print_adapter_info(struct bce_softc *sc)
585 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
587 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
588 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
591 if (sc->bce_flags & BCE_PCIE_FLAG) {
592 kprintf("Bus (PCIe x%d, ", sc->link_width);
593 switch (sc->link_speed) {
595 kprintf("2.5Gbps); ");
601 kprintf("Unknown link speed); ");
605 kprintf("Bus (PCI%s, %s, %dMHz); ",
606 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
607 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
611 /* Firmware version and device features. */
612 kprintf("B/C (%s)", sc->bce_bc_ver);
614 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
615 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
617 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
618 kprintf("MFW[%s]", sc->bce_mfw_ver);
619 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
627 /****************************************************************************/
628 /* PCI Capabilities Probe Function. */
630 /* Walks the PCI capabiites list for the device to find what features are */
635 /****************************************************************************/
637 bce_probe_pci_caps(struct bce_softc *sc)
639 device_t dev = sc->bce_dev;
642 if (pci_is_pcix(dev))
643 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
645 ptr = pci_get_pciecap_ptr(dev);
647 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
649 sc->link_speed = link_status & 0xf;
650 sc->link_width = (link_status >> 4) & 0x3f;
651 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
652 sc->bce_flags |= BCE_PCIE_FLAG;
657 /****************************************************************************/
658 /* Device attach function. */
660 /* Allocates device resources, performs secondary chip identification, */
661 /* resets and initializes the hardware, and initializes driver instance */
665 /* 0 on success, positive value on failure. */
666 /****************************************************************************/
668 bce_attach(device_t dev)
670 struct bce_softc *sc = device_get_softc(dev);
671 struct ifnet *ifp = &sc->arpcom.ac_if;
674 void (*irq_handle)(void *);
679 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
681 pci_enable_busmaster(dev);
683 bce_probe_pci_caps(sc);
685 /* Allocate PCI memory resources. */
687 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
688 RF_ACTIVE | PCI_RF_DENSE);
689 if (sc->bce_res_mem == NULL) {
690 device_printf(dev, "PCI memory allocation failed\n");
693 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
694 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
696 /* Allocate PCI IRQ resources. */
697 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
698 &sc->bce_irq_rid, &irq_flags);
700 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
701 &sc->bce_irq_rid, irq_flags);
702 if (sc->bce_res_irq == NULL) {
703 device_printf(dev, "PCI map interrupt failed\n");
709 * Configure byte swap and enable indirect register access.
710 * Rely on CPU to do target byte swapping on big endian systems.
711 * Access to registers outside of PCI configurtion space are not
712 * valid until this is done.
714 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
715 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
716 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
718 /* Save ASIC revsion info. */
719 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
721 /* Weed out any non-production controller revisions. */
722 switch (BCE_CHIP_ID(sc)) {
723 case BCE_CHIP_ID_5706_A0:
724 case BCE_CHIP_ID_5706_A1:
725 case BCE_CHIP_ID_5708_A0:
726 case BCE_CHIP_ID_5708_B0:
727 case BCE_CHIP_ID_5709_A0:
728 case BCE_CHIP_ID_5709_B0:
729 case BCE_CHIP_ID_5709_B1:
731 /* 5709C B2 seems to work fine */
732 case BCE_CHIP_ID_5709_B2:
734 device_printf(dev, "Unsupported chip id 0x%08x!\n",
740 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
741 irq_handle = bce_intr_legacy;
742 } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
743 irq_handle = bce_intr_msi;
744 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
745 irq_handle = bce_intr_msi_oneshot;
746 sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
749 panic("%s: unsupported intr type %d",
750 device_get_nameunit(dev), sc->bce_irq_type);
754 * Find the base address for shared memory access.
755 * Newer versions of bootcode use a signature and offset
756 * while older versions use a fixed address.
758 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
759 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
760 BCE_SHM_HDR_SIGNATURE_SIG) {
761 /* Multi-port devices use different offsets in shared memory. */
762 sc->bce_shmem_base = REG_RD_IND(sc,
763 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
765 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
767 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
769 /* Fetch the bootcode revision. */
770 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
771 for (i = 0, j = 0; i < 3; i++) {
775 num = (uint8_t)(val >> (24 - (i * 8)));
776 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
777 if (num >= k || !skip0 || k == 1) {
778 sc->bce_bc_ver[j++] = (num / k) + '0';
783 sc->bce_bc_ver[j++] = '.';
786 /* Check if any management firwmare is running. */
787 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
788 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
789 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
791 /* Allow time for firmware to enter the running state. */
792 for (i = 0; i < 30; i++) {
793 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
794 if (val & BCE_CONDITION_MFW_RUN_MASK)
800 /* Check the current bootcode state. */
801 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
802 BCE_CONDITION_MFW_RUN_MASK;
803 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
804 val != BCE_CONDITION_MFW_RUN_NONE) {
805 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
807 for (i = 0, j = 0; j < 3; j++) {
808 val = bce_reg_rd_ind(sc, addr + j * 4);
810 memcpy(&sc->bce_mfw_ver[i], &val, 4);
815 /* Get PCI bus information (speed and type). */
816 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
817 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
820 sc->bce_flags |= BCE_PCIX_FLAG;
822 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
823 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
825 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
826 sc->bus_speed_mhz = 133;
829 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
830 sc->bus_speed_mhz = 100;
833 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
834 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
835 sc->bus_speed_mhz = 66;
838 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
839 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
840 sc->bus_speed_mhz = 50;
843 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
844 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
845 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
846 sc->bus_speed_mhz = 33;
850 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
851 sc->bus_speed_mhz = 66;
853 sc->bus_speed_mhz = 33;
856 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
857 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
859 /* Reset the controller. */
860 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
864 /* Initialize the controller. */
865 rc = bce_chipinit(sc);
867 device_printf(dev, "Controller initialization failed!\n");
871 /* Perform NVRAM test. */
872 rc = bce_nvram_test(sc);
874 device_printf(dev, "NVRAM test failed!\n");
878 /* Fetch the permanent Ethernet MAC address. */
879 bce_get_mac_addr(sc);
882 * Trip points control how many BDs
883 * should be ready before generating an
884 * interrupt while ticks control how long
885 * a BD can sit in the chain before
886 * generating an interrupt. Set the default
887 * values for the RX and TX rings.
891 /* Force more frequent interrupts. */
892 sc->bce_tx_quick_cons_trip_int = 1;
893 sc->bce_tx_quick_cons_trip = 1;
894 sc->bce_tx_ticks_int = 0;
895 sc->bce_tx_ticks = 0;
897 sc->bce_rx_quick_cons_trip_int = 1;
898 sc->bce_rx_quick_cons_trip = 1;
899 sc->bce_rx_ticks_int = 0;
900 sc->bce_rx_ticks = 0;
902 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
903 sc->bce_tx_quick_cons_trip = bce_tx_bds;
904 sc->bce_tx_ticks_int = bce_tx_ticks_int;
905 sc->bce_tx_ticks = bce_tx_ticks;
907 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
908 sc->bce_rx_quick_cons_trip = bce_rx_bds;
909 sc->bce_rx_ticks_int = bce_rx_ticks_int;
910 sc->bce_rx_ticks = bce_rx_ticks;
913 /* Update statistics once every second. */
914 sc->bce_stats_ticks = 1000000 & 0xffff00;
916 /* Find the media type for the adapter. */
919 /* Allocate DMA memory resources. */
920 rc = bce_dma_alloc(sc);
922 device_printf(dev, "DMA resource allocation failed!\n");
926 /* Initialize the ifnet interface. */
928 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
929 ifp->if_ioctl = bce_ioctl;
930 ifp->if_start = bce_start;
931 ifp->if_init = bce_init;
932 ifp->if_watchdog = bce_watchdog;
933 #ifdef DEVICE_POLLING
934 ifp->if_poll = bce_poll;
936 ifp->if_mtu = ETHERMTU;
937 ifp->if_hwassist = BCE_IF_HWASSIST;
938 ifp->if_capabilities = BCE_IF_CAPABILITIES;
939 ifp->if_capenable = ifp->if_capabilities;
940 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
941 ifq_set_ready(&ifp->if_snd);
943 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
944 ifp->if_baudrate = IF_Gbps(2.5);
946 ifp->if_baudrate = IF_Gbps(1);
948 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
949 sc->mbuf_alloc_size = MCLBYTES;
951 /* Look for our PHY. */
952 rc = mii_phy_probe(dev, &sc->bce_miibus,
953 bce_ifmedia_upd, bce_ifmedia_sts);
955 device_printf(dev, "PHY probe failed!\n");
959 /* Attach to the Ethernet interface list. */
960 ether_ifattach(ifp, sc->eaddr, NULL);
962 callout_init_mp(&sc->bce_tick_callout);
963 callout_init_mp(&sc->bce_pulse_callout);
965 /* Hookup IRQ last. */
966 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
967 &sc->bce_intrhand, ifp->if_serializer);
969 device_printf(dev, "Failed to setup IRQ!\n");
974 ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
975 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
977 /* Print some important debugging info. */
978 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
980 /* Add the supported sysctls to the kernel. */
984 * The chip reset earlier notified the bootcode that
985 * a driver is present. We now need to start our pulse
986 * routine so that the bootcode is reminded that we're
991 /* Get the firmware running so IPMI still works */
995 bce_print_adapter_info(sc);
1004 /****************************************************************************/
1005 /* Device detach function. */
1007 /* Stops the controller, resets the controller, and releases resources. */
1010 /* 0 on success, positive value on failure. */
1011 /****************************************************************************/
1013 bce_detach(device_t dev)
1015 struct bce_softc *sc = device_get_softc(dev);
1017 if (device_is_attached(dev)) {
1018 struct ifnet *ifp = &sc->arpcom.ac_if;
1021 /* Stop and reset the controller. */
1022 lwkt_serialize_enter(ifp->if_serializer);
1023 callout_stop(&sc->bce_pulse_callout);
1025 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1026 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1028 msg = BCE_DRV_MSG_CODE_UNLOAD;
1030 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1031 lwkt_serialize_exit(ifp->if_serializer);
1033 ether_ifdetach(ifp);
1036 /* If we have a child device on the MII bus remove it too. */
1038 device_delete_child(dev, sc->bce_miibus);
1039 bus_generic_detach(dev);
1041 if (sc->bce_res_irq != NULL) {
1042 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1046 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1047 pci_release_msi(dev);
1049 if (sc->bce_res_mem != NULL) {
1050 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1056 if (sc->bce_sysctl_tree != NULL)
1057 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1063 /****************************************************************************/
1064 /* Device shutdown function. */
1066 /* Stops and resets the controller. */
1070 /****************************************************************************/
1072 bce_shutdown(device_t dev)
1074 struct bce_softc *sc = device_get_softc(dev);
1075 struct ifnet *ifp = &sc->arpcom.ac_if;
1078 lwkt_serialize_enter(ifp->if_serializer);
1080 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1081 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1083 msg = BCE_DRV_MSG_CODE_UNLOAD;
1085 lwkt_serialize_exit(ifp->if_serializer);
1089 /****************************************************************************/
1090 /* Indirect register read. */
1092 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1093 /* configuration space. Using this mechanism avoids issues with posted */
1094 /* reads but is much slower than memory-mapped I/O. */
1097 /* The value of the register. */
1098 /****************************************************************************/
1100 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1102 device_t dev = sc->bce_dev;
1104 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1108 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1109 DBPRINT(sc, BCE_EXCESSIVE,
1110 "%s(); offset = 0x%08X, val = 0x%08X\n",
1111 __func__, offset, val);
1115 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1120 /****************************************************************************/
1121 /* Indirect register write. */
1123 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1124 /* configuration space. Using this mechanism avoids issues with posted */
1125 /* writes but is muchh slower than memory-mapped I/O. */
1129 /****************************************************************************/
1131 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1133 device_t dev = sc->bce_dev;
1135 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1136 __func__, offset, val);
1138 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1139 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1143 /****************************************************************************/
1144 /* Shared memory write. */
1146 /* Writes NetXtreme II shared memory region. */
1150 /****************************************************************************/
1152 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1154 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1158 /****************************************************************************/
1159 /* Shared memory read. */
1161 /* Reads NetXtreme II shared memory region. */
1164 /* The 32 bit value read. */
1165 /****************************************************************************/
1167 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1169 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1173 /****************************************************************************/
1174 /* Context memory write. */
1176 /* The NetXtreme II controller uses context memory to track connection */
1177 /* information for L2 and higher network protocols. */
1181 /****************************************************************************/
1183 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1186 uint32_t idx, offset = ctx_offset + cid_addr;
1187 uint32_t val, retry_cnt = 5;
1189 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1190 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1191 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1192 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1194 for (idx = 0; idx < retry_cnt; idx++) {
1195 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1196 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1201 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1202 device_printf(sc->bce_dev,
1203 "Unable to write CTX memory: "
1204 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1205 cid_addr, ctx_offset);
1208 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1209 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1214 /****************************************************************************/
1215 /* PHY register read. */
1217 /* Implements register reads on the MII bus. */
1220 /* The value of the register. */
1221 /****************************************************************************/
1223 bce_miibus_read_reg(device_t dev, int phy, int reg)
1225 struct bce_softc *sc = device_get_softc(dev);
1229 /* Make sure we are accessing the correct PHY address. */
1230 if (phy != sc->bce_phy_addr) {
1231 DBPRINT(sc, BCE_VERBOSE,
1232 "Invalid PHY address %d for PHY read!\n", phy);
1236 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1237 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1238 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1240 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1241 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1246 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1247 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1248 BCE_EMAC_MDIO_COMM_START_BUSY;
1249 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1251 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1254 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1255 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1258 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1259 val &= BCE_EMAC_MDIO_COMM_DATA;
1264 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1265 if_printf(&sc->arpcom.ac_if,
1266 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1270 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1273 DBPRINT(sc, BCE_EXCESSIVE,
1274 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1275 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1277 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1278 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1279 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1281 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1282 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1286 return (val & 0xffff);
1290 /****************************************************************************/
1291 /* PHY register write. */
1293 /* Implements register writes on the MII bus. */
1296 /* The value of the register. */
1297 /****************************************************************************/
1299 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1301 struct bce_softc *sc = device_get_softc(dev);
1305 /* Make sure we are accessing the correct PHY address. */
1306 if (phy != sc->bce_phy_addr) {
1307 DBPRINT(sc, BCE_WARN,
1308 "Invalid PHY address %d for PHY write!\n", phy);
1312 DBPRINT(sc, BCE_EXCESSIVE,
1313 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1314 __func__, phy, (uint16_t)(reg & 0xffff),
1315 (uint16_t)(val & 0xffff));
1317 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1318 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1319 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1321 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1322 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1327 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1328 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1329 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1330 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1332 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1335 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1336 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1342 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1343 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1345 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1346 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1347 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1349 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1350 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1358 /****************************************************************************/
1359 /* MII bus status change. */
1361 /* Called by the MII bus driver when the PHY establishes link to set the */
1362 /* MAC interface registers. */
1366 /****************************************************************************/
1368 bce_miibus_statchg(device_t dev)
1370 struct bce_softc *sc = device_get_softc(dev);
1371 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1373 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1374 mii->mii_media_active);
1377 /* Decode the interface media flags. */
1378 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1379 switch(IFM_TYPE(mii->mii_media_active)) {
1381 kprintf("Ethernet )");
1384 kprintf("Unknown )");
1388 kprintf(" Media Options: ( ");
1389 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1391 kprintf("Autoselect )");
1394 kprintf("Manual )");
1400 kprintf("10Base-T )");
1403 kprintf("100Base-TX )");
1406 kprintf("1000Base-SX )");
1409 kprintf("1000Base-T )");
1416 kprintf(" Global Options: (");
1417 if (mii->mii_media_active & IFM_FDX)
1418 kprintf(" FullDuplex");
1419 if (mii->mii_media_active & IFM_HDX)
1420 kprintf(" HalfDuplex");
1421 if (mii->mii_media_active & IFM_LOOP)
1422 kprintf(" Loopback");
1423 if (mii->mii_media_active & IFM_FLAG0)
1425 if (mii->mii_media_active & IFM_FLAG1)
1427 if (mii->mii_media_active & IFM_FLAG2)
1432 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1435 * Set MII or GMII interface based on the speed negotiated
1438 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1439 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1440 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1441 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1443 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1444 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1448 * Set half or full duplex based on the duplicity negotiated
1451 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1452 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1453 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1455 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1456 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1461 /****************************************************************************/
1462 /* Acquire NVRAM lock. */
1464 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1465 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1466 /* for use by the driver. */
1469 /* 0 on success, positive value on failure. */
1470 /****************************************************************************/
1472 bce_acquire_nvram_lock(struct bce_softc *sc)
1477 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1479 /* Request access to the flash interface. */
1480 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1481 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1482 val = REG_RD(sc, BCE_NVM_SW_ARB);
1483 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1489 if (j >= NVRAM_TIMEOUT_COUNT) {
1490 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1497 /****************************************************************************/
1498 /* Release NVRAM lock. */
1500 /* When the caller is finished accessing NVRAM the lock must be released. */
1501 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1502 /* for use by the driver. */
1505 /* 0 on success, positive value on failure. */
1506 /****************************************************************************/
1508 bce_release_nvram_lock(struct bce_softc *sc)
1513 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1516 * Relinquish nvram interface.
1518 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1520 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1521 val = REG_RD(sc, BCE_NVM_SW_ARB);
1522 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1528 if (j >= NVRAM_TIMEOUT_COUNT) {
1529 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1536 /****************************************************************************/
1537 /* Enable NVRAM access. */
1539 /* Before accessing NVRAM for read or write operations the caller must */
1540 /* enabled NVRAM access. */
1544 /****************************************************************************/
1546 bce_enable_nvram_access(struct bce_softc *sc)
1550 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1552 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1553 /* Enable both bits, even on read. */
1554 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1555 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1559 /****************************************************************************/
1560 /* Disable NVRAM access. */
1562 /* When the caller is finished accessing NVRAM access must be disabled. */
1566 /****************************************************************************/
1568 bce_disable_nvram_access(struct bce_softc *sc)
1572 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1574 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1576 /* Disable both bits, even after read. */
1577 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1578 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1582 /****************************************************************************/
1583 /* Read a dword (32 bits) from NVRAM. */
1585 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1586 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1589 /* 0 on success and the 32 bit value read, positive value on failure. */
1590 /****************************************************************************/
1592 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1598 /* Build the command word. */
1599 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1601 /* Calculate the offset for buffered flash. */
1602 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1603 offset = ((offset / sc->bce_flash_info->page_size) <<
1604 sc->bce_flash_info->page_bits) +
1605 (offset % sc->bce_flash_info->page_size);
1609 * Clear the DONE bit separately, set the address to read,
1610 * and issue the read.
1612 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1613 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1614 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1616 /* Wait for completion. */
1617 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1622 val = REG_RD(sc, BCE_NVM_COMMAND);
1623 if (val & BCE_NVM_COMMAND_DONE) {
1624 val = REG_RD(sc, BCE_NVM_READ);
1627 memcpy(ret_val, &val, 4);
1632 /* Check for errors. */
1633 if (i >= NVRAM_TIMEOUT_COUNT) {
1634 if_printf(&sc->arpcom.ac_if,
1635 "Timeout error reading NVRAM at offset 0x%08X!\n",
1643 /****************************************************************************/
1644 /* Initialize NVRAM access. */
1646 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1647 /* access that device. */
1650 /* 0 on success, positive value on failure. */
1651 /****************************************************************************/
1653 bce_init_nvram(struct bce_softc *sc)
1656 int j, entry_count, rc = 0;
1657 const struct flash_spec *flash;
1659 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1661 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1662 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1663 sc->bce_flash_info = &flash_5709;
1664 goto bce_init_nvram_get_flash_size;
1667 /* Determine the selected interface. */
1668 val = REG_RD(sc, BCE_NVM_CFG1);
1670 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1673 * Flash reconfiguration is required to support additional
1674 * NVRAM devices not directly supported in hardware.
1675 * Check if the flash interface was reconfigured
1679 if (val & 0x40000000) {
1680 /* Flash interface reconfigured by bootcode. */
1682 DBPRINT(sc, BCE_INFO_LOAD,
1683 "%s(): Flash WAS reconfigured.\n", __func__);
1685 for (j = 0, flash = flash_table; j < entry_count;
1687 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1688 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1689 sc->bce_flash_info = flash;
1694 /* Flash interface not yet reconfigured. */
1697 DBPRINT(sc, BCE_INFO_LOAD,
1698 "%s(): Flash was NOT reconfigured.\n", __func__);
1700 if (val & (1 << 23))
1701 mask = FLASH_BACKUP_STRAP_MASK;
1703 mask = FLASH_STRAP_MASK;
1705 /* Look for the matching NVRAM device configuration data. */
1706 for (j = 0, flash = flash_table; j < entry_count;
1708 /* Check if the device matches any of the known devices. */
1709 if ((val & mask) == (flash->strapping & mask)) {
1710 /* Found a device match. */
1711 sc->bce_flash_info = flash;
1713 /* Request access to the flash interface. */
1714 rc = bce_acquire_nvram_lock(sc);
1718 /* Reconfigure the flash interface. */
1719 bce_enable_nvram_access(sc);
1720 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1721 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1722 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1723 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1724 bce_disable_nvram_access(sc);
1725 bce_release_nvram_lock(sc);
1731 /* Check if a matching device was found. */
1732 if (j == entry_count) {
1733 sc->bce_flash_info = NULL;
1734 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1738 bce_init_nvram_get_flash_size:
1739 /* Write the flash config data to the shared memory interface. */
1740 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1741 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1743 sc->bce_flash_size = val;
1745 sc->bce_flash_size = sc->bce_flash_info->total_size;
1747 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1748 __func__, sc->bce_flash_info->total_size);
1750 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1756 /****************************************************************************/
1757 /* Read an arbitrary range of data from NVRAM. */
1759 /* Prepares the NVRAM interface for access and reads the requested data */
1760 /* into the supplied buffer. */
1763 /* 0 on success and the data read, positive value on failure. */
1764 /****************************************************************************/
1766 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1769 uint32_t cmd_flags, offset32, len32, extra;
1775 /* Request access to the flash interface. */
1776 rc = bce_acquire_nvram_lock(sc);
1780 /* Enable access to flash interface */
1781 bce_enable_nvram_access(sc);
1789 /* XXX should we release nvram lock if read_dword() fails? */
1795 pre_len = 4 - (offset & 3);
1797 if (pre_len >= len32) {
1799 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1801 cmd_flags = BCE_NVM_COMMAND_FIRST;
1804 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1808 memcpy(ret_buf, buf + (offset & 3), pre_len);
1816 extra = 4 - (len32 & 3);
1817 len32 = (len32 + 4) & ~3;
1824 cmd_flags = BCE_NVM_COMMAND_LAST;
1826 cmd_flags = BCE_NVM_COMMAND_FIRST |
1827 BCE_NVM_COMMAND_LAST;
1829 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1831 memcpy(ret_buf, buf, 4 - extra);
1832 } else if (len32 > 0) {
1835 /* Read the first word. */
1839 cmd_flags = BCE_NVM_COMMAND_FIRST;
1841 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1843 /* Advance to the next dword. */
1848 while (len32 > 4 && rc == 0) {
1849 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1851 /* Advance to the next dword. */
1858 goto bce_nvram_read_locked_exit;
1860 cmd_flags = BCE_NVM_COMMAND_LAST;
1861 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1863 memcpy(ret_buf, buf, 4 - extra);
1866 bce_nvram_read_locked_exit:
1867 /* Disable access to flash interface and release the lock. */
1868 bce_disable_nvram_access(sc);
1869 bce_release_nvram_lock(sc);
1875 /****************************************************************************/
1876 /* Verifies that NVRAM is accessible and contains valid data. */
1878 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1882 /* 0 on success, positive value on failure. */
1883 /****************************************************************************/
1885 bce_nvram_test(struct bce_softc *sc)
1887 uint32_t buf[BCE_NVRAM_SIZE / 4];
1888 uint32_t magic, csum;
1889 uint8_t *data = (uint8_t *)buf;
1893 * Check that the device NVRAM is valid by reading
1894 * the magic value at offset 0.
1896 rc = bce_nvram_read(sc, 0, data, 4);
1900 magic = be32toh(buf[0]);
1901 if (magic != BCE_NVRAM_MAGIC) {
1902 if_printf(&sc->arpcom.ac_if,
1903 "Invalid NVRAM magic value! Expected: 0x%08X, "
1904 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1909 * Verify that the device NVRAM includes valid
1910 * configuration data.
1912 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1916 csum = ether_crc32_le(data, 0x100);
1917 if (csum != BCE_CRC32_RESIDUAL) {
1918 if_printf(&sc->arpcom.ac_if,
1919 "Invalid Manufacturing Information NVRAM CRC! "
1920 "Expected: 0x%08X, Found: 0x%08X\n",
1921 BCE_CRC32_RESIDUAL, csum);
1925 csum = ether_crc32_le(data + 0x100, 0x100);
1926 if (csum != BCE_CRC32_RESIDUAL) {
1927 if_printf(&sc->arpcom.ac_if,
1928 "Invalid Feature Configuration Information "
1929 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1930 BCE_CRC32_RESIDUAL, csum);
1937 /****************************************************************************/
1938 /* Identifies the current media type of the controller and sets the PHY */
1943 /****************************************************************************/
1945 bce_get_media(struct bce_softc *sc)
1949 sc->bce_phy_addr = 1;
1951 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1952 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1953 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1954 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1958 * The BCM5709S is software configurable
1959 * for Copper or SerDes operation.
1961 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1963 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1964 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1968 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1969 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1972 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1975 if (pci_get_function(sc->bce_dev) == 0) {
1980 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1988 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1992 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1993 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1996 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1997 sc->bce_flags |= BCE_NO_WOL_FLAG;
1998 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1999 sc->bce_phy_addr = 2;
2000 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2001 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2002 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2004 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2005 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2006 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2011 /****************************************************************************/
2012 /* Free any DMA memory owned by the driver. */
2014 /* Scans through each data structre that requires DMA memory and frees */
2015 /* the memory if allocated. */
2019 /****************************************************************************/
2021 bce_dma_free(struct bce_softc *sc)
2025 /* Destroy the status block. */
2026 if (sc->status_tag != NULL) {
2027 if (sc->status_block != NULL) {
2028 bus_dmamap_unload(sc->status_tag, sc->status_map);
2029 bus_dmamem_free(sc->status_tag, sc->status_block,
2032 bus_dma_tag_destroy(sc->status_tag);
2036 /* Destroy the statistics block. */
2037 if (sc->stats_tag != NULL) {
2038 if (sc->stats_block != NULL) {
2039 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2040 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2043 bus_dma_tag_destroy(sc->stats_tag);
2046 /* Destroy the CTX DMA stuffs. */
2047 if (sc->ctx_tag != NULL) {
2048 for (i = 0; i < sc->ctx_pages; i++) {
2049 if (sc->ctx_block[i] != NULL) {
2050 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2051 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2055 bus_dma_tag_destroy(sc->ctx_tag);
2058 /* Destroy the TX buffer descriptor DMA stuffs. */
2059 if (sc->tx_bd_chain_tag != NULL) {
2060 for (i = 0; i < TX_PAGES; i++) {
2061 if (sc->tx_bd_chain[i] != NULL) {
2062 bus_dmamap_unload(sc->tx_bd_chain_tag,
2063 sc->tx_bd_chain_map[i]);
2064 bus_dmamem_free(sc->tx_bd_chain_tag,
2066 sc->tx_bd_chain_map[i]);
2069 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2072 /* Destroy the RX buffer descriptor DMA stuffs. */
2073 if (sc->rx_bd_chain_tag != NULL) {
2074 for (i = 0; i < RX_PAGES; i++) {
2075 if (sc->rx_bd_chain[i] != NULL) {
2076 bus_dmamap_unload(sc->rx_bd_chain_tag,
2077 sc->rx_bd_chain_map[i]);
2078 bus_dmamem_free(sc->rx_bd_chain_tag,
2080 sc->rx_bd_chain_map[i]);
2083 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2086 /* Destroy the TX mbuf DMA stuffs. */
2087 if (sc->tx_mbuf_tag != NULL) {
2088 for (i = 0; i < TOTAL_TX_BD; i++) {
2089 /* Must have been unloaded in bce_stop() */
2090 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2091 bus_dmamap_destroy(sc->tx_mbuf_tag,
2092 sc->tx_mbuf_map[i]);
2094 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2097 /* Destroy the RX mbuf DMA stuffs. */
2098 if (sc->rx_mbuf_tag != NULL) {
2099 for (i = 0; i < TOTAL_RX_BD; i++) {
2100 /* Must have been unloaded in bce_stop() */
2101 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2102 bus_dmamap_destroy(sc->rx_mbuf_tag,
2103 sc->rx_mbuf_map[i]);
2105 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2106 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2109 /* Destroy the parent tag */
2110 if (sc->parent_tag != NULL)
2111 bus_dma_tag_destroy(sc->parent_tag);
2115 /****************************************************************************/
2116 /* Get DMA memory from the OS. */
2118 /* Validates that the OS has provided DMA buffers in response to a */
2119 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2120 /* When the callback is used the OS will return 0 for the mapping function */
2121 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2122 /* failures back to the caller. */
2126 /****************************************************************************/
2128 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2130 bus_addr_t *busaddr = arg;
2133 * Simulate a mapping failure.
2136 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2137 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2138 __FILE__, __LINE__);
2141 /* Check for an error and signal the caller that an error occurred. */
2145 KASSERT(nseg == 1, ("only one segment is allowed"));
2146 *busaddr = segs->ds_addr;
2150 /****************************************************************************/
2151 /* Allocate any DMA memory needed by the driver. */
2153 /* Allocates DMA memory needed for the various global structures needed by */
2156 /* Memory alignment requirements: */
2157 /* -----------------+----------+----------+----------+----------+ */
2158 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2159 /* -----------------+----------+----------+----------+----------+ */
2160 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2161 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2162 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2163 /* PG Buffers | none | none | none | none | */
2164 /* TX Buffers | none | none | none | none | */
2165 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2166 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2167 /* -----------------+----------+----------+----------+----------+ */
2169 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2172 /* 0 for success, positive value for failure. */
2173 /****************************************************************************/
2175 bce_dma_alloc(struct bce_softc *sc)
2177 struct ifnet *ifp = &sc->arpcom.ac_if;
2179 bus_addr_t busaddr, max_busaddr;
2180 bus_size_t status_align, stats_align;
2183 * The embedded PCIe to PCI-X bridge (EPB)
2184 * in the 5708 cannot address memory above
2185 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2187 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2188 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2190 max_busaddr = BUS_SPACE_MAXADDR;
2193 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2195 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2196 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2197 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2198 if (sc->ctx_pages == 0)
2200 if (sc->ctx_pages > BCE_CTX_PAGES) {
2201 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2213 * Allocate the parent bus DMA tag appropriate for PCI.
2215 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2216 max_busaddr, BUS_SPACE_MAXADDR,
2218 BUS_SPACE_MAXSIZE_32BIT, 0,
2219 BUS_SPACE_MAXSIZE_32BIT,
2220 0, &sc->parent_tag);
2222 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2227 * Allocate status block.
2229 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2230 status_align, BCE_STATUS_BLK_SZ,
2231 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2232 &sc->status_tag, &sc->status_map,
2233 &sc->status_block_paddr);
2234 if (sc->status_block == NULL) {
2235 if_printf(ifp, "Could not allocate status block!\n");
2240 * Allocate statistics block.
2242 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2243 stats_align, BCE_STATS_BLK_SZ,
2244 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2245 &sc->stats_tag, &sc->stats_map,
2246 &sc->stats_block_paddr);
2247 if (sc->stats_block == NULL) {
2248 if_printf(ifp, "Could not allocate statistics block!\n");
2253 * Allocate context block, if needed
2255 if (sc->ctx_pages != 0) {
2256 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2257 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2259 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2262 if_printf(ifp, "Could not allocate "
2263 "context block DMA tag!\n");
2267 for (i = 0; i < sc->ctx_pages; i++) {
2268 rc = bus_dmamem_alloc(sc->ctx_tag,
2269 (void **)&sc->ctx_block[i],
2270 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2274 if_printf(ifp, "Could not allocate %dth context "
2275 "DMA memory!\n", i);
2279 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2280 sc->ctx_block[i], BCM_PAGE_SIZE,
2281 bce_dma_map_addr, &busaddr,
2284 if (rc == EINPROGRESS) {
2285 panic("%s coherent memory loading "
2286 "is still in progress!", ifp->if_xname);
2288 if_printf(ifp, "Could not map %dth context "
2289 "DMA memory!\n", i);
2290 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2292 sc->ctx_block[i] = NULL;
2295 sc->ctx_paddr[i] = busaddr;
2300 * Create a DMA tag for the TX buffer descriptor chain,
2301 * allocate and clear the memory, and fetch the
2302 * physical address of the block.
2304 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2305 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2307 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2308 0, &sc->tx_bd_chain_tag);
2310 if_printf(ifp, "Could not allocate "
2311 "TX descriptor chain DMA tag!\n");
2315 for (i = 0; i < TX_PAGES; i++) {
2316 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2317 (void **)&sc->tx_bd_chain[i],
2318 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2320 &sc->tx_bd_chain_map[i]);
2322 if_printf(ifp, "Could not allocate %dth TX descriptor "
2323 "chain DMA memory!\n", i);
2327 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2328 sc->tx_bd_chain_map[i],
2329 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2330 bce_dma_map_addr, &busaddr,
2333 if (rc == EINPROGRESS) {
2334 panic("%s coherent memory loading "
2335 "is still in progress!", ifp->if_xname);
2337 if_printf(ifp, "Could not map %dth TX descriptor "
2338 "chain DMA memory!\n", i);
2339 bus_dmamem_free(sc->tx_bd_chain_tag,
2341 sc->tx_bd_chain_map[i]);
2342 sc->tx_bd_chain[i] = NULL;
2346 sc->tx_bd_chain_paddr[i] = busaddr;
2347 /* DRC - Fix for 64 bit systems. */
2348 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2349 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2352 /* Create a DMA tag for TX mbufs. */
2353 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2354 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2356 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2357 BCE_MAX_SEGMENTS, MCLBYTES,
2358 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2362 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2366 /* Create DMA maps for the TX mbufs clusters. */
2367 for (i = 0; i < TOTAL_TX_BD; i++) {
2368 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2369 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2370 &sc->tx_mbuf_map[i]);
2372 for (j = 0; j < i; ++j) {
2373 bus_dmamap_destroy(sc->tx_mbuf_tag,
2374 sc->tx_mbuf_map[i]);
2376 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2377 sc->tx_mbuf_tag = NULL;
2379 if_printf(ifp, "Unable to create "
2380 "%dth TX mbuf DMA map!\n", i);
2386 * Create a DMA tag for the RX buffer descriptor chain,
2387 * allocate and clear the memory, and fetch the physical
2388 * address of the blocks.
2390 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2391 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2393 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2394 0, &sc->rx_bd_chain_tag);
2396 if_printf(ifp, "Could not allocate "
2397 "RX descriptor chain DMA tag!\n");
2401 for (i = 0; i < RX_PAGES; i++) {
2402 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2403 (void **)&sc->rx_bd_chain[i],
2404 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2406 &sc->rx_bd_chain_map[i]);
2408 if_printf(ifp, "Could not allocate %dth RX descriptor "
2409 "chain DMA memory!\n", i);
2413 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2414 sc->rx_bd_chain_map[i],
2415 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2416 bce_dma_map_addr, &busaddr,
2419 if (rc == EINPROGRESS) {
2420 panic("%s coherent memory loading "
2421 "is still in progress!", ifp->if_xname);
2423 if_printf(ifp, "Could not map %dth RX descriptor "
2424 "chain DMA memory!\n", i);
2425 bus_dmamem_free(sc->rx_bd_chain_tag,
2427 sc->rx_bd_chain_map[i]);
2428 sc->rx_bd_chain[i] = NULL;
2432 sc->rx_bd_chain_paddr[i] = busaddr;
2433 /* DRC - Fix for 64 bit systems. */
2434 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2435 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2438 /* Create a DMA tag for RX mbufs. */
2439 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2440 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2442 MCLBYTES, 1, MCLBYTES,
2443 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2447 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2451 /* Create tmp DMA map for RX mbuf clusters. */
2452 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2453 &sc->rx_mbuf_tmpmap);
2455 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2456 sc->rx_mbuf_tag = NULL;
2458 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2462 /* Create DMA maps for the RX mbuf clusters. */
2463 for (i = 0; i < TOTAL_RX_BD; i++) {
2464 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2465 &sc->rx_mbuf_map[i]);
2467 for (j = 0; j < i; ++j) {
2468 bus_dmamap_destroy(sc->rx_mbuf_tag,
2469 sc->rx_mbuf_map[j]);
2471 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2472 sc->rx_mbuf_tag = NULL;
2474 if_printf(ifp, "Unable to create "
2475 "%dth RX mbuf DMA map!\n", i);
2483 /****************************************************************************/
2484 /* Firmware synchronization. */
2486 /* Before performing certain events such as a chip reset, synchronize with */
2487 /* the firmware first. */
2490 /* 0 for success, positive value for failure. */
2491 /****************************************************************************/
2493 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2498 /* Don't waste any time if we've timed out before. */
2499 if (sc->bce_fw_timed_out)
2502 /* Increment the message sequence number. */
2503 sc->bce_fw_wr_seq++;
2504 msg_data |= sc->bce_fw_wr_seq;
2506 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2508 /* Send the message to the bootcode driver mailbox. */
2509 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2511 /* Wait for the bootcode to acknowledge the message. */
2512 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2513 /* Check for a response in the bootcode firmware mailbox. */
2514 val = bce_shmem_rd(sc, BCE_FW_MB);
2515 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2520 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2521 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2522 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2523 if_printf(&sc->arpcom.ac_if,
2524 "Firmware synchronization timeout! "
2525 "msg_data = 0x%08X\n", msg_data);
2527 msg_data &= ~BCE_DRV_MSG_CODE;
2528 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2530 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2532 sc->bce_fw_timed_out = 1;
2539 /****************************************************************************/
2540 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2544 /****************************************************************************/
2546 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2547 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2552 for (i = 0; i < rv2p_code_len; i += 8) {
2553 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2555 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2558 if (rv2p_proc == RV2P_PROC1) {
2559 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2560 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2562 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2563 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2567 /* Reset the processor, un-stall is done later. */
2568 if (rv2p_proc == RV2P_PROC1)
2569 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2571 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2575 /****************************************************************************/
2576 /* Load RISC processor firmware. */
2578 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2579 /* associated with a particular processor. */
2583 /****************************************************************************/
2585 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2591 bce_halt_cpu(sc, cpu_reg);
2593 /* Load the Text area. */
2594 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2596 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2597 REG_WR_IND(sc, offset, fw->text[j]);
2600 /* Load the Data area. */
2601 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2603 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2604 REG_WR_IND(sc, offset, fw->data[j]);
2607 /* Load the SBSS area. */
2608 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2610 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2611 REG_WR_IND(sc, offset, fw->sbss[j]);
2614 /* Load the BSS area. */
2615 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2617 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2618 REG_WR_IND(sc, offset, fw->bss[j]);
2621 /* Load the Read-Only area. */
2622 offset = cpu_reg->spad_base +
2623 (fw->rodata_addr - cpu_reg->mips_view_base);
2625 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2626 REG_WR_IND(sc, offset, fw->rodata[j]);
2629 /* Clear the pre-fetch instruction and set the FW start address. */
2630 REG_WR_IND(sc, cpu_reg->inst, 0);
2631 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2635 /****************************************************************************/
2636 /* Starts the RISC processor. */
2638 /* Assumes the CPU starting address has already been set. */
2642 /****************************************************************************/
2644 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2648 /* Start the CPU. */
2649 val = REG_RD_IND(sc, cpu_reg->mode);
2650 val &= ~cpu_reg->mode_value_halt;
2651 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2652 REG_WR_IND(sc, cpu_reg->mode, val);
2656 /****************************************************************************/
2657 /* Halts the RISC processor. */
2661 /****************************************************************************/
2663 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2668 val = REG_RD_IND(sc, cpu_reg->mode);
2669 val |= cpu_reg->mode_value_halt;
2670 REG_WR_IND(sc, cpu_reg->mode, val);
2671 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2675 /****************************************************************************/
2676 /* Start the RX CPU. */
2680 /****************************************************************************/
2682 bce_start_rxp_cpu(struct bce_softc *sc)
2684 struct cpu_reg cpu_reg;
2686 cpu_reg.mode = BCE_RXP_CPU_MODE;
2687 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2688 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2689 cpu_reg.state = BCE_RXP_CPU_STATE;
2690 cpu_reg.state_value_clear = 0xffffff;
2691 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2692 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2693 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2694 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2695 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2696 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2697 cpu_reg.mips_view_base = 0x8000000;
2699 bce_start_cpu(sc, &cpu_reg);
2703 /****************************************************************************/
2704 /* Initialize the RX CPU. */
2708 /****************************************************************************/
2710 bce_init_rxp_cpu(struct bce_softc *sc)
2712 struct cpu_reg cpu_reg;
2715 cpu_reg.mode = BCE_RXP_CPU_MODE;
2716 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2717 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2718 cpu_reg.state = BCE_RXP_CPU_STATE;
2719 cpu_reg.state_value_clear = 0xffffff;
2720 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2721 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2722 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2723 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2724 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2725 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2726 cpu_reg.mips_view_base = 0x8000000;
2728 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2729 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2730 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2731 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2732 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2733 fw.start_addr = bce_RXP_b09FwStartAddr;
2735 fw.text_addr = bce_RXP_b09FwTextAddr;
2736 fw.text_len = bce_RXP_b09FwTextLen;
2738 fw.text = bce_RXP_b09FwText;
2740 fw.data_addr = bce_RXP_b09FwDataAddr;
2741 fw.data_len = bce_RXP_b09FwDataLen;
2743 fw.data = bce_RXP_b09FwData;
2745 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2746 fw.sbss_len = bce_RXP_b09FwSbssLen;
2748 fw.sbss = bce_RXP_b09FwSbss;
2750 fw.bss_addr = bce_RXP_b09FwBssAddr;
2751 fw.bss_len = bce_RXP_b09FwBssLen;
2753 fw.bss = bce_RXP_b09FwBss;
2755 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2756 fw.rodata_len = bce_RXP_b09FwRodataLen;
2757 fw.rodata_index = 0;
2758 fw.rodata = bce_RXP_b09FwRodata;
2760 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2761 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2762 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2763 fw.start_addr = bce_RXP_b06FwStartAddr;
2765 fw.text_addr = bce_RXP_b06FwTextAddr;
2766 fw.text_len = bce_RXP_b06FwTextLen;
2768 fw.text = bce_RXP_b06FwText;
2770 fw.data_addr = bce_RXP_b06FwDataAddr;
2771 fw.data_len = bce_RXP_b06FwDataLen;
2773 fw.data = bce_RXP_b06FwData;
2775 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2776 fw.sbss_len = bce_RXP_b06FwSbssLen;
2778 fw.sbss = bce_RXP_b06FwSbss;
2780 fw.bss_addr = bce_RXP_b06FwBssAddr;
2781 fw.bss_len = bce_RXP_b06FwBssLen;
2783 fw.bss = bce_RXP_b06FwBss;
2785 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2786 fw.rodata_len = bce_RXP_b06FwRodataLen;
2787 fw.rodata_index = 0;
2788 fw.rodata = bce_RXP_b06FwRodata;
2791 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2792 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2793 /* Delay RXP start until initialization is complete. */
2797 /****************************************************************************/
2798 /* Initialize the TX CPU. */
2802 /****************************************************************************/
2804 bce_init_txp_cpu(struct bce_softc *sc)
2806 struct cpu_reg cpu_reg;
2809 cpu_reg.mode = BCE_TXP_CPU_MODE;
2810 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2811 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2812 cpu_reg.state = BCE_TXP_CPU_STATE;
2813 cpu_reg.state_value_clear = 0xffffff;
2814 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2815 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2816 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2817 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2818 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2819 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2820 cpu_reg.mips_view_base = 0x8000000;
2822 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2823 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2824 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2825 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2826 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2827 fw.start_addr = bce_TXP_b09FwStartAddr;
2829 fw.text_addr = bce_TXP_b09FwTextAddr;
2830 fw.text_len = bce_TXP_b09FwTextLen;
2832 fw.text = bce_TXP_b09FwText;
2834 fw.data_addr = bce_TXP_b09FwDataAddr;
2835 fw.data_len = bce_TXP_b09FwDataLen;
2837 fw.data = bce_TXP_b09FwData;
2839 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2840 fw.sbss_len = bce_TXP_b09FwSbssLen;
2842 fw.sbss = bce_TXP_b09FwSbss;
2844 fw.bss_addr = bce_TXP_b09FwBssAddr;
2845 fw.bss_len = bce_TXP_b09FwBssLen;
2847 fw.bss = bce_TXP_b09FwBss;
2849 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2850 fw.rodata_len = bce_TXP_b09FwRodataLen;
2851 fw.rodata_index = 0;
2852 fw.rodata = bce_TXP_b09FwRodata;
2854 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2855 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2856 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2857 fw.start_addr = bce_TXP_b06FwStartAddr;
2859 fw.text_addr = bce_TXP_b06FwTextAddr;
2860 fw.text_len = bce_TXP_b06FwTextLen;
2862 fw.text = bce_TXP_b06FwText;
2864 fw.data_addr = bce_TXP_b06FwDataAddr;
2865 fw.data_len = bce_TXP_b06FwDataLen;
2867 fw.data = bce_TXP_b06FwData;
2869 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2870 fw.sbss_len = bce_TXP_b06FwSbssLen;
2872 fw.sbss = bce_TXP_b06FwSbss;
2874 fw.bss_addr = bce_TXP_b06FwBssAddr;
2875 fw.bss_len = bce_TXP_b06FwBssLen;
2877 fw.bss = bce_TXP_b06FwBss;
2879 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2880 fw.rodata_len = bce_TXP_b06FwRodataLen;
2881 fw.rodata_index = 0;
2882 fw.rodata = bce_TXP_b06FwRodata;
2885 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2886 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2887 bce_start_cpu(sc, &cpu_reg);
2891 /****************************************************************************/
2892 /* Initialize the TPAT CPU. */
2896 /****************************************************************************/
2898 bce_init_tpat_cpu(struct bce_softc *sc)
2900 struct cpu_reg cpu_reg;
2903 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2904 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2905 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2906 cpu_reg.state = BCE_TPAT_CPU_STATE;
2907 cpu_reg.state_value_clear = 0xffffff;
2908 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2909 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2910 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2911 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2912 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2913 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2914 cpu_reg.mips_view_base = 0x8000000;
2916 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2917 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2918 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2919 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2920 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2921 fw.start_addr = bce_TPAT_b09FwStartAddr;
2923 fw.text_addr = bce_TPAT_b09FwTextAddr;
2924 fw.text_len = bce_TPAT_b09FwTextLen;
2926 fw.text = bce_TPAT_b09FwText;
2928 fw.data_addr = bce_TPAT_b09FwDataAddr;
2929 fw.data_len = bce_TPAT_b09FwDataLen;
2931 fw.data = bce_TPAT_b09FwData;
2933 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2934 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2936 fw.sbss = bce_TPAT_b09FwSbss;
2938 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2939 fw.bss_len = bce_TPAT_b09FwBssLen;
2941 fw.bss = bce_TPAT_b09FwBss;
2943 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2944 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2945 fw.rodata_index = 0;
2946 fw.rodata = bce_TPAT_b09FwRodata;
2948 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2949 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2950 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2951 fw.start_addr = bce_TPAT_b06FwStartAddr;
2953 fw.text_addr = bce_TPAT_b06FwTextAddr;
2954 fw.text_len = bce_TPAT_b06FwTextLen;
2956 fw.text = bce_TPAT_b06FwText;
2958 fw.data_addr = bce_TPAT_b06FwDataAddr;
2959 fw.data_len = bce_TPAT_b06FwDataLen;
2961 fw.data = bce_TPAT_b06FwData;
2963 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2964 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2966 fw.sbss = bce_TPAT_b06FwSbss;
2968 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2969 fw.bss_len = bce_TPAT_b06FwBssLen;
2971 fw.bss = bce_TPAT_b06FwBss;
2973 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2974 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2975 fw.rodata_index = 0;
2976 fw.rodata = bce_TPAT_b06FwRodata;
2979 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2980 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2981 bce_start_cpu(sc, &cpu_reg);
2985 /****************************************************************************/
2986 /* Initialize the CP CPU. */
2990 /****************************************************************************/
2992 bce_init_cp_cpu(struct bce_softc *sc)
2994 struct cpu_reg cpu_reg;
2997 cpu_reg.mode = BCE_CP_CPU_MODE;
2998 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2999 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3000 cpu_reg.state = BCE_CP_CPU_STATE;
3001 cpu_reg.state_value_clear = 0xffffff;
3002 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3003 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3004 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3005 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3006 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3007 cpu_reg.spad_base = BCE_CP_SCRATCH;
3008 cpu_reg.mips_view_base = 0x8000000;
3010 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3011 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3012 fw.ver_major = bce_CP_b09FwReleaseMajor;
3013 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3014 fw.ver_fix = bce_CP_b09FwReleaseFix;
3015 fw.start_addr = bce_CP_b09FwStartAddr;
3017 fw.text_addr = bce_CP_b09FwTextAddr;
3018 fw.text_len = bce_CP_b09FwTextLen;
3020 fw.text = bce_CP_b09FwText;
3022 fw.data_addr = bce_CP_b09FwDataAddr;
3023 fw.data_len = bce_CP_b09FwDataLen;
3025 fw.data = bce_CP_b09FwData;
3027 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3028 fw.sbss_len = bce_CP_b09FwSbssLen;
3030 fw.sbss = bce_CP_b09FwSbss;
3032 fw.bss_addr = bce_CP_b09FwBssAddr;
3033 fw.bss_len = bce_CP_b09FwBssLen;
3035 fw.bss = bce_CP_b09FwBss;
3037 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3038 fw.rodata_len = bce_CP_b09FwRodataLen;
3039 fw.rodata_index = 0;
3040 fw.rodata = bce_CP_b09FwRodata;
3042 fw.ver_major = bce_CP_b06FwReleaseMajor;
3043 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3044 fw.ver_fix = bce_CP_b06FwReleaseFix;
3045 fw.start_addr = bce_CP_b06FwStartAddr;
3047 fw.text_addr = bce_CP_b06FwTextAddr;
3048 fw.text_len = bce_CP_b06FwTextLen;
3050 fw.text = bce_CP_b06FwText;
3052 fw.data_addr = bce_CP_b06FwDataAddr;
3053 fw.data_len = bce_CP_b06FwDataLen;
3055 fw.data = bce_CP_b06FwData;
3057 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3058 fw.sbss_len = bce_CP_b06FwSbssLen;
3060 fw.sbss = bce_CP_b06FwSbss;
3062 fw.bss_addr = bce_CP_b06FwBssAddr;
3063 fw.bss_len = bce_CP_b06FwBssLen;
3065 fw.bss = bce_CP_b06FwBss;
3067 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3068 fw.rodata_len = bce_CP_b06FwRodataLen;
3069 fw.rodata_index = 0;
3070 fw.rodata = bce_CP_b06FwRodata;
3073 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3074 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3075 bce_start_cpu(sc, &cpu_reg);
3079 /****************************************************************************/
3080 /* Initialize the COM CPU. */
3084 /****************************************************************************/
3086 bce_init_com_cpu(struct bce_softc *sc)
3088 struct cpu_reg cpu_reg;
3091 cpu_reg.mode = BCE_COM_CPU_MODE;
3092 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3093 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3094 cpu_reg.state = BCE_COM_CPU_STATE;
3095 cpu_reg.state_value_clear = 0xffffff;
3096 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3097 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3098 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3099 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3100 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3101 cpu_reg.spad_base = BCE_COM_SCRATCH;
3102 cpu_reg.mips_view_base = 0x8000000;
3104 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3105 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3106 fw.ver_major = bce_COM_b09FwReleaseMajor;
3107 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3108 fw.ver_fix = bce_COM_b09FwReleaseFix;
3109 fw.start_addr = bce_COM_b09FwStartAddr;
3111 fw.text_addr = bce_COM_b09FwTextAddr;
3112 fw.text_len = bce_COM_b09FwTextLen;
3114 fw.text = bce_COM_b09FwText;
3116 fw.data_addr = bce_COM_b09FwDataAddr;
3117 fw.data_len = bce_COM_b09FwDataLen;
3119 fw.data = bce_COM_b09FwData;
3121 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3122 fw.sbss_len = bce_COM_b09FwSbssLen;
3124 fw.sbss = bce_COM_b09FwSbss;
3126 fw.bss_addr = bce_COM_b09FwBssAddr;
3127 fw.bss_len = bce_COM_b09FwBssLen;
3129 fw.bss = bce_COM_b09FwBss;
3131 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3132 fw.rodata_len = bce_COM_b09FwRodataLen;
3133 fw.rodata_index = 0;
3134 fw.rodata = bce_COM_b09FwRodata;
3136 fw.ver_major = bce_COM_b06FwReleaseMajor;
3137 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3138 fw.ver_fix = bce_COM_b06FwReleaseFix;
3139 fw.start_addr = bce_COM_b06FwStartAddr;
3141 fw.text_addr = bce_COM_b06FwTextAddr;
3142 fw.text_len = bce_COM_b06FwTextLen;
3144 fw.text = bce_COM_b06FwText;
3146 fw.data_addr = bce_COM_b06FwDataAddr;
3147 fw.data_len = bce_COM_b06FwDataLen;
3149 fw.data = bce_COM_b06FwData;
3151 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3152 fw.sbss_len = bce_COM_b06FwSbssLen;
3154 fw.sbss = bce_COM_b06FwSbss;
3156 fw.bss_addr = bce_COM_b06FwBssAddr;
3157 fw.bss_len = bce_COM_b06FwBssLen;
3159 fw.bss = bce_COM_b06FwBss;
3161 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3162 fw.rodata_len = bce_COM_b06FwRodataLen;
3163 fw.rodata_index = 0;
3164 fw.rodata = bce_COM_b06FwRodata;
3167 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3168 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3169 bce_start_cpu(sc, &cpu_reg);
3173 /****************************************************************************/
3174 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3176 /* Loads the firmware for each CPU and starts the CPU. */
3180 /****************************************************************************/
3182 bce_init_cpus(struct bce_softc *sc)
3184 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3185 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3186 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3187 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3188 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3189 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3190 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3192 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3193 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3194 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3195 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3198 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3199 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3200 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3201 sizeof(bce_rv2p_proc2), RV2P_PROC2);
3204 bce_init_rxp_cpu(sc);
3205 bce_init_txp_cpu(sc);
3206 bce_init_tpat_cpu(sc);
3207 bce_init_com_cpu(sc);
3208 bce_init_cp_cpu(sc);
3212 /****************************************************************************/
3213 /* Initialize context memory. */
3215 /* Clears the memory associated with each Context ID (CID). */
3219 /****************************************************************************/
3221 bce_init_ctx(struct bce_softc *sc)
3223 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3224 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3225 /* DRC: Replace this constant value with a #define. */
3226 int i, retry_cnt = 10;
3230 * BCM5709 context memory may be cached
3231 * in host memory so prepare the host memory
3234 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3236 val |= (BCM_PAGE_BITS - 8) << 16;
3237 REG_WR(sc, BCE_CTX_COMMAND, val);
3239 /* Wait for mem init command to complete. */
3240 for (i = 0; i < retry_cnt; i++) {
3241 val = REG_RD(sc, BCE_CTX_COMMAND);
3242 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3246 if (i == retry_cnt) {
3247 device_printf(sc->bce_dev,
3248 "Context memory initialization failed!\n");
3252 for (i = 0; i < sc->ctx_pages; i++) {
3256 * Set the physical address of the context
3259 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3260 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3261 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3262 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3263 BCE_ADDR_HI(sc->ctx_paddr[i]));
3264 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3265 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3268 * Verify that the context memory write was successful.
3270 for (j = 0; j < retry_cnt; j++) {
3271 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3273 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3277 if (j == retry_cnt) {
3278 device_printf(sc->bce_dev,
3279 "Failed to initialize context page!\n");
3284 uint32_t vcid_addr, offset;
3287 * For the 5706/5708, context memory is local to
3288 * the controller, so initialize the controller
3292 vcid_addr = GET_CID_ADDR(96);
3294 vcid_addr -= PHY_CTX_SIZE;
3296 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3297 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3299 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3300 CTX_WR(sc, 0x00, offset, 0);
3302 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3303 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3310 /****************************************************************************/
3311 /* Fetch the permanent MAC address of the controller. */
3315 /****************************************************************************/
3317 bce_get_mac_addr(struct bce_softc *sc)
3319 uint32_t mac_lo = 0, mac_hi = 0;
3322 * The NetXtreme II bootcode populates various NIC
3323 * power-on and runtime configuration items in a
3324 * shared memory area. The factory configured MAC
3325 * address is available from both NVRAM and the
3326 * shared memory area so we'll read the value from
3327 * shared memory for speed.
3330 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3331 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3333 if (mac_lo == 0 && mac_hi == 0) {
3334 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3336 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3337 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3338 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3339 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3340 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3341 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3344 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3348 /****************************************************************************/
3349 /* Program the MAC address. */
3353 /****************************************************************************/
3355 bce_set_mac_addr(struct bce_softc *sc)
3357 const uint8_t *mac_addr = sc->eaddr;
3360 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3363 val = (mac_addr[0] << 8) | mac_addr[1];
3364 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3366 val = (mac_addr[2] << 24) |
3367 (mac_addr[3] << 16) |
3368 (mac_addr[4] << 8) |
3370 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3374 /****************************************************************************/
3375 /* Stop the controller. */
3379 /****************************************************************************/
3381 bce_stop(struct bce_softc *sc)
3383 struct ifnet *ifp = &sc->arpcom.ac_if;
3385 ASSERT_SERIALIZED(ifp->if_serializer);
3387 callout_stop(&sc->bce_tick_callout);
3389 /* Disable the transmit/receive blocks. */
3390 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3391 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3394 bce_disable_intr(sc);
3396 /* Free the RX lists. */
3397 bce_free_rx_chain(sc);
3399 /* Free TX buffers. */
3400 bce_free_tx_chain(sc);
3403 sc->bce_coalchg_mask = 0;
3405 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3411 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3416 /* Wait for pending PCI transactions to complete. */
3417 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3418 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3419 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3420 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3421 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3422 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3426 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3427 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3428 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3429 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3430 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3433 /* Assume bootcode is running. */
3434 sc->bce_fw_timed_out = 0;
3435 sc->bce_drv_cardiac_arrest = 0;
3437 /* Give the firmware a chance to prepare for the reset. */
3438 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3440 if_printf(&sc->arpcom.ac_if,
3441 "Firmware is not ready for reset\n");
3445 /* Set a firmware reminder that this is a soft reset. */
3446 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3447 BCE_DRV_RESET_SIGNATURE_MAGIC);
3449 /* Dummy read to force the chip to complete all current transactions. */
3450 val = REG_RD(sc, BCE_MISC_ID);
3453 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3454 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3455 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3456 REG_RD(sc, BCE_MISC_COMMAND);
3459 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3460 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3462 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3464 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3465 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3466 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3467 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3469 /* Allow up to 30us for reset to complete. */
3470 for (i = 0; i < 10; i++) {
3471 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3472 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3473 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3478 /* Check that reset completed successfully. */
3479 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3480 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3481 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3486 /* Make sure byte swapping is properly configured. */
3487 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3488 if (val != 0x01020304) {
3489 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3493 /* Just completed a reset, assume that firmware is running again. */
3494 sc->bce_fw_timed_out = 0;
3495 sc->bce_drv_cardiac_arrest = 0;
3497 /* Wait for the firmware to finish its initialization. */
3498 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3500 if_printf(&sc->arpcom.ac_if,
3501 "Firmware did not complete initialization!\n");
3508 bce_chipinit(struct bce_softc *sc)
3513 /* Make sure the interrupt is not active. */
3514 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3515 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3518 * Initialize DMA byte/word swapping, configure the number of DMA
3519 * channels and PCI clock compensation delay.
3521 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3522 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3523 #if BYTE_ORDER == BIG_ENDIAN
3524 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3526 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3527 DMA_READ_CHANS << 12 |
3528 DMA_WRITE_CHANS << 16;
3530 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3532 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3533 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3536 * This setting resolves a problem observed on certain Intel PCI
3537 * chipsets that cannot handle multiple outstanding DMA operations.
3538 * See errata E9_5706A1_65.
3540 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3541 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3542 !(sc->bce_flags & BCE_PCIX_FLAG))
3543 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3545 REG_WR(sc, BCE_DMA_CONFIG, val);
3547 /* Enable the RX_V2P and Context state machines before access. */
3548 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3549 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3550 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3551 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3553 /* Initialize context mapping and zero out the quick contexts. */
3554 rc = bce_init_ctx(sc);
3558 /* Initialize the on-boards CPUs */
3561 /* Enable management frames (NC-SI) to flow to the MCP. */
3562 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3563 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3564 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3565 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3568 /* Prepare NVRAM for access. */
3569 rc = bce_init_nvram(sc);
3573 /* Set the kernel bypass block size */
3574 val = REG_RD(sc, BCE_MQ_CONFIG);
3575 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3576 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3578 /* Enable bins used on the 5709/5716. */
3579 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3580 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3581 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3582 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3583 val |= BCE_MQ_CONFIG_HALT_DIS;
3586 REG_WR(sc, BCE_MQ_CONFIG, val);
3588 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3589 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3590 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3592 /* Set the page size and clear the RV2P processor stall bits. */
3593 val = (BCM_PAGE_BITS - 8) << 24;
3594 REG_WR(sc, BCE_RV2P_CONFIG, val);
3596 /* Configure page size. */
3597 val = REG_RD(sc, BCE_TBDR_CONFIG);
3598 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3599 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3600 REG_WR(sc, BCE_TBDR_CONFIG, val);
3602 /* Set the perfect match control register to default. */
3603 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3609 /****************************************************************************/
3610 /* Initialize the controller in preparation to send/receive traffic. */
3613 /* 0 for success, positive value for failure. */
3614 /****************************************************************************/
3616 bce_blockinit(struct bce_softc *sc)
3621 /* Load the hardware default MAC address. */
3622 bce_set_mac_addr(sc);
3624 /* Set the Ethernet backoff seed value */
3625 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3626 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3627 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3629 sc->last_status_idx = 0;
3630 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3632 sc->pulse_check_status_idx = 0xffff;
3634 /* Set up link change interrupt generation. */
3635 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3637 /* Program the physical address of the status block. */
3638 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3639 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3641 /* Program the physical address of the statistics block. */
3642 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3643 BCE_ADDR_LO(sc->stats_block_paddr));
3644 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3645 BCE_ADDR_HI(sc->stats_block_paddr));
3647 /* Program various host coalescing parameters. */
3648 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3649 (sc->bce_tx_quick_cons_trip_int << 16) |
3650 sc->bce_tx_quick_cons_trip);
3651 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3652 (sc->bce_rx_quick_cons_trip_int << 16) |
3653 sc->bce_rx_quick_cons_trip);
3654 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3655 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3656 REG_WR(sc, BCE_HC_TX_TICKS,
3657 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3658 REG_WR(sc, BCE_HC_RX_TICKS,
3659 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3660 REG_WR(sc, BCE_HC_COM_TICKS,
3661 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3662 REG_WR(sc, BCE_HC_CMD_TICKS,
3663 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3664 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3665 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3667 val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3668 if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3670 if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3671 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3673 REG_WR(sc, BCE_HC_CONFIG, val);
3675 /* Clear the internal statistics counters. */
3676 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3678 /* Verify that bootcode is running. */
3679 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3681 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3682 if_printf(&sc->arpcom.ac_if,
3683 "%s(%d): Simulating bootcode failure.\n",
3684 __FILE__, __LINE__);
3687 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3688 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3689 if_printf(&sc->arpcom.ac_if,
3690 "Bootcode not running! Found: 0x%08X, "
3691 "Expected: 08%08X\n",
3692 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3693 BCE_DEV_INFO_SIGNATURE_MAGIC);
3698 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3699 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3700 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3701 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3702 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3705 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3706 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3708 /* Enable link state change interrupt generation. */
3709 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3711 /* Enable the RXP. */
3712 bce_start_rxp_cpu(sc);
3714 /* Disable management frames (NC-SI) from flowing to the MCP. */
3715 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3716 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3717 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3718 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3721 /* Enable all remaining blocks in the MAC. */
3722 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3723 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3724 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3725 BCE_MISC_ENABLE_DEFAULT_XI);
3727 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3729 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3732 /* Save the current host coalescing block settings. */
3733 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3739 /****************************************************************************/
3740 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3742 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3743 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3747 /* 0 for success, positive value for failure. */
3748 /****************************************************************************/
3750 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3751 uint32_t *prod_bseq, int init)
3754 bus_dma_segment_t seg;
3758 uint16_t debug_chain_prod = *chain_prod;
3761 /* Make sure the inputs are valid. */
3762 DBRUNIF((*chain_prod > MAX_RX_BD),
3763 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3764 "RX producer out of range: 0x%04X > 0x%04X\n",
3766 *chain_prod, (uint16_t)MAX_RX_BD));
3768 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3769 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3771 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3772 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3773 "Simulating mbuf allocation failure.\n",
3774 __FILE__, __LINE__);
3775 sc->mbuf_alloc_failed++;
3778 /* This is a new mbuf allocation. */
3779 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3782 DBRUNIF(1, sc->rx_mbuf_alloc++);
3784 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3786 /* Map the mbuf cluster into device memory. */
3787 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3788 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3793 if_printf(&sc->arpcom.ac_if,
3794 "Error mapping mbuf into RX chain!\n");
3796 DBRUNIF(1, sc->rx_mbuf_alloc--);
3800 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3801 bus_dmamap_unload(sc->rx_mbuf_tag,
3802 sc->rx_mbuf_map[*chain_prod]);
3805 map = sc->rx_mbuf_map[*chain_prod];
3806 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3807 sc->rx_mbuf_tmpmap = map;
3809 /* Watch for overflow. */
3810 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3811 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3812 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3813 __FILE__, __LINE__, sc->free_rx_bd,
3814 (uint16_t)USABLE_RX_BD));
3816 /* Update some debug statistic counters */
3817 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3818 sc->rx_low_watermark = sc->free_rx_bd);
3819 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3821 /* Save the mbuf and update our counter. */
3822 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3823 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3826 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3828 DBRUN(BCE_VERBOSE_RECV,
3829 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3831 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3832 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3839 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3845 paddr = sc->rx_mbuf_paddr[chain_prod];
3846 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3848 /* Setup the rx_bd for the first segment. */
3849 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3851 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3852 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3853 rxbd->rx_bd_len = htole32(len);
3854 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3857 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3861 /****************************************************************************/
3862 /* Initialize the TX context memory. */
3866 /****************************************************************************/
3868 bce_init_tx_context(struct bce_softc *sc)
3872 /* Initialize the context ID for an L2 TX chain. */
3873 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3874 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3875 /* Set the CID type to support an L2 connection. */
3876 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3877 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3878 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3879 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3881 /* Point the hardware to the first page in the chain. */
3882 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3883 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3884 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3885 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3886 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3887 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3889 /* Set the CID type to support an L2 connection. */
3890 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3891 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3892 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3893 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3895 /* Point the hardware to the first page in the chain. */
3896 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3897 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3898 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3899 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3900 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3901 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3906 /****************************************************************************/
3907 /* Allocate memory and initialize the TX data structures. */
3910 /* 0 for success, positive value for failure. */
3911 /****************************************************************************/
3913 bce_init_tx_chain(struct bce_softc *sc)
3918 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3920 /* Set the initial TX producer/consumer indices. */
3923 sc->tx_prod_bseq = 0;
3925 sc->max_tx_bd = USABLE_TX_BD;
3926 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3927 DBRUNIF(1, sc->tx_full_count = 0);
3930 * The NetXtreme II supports a linked-list structre called
3931 * a Buffer Descriptor Chain (or BD chain). A BD chain
3932 * consists of a series of 1 or more chain pages, each of which
3933 * consists of a fixed number of BD entries.
3934 * The last BD entry on each page is a pointer to the next page
3935 * in the chain, and the last pointer in the BD chain
3936 * points back to the beginning of the chain.
3939 /* Set the TX next pointer chain entries. */
3940 for (i = 0; i < TX_PAGES; i++) {
3943 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3945 /* Check if we've reached the last page. */
3946 if (i == (TX_PAGES - 1))
3951 txbd->tx_bd_haddr_hi =
3952 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3953 txbd->tx_bd_haddr_lo =
3954 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3956 bce_init_tx_context(sc);
3962 /****************************************************************************/
3963 /* Free memory and clear the TX data structures. */
3967 /****************************************************************************/
3969 bce_free_tx_chain(struct bce_softc *sc)
3973 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3975 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3976 for (i = 0; i < TOTAL_TX_BD; i++) {
3977 if (sc->tx_mbuf_ptr[i] != NULL) {
3978 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3979 m_freem(sc->tx_mbuf_ptr[i]);
3980 sc->tx_mbuf_ptr[i] = NULL;
3981 DBRUNIF(1, sc->tx_mbuf_alloc--);
3985 /* Clear each TX chain page. */
3986 for (i = 0; i < TX_PAGES; i++)
3987 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3990 /* Check if we lost any mbufs in the process. */
3991 DBRUNIF((sc->tx_mbuf_alloc),
3992 if_printf(&sc->arpcom.ac_if,
3993 "%s(%d): Memory leak! "
3994 "Lost %d mbufs from tx chain!\n",
3995 __FILE__, __LINE__, sc->tx_mbuf_alloc));
3997 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4001 /****************************************************************************/
4002 /* Initialize the RX context memory. */
4006 /****************************************************************************/
4008 bce_init_rx_context(struct bce_softc *sc)
4012 /* Initialize the context ID for an L2 RX chain. */
4013 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4014 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4017 * Set the level for generating pause frames
4018 * when the number of available rx_bd's gets
4019 * too low (the low watermark) and the level
4020 * when pause frames can be stopped (the high
4023 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4024 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4025 uint32_t lo_water, hi_water;
4027 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4028 hi_water = USABLE_RX_BD / 4;
4030 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4031 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4035 else if (hi_water == 0)
4038 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4041 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4043 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4044 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4045 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4046 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4047 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4050 /* Point the hardware to the first page in the chain. */
4051 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4052 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4053 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4054 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4058 /****************************************************************************/
4059 /* Allocate memory and initialize the RX data structures. */
4062 /* 0 for success, positive value for failure. */
4063 /****************************************************************************/
4065 bce_init_rx_chain(struct bce_softc *sc)
4069 uint16_t prod, chain_prod;
4072 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4074 /* Initialize the RX producer and consumer indices. */
4077 sc->rx_prod_bseq = 0;
4078 sc->free_rx_bd = USABLE_RX_BD;
4079 sc->max_rx_bd = USABLE_RX_BD;
4080 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
4081 DBRUNIF(1, sc->rx_empty_count = 0);
4083 /* Initialize the RX next pointer chain entries. */
4084 for (i = 0; i < RX_PAGES; i++) {
4087 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4089 /* Check if we've reached the last page. */
4090 if (i == (RX_PAGES - 1))
4095 /* Setup the chain page pointers. */
4096 rxbd->rx_bd_haddr_hi =
4097 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4098 rxbd->rx_bd_haddr_lo =
4099 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4102 /* Allocate mbuf clusters for the rx_bd chain. */
4103 prod = prod_bseq = 0;
4104 while (prod < TOTAL_RX_BD) {
4105 chain_prod = RX_CHAIN_IDX(prod);
4106 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4107 if_printf(&sc->arpcom.ac_if,
4108 "Error filling RX chain: rx_bd[0x%04X]!\n",
4113 prod = NEXT_RX_BD(prod);
4116 /* Save the RX chain producer index. */
4118 sc->rx_prod_bseq = prod_bseq;
4120 /* Tell the chip about the waiting rx_bd's. */
4121 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4123 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4126 bce_init_rx_context(sc);
4132 /****************************************************************************/
4133 /* Free memory and clear the RX data structures. */
4137 /****************************************************************************/
4139 bce_free_rx_chain(struct bce_softc *sc)
4143 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4145 /* Free any mbufs still in the RX mbuf chain. */
4146 for (i = 0; i < TOTAL_RX_BD; i++) {
4147 if (sc->rx_mbuf_ptr[i] != NULL) {
4148 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4149 m_freem(sc->rx_mbuf_ptr[i]);
4150 sc->rx_mbuf_ptr[i] = NULL;
4151 DBRUNIF(1, sc->rx_mbuf_alloc--);
4155 /* Clear each RX chain page. */
4156 for (i = 0; i < RX_PAGES; i++)
4157 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4159 /* Check if we lost any mbufs in the process. */
4160 DBRUNIF((sc->rx_mbuf_alloc),
4161 if_printf(&sc->arpcom.ac_if,
4162 "%s(%d): Memory leak! "
4163 "Lost %d mbufs from rx chain!\n",
4164 __FILE__, __LINE__, sc->rx_mbuf_alloc));
4166 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4170 /****************************************************************************/
4171 /* Set media options. */
4174 /* 0 for success, positive value for failure. */
4175 /****************************************************************************/
4177 bce_ifmedia_upd(struct ifnet *ifp)
4179 struct bce_softc *sc = ifp->if_softc;
4180 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4184 * 'mii' will be NULL, when this function is called on following
4185 * code path: bce_attach() -> bce_mgmt_init()
4188 /* Make sure the MII bus has been enumerated. */
4190 if (mii->mii_instance) {
4191 struct mii_softc *miisc;
4193 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4194 mii_phy_reset(miisc);
4196 error = mii_mediachg(mii);
4202 /****************************************************************************/
4203 /* Reports current media status. */
4207 /****************************************************************************/
4209 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4211 struct bce_softc *sc = ifp->if_softc;
4212 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4215 ifmr->ifm_active = mii->mii_media_active;
4216 ifmr->ifm_status = mii->mii_media_status;
4220 /****************************************************************************/
4221 /* Handles PHY generated interrupt events. */
4225 /****************************************************************************/
4227 bce_phy_intr(struct bce_softc *sc)
4229 uint32_t new_link_state, old_link_state;
4230 struct ifnet *ifp = &sc->arpcom.ac_if;
4232 ASSERT_SERIALIZED(ifp->if_serializer);
4234 new_link_state = sc->status_block->status_attn_bits &
4235 STATUS_ATTN_BITS_LINK_STATE;
4236 old_link_state = sc->status_block->status_attn_bits_ack &
4237 STATUS_ATTN_BITS_LINK_STATE;
4239 /* Handle any changes if the link state has changed. */
4240 if (new_link_state != old_link_state) { /* XXX redundant? */
4241 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4243 /* Update the status_attn_bits_ack field in the status block. */
4244 if (new_link_state) {
4245 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4246 STATUS_ATTN_BITS_LINK_STATE);
4248 if_printf(ifp, "Link is now UP.\n");
4250 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4251 STATUS_ATTN_BITS_LINK_STATE);
4253 if_printf(ifp, "Link is now DOWN.\n");
4257 * Assume link is down and allow tick routine to
4258 * update the state based on the actual media state.
4261 callout_stop(&sc->bce_tick_callout);
4262 bce_tick_serialized(sc);
4265 /* Acknowledge the link change interrupt. */
4266 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4270 /****************************************************************************/
4271 /* Reads the receive consumer value from the status block (skipping over */
4272 /* chain page pointer if necessary). */
4276 /****************************************************************************/
4277 static __inline uint16_t
4278 bce_get_hw_rx_cons(struct bce_softc *sc)
4280 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4282 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4288 /****************************************************************************/
4289 /* Handles received frame interrupt events. */
4293 /****************************************************************************/
4295 bce_rx_intr(struct bce_softc *sc, int count)
4297 struct ifnet *ifp = &sc->arpcom.ac_if;
4298 uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4299 uint32_t sw_prod_bseq;
4301 ASSERT_SERIALIZED(ifp->if_serializer);
4303 DBRUNIF(1, sc->rx_interrupts++);
4305 /* Get the hardware's view of the RX consumer index. */
4306 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4308 /* Get working copies of the driver's view of the RX indices. */
4309 sw_cons = sc->rx_cons;
4310 sw_prod = sc->rx_prod;
4311 sw_prod_bseq = sc->rx_prod_bseq;
4313 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4314 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4315 __func__, sw_prod, sw_cons, sw_prod_bseq);
4317 /* Prevent speculative reads from getting ahead of the status block. */
4318 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4319 BUS_SPACE_BARRIER_READ);
4321 /* Update some debug statistics counters */
4322 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4323 sc->rx_low_watermark = sc->free_rx_bd);
4324 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4326 /* Scan through the receive chain as long as there is work to do. */
4327 while (sw_cons != hw_cons) {
4328 struct mbuf *m = NULL;
4329 struct l2_fhdr *l2fhdr = NULL;
4332 uint32_t status = 0;
4334 #ifdef DEVICE_POLLING
4335 if (count >= 0 && count-- == 0) {
4336 sc->hw_rx_cons = sw_cons;
4342 * Convert the producer/consumer indices
4343 * to an actual rx_bd index.
4345 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4346 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4348 /* Get the used rx_bd. */
4349 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4350 [RX_IDX(sw_chain_cons)];
4353 DBRUN(BCE_VERBOSE_RECV,
4354 if_printf(ifp, "%s(): ", __func__);
4355 bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4357 /* The mbuf is stored with the last rx_bd entry of a packet. */
4358 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4359 /* Validate that this is the last rx_bd. */
4360 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4361 if_printf(ifp, "%s(%d): "
4362 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4363 __FILE__, __LINE__, sw_chain_cons);
4364 bce_breakpoint(sc));
4366 if (sw_chain_cons != sw_chain_prod) {
4367 if_printf(ifp, "RX cons(%d) != prod(%d), "
4368 "drop!\n", sw_chain_cons,
4372 bce_setup_rxdesc_std(sc, sw_chain_cons,
4375 goto bce_rx_int_next_rx;
4378 /* Unmap the mbuf from DMA space. */
4379 bus_dmamap_sync(sc->rx_mbuf_tag,
4380 sc->rx_mbuf_map[sw_chain_cons],
4381 BUS_DMASYNC_POSTREAD);
4383 /* Save the mbuf from the driver's chain. */
4384 m = sc->rx_mbuf_ptr[sw_chain_cons];
4387 * Frames received on the NetXteme II are prepended
4388 * with an l2_fhdr structure which provides status
4389 * information about the received frame (including
4390 * VLAN tags and checksum info). The frames are also
4391 * automatically adjusted to align the IP header
4392 * (i.e. two null bytes are inserted before the
4393 * Ethernet header). As a result the data DMA'd by
4394 * the controller into the mbuf is as follows:
4396 * +---------+-----+---------------------+-----+
4397 * | l2_fhdr | pad | packet data | FCS |
4398 * +---------+-----+---------------------+-----+
4400 * The l2_fhdr needs to be checked and skipped and the
4401 * FCS needs to be stripped before sending the packet
4404 l2fhdr = mtod(m, struct l2_fhdr *);
4406 len = l2fhdr->l2_fhdr_pkt_len;
4407 status = l2fhdr->l2_fhdr_status;
4409 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4411 "Simulating l2_fhdr status error.\n");
4412 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4414 /* Watch for unusual sized frames. */
4415 DBRUNIF((len < BCE_MIN_MTU ||
4416 len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4418 "%s(%d): Unusual frame size found. "
4419 "Min(%d), Actual(%d), Max(%d)\n",
4421 (int)BCE_MIN_MTU, len,
4422 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4423 bce_dump_mbuf(sc, m);
4424 bce_breakpoint(sc));
4426 len -= ETHER_CRC_LEN;
4428 /* Check the received frame for errors. */
4429 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4430 L2_FHDR_ERRORS_PHY_DECODE |
4431 L2_FHDR_ERRORS_ALIGNMENT |
4432 L2_FHDR_ERRORS_TOO_SHORT |
4433 L2_FHDR_ERRORS_GIANT_FRAME)) {
4435 DBRUNIF(1, sc->l2fhdr_status_errors++);
4437 /* Reuse the mbuf for a new frame. */
4438 bce_setup_rxdesc_std(sc, sw_chain_prod,
4441 goto bce_rx_int_next_rx;
4445 * Get a new mbuf for the rx_bd. If no new
4446 * mbufs are available then reuse the current mbuf,
4447 * log an ierror on the interface, and generate
4448 * an error in the system log.
4450 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4451 &sw_prod_bseq, 0)) {
4454 "%s(%d): Failed to allocate new mbuf, "
4455 "incoming frame dropped!\n",
4456 __FILE__, __LINE__));
4460 /* Try and reuse the exisitng mbuf. */
4461 bce_setup_rxdesc_std(sc, sw_chain_prod,
4464 goto bce_rx_int_next_rx;
4468 * Skip over the l2_fhdr when passing
4469 * the data up the stack.
4471 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4473 m->m_pkthdr.len = m->m_len = len;
4474 m->m_pkthdr.rcvif = ifp;
4476 DBRUN(BCE_VERBOSE_RECV,
4477 struct ether_header *eh;
4478 eh = mtod(m, struct ether_header *);
4479 if_printf(ifp, "%s(): to: %6D, from: %6D, "
4480 "type: 0x%04X\n", __func__,
4481 eh->ether_dhost, ":",
4482 eh->ether_shost, ":",
4483 htons(eh->ether_type)));
4485 /* Validate the checksum if offload enabled. */
4486 if (ifp->if_capenable & IFCAP_RXCSUM) {
4487 /* Check for an IP datagram. */
4488 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4489 m->m_pkthdr.csum_flags |=
4492 /* Check if the IP checksum is valid. */
4493 if ((l2fhdr->l2_fhdr_ip_xsum ^
4495 m->m_pkthdr.csum_flags |=
4498 DBPRINT(sc, BCE_WARN_RECV,
4499 "%s(): Invalid IP checksum = 0x%04X!\n",
4500 __func__, l2fhdr->l2_fhdr_ip_xsum);
4504 /* Check for a valid TCP/UDP frame. */
4505 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4506 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4508 /* Check for a good TCP/UDP checksum. */
4510 (L2_FHDR_ERRORS_TCP_XSUM |
4511 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4512 m->m_pkthdr.csum_data =
4513 l2fhdr->l2_fhdr_tcp_udp_xsum;
4514 m->m_pkthdr.csum_flags |=
4518 DBPRINT(sc, BCE_WARN_RECV,
4519 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4520 __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4527 sw_prod = NEXT_RX_BD(sw_prod);
4530 sw_cons = NEXT_RX_BD(sw_cons);
4532 /* If we have a packet, pass it up the stack */
4534 DBPRINT(sc, BCE_VERBOSE_RECV,
4535 "%s(): Passing received frame up.\n", __func__);
4537 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4538 m->m_flags |= M_VLANTAG;
4539 m->m_pkthdr.ether_vlantag =
4540 l2fhdr->l2_fhdr_vlan_tag;
4542 ifp->if_input(ifp, m);
4544 DBRUNIF(1, sc->rx_mbuf_alloc--);
4548 * If polling(4) is not enabled, refresh hw_cons to see
4549 * whether there's new work.
4551 * If polling(4) is enabled, i.e count >= 0, refreshing
4552 * should not be performed, so that we would not spend
4553 * too much time in RX processing.
4555 if (count < 0 && sw_cons == hw_cons)
4556 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4559 * Prevent speculative reads from getting ahead
4560 * of the status block.
4562 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4563 BUS_SPACE_BARRIER_READ);
4566 sc->rx_cons = sw_cons;
4567 sc->rx_prod = sw_prod;
4568 sc->rx_prod_bseq = sw_prod_bseq;
4570 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4572 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4575 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4576 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4577 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4581 /****************************************************************************/
4582 /* Reads the transmit consumer value from the status block (skipping over */
4583 /* chain page pointer if necessary). */
4587 /****************************************************************************/
4588 static __inline uint16_t
4589 bce_get_hw_tx_cons(struct bce_softc *sc)
4591 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4593 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4599 /****************************************************************************/
4600 /* Handles transmit completion interrupt events. */
4604 /****************************************************************************/
4606 bce_tx_intr(struct bce_softc *sc)
4608 struct ifnet *ifp = &sc->arpcom.ac_if;
4609 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4611 ASSERT_SERIALIZED(ifp->if_serializer);
4613 DBRUNIF(1, sc->tx_interrupts++);
4615 /* Get the hardware's view of the TX consumer index. */
4616 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4617 sw_tx_cons = sc->tx_cons;
4619 /* Prevent speculative reads from getting ahead of the status block. */
4620 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4621 BUS_SPACE_BARRIER_READ);
4623 /* Cycle through any completed TX chain page entries. */
4624 while (sw_tx_cons != hw_tx_cons) {
4626 struct tx_bd *txbd = NULL;
4628 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4630 DBPRINT(sc, BCE_INFO_SEND,
4631 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4632 "sw_tx_chain_cons = 0x%04X\n",
4633 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4635 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4636 if_printf(ifp, "%s(%d): "
4637 "TX chain consumer out of range! "
4638 " 0x%04X > 0x%04X\n",
4639 __FILE__, __LINE__, sw_tx_chain_cons,
4641 bce_breakpoint(sc));
4643 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4644 [TX_IDX(sw_tx_chain_cons)]);
4646 DBRUNIF((txbd == NULL),
4647 if_printf(ifp, "%s(%d): "
4648 "Unexpected NULL tx_bd[0x%04X]!\n",
4649 __FILE__, __LINE__, sw_tx_chain_cons);
4650 bce_breakpoint(sc));
4652 DBRUN(BCE_INFO_SEND,
4653 if_printf(ifp, "%s(): ", __func__);
4654 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4657 * Free the associated mbuf. Remember
4658 * that only the last tx_bd of a packet
4659 * has an mbuf pointer and DMA map.
4661 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4662 /* Validate that this is the last tx_bd. */
4663 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4664 if_printf(ifp, "%s(%d): "
4665 "tx_bd END flag not set but "
4666 "txmbuf == NULL!\n", __FILE__, __LINE__);
4667 bce_breakpoint(sc));
4669 DBRUN(BCE_INFO_SEND,
4670 if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4671 "from tx_bd[0x%04X]\n", __func__,
4674 /* Unmap the mbuf. */
4675 bus_dmamap_unload(sc->tx_mbuf_tag,
4676 sc->tx_mbuf_map[sw_tx_chain_cons]);
4678 /* Free the mbuf. */
4679 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4680 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4681 DBRUNIF(1, sc->tx_mbuf_alloc--);
4687 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4689 if (sw_tx_cons == hw_tx_cons) {
4690 /* Refresh hw_cons to see if there's new work. */
4691 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4695 * Prevent speculative reads from getting
4696 * ahead of the status block.
4698 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4699 BUS_SPACE_BARRIER_READ);
4702 if (sc->used_tx_bd == 0) {
4703 /* Clear the TX timeout timer. */
4707 /* Clear the tx hardware queue full flag. */
4708 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4709 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4710 DBPRINT(sc, BCE_WARN_SEND,
4711 "%s(): Open TX chain! %d/%d (used/total)\n",
4712 __func__, sc->used_tx_bd, sc->max_tx_bd));
4713 ifp->if_flags &= ~IFF_OACTIVE;
4715 sc->tx_cons = sw_tx_cons;
4719 /****************************************************************************/
4720 /* Disables interrupt generation. */
4724 /****************************************************************************/
4726 bce_disable_intr(struct bce_softc *sc)
4728 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4729 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4730 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4734 /****************************************************************************/
4735 /* Enables interrupt generation. */
4739 /****************************************************************************/
4741 bce_enable_intr(struct bce_softc *sc, int coal_now)
4743 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4745 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4746 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4747 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4749 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4750 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4753 REG_WR(sc, BCE_HC_COMMAND,
4754 sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4759 /****************************************************************************/
4760 /* Handles controller initialization. */
4764 /****************************************************************************/
4768 struct bce_softc *sc = xsc;
4769 struct ifnet *ifp = &sc->arpcom.ac_if;
4773 ASSERT_SERIALIZED(ifp->if_serializer);
4775 /* Check if the driver is still running and bail out if it is. */
4776 if (ifp->if_flags & IFF_RUNNING)
4781 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4783 if_printf(ifp, "Controller reset failed!\n");
4787 error = bce_chipinit(sc);
4789 if_printf(ifp, "Controller initialization failed!\n");
4793 error = bce_blockinit(sc);
4795 if_printf(ifp, "Block initialization failed!\n");
4799 /* Load our MAC address. */
4800 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4801 bce_set_mac_addr(sc);
4803 /* Calculate and program the Ethernet MTU size. */
4804 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4806 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4809 * Program the mtu, enabling jumbo frame
4810 * support if necessary. Also set the mbuf
4811 * allocation count for RX frames.
4813 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4815 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4816 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4817 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4818 sc->mbuf_alloc_size = MJUM9BYTES;
4820 panic("jumbo buffer is not supported yet");
4823 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4824 sc->mbuf_alloc_size = MCLBYTES;
4827 /* Calculate the RX Ethernet frame size for rx_bd's. */
4828 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4830 DBPRINT(sc, BCE_INFO,
4831 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4832 "max_frame_size = %d\n",
4833 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4834 sc->max_frame_size);
4836 /* Program appropriate promiscuous/multicast filtering. */
4837 bce_set_rx_mode(sc);
4839 /* Init RX buffer descriptor chain. */
4840 bce_init_rx_chain(sc); /* XXX return value */
4842 /* Init TX buffer descriptor chain. */
4843 bce_init_tx_chain(sc); /* XXX return value */
4845 #ifdef DEVICE_POLLING
4846 /* Disable interrupts if we are polling. */
4847 if (ifp->if_flags & IFF_POLLING) {
4848 bce_disable_intr(sc);
4850 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4851 (1 << 16) | sc->bce_rx_quick_cons_trip);
4852 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4853 (1 << 16) | sc->bce_tx_quick_cons_trip);
4856 /* Enable host interrupts. */
4857 bce_enable_intr(sc, 1);
4859 bce_ifmedia_upd(ifp);
4861 ifp->if_flags |= IFF_RUNNING;
4862 ifp->if_flags &= ~IFF_OACTIVE;
4864 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4871 /****************************************************************************/
4872 /* Initialize the controller just enough so that any management firmware */
4873 /* running on the device will continue to operate corectly. */
4877 /****************************************************************************/
4879 bce_mgmt_init(struct bce_softc *sc)
4881 struct ifnet *ifp = &sc->arpcom.ac_if;
4883 /* Bail out if management firmware is not running. */
4884 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4887 /* Enable all critical blocks in the MAC. */
4888 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4889 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4890 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4891 BCE_MISC_ENABLE_DEFAULT_XI);
4893 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4895 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4898 bce_ifmedia_upd(ifp);
4902 /****************************************************************************/
4903 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4904 /* memory visible to the controller. */
4907 /* 0 for success, positive value for failure. */
4908 /****************************************************************************/
4910 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4912 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4913 bus_dmamap_t map, tmp_map;
4914 struct mbuf *m0 = *m_head;
4915 struct tx_bd *txbd = NULL;
4916 uint16_t vlan_tag = 0, flags = 0;
4917 uint16_t chain_prod, chain_prod_start, prod;
4919 int i, error, maxsegs, nsegs;
4921 uint16_t debug_prod;
4924 /* Transfer any checksum offload flags to the bd. */
4925 if (m0->m_pkthdr.csum_flags) {
4926 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4927 flags |= TX_BD_FLAGS_IP_CKSUM;
4928 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4929 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4932 /* Transfer any VLAN tags to the bd. */
4933 if (m0->m_flags & M_VLANTAG) {
4934 flags |= TX_BD_FLAGS_VLAN_TAG;
4935 vlan_tag = m0->m_pkthdr.ether_vlantag;
4939 chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4941 /* Map the mbuf into DMAable memory. */
4942 map = sc->tx_mbuf_map[chain_prod_start];
4944 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4945 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4946 ("not enough segments %d", maxsegs));
4947 if (maxsegs > BCE_MAX_SEGMENTS)
4948 maxsegs = BCE_MAX_SEGMENTS;
4950 /* Map the mbuf into our DMA address space. */
4951 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4952 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4955 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4960 /* prod points to an empty tx_bd at this point. */
4961 prod_bseq = sc->tx_prod_bseq;
4964 debug_prod = chain_prod;
4967 DBPRINT(sc, BCE_INFO_SEND,
4968 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4969 "prod_bseq = 0x%08X\n",
4970 __func__, prod, chain_prod, prod_bseq);
4973 * Cycle through each mbuf segment that makes up
4974 * the outgoing frame, gathering the mapping info
4975 * for that segment and creating a tx_bd to for
4978 for (i = 0; i < nsegs; i++) {
4979 chain_prod = TX_CHAIN_IDX(prod);
4980 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4982 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4983 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4984 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4985 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4986 txbd->tx_bd_flags = htole16(flags);
4987 prod_bseq += segs[i].ds_len;
4989 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4990 prod = NEXT_TX_BD(prod);
4993 /* Set the END flag on the last TX buffer descriptor. */
4994 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4996 DBRUN(BCE_EXCESSIVE_SEND,
4997 bce_dump_tx_chain(sc, debug_prod, nsegs));
4999 DBPRINT(sc, BCE_INFO_SEND,
5000 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
5001 "prod_bseq = 0x%08X\n",
5002 __func__, prod, chain_prod, prod_bseq);
5005 * Ensure that the mbuf pointer for this transmission
5006 * is placed at the array index of the last
5007 * descriptor in this chain. This is done
5008 * because a single map is used for all
5009 * segments of the mbuf and we don't want to
5010 * unload the map before all of the segments
5013 sc->tx_mbuf_ptr[chain_prod] = m0;
5015 tmp_map = sc->tx_mbuf_map[chain_prod];
5016 sc->tx_mbuf_map[chain_prod] = map;
5017 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
5019 sc->used_tx_bd += nsegs;
5021 /* Update some debug statistic counters */
5022 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5023 sc->tx_hi_watermark = sc->used_tx_bd);
5024 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5025 DBRUNIF(1, sc->tx_mbuf_alloc++);
5027 DBRUN(BCE_VERBOSE_SEND,
5028 bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5030 /* prod points to the next free tx_bd at this point. */
5032 sc->tx_prod_bseq = prod_bseq;
5042 /****************************************************************************/
5043 /* Main transmit routine when called from another routine with a lock. */
5047 /****************************************************************************/
5049 bce_start(struct ifnet *ifp)
5051 struct bce_softc *sc = ifp->if_softc;
5054 ASSERT_SERIALIZED(ifp->if_serializer);
5056 /* If there's no link or the transmit queue is empty then just exit. */
5057 if (!sc->bce_link) {
5058 ifq_purge(&ifp->if_snd);
5062 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5065 DBPRINT(sc, BCE_INFO_SEND,
5066 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5067 "tx_prod_bseq = 0x%08X\n",
5069 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5072 struct mbuf *m_head;
5075 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5078 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5079 ifp->if_flags |= IFF_OACTIVE;
5083 /* Check for any frames to send. */
5084 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5089 * Pack the data into the transmit ring. If we
5090 * don't have room, place the mbuf back at the
5091 * head of the queue and set the OACTIVE flag
5092 * to wait for the NIC to drain the chain.
5094 if (bce_encap(sc, &m_head)) {
5096 if (sc->used_tx_bd == 0) {
5099 ifp->if_flags |= IFF_OACTIVE;
5106 /* Send a copy of the frame to any BPF listeners. */
5107 ETHER_BPF_MTAP(ifp, m_head);
5111 /* no packets were dequeued */
5112 DBPRINT(sc, BCE_VERBOSE_SEND,
5113 "%s(): No packets were dequeued\n", __func__);
5117 DBPRINT(sc, BCE_INFO_SEND,
5118 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5119 "tx_prod_bseq = 0x%08X\n",
5121 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
5123 REG_WR(sc, BCE_MQ_COMMAND,
5124 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5126 /* Start the transmit. */
5127 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5128 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5130 /* Set the tx timeout. */
5131 ifp->if_timer = BCE_TX_TIMEOUT;
5135 /****************************************************************************/
5136 /* Handles any IOCTL calls from the operating system. */
5139 /* 0 for success, positive value for failure. */
5140 /****************************************************************************/
5142 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5144 struct bce_softc *sc = ifp->if_softc;
5145 struct ifreq *ifr = (struct ifreq *)data;
5146 struct mii_data *mii;
5147 int mask, error = 0;
5149 ASSERT_SERIALIZED(ifp->if_serializer);
5153 /* Check that the MTU setting is supported. */
5154 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5156 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5158 ifr->ifr_mtu > ETHERMTU
5165 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5167 ifp->if_mtu = ifr->ifr_mtu;
5168 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5173 if (ifp->if_flags & IFF_UP) {
5174 if (ifp->if_flags & IFF_RUNNING) {
5175 mask = ifp->if_flags ^ sc->bce_if_flags;
5177 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5178 bce_set_rx_mode(sc);
5182 } else if (ifp->if_flags & IFF_RUNNING) {
5185 /* If MFW is running, restart the controller a bit. */
5186 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5187 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5192 sc->bce_if_flags = ifp->if_flags;
5197 if (ifp->if_flags & IFF_RUNNING)
5198 bce_set_rx_mode(sc);
5203 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5205 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5207 mii = device_get_softc(sc->bce_miibus);
5208 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5212 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5213 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5216 if (mask & IFCAP_HWCSUM) {
5217 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5218 if (IFCAP_HWCSUM & ifp->if_capenable)
5219 ifp->if_hwassist = BCE_IF_HWASSIST;
5221 ifp->if_hwassist = 0;
5226 error = ether_ioctl(ifp, command, data);
5233 /****************************************************************************/
5234 /* Transmit timeout handler. */
5238 /****************************************************************************/
5240 bce_watchdog(struct ifnet *ifp)
5242 struct bce_softc *sc = ifp->if_softc;
5244 ASSERT_SERIALIZED(ifp->if_serializer);
5246 DBRUN(BCE_VERBOSE_SEND,
5247 bce_dump_driver_state(sc);
5248 bce_dump_status_block(sc));
5251 * If we are in this routine because of pause frames, then
5252 * don't reset the hardware.
5254 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5257 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5259 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5261 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5266 if (!ifq_is_empty(&ifp->if_snd))
5271 #ifdef DEVICE_POLLING
5274 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5276 struct bce_softc *sc = ifp->if_softc;
5277 struct status_block *sblk = sc->status_block;
5278 uint16_t hw_tx_cons, hw_rx_cons;
5280 ASSERT_SERIALIZED(ifp->if_serializer);
5284 bce_disable_intr(sc);
5286 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5287 (1 << 16) | sc->bce_rx_quick_cons_trip);
5288 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5289 (1 << 16) | sc->bce_tx_quick_cons_trip);
5291 case POLL_DEREGISTER:
5292 bce_enable_intr(sc, 1);
5294 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5295 (sc->bce_tx_quick_cons_trip_int << 16) |
5296 sc->bce_tx_quick_cons_trip);
5297 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5298 (sc->bce_rx_quick_cons_trip_int << 16) |
5299 sc->bce_rx_quick_cons_trip);
5305 if (cmd == POLL_AND_CHECK_STATUS) {
5306 uint32_t status_attn_bits;
5308 status_attn_bits = sblk->status_attn_bits;
5310 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5312 "Simulating unexpected status attention bit set.");
5313 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5315 /* Was it a link change interrupt? */
5316 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5317 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5320 /* Clear any transient status updates during link state change. */
5321 REG_WR(sc, BCE_HC_COMMAND,
5322 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5323 REG_RD(sc, BCE_HC_COMMAND);
5326 * If any other attention is asserted then
5327 * the chip is toast.
5329 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5330 (sblk->status_attn_bits_ack &
5331 ~STATUS_ATTN_BITS_LINK_STATE)) {
5332 DBRUN(1, sc->unexpected_attentions++);
5334 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5335 sblk->status_attn_bits);
5338 if (bce_debug_unexpected_attention == 0)
5339 bce_breakpoint(sc));
5346 hw_rx_cons = bce_get_hw_rx_cons(sc);
5347 hw_tx_cons = bce_get_hw_tx_cons(sc);
5349 /* Check for any completed RX frames. */
5350 if (hw_rx_cons != sc->hw_rx_cons)
5351 bce_rx_intr(sc, count);
5353 /* Check for any completed TX frames. */
5354 if (hw_tx_cons != sc->hw_tx_cons)
5357 /* Check for new frames to transmit. */
5358 if (!ifq_is_empty(&ifp->if_snd))
5362 #endif /* DEVICE_POLLING */
5366 * Interrupt handler.
5368 /****************************************************************************/
5369 /* Main interrupt entry point. Verifies that the controller generated the */
5370 /* interrupt and then calls a separate routine for handle the various */
5371 /* interrupt causes (PHY, TX, RX). */
5374 /* 0 for success, positive value for failure. */
5375 /****************************************************************************/
5377 bce_intr(struct bce_softc *sc)
5379 struct ifnet *ifp = &sc->arpcom.ac_if;
5380 struct status_block *sblk;
5381 uint16_t hw_rx_cons, hw_tx_cons;
5383 ASSERT_SERIALIZED(ifp->if_serializer);
5385 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5386 DBRUNIF(1, sc->interrupts_generated++);
5388 sblk = sc->status_block;
5390 /* Check if the hardware has finished any work. */
5391 hw_rx_cons = bce_get_hw_rx_cons(sc);
5392 hw_tx_cons = bce_get_hw_tx_cons(sc);
5394 /* Keep processing data as long as there is work to do. */
5396 uint32_t status_attn_bits;
5398 status_attn_bits = sblk->status_attn_bits;
5400 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5402 "Simulating unexpected status attention bit set.");
5403 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5405 /* Was it a link change interrupt? */
5406 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5407 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5411 * Clear any transient status updates during link state
5414 REG_WR(sc, BCE_HC_COMMAND,
5415 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5416 REG_RD(sc, BCE_HC_COMMAND);
5420 * If any other attention is asserted then
5421 * the chip is toast.
5423 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5424 (sblk->status_attn_bits_ack &
5425 ~STATUS_ATTN_BITS_LINK_STATE)) {
5426 DBRUN(1, sc->unexpected_attentions++);
5428 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5429 sblk->status_attn_bits);
5432 if (bce_debug_unexpected_attention == 0)
5433 bce_breakpoint(sc));
5439 /* Check for any completed RX frames. */
5440 if (hw_rx_cons != sc->hw_rx_cons)
5441 bce_rx_intr(sc, -1);
5443 /* Check for any completed TX frames. */
5444 if (hw_tx_cons != sc->hw_tx_cons)
5448 * Save the status block index value
5449 * for use during the next interrupt.
5451 sc->last_status_idx = sblk->status_idx;
5454 * Prevent speculative reads from getting
5455 * ahead of the status block.
5457 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5458 BUS_SPACE_BARRIER_READ);
5461 * If there's no work left then exit the
5462 * interrupt service routine.
5464 hw_rx_cons = bce_get_hw_rx_cons(sc);
5465 hw_tx_cons = bce_get_hw_tx_cons(sc);
5466 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5470 /* Re-enable interrupts. */
5471 bce_enable_intr(sc, 0);
5473 if (sc->bce_coalchg_mask)
5474 bce_coal_change(sc);
5476 /* Handle any frames that arrived while handling the interrupt. */
5477 if (!ifq_is_empty(&ifp->if_snd))
5482 bce_intr_legacy(void *xsc)
5484 struct bce_softc *sc = xsc;
5485 struct status_block *sblk;
5487 sblk = sc->status_block;
5490 * If the hardware status block index matches the last value
5491 * read by the driver and we haven't asserted our interrupt
5492 * then there's nothing to do.
5494 if (sblk->status_idx == sc->last_status_idx &&
5495 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5496 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5499 /* Ack the interrupt and stop others from occuring. */
5500 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5501 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5502 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5505 * Read back to deassert IRQ immediately to avoid too
5506 * many spurious interrupts.
5508 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5514 bce_intr_msi(void *xsc)
5516 struct bce_softc *sc = xsc;
5518 /* Ack the interrupt and stop others from occuring. */
5519 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5520 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5521 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5527 bce_intr_msi_oneshot(void *xsc)
5533 /****************************************************************************/
5534 /* Programs the various packet receive modes (broadcast and multicast). */
5538 /****************************************************************************/
5540 bce_set_rx_mode(struct bce_softc *sc)
5542 struct ifnet *ifp = &sc->arpcom.ac_if;
5543 struct ifmultiaddr *ifma;
5544 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5545 uint32_t rx_mode, sort_mode;
5548 ASSERT_SERIALIZED(ifp->if_serializer);
5550 /* Initialize receive mode default settings. */
5551 rx_mode = sc->rx_mode &
5552 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5553 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5554 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5557 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5560 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5561 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5562 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5565 * Check for promiscuous, all multicast, or selected
5566 * multicast address filtering.
5568 if (ifp->if_flags & IFF_PROMISC) {
5569 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5571 /* Enable promiscuous mode. */
5572 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5573 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5574 } else if (ifp->if_flags & IFF_ALLMULTI) {
5575 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5577 /* Enable all multicast addresses. */
5578 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5579 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5582 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5584 /* Accept one or more multicast(s). */
5585 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5587 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5588 if (ifma->ifma_addr->sa_family != AF_LINK)
5591 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5592 ETHER_ADDR_LEN) & 0xFF;
5593 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5596 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5597 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5600 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5603 /* Only make changes if the recive mode has actually changed. */
5604 if (rx_mode != sc->rx_mode) {
5605 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5608 sc->rx_mode = rx_mode;
5609 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5612 /* Disable and clear the exisitng sort before enabling a new sort. */
5613 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5614 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5615 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5619 /****************************************************************************/
5620 /* Called periodically to updates statistics from the controllers */
5621 /* statistics block. */
5625 /****************************************************************************/
5627 bce_stats_update(struct bce_softc *sc)
5629 struct ifnet *ifp = &sc->arpcom.ac_if;
5630 struct statistics_block *stats = sc->stats_block;
5632 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5634 ASSERT_SERIALIZED(ifp->if_serializer);
5637 * Certain controllers don't report carrier sense errors correctly.
5638 * See errata E11_5708CA0_1165.
5640 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5641 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5643 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5647 * Update the sysctl statistics from the hardware statistics.
5649 sc->stat_IfHCInOctets =
5650 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5651 (uint64_t)stats->stat_IfHCInOctets_lo;
5653 sc->stat_IfHCInBadOctets =
5654 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5655 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5657 sc->stat_IfHCOutOctets =
5658 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5659 (uint64_t)stats->stat_IfHCOutOctets_lo;
5661 sc->stat_IfHCOutBadOctets =
5662 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5663 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5665 sc->stat_IfHCInUcastPkts =
5666 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5667 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5669 sc->stat_IfHCInMulticastPkts =
5670 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5671 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5673 sc->stat_IfHCInBroadcastPkts =
5674 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5675 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5677 sc->stat_IfHCOutUcastPkts =
5678 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5679 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5681 sc->stat_IfHCOutMulticastPkts =
5682 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5683 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5685 sc->stat_IfHCOutBroadcastPkts =
5686 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5687 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5689 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5690 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5692 sc->stat_Dot3StatsCarrierSenseErrors =
5693 stats->stat_Dot3StatsCarrierSenseErrors;
5695 sc->stat_Dot3StatsFCSErrors =
5696 stats->stat_Dot3StatsFCSErrors;
5698 sc->stat_Dot3StatsAlignmentErrors =
5699 stats->stat_Dot3StatsAlignmentErrors;
5701 sc->stat_Dot3StatsSingleCollisionFrames =
5702 stats->stat_Dot3StatsSingleCollisionFrames;
5704 sc->stat_Dot3StatsMultipleCollisionFrames =
5705 stats->stat_Dot3StatsMultipleCollisionFrames;
5707 sc->stat_Dot3StatsDeferredTransmissions =
5708 stats->stat_Dot3StatsDeferredTransmissions;
5710 sc->stat_Dot3StatsExcessiveCollisions =
5711 stats->stat_Dot3StatsExcessiveCollisions;
5713 sc->stat_Dot3StatsLateCollisions =
5714 stats->stat_Dot3StatsLateCollisions;
5716 sc->stat_EtherStatsCollisions =
5717 stats->stat_EtherStatsCollisions;
5719 sc->stat_EtherStatsFragments =
5720 stats->stat_EtherStatsFragments;
5722 sc->stat_EtherStatsJabbers =
5723 stats->stat_EtherStatsJabbers;
5725 sc->stat_EtherStatsUndersizePkts =
5726 stats->stat_EtherStatsUndersizePkts;
5728 sc->stat_EtherStatsOverrsizePkts =
5729 stats->stat_EtherStatsOverrsizePkts;
5731 sc->stat_EtherStatsPktsRx64Octets =
5732 stats->stat_EtherStatsPktsRx64Octets;
5734 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5735 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5737 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5738 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5740 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5741 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5743 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5744 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5746 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5747 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5749 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5750 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5752 sc->stat_EtherStatsPktsTx64Octets =
5753 stats->stat_EtherStatsPktsTx64Octets;
5755 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5756 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5758 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5759 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5761 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5762 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5764 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5765 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5767 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5768 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5770 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5771 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5773 sc->stat_XonPauseFramesReceived =
5774 stats->stat_XonPauseFramesReceived;
5776 sc->stat_XoffPauseFramesReceived =
5777 stats->stat_XoffPauseFramesReceived;
5779 sc->stat_OutXonSent =
5780 stats->stat_OutXonSent;
5782 sc->stat_OutXoffSent =
5783 stats->stat_OutXoffSent;
5785 sc->stat_FlowControlDone =
5786 stats->stat_FlowControlDone;
5788 sc->stat_MacControlFramesReceived =
5789 stats->stat_MacControlFramesReceived;
5791 sc->stat_XoffStateEntered =
5792 stats->stat_XoffStateEntered;
5794 sc->stat_IfInFramesL2FilterDiscards =
5795 stats->stat_IfInFramesL2FilterDiscards;
5797 sc->stat_IfInRuleCheckerDiscards =
5798 stats->stat_IfInRuleCheckerDiscards;
5800 sc->stat_IfInFTQDiscards =
5801 stats->stat_IfInFTQDiscards;
5803 sc->stat_IfInMBUFDiscards =
5804 stats->stat_IfInMBUFDiscards;
5806 sc->stat_IfInRuleCheckerP4Hit =
5807 stats->stat_IfInRuleCheckerP4Hit;
5809 sc->stat_CatchupInRuleCheckerDiscards =
5810 stats->stat_CatchupInRuleCheckerDiscards;
5812 sc->stat_CatchupInFTQDiscards =
5813 stats->stat_CatchupInFTQDiscards;
5815 sc->stat_CatchupInMBUFDiscards =
5816 stats->stat_CatchupInMBUFDiscards;
5818 sc->stat_CatchupInRuleCheckerP4Hit =
5819 stats->stat_CatchupInRuleCheckerP4Hit;
5821 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5824 * Update the interface statistics from the
5825 * hardware statistics.
5827 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5829 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5830 (u_long)sc->stat_EtherStatsOverrsizePkts +
5831 (u_long)sc->stat_IfInMBUFDiscards +
5832 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5833 (u_long)sc->stat_Dot3StatsFCSErrors +
5834 (u_long)sc->stat_IfInRuleCheckerDiscards +
5835 (u_long)sc->stat_IfInFTQDiscards +
5836 (u_long)sc->com_no_buffers;
5839 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5840 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5841 (u_long)sc->stat_Dot3StatsLateCollisions;
5843 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5847 /****************************************************************************/
5848 /* Periodic function to notify the bootcode that the driver is still */
5853 /****************************************************************************/
5855 bce_pulse(void *xsc)
5857 struct bce_softc *sc = xsc;
5858 struct ifnet *ifp = &sc->arpcom.ac_if;
5861 lwkt_serialize_enter(ifp->if_serializer);
5863 if (ifp->if_flags & IFF_RUNNING) {
5864 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI &&
5865 (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) == 0)
5866 bce_pulse_check_msi(sc);
5869 /* Tell the firmware that the driver is still running. */
5870 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5871 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5873 /* Update the bootcode condition. */
5874 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5876 /* Report whether the bootcode still knows the driver is running. */
5877 if (!sc->bce_drv_cardiac_arrest) {
5878 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5879 sc->bce_drv_cardiac_arrest = 1;
5880 if_printf(ifp, "Bootcode lost the driver pulse! "
5881 "(bc_state = 0x%08X)\n", sc->bc_state);
5885 * Not supported by all bootcode versions.
5886 * (v5.0.11+ and v5.2.1+) Older bootcode
5887 * will require the driver to reset the
5888 * controller to clear this condition.
5890 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5891 sc->bce_drv_cardiac_arrest = 0;
5892 if_printf(ifp, "Bootcode found the driver pulse! "
5893 "(bc_state = 0x%08X)\n", sc->bc_state);
5897 /* Schedule the next pulse. */
5898 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5900 lwkt_serialize_exit(ifp->if_serializer);
5904 bce_pulse_check_msi(struct bce_softc *sc)
5908 if (bce_get_hw_rx_cons(sc) != sc->hw_rx_cons) {
5910 } else if (bce_get_hw_tx_cons(sc) != sc->hw_tx_cons) {
5913 struct status_block *sblk = sc->status_block;
5915 if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5916 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5923 msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
5924 if ((msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) == 0)
5927 if (sc->pulse_check_status_idx == sc->last_status_idx) {
5928 if_printf(&sc->arpcom.ac_if, "missing MSI\n");
5930 REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
5931 msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
5932 REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
5937 sc->pulse_check_status_idx = sc->last_status_idx;
5940 /****************************************************************************/
5941 /* Periodic function to perform maintenance tasks. */
5945 /****************************************************************************/
5947 bce_tick_serialized(struct bce_softc *sc)
5949 struct ifnet *ifp = &sc->arpcom.ac_if;
5950 struct mii_data *mii;
5952 ASSERT_SERIALIZED(ifp->if_serializer);
5954 /* Update the statistics from the hardware statistics block. */
5955 bce_stats_update(sc);
5957 /* Schedule the next tick. */
5958 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5960 /* If link is up already up then we're done. */
5964 mii = device_get_softc(sc->bce_miibus);
5967 /* Check if the link has come up. */
5968 if ((mii->mii_media_status & IFM_ACTIVE) &&
5969 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5971 /* Now that link is up, handle any outstanding TX traffic. */
5972 if (!ifq_is_empty(&ifp->if_snd))
5981 struct bce_softc *sc = xsc;
5982 struct ifnet *ifp = &sc->arpcom.ac_if;
5984 lwkt_serialize_enter(ifp->if_serializer);
5985 bce_tick_serialized(sc);
5986 lwkt_serialize_exit(ifp->if_serializer);
5991 /****************************************************************************/
5992 /* Allows the driver state to be dumped through the sysctl interface. */
5995 /* 0 for success, positive value for failure. */
5996 /****************************************************************************/
5998 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
6002 struct bce_softc *sc;
6005 error = sysctl_handle_int(oidp, &result, 0, req);
6007 if (error || !req->newptr)
6011 sc = (struct bce_softc *)arg1;
6012 bce_dump_driver_state(sc);
6019 /****************************************************************************/
6020 /* Allows the hardware state to be dumped through the sysctl interface. */
6023 /* 0 for success, positive value for failure. */
6024 /****************************************************************************/
6026 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
6030 struct bce_softc *sc;
6033 error = sysctl_handle_int(oidp, &result, 0, req);
6035 if (error || !req->newptr)
6039 sc = (struct bce_softc *)arg1;
6040 bce_dump_hw_state(sc);
6047 /****************************************************************************/
6048 /* Provides a sysctl interface to allows dumping the RX chain. */
6051 /* 0 for success, positive value for failure. */
6052 /****************************************************************************/
6054 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
6058 struct bce_softc *sc;
6061 error = sysctl_handle_int(oidp, &result, 0, req);
6063 if (error || !req->newptr)
6067 sc = (struct bce_softc *)arg1;
6068 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
6075 /****************************************************************************/
6076 /* Provides a sysctl interface to allows dumping the TX chain. */
6079 /* 0 for success, positive value for failure. */
6080 /****************************************************************************/
6082 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
6086 struct bce_softc *sc;
6089 error = sysctl_handle_int(oidp, &result, 0, req);
6091 if (error || !req->newptr)
6095 sc = (struct bce_softc *)arg1;
6096 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
6103 /****************************************************************************/
6104 /* Provides a sysctl interface to allow reading arbitrary registers in the */
6105 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6108 /* 0 for success, positive value for failure. */
6109 /****************************************************************************/
6111 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6113 struct bce_softc *sc;
6115 uint32_t val, result;
6118 error = sysctl_handle_int(oidp, &result, 0, req);
6119 if (error || (req->newptr == NULL))
6122 /* Make sure the register is accessible. */
6123 if (result < 0x8000) {
6124 sc = (struct bce_softc *)arg1;
6125 val = REG_RD(sc, result);
6126 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6128 } else if (result < 0x0280000) {
6129 sc = (struct bce_softc *)arg1;
6130 val = REG_RD_IND(sc, result);
6131 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6138 /****************************************************************************/
6139 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
6140 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6143 /* 0 for success, positive value for failure. */
6144 /****************************************************************************/
6146 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6148 struct bce_softc *sc;
6154 error = sysctl_handle_int(oidp, &result, 0, req);
6155 if (error || (req->newptr == NULL))
6158 /* Make sure the register is accessible. */
6159 if (result < 0x20) {
6160 sc = (struct bce_softc *)arg1;
6162 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6163 if_printf(&sc->arpcom.ac_if,
6164 "phy 0x%02X = 0x%04X\n", result, val);
6170 /****************************************************************************/
6171 /* Provides a sysctl interface to forcing the driver to dump state and */
6172 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6175 /* 0 for success, positive value for failure. */
6176 /****************************************************************************/
6178 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6182 struct bce_softc *sc;
6185 error = sysctl_handle_int(oidp, &result, 0, req);
6187 if (error || !req->newptr)
6191 sc = (struct bce_softc *)arg1;
6200 /****************************************************************************/
6201 /* Adds any sysctl parameters for tuning or debugging purposes. */
6204 /* 0 for success, positive value for failure. */
6205 /****************************************************************************/
6207 bce_add_sysctls(struct bce_softc *sc)
6209 struct sysctl_ctx_list *ctx;
6210 struct sysctl_oid_list *children;
6212 sysctl_ctx_init(&sc->bce_sysctl_ctx);
6213 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6214 SYSCTL_STATIC_CHILDREN(_hw),
6216 device_get_nameunit(sc->bce_dev),
6218 if (sc->bce_sysctl_tree == NULL) {
6219 device_printf(sc->bce_dev, "can't add sysctl node\n");
6223 ctx = &sc->bce_sysctl_ctx;
6224 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6226 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6227 CTLTYPE_INT | CTLFLAG_RW,
6228 sc, 0, bce_sysctl_tx_bds_int, "I",
6229 "Send max coalesced BD count during interrupt");
6230 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6231 CTLTYPE_INT | CTLFLAG_RW,
6232 sc, 0, bce_sysctl_tx_bds, "I",
6233 "Send max coalesced BD count");
6234 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6235 CTLTYPE_INT | CTLFLAG_RW,
6236 sc, 0, bce_sysctl_tx_ticks_int, "I",
6237 "Send coalescing ticks during interrupt");
6238 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6239 CTLTYPE_INT | CTLFLAG_RW,
6240 sc, 0, bce_sysctl_tx_ticks, "I",
6241 "Send coalescing ticks");
6243 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6244 CTLTYPE_INT | CTLFLAG_RW,
6245 sc, 0, bce_sysctl_rx_bds_int, "I",
6246 "Receive max coalesced BD count during interrupt");
6247 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6248 CTLTYPE_INT | CTLFLAG_RW,
6249 sc, 0, bce_sysctl_rx_bds, "I",
6250 "Receive max coalesced BD count");
6251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6252 CTLTYPE_INT | CTLFLAG_RW,
6253 sc, 0, bce_sysctl_rx_ticks_int, "I",
6254 "Receive coalescing ticks during interrupt");
6255 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6256 CTLTYPE_INT | CTLFLAG_RW,
6257 sc, 0, bce_sysctl_rx_ticks, "I",
6258 "Receive coalescing ticks");
6261 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6263 CTLFLAG_RD, &sc->rx_low_watermark,
6264 0, "Lowest level of free rx_bd's");
6266 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6268 CTLFLAG_RD, &sc->rx_empty_count,
6269 0, "Number of times the RX chain was empty");
6271 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6273 CTLFLAG_RD, &sc->tx_hi_watermark,
6274 0, "Highest level of used tx_bd's");
6276 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6278 CTLFLAG_RD, &sc->tx_full_count,
6279 0, "Number of times the TX chain was full");
6281 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6282 "l2fhdr_status_errors",
6283 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6284 0, "l2_fhdr status errors");
6286 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6287 "unexpected_attentions",
6288 CTLFLAG_RD, &sc->unexpected_attentions,
6289 0, "unexpected attentions");
6291 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6292 "lost_status_block_updates",
6293 CTLFLAG_RD, &sc->lost_status_block_updates,
6294 0, "lost status block updates");
6296 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6297 "mbuf_alloc_failed",
6298 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6299 0, "mbuf cluster allocation failures");
6302 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6303 "stat_IfHCInOctets",
6304 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6307 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6308 "stat_IfHCInBadOctets",
6309 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6310 "Bad bytes received");
6312 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6313 "stat_IfHCOutOctets",
6314 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6317 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6318 "stat_IfHCOutBadOctets",
6319 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6322 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6323 "stat_IfHCInUcastPkts",
6324 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6325 "Unicast packets received");
6327 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6328 "stat_IfHCInMulticastPkts",
6329 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6330 "Multicast packets received");
6332 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6333 "stat_IfHCInBroadcastPkts",
6334 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6335 "Broadcast packets received");
6337 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6338 "stat_IfHCOutUcastPkts",
6339 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6340 "Unicast packets sent");
6342 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6343 "stat_IfHCOutMulticastPkts",
6344 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6345 "Multicast packets sent");
6347 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6348 "stat_IfHCOutBroadcastPkts",
6349 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6350 "Broadcast packets sent");
6352 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6353 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6354 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6355 0, "Internal MAC transmit errors");
6357 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6358 "stat_Dot3StatsCarrierSenseErrors",
6359 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6360 0, "Carrier sense errors");
6362 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6363 "stat_Dot3StatsFCSErrors",
6364 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6365 0, "Frame check sequence errors");
6367 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6368 "stat_Dot3StatsAlignmentErrors",
6369 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6370 0, "Alignment errors");
6372 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6373 "stat_Dot3StatsSingleCollisionFrames",
6374 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6375 0, "Single Collision Frames");
6377 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6378 "stat_Dot3StatsMultipleCollisionFrames",
6379 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6380 0, "Multiple Collision Frames");
6382 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6383 "stat_Dot3StatsDeferredTransmissions",
6384 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6385 0, "Deferred Transmissions");
6387 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6388 "stat_Dot3StatsExcessiveCollisions",
6389 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6390 0, "Excessive Collisions");
6392 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6393 "stat_Dot3StatsLateCollisions",
6394 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6395 0, "Late Collisions");
6397 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6398 "stat_EtherStatsCollisions",
6399 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6402 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6403 "stat_EtherStatsFragments",
6404 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6407 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6408 "stat_EtherStatsJabbers",
6409 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6412 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6413 "stat_EtherStatsUndersizePkts",
6414 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6415 0, "Undersize packets");
6417 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6418 "stat_EtherStatsOverrsizePkts",
6419 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6420 0, "stat_EtherStatsOverrsizePkts");
6422 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6423 "stat_EtherStatsPktsRx64Octets",
6424 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6425 0, "Bytes received in 64 byte packets");
6427 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6428 "stat_EtherStatsPktsRx65Octetsto127Octets",
6429 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6430 0, "Bytes received in 65 to 127 byte packets");
6432 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6433 "stat_EtherStatsPktsRx128Octetsto255Octets",
6434 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6435 0, "Bytes received in 128 to 255 byte packets");
6437 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6438 "stat_EtherStatsPktsRx256Octetsto511Octets",
6439 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6440 0, "Bytes received in 256 to 511 byte packets");
6442 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6443 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6444 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6445 0, "Bytes received in 512 to 1023 byte packets");
6447 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6448 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6449 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6450 0, "Bytes received in 1024 t0 1522 byte packets");
6452 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6453 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6454 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6455 0, "Bytes received in 1523 to 9022 byte packets");
6457 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6458 "stat_EtherStatsPktsTx64Octets",
6459 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6460 0, "Bytes sent in 64 byte packets");
6462 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6463 "stat_EtherStatsPktsTx65Octetsto127Octets",
6464 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6465 0, "Bytes sent in 65 to 127 byte packets");
6467 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6468 "stat_EtherStatsPktsTx128Octetsto255Octets",
6469 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6470 0, "Bytes sent in 128 to 255 byte packets");
6472 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6473 "stat_EtherStatsPktsTx256Octetsto511Octets",
6474 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6475 0, "Bytes sent in 256 to 511 byte packets");
6477 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6478 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6479 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6480 0, "Bytes sent in 512 to 1023 byte packets");
6482 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6483 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6484 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6485 0, "Bytes sent in 1024 to 1522 byte packets");
6487 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6488 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6489 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6490 0, "Bytes sent in 1523 to 9022 byte packets");
6492 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6493 "stat_XonPauseFramesReceived",
6494 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6495 0, "XON pause frames receved");
6497 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6498 "stat_XoffPauseFramesReceived",
6499 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6500 0, "XOFF pause frames received");
6502 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6504 CTLFLAG_RD, &sc->stat_OutXonSent,
6505 0, "XON pause frames sent");
6507 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6509 CTLFLAG_RD, &sc->stat_OutXoffSent,
6510 0, "XOFF pause frames sent");
6512 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6513 "stat_FlowControlDone",
6514 CTLFLAG_RD, &sc->stat_FlowControlDone,
6515 0, "Flow control done");
6517 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6518 "stat_MacControlFramesReceived",
6519 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6520 0, "MAC control frames received");
6522 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6523 "stat_XoffStateEntered",
6524 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6525 0, "XOFF state entered");
6527 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6528 "stat_IfInFramesL2FilterDiscards",
6529 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6530 0, "Received L2 packets discarded");
6532 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6533 "stat_IfInRuleCheckerDiscards",
6534 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6535 0, "Received packets discarded by rule");
6537 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6538 "stat_IfInFTQDiscards",
6539 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6540 0, "Received packet FTQ discards");
6542 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6543 "stat_IfInMBUFDiscards",
6544 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6545 0, "Received packets discarded due to lack of controller buffer memory");
6547 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6548 "stat_IfInRuleCheckerP4Hit",
6549 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6550 0, "Received packets rule checker hits");
6552 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6553 "stat_CatchupInRuleCheckerDiscards",
6554 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6555 0, "Received packets discarded in Catchup path");
6557 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6558 "stat_CatchupInFTQDiscards",
6559 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6560 0, "Received packets discarded in FTQ in Catchup path");
6562 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6563 "stat_CatchupInMBUFDiscards",
6564 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6565 0, "Received packets discarded in controller buffer memory in Catchup path");
6567 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6568 "stat_CatchupInRuleCheckerP4Hit",
6569 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6570 0, "Received packets rule checker hits in Catchup path");
6572 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6574 CTLFLAG_RD, &sc->com_no_buffers,
6575 0, "Valid packets received but no RX buffers available");
6578 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6579 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6581 bce_sysctl_driver_state, "I", "Drive state information");
6583 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6584 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6586 bce_sysctl_hw_state, "I", "Hardware state information");
6588 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6589 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6591 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6593 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6594 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6596 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6598 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6599 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6601 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6603 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6604 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6606 bce_sysctl_reg_read, "I", "Register read");
6608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6609 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6611 bce_sysctl_phy_read, "I", "PHY register read");
6618 /****************************************************************************/
6619 /* BCE Debug Routines */
6620 /****************************************************************************/
6623 /****************************************************************************/
6624 /* Freezes the controller to allow for a cohesive state dump. */
6628 /****************************************************************************/
6630 bce_freeze_controller(struct bce_softc *sc)
6634 val = REG_RD(sc, BCE_MISC_COMMAND);
6635 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6636 REG_WR(sc, BCE_MISC_COMMAND, val);
6640 /****************************************************************************/
6641 /* Unfreezes the controller after a freeze operation. This may not always */
6642 /* work and the controller will require a reset! */
6646 /****************************************************************************/
6648 bce_unfreeze_controller(struct bce_softc *sc)
6652 val = REG_RD(sc, BCE_MISC_COMMAND);
6653 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6654 REG_WR(sc, BCE_MISC_COMMAND, val);
6658 /****************************************************************************/
6659 /* Prints out information about an mbuf. */
6663 /****************************************************************************/
6665 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6667 struct ifnet *ifp = &sc->arpcom.ac_if;
6668 uint32_t val_hi, val_lo;
6669 struct mbuf *mp = m;
6672 /* Index out of range. */
6673 if_printf(ifp, "mbuf: null pointer\n");
6678 val_hi = BCE_ADDR_HI(mp);
6679 val_lo = BCE_ADDR_LO(mp);
6680 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6681 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6683 if (mp->m_flags & M_EXT)
6685 if (mp->m_flags & M_PKTHDR)
6686 kprintf("M_PKTHDR ");
6687 if (mp->m_flags & M_EOR)
6690 if (mp->m_flags & M_RDONLY)
6691 kprintf("M_RDONLY ");
6694 val_hi = BCE_ADDR_HI(mp->m_data);
6695 val_lo = BCE_ADDR_LO(mp->m_data);
6696 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6698 if (mp->m_flags & M_PKTHDR) {
6699 if_printf(ifp, "- m_pkthdr: flags = ( ");
6700 if (mp->m_flags & M_BCAST)
6701 kprintf("M_BCAST ");
6702 if (mp->m_flags & M_MCAST)
6703 kprintf("M_MCAST ");
6704 if (mp->m_flags & M_FRAG)
6706 if (mp->m_flags & M_FIRSTFRAG)
6707 kprintf("M_FIRSTFRAG ");
6708 if (mp->m_flags & M_LASTFRAG)
6709 kprintf("M_LASTFRAG ");
6711 if (mp->m_flags & M_VLANTAG)
6712 kprintf("M_VLANTAG ");
6715 if (mp->m_flags & M_PROMISC)
6716 kprintf("M_PROMISC ");
6718 kprintf(") csum_flags = ( ");
6719 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6720 kprintf("CSUM_IP ");
6721 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6722 kprintf("CSUM_TCP ");
6723 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6724 kprintf("CSUM_UDP ");
6725 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6726 kprintf("CSUM_IP_FRAGS ");
6727 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6728 kprintf("CSUM_FRAGMENT ");
6730 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6731 kprintf("CSUM_TSO ");
6733 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6734 kprintf("CSUM_IP_CHECKED ");
6735 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6736 kprintf("CSUM_IP_VALID ");
6737 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6738 kprintf("CSUM_DATA_VALID ");
6742 if (mp->m_flags & M_EXT) {
6743 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6744 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6745 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6747 val_hi, val_lo, mp->m_ext.ext_size);
6754 /****************************************************************************/
6755 /* Prints out the mbufs in the TX mbuf chain. */
6759 /****************************************************************************/
6761 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6763 struct ifnet *ifp = &sc->arpcom.ac_if;
6767 "----------------------------"
6769 "----------------------------\n");
6771 for (i = 0; i < count; i++) {
6772 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6773 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6774 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6778 "----------------------------"
6780 "----------------------------\n");
6784 /****************************************************************************/
6785 /* Prints out the mbufs in the RX mbuf chain. */
6789 /****************************************************************************/
6791 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6793 struct ifnet *ifp = &sc->arpcom.ac_if;
6797 "----------------------------"
6799 "----------------------------\n");
6801 for (i = 0; i < count; i++) {
6802 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6803 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6804 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6808 "----------------------------"
6810 "----------------------------\n");
6814 /****************************************************************************/
6815 /* Prints out a tx_bd structure. */
6819 /****************************************************************************/
6821 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6823 struct ifnet *ifp = &sc->arpcom.ac_if;
6825 if (idx > MAX_TX_BD) {
6826 /* Index out of range. */
6827 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6828 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6829 /* TX Chain page pointer. */
6830 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6831 "chain page pointer\n",
6832 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6834 /* Normal tx_bd entry. */
6835 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6837 "vlan tag= 0x%04X, flags = 0x%04X (",
6838 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6839 txbd->tx_bd_mss_nbytes,
6840 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6842 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6843 kprintf(" CONN_FAULT");
6845 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6846 kprintf(" TCP_UDP_CKSUM");
6848 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6849 kprintf(" IP_CKSUM");
6851 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6854 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6855 kprintf(" COAL_NOW");
6857 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6858 kprintf(" DONT_GEN_CRC");
6860 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6863 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6866 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6869 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6870 kprintf(" OPTION_WORD");
6872 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6875 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6883 /****************************************************************************/
6884 /* Prints out a rx_bd structure. */
6888 /****************************************************************************/
6890 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6892 struct ifnet *ifp = &sc->arpcom.ac_if;
6894 if (idx > MAX_RX_BD) {
6895 /* Index out of range. */
6896 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6897 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6898 /* TX Chain page pointer. */
6899 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6900 "chain page pointer\n",
6901 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6903 /* Normal tx_bd entry. */
6904 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6905 "nbytes = 0x%08X, flags = 0x%08X\n",
6906 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6907 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6912 /****************************************************************************/
6913 /* Prints out a l2_fhdr structure. */
6917 /****************************************************************************/
6919 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6921 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6922 "pkt_len = 0x%04X, vlan = 0x%04x, "
6923 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6924 idx, l2fhdr->l2_fhdr_status,
6925 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6926 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6930 /****************************************************************************/
6931 /* Prints out the tx chain. */
6935 /****************************************************************************/
6937 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6939 struct ifnet *ifp = &sc->arpcom.ac_if;
6942 /* First some info about the tx_bd chain structure. */
6944 "----------------------------"
6946 "----------------------------\n");
6948 if_printf(ifp, "page size = 0x%08X, "
6949 "tx chain pages = 0x%08X\n",
6950 (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6952 if_printf(ifp, "tx_bd per page = 0x%08X, "
6953 "usable tx_bd per page = 0x%08X\n",
6954 (uint32_t)TOTAL_TX_BD_PER_PAGE,
6955 (uint32_t)USABLE_TX_BD_PER_PAGE);
6957 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6960 "----------------------------"
6962 "----------------------------\n");
6964 /* Now print out the tx_bd's themselves. */
6965 for (i = 0; i < count; i++) {
6968 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6969 bce_dump_txbd(sc, tx_prod, txbd);
6970 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6974 "----------------------------"
6976 "----------------------------\n");
6980 /****************************************************************************/
6981 /* Prints out the rx chain. */
6985 /****************************************************************************/
6987 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6989 struct ifnet *ifp = &sc->arpcom.ac_if;
6992 /* First some info about the tx_bd chain structure. */
6994 "----------------------------"
6996 "----------------------------\n");
6998 if_printf(ifp, "page size = 0x%08X, "
6999 "rx chain pages = 0x%08X\n",
7000 (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
7002 if_printf(ifp, "rx_bd per page = 0x%08X, "
7003 "usable rx_bd per page = 0x%08X\n",
7004 (uint32_t)TOTAL_RX_BD_PER_PAGE,
7005 (uint32_t)USABLE_RX_BD_PER_PAGE);
7007 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
7010 "----------------------------"
7012 "----------------------------\n");
7014 /* Now print out the rx_bd's themselves. */
7015 for (i = 0; i < count; i++) {
7018 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
7019 bce_dump_rxbd(sc, rx_prod, rxbd);
7020 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
7024 "----------------------------"
7026 "----------------------------\n");
7030 /****************************************************************************/
7031 /* Prints out the status block from host memory. */
7035 /****************************************************************************/
7037 bce_dump_status_block(struct bce_softc *sc)
7039 struct status_block *sblk = sc->status_block;
7040 struct ifnet *ifp = &sc->arpcom.ac_if;
7043 "----------------------------"
7045 "----------------------------\n");
7047 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
7049 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
7050 sblk->status_attn_bits_ack);
7052 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
7053 sblk->status_rx_quick_consumer_index0,
7054 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
7056 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
7057 sblk->status_tx_quick_consumer_index0,
7058 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
7060 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
7062 /* Theses indices are not used for normal L2 drivers. */
7063 if (sblk->status_rx_quick_consumer_index1) {
7064 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
7065 sblk->status_rx_quick_consumer_index1,
7066 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
7069 if (sblk->status_tx_quick_consumer_index1) {
7070 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
7071 sblk->status_tx_quick_consumer_index1,
7072 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
7075 if (sblk->status_rx_quick_consumer_index2) {
7076 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
7077 sblk->status_rx_quick_consumer_index2,
7078 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
7081 if (sblk->status_tx_quick_consumer_index2) {
7082 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
7083 sblk->status_tx_quick_consumer_index2,
7084 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
7087 if (sblk->status_rx_quick_consumer_index3) {
7088 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7089 sblk->status_rx_quick_consumer_index3,
7090 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
7093 if (sblk->status_tx_quick_consumer_index3) {
7094 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7095 sblk->status_tx_quick_consumer_index3,
7096 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
7099 if (sblk->status_rx_quick_consumer_index4 ||
7100 sblk->status_rx_quick_consumer_index5) {
7101 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
7102 sblk->status_rx_quick_consumer_index4,
7103 sblk->status_rx_quick_consumer_index5);
7106 if (sblk->status_rx_quick_consumer_index6 ||
7107 sblk->status_rx_quick_consumer_index7) {
7108 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
7109 sblk->status_rx_quick_consumer_index6,
7110 sblk->status_rx_quick_consumer_index7);
7113 if (sblk->status_rx_quick_consumer_index8 ||
7114 sblk->status_rx_quick_consumer_index9) {
7115 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
7116 sblk->status_rx_quick_consumer_index8,
7117 sblk->status_rx_quick_consumer_index9);
7120 if (sblk->status_rx_quick_consumer_index10 ||
7121 sblk->status_rx_quick_consumer_index11) {
7122 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
7123 sblk->status_rx_quick_consumer_index10,
7124 sblk->status_rx_quick_consumer_index11);
7127 if (sblk->status_rx_quick_consumer_index12 ||
7128 sblk->status_rx_quick_consumer_index13) {
7129 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
7130 sblk->status_rx_quick_consumer_index12,
7131 sblk->status_rx_quick_consumer_index13);
7134 if (sblk->status_rx_quick_consumer_index14 ||
7135 sblk->status_rx_quick_consumer_index15) {
7136 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
7137 sblk->status_rx_quick_consumer_index14,
7138 sblk->status_rx_quick_consumer_index15);
7141 if (sblk->status_completion_producer_index ||
7142 sblk->status_cmd_consumer_index) {
7143 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
7144 sblk->status_completion_producer_index,
7145 sblk->status_cmd_consumer_index);
7149 "----------------------------"
7151 "----------------------------\n");
7155 /****************************************************************************/
7156 /* Prints out the statistics block. */
7160 /****************************************************************************/
7162 bce_dump_stats_block(struct bce_softc *sc)
7164 struct statistics_block *sblk = sc->stats_block;
7165 struct ifnet *ifp = &sc->arpcom.ac_if;
7169 " Stats Block (All Stats Not Shown Are 0) "
7170 "---------------\n");
7172 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7173 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7174 sblk->stat_IfHCInOctets_hi,
7175 sblk->stat_IfHCInOctets_lo);
7178 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7179 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7180 sblk->stat_IfHCInBadOctets_hi,
7181 sblk->stat_IfHCInBadOctets_lo);
7184 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7185 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7186 sblk->stat_IfHCOutOctets_hi,
7187 sblk->stat_IfHCOutOctets_lo);
7190 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7191 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7192 sblk->stat_IfHCOutBadOctets_hi,
7193 sblk->stat_IfHCOutBadOctets_lo);
7196 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7197 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7198 sblk->stat_IfHCInUcastPkts_hi,
7199 sblk->stat_IfHCInUcastPkts_lo);
7202 if (sblk->stat_IfHCInBroadcastPkts_hi ||
7203 sblk->stat_IfHCInBroadcastPkts_lo) {
7204 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7205 sblk->stat_IfHCInBroadcastPkts_hi,
7206 sblk->stat_IfHCInBroadcastPkts_lo);
7209 if (sblk->stat_IfHCInMulticastPkts_hi ||
7210 sblk->stat_IfHCInMulticastPkts_lo) {
7211 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7212 sblk->stat_IfHCInMulticastPkts_hi,
7213 sblk->stat_IfHCInMulticastPkts_lo);
7216 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7217 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7218 sblk->stat_IfHCOutUcastPkts_hi,
7219 sblk->stat_IfHCOutUcastPkts_lo);
7222 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7223 sblk->stat_IfHCOutBroadcastPkts_lo) {
7224 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7225 sblk->stat_IfHCOutBroadcastPkts_hi,
7226 sblk->stat_IfHCOutBroadcastPkts_lo);
7229 if (sblk->stat_IfHCOutMulticastPkts_hi ||
7230 sblk->stat_IfHCOutMulticastPkts_lo) {
7231 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7232 sblk->stat_IfHCOutMulticastPkts_hi,
7233 sblk->stat_IfHCOutMulticastPkts_lo);
7236 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7237 if_printf(ifp, " 0x%08X : "
7238 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7239 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7242 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7243 if_printf(ifp, " 0x%08X : "
7244 "Dot3StatsCarrierSenseErrors\n",
7245 sblk->stat_Dot3StatsCarrierSenseErrors);
7248 if (sblk->stat_Dot3StatsFCSErrors) {
7249 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
7250 sblk->stat_Dot3StatsFCSErrors);
7253 if (sblk->stat_Dot3StatsAlignmentErrors) {
7254 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
7255 sblk->stat_Dot3StatsAlignmentErrors);
7258 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7259 if_printf(ifp, " 0x%08X : "
7260 "Dot3StatsSingleCollisionFrames\n",
7261 sblk->stat_Dot3StatsSingleCollisionFrames);
7264 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7265 if_printf(ifp, " 0x%08X : "
7266 "Dot3StatsMultipleCollisionFrames\n",
7267 sblk->stat_Dot3StatsMultipleCollisionFrames);
7270 if (sblk->stat_Dot3StatsDeferredTransmissions) {
7271 if_printf(ifp, " 0x%08X : "
7272 "Dot3StatsDeferredTransmissions\n",
7273 sblk->stat_Dot3StatsDeferredTransmissions);
7276 if (sblk->stat_Dot3StatsExcessiveCollisions) {
7277 if_printf(ifp, " 0x%08X : "
7278 "Dot3StatsExcessiveCollisions\n",
7279 sblk->stat_Dot3StatsExcessiveCollisions);
7282 if (sblk->stat_Dot3StatsLateCollisions) {
7283 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
7284 sblk->stat_Dot3StatsLateCollisions);
7287 if (sblk->stat_EtherStatsCollisions) {
7288 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
7289 sblk->stat_EtherStatsCollisions);
7292 if (sblk->stat_EtherStatsFragments) {
7293 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
7294 sblk->stat_EtherStatsFragments);
7297 if (sblk->stat_EtherStatsJabbers) {
7298 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
7299 sblk->stat_EtherStatsJabbers);
7302 if (sblk->stat_EtherStatsUndersizePkts) {
7303 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
7304 sblk->stat_EtherStatsUndersizePkts);
7307 if (sblk->stat_EtherStatsOverrsizePkts) {
7308 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7309 sblk->stat_EtherStatsOverrsizePkts);
7312 if (sblk->stat_EtherStatsPktsRx64Octets) {
7313 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7314 sblk->stat_EtherStatsPktsRx64Octets);
7317 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7318 if_printf(ifp, " 0x%08X : "
7319 "EtherStatsPktsRx65Octetsto127Octets\n",
7320 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7323 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7324 if_printf(ifp, " 0x%08X : "
7325 "EtherStatsPktsRx128Octetsto255Octets\n",
7326 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7329 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7330 if_printf(ifp, " 0x%08X : "
7331 "EtherStatsPktsRx256Octetsto511Octets\n",
7332 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7335 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7336 if_printf(ifp, " 0x%08X : "
7337 "EtherStatsPktsRx512Octetsto1023Octets\n",
7338 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7341 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7342 if_printf(ifp, " 0x%08X : "
7343 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7344 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7347 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7348 if_printf(ifp, " 0x%08X : "
7349 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7350 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7353 if (sblk->stat_EtherStatsPktsTx64Octets) {
7354 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7355 sblk->stat_EtherStatsPktsTx64Octets);
7358 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7359 if_printf(ifp, " 0x%08X : "
7360 "EtherStatsPktsTx65Octetsto127Octets\n",
7361 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7364 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7365 if_printf(ifp, " 0x%08X : "
7366 "EtherStatsPktsTx128Octetsto255Octets\n",
7367 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7370 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7371 if_printf(ifp, " 0x%08X : "
7372 "EtherStatsPktsTx256Octetsto511Octets\n",
7373 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7376 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7377 if_printf(ifp, " 0x%08X : "
7378 "EtherStatsPktsTx512Octetsto1023Octets\n",
7379 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7382 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7383 if_printf(ifp, " 0x%08X : "
7384 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7385 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7388 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7389 if_printf(ifp, " 0x%08X : "
7390 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7391 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7394 if (sblk->stat_XonPauseFramesReceived) {
7395 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7396 sblk->stat_XonPauseFramesReceived);
7399 if (sblk->stat_XoffPauseFramesReceived) {
7400 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7401 sblk->stat_XoffPauseFramesReceived);
7404 if (sblk->stat_OutXonSent) {
7405 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7406 sblk->stat_OutXonSent);
7409 if (sblk->stat_OutXoffSent) {
7410 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7411 sblk->stat_OutXoffSent);
7414 if (sblk->stat_FlowControlDone) {
7415 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7416 sblk->stat_FlowControlDone);
7419 if (sblk->stat_MacControlFramesReceived) {
7420 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7421 sblk->stat_MacControlFramesReceived);
7424 if (sblk->stat_XoffStateEntered) {
7425 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7426 sblk->stat_XoffStateEntered);
7429 if (sblk->stat_IfInFramesL2FilterDiscards) {
7430 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7433 if (sblk->stat_IfInRuleCheckerDiscards) {
7434 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7435 sblk->stat_IfInRuleCheckerDiscards);
7438 if (sblk->stat_IfInFTQDiscards) {
7439 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7440 sblk->stat_IfInFTQDiscards);
7443 if (sblk->stat_IfInMBUFDiscards) {
7444 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7445 sblk->stat_IfInMBUFDiscards);
7448 if (sblk->stat_IfInRuleCheckerP4Hit) {
7449 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7450 sblk->stat_IfInRuleCheckerP4Hit);
7453 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7454 if_printf(ifp, " 0x%08X : "
7455 "CatchupInRuleCheckerDiscards\n",
7456 sblk->stat_CatchupInRuleCheckerDiscards);
7459 if (sblk->stat_CatchupInFTQDiscards) {
7460 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7461 sblk->stat_CatchupInFTQDiscards);
7464 if (sblk->stat_CatchupInMBUFDiscards) {
7465 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7466 sblk->stat_CatchupInMBUFDiscards);
7469 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7470 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7471 sblk->stat_CatchupInRuleCheckerP4Hit);
7475 "----------------------------"
7477 "----------------------------\n");
7481 /****************************************************************************/
7482 /* Prints out a summary of the driver state. */
7486 /****************************************************************************/
7488 bce_dump_driver_state(struct bce_softc *sc)
7490 struct ifnet *ifp = &sc->arpcom.ac_if;
7491 uint32_t val_hi, val_lo;
7494 "-----------------------------"
7496 "-----------------------------\n");
7498 val_hi = BCE_ADDR_HI(sc);
7499 val_lo = BCE_ADDR_LO(sc);
7500 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7501 "virtual address\n", val_hi, val_lo);
7503 val_hi = BCE_ADDR_HI(sc->status_block);
7504 val_lo = BCE_ADDR_LO(sc->status_block);
7505 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7506 "virtual address\n", val_hi, val_lo);
7508 val_hi = BCE_ADDR_HI(sc->stats_block);
7509 val_lo = BCE_ADDR_LO(sc->stats_block);
7510 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7511 "virtual address\n", val_hi, val_lo);
7513 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7514 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7515 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7516 "virtual adddress\n", val_hi, val_lo);
7518 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7519 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7520 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7521 "virtual address\n", val_hi, val_lo);
7523 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7524 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7525 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7526 "virtual address\n", val_hi, val_lo);
7528 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7529 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7530 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7531 "virtual address\n", val_hi, val_lo);
7533 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7534 "h/w intrs\n", sc->interrupts_generated);
7536 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7537 "rx interrupts handled\n", sc->rx_interrupts);
7539 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7540 "tx interrupts handled\n", sc->tx_interrupts);
7542 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7543 "status block index\n", sc->last_status_idx);
7545 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7546 "tx producer index\n",
7547 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7549 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7550 "tx consumer index\n",
7551 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7553 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7554 "tx producer bseq index\n", sc->tx_prod_bseq);
7556 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7557 "rx producer index\n",
7558 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7560 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7561 "rx consumer index\n",
7562 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7564 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7565 "rx producer bseq index\n", sc->rx_prod_bseq);
7567 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7568 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7570 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7571 "free rx_bd's\n", sc->free_rx_bd);
7573 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7574 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7576 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7577 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7579 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7580 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7582 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7585 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7586 sc->tx_hi_watermark, sc->max_tx_bd);
7588 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7589 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7592 "----------------------------"
7594 "----------------------------\n");
7598 /****************************************************************************/
7599 /* Prints out the hardware state through a summary of important registers, */
7600 /* followed by a complete register dump. */
7604 /****************************************************************************/
7606 bce_dump_hw_state(struct bce_softc *sc)
7608 struct ifnet *ifp = &sc->arpcom.ac_if;
7613 "----------------------------"
7615 "----------------------------\n");
7617 if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7619 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7620 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7621 val1, BCE_MISC_ENABLE_STATUS_BITS);
7623 val1 = REG_RD(sc, BCE_DMA_STATUS);
7624 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7626 val1 = REG_RD(sc, BCE_CTX_STATUS);
7627 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7629 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7630 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7631 val1, BCE_EMAC_STATUS);
7633 val1 = REG_RD(sc, BCE_RPM_STATUS);
7634 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7636 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7637 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7638 val1, BCE_TBDR_STATUS);
7640 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7641 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7642 val1, BCE_TDMA_STATUS);
7644 val1 = REG_RD(sc, BCE_HC_STATUS);
7645 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7647 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7648 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7649 val1, BCE_TXP_CPU_STATE);
7651 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7652 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7653 val1, BCE_TPAT_CPU_STATE);
7655 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7656 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7657 val1, BCE_RXP_CPU_STATE);
7659 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7660 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7661 val1, BCE_COM_CPU_STATE);
7663 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7664 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7665 val1, BCE_MCP_CPU_STATE);
7667 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7668 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7669 val1, BCE_CP_CPU_STATE);
7672 "----------------------------"
7674 "----------------------------\n");
7677 "----------------------------"
7679 "----------------------------\n");
7681 for (i = 0x400; i < 0x8000; i += 0x10) {
7682 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7684 REG_RD(sc, i + 0x4),
7685 REG_RD(sc, i + 0x8),
7686 REG_RD(sc, i + 0xc));
7690 "----------------------------"
7692 "----------------------------\n");
7696 /****************************************************************************/
7697 /* Prints out the TXP state. */
7701 /****************************************************************************/
7703 bce_dump_txp_state(struct bce_softc *sc)
7705 struct ifnet *ifp = &sc->arpcom.ac_if;
7710 "----------------------------"
7712 "----------------------------\n");
7714 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7715 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7716 val1, BCE_TXP_CPU_MODE);
7718 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7719 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7720 val1, BCE_TXP_CPU_STATE);
7722 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7723 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7724 val1, BCE_TXP_CPU_EVENT_MASK);
7727 "----------------------------"
7729 "----------------------------\n");
7731 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7732 /* Skip the big blank spaces */
7733 if (i < 0x454000 && i > 0x5ffff) {
7734 if_printf(ifp, "0x%04X: "
7735 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7737 REG_RD_IND(sc, i + 0x4),
7738 REG_RD_IND(sc, i + 0x8),
7739 REG_RD_IND(sc, i + 0xc));
7744 "----------------------------"
7746 "----------------------------\n");
7750 /****************************************************************************/
7751 /* Prints out the RXP state. */
7755 /****************************************************************************/
7757 bce_dump_rxp_state(struct bce_softc *sc)
7759 struct ifnet *ifp = &sc->arpcom.ac_if;
7764 "----------------------------"
7766 "----------------------------\n");
7768 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7769 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7770 val1, BCE_RXP_CPU_MODE);
7772 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7773 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7774 val1, BCE_RXP_CPU_STATE);
7776 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7777 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7778 val1, BCE_RXP_CPU_EVENT_MASK);
7781 "----------------------------"
7783 "----------------------------\n");
7785 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7786 /* Skip the big blank sapces */
7787 if (i < 0xc5400 && i > 0xdffff) {
7788 if_printf(ifp, "0x%04X: "
7789 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7791 REG_RD_IND(sc, i + 0x4),
7792 REG_RD_IND(sc, i + 0x8),
7793 REG_RD_IND(sc, i + 0xc));
7798 "----------------------------"
7800 "----------------------------\n");
7804 /****************************************************************************/
7805 /* Prints out the TPAT state. */
7809 /****************************************************************************/
7811 bce_dump_tpat_state(struct bce_softc *sc)
7813 struct ifnet *ifp = &sc->arpcom.ac_if;
7818 "----------------------------"
7820 "----------------------------\n");
7822 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7823 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7824 val1, BCE_TPAT_CPU_MODE);
7826 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7827 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7828 val1, BCE_TPAT_CPU_STATE);
7830 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7831 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7832 val1, BCE_TPAT_CPU_EVENT_MASK);
7835 "----------------------------"
7837 "----------------------------\n");
7839 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7840 /* Skip the big blank spaces */
7841 if (i < 0x854000 && i > 0x9ffff) {
7842 if_printf(ifp, "0x%04X: "
7843 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7845 REG_RD_IND(sc, i + 0x4),
7846 REG_RD_IND(sc, i + 0x8),
7847 REG_RD_IND(sc, i + 0xc));
7852 "----------------------------"
7854 "----------------------------\n");
7858 /****************************************************************************/
7859 /* Prints out the driver state and then enters the debugger. */
7863 /****************************************************************************/
7865 bce_breakpoint(struct bce_softc *sc)
7868 bce_freeze_controller(sc);
7871 bce_dump_driver_state(sc);
7872 bce_dump_status_block(sc);
7873 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7874 bce_dump_hw_state(sc);
7875 bce_dump_txp_state(sc);
7878 bce_unfreeze_controller(sc);
7881 /* Call the debugger. */
7885 #endif /* BCE_DEBUG */
7888 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7890 struct bce_softc *sc = arg1;
7892 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7893 &sc->bce_tx_quick_cons_trip_int,
7894 BCE_COALMASK_TX_BDS_INT);
7898 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7900 struct bce_softc *sc = arg1;
7902 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7903 &sc->bce_tx_quick_cons_trip,
7904 BCE_COALMASK_TX_BDS);
7908 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7910 struct bce_softc *sc = arg1;
7912 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7913 &sc->bce_tx_ticks_int,
7914 BCE_COALMASK_TX_TICKS_INT);
7918 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7920 struct bce_softc *sc = arg1;
7922 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7924 BCE_COALMASK_TX_TICKS);
7928 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7930 struct bce_softc *sc = arg1;
7932 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7933 &sc->bce_rx_quick_cons_trip_int,
7934 BCE_COALMASK_RX_BDS_INT);
7938 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7940 struct bce_softc *sc = arg1;
7942 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7943 &sc->bce_rx_quick_cons_trip,
7944 BCE_COALMASK_RX_BDS);
7948 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7950 struct bce_softc *sc = arg1;
7952 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7953 &sc->bce_rx_ticks_int,
7954 BCE_COALMASK_RX_TICKS_INT);
7958 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7960 struct bce_softc *sc = arg1;
7962 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7964 BCE_COALMASK_RX_TICKS);
7968 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7969 uint32_t coalchg_mask)
7971 struct bce_softc *sc = arg1;
7972 struct ifnet *ifp = &sc->arpcom.ac_if;
7975 lwkt_serialize_enter(ifp->if_serializer);
7978 error = sysctl_handle_int(oidp, &v, 0, req);
7979 if (!error && req->newptr != NULL) {
7984 sc->bce_coalchg_mask |= coalchg_mask;
7988 lwkt_serialize_exit(ifp->if_serializer);
7993 bce_coal_change(struct bce_softc *sc)
7995 struct ifnet *ifp = &sc->arpcom.ac_if;
7997 ASSERT_SERIALIZED(ifp->if_serializer);
7999 if ((ifp->if_flags & IFF_RUNNING) == 0) {
8000 sc->bce_coalchg_mask = 0;
8004 if (sc->bce_coalchg_mask &
8005 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
8006 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
8007 (sc->bce_tx_quick_cons_trip_int << 16) |
8008 sc->bce_tx_quick_cons_trip);
8010 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
8011 sc->bce_tx_quick_cons_trip,
8012 sc->bce_tx_quick_cons_trip_int);
8016 if (sc->bce_coalchg_mask &
8017 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
8018 REG_WR(sc, BCE_HC_TX_TICKS,
8019 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
8021 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
8022 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
8026 if (sc->bce_coalchg_mask &
8027 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
8028 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
8029 (sc->bce_rx_quick_cons_trip_int << 16) |
8030 sc->bce_rx_quick_cons_trip);
8032 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
8033 sc->bce_rx_quick_cons_trip,
8034 sc->bce_rx_quick_cons_trip_int);
8038 if (sc->bce_coalchg_mask &
8039 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
8040 REG_WR(sc, BCE_HC_RX_TICKS,
8041 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
8043 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
8044 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
8048 sc->bce_coalchg_mask = 0;