2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
36 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
37 * available from http://www.sis.com.tw.
39 * This driver also supports the NatSemi DP83815. Datasheets are
40 * available from http://www.national.com.
42 * Written by Bill Paul <wpaul@ee.columbia.edu>
43 * Electrical Engineering Department
44 * Columbia University, New York City
48 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
49 * simple TX and RX descriptors of 3 longwords in size. The receiver
50 * has a single perfect filter entry for the station address and a
51 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
52 * transceiver while the 7016 requires an external transceiver chip.
53 * Both chips offer the standard bit-bang MII interface as well as
54 * an enchanced PHY interface which simplifies accessing MII registers.
56 * The only downside to this chipset is that RX descriptors must be
60 #include "opt_polling.h"
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/sockio.h>
66 #include <sys/malloc.h>
67 #include <sys/kernel.h>
68 #include <sys/socket.h>
69 #include <sys/sysctl.h>
70 #include <sys/serialize.h>
71 #include <sys/thread2.h>
74 #include <sys/interrupt.h>
77 #include <net/ifq_var.h>
78 #include <net/if_arp.h>
79 #include <net/ethernet.h>
80 #include <net/if_dl.h>
81 #include <net/if_media.h>
82 #include <net/if_types.h>
83 #include <net/vlan/if_vlan_var.h>
87 #include <dev/netif/mii_layer/mii.h>
88 #include <dev/netif/mii_layer/miivar.h>
90 #include <bus/pci/pcidevs.h>
91 #include <bus/pci/pcireg.h>
92 #include <bus/pci/pcivar.h>
94 #define SIS_USEIOSPACE
96 #include "if_sisreg.h"
98 /* "controller miibus0" required. See GENERIC if you get errors here. */
99 #include "miibus_if.h"
102 * Various supported device vendors/types and their names.
104 static struct sis_type sis_devs[] = {
105 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_900, "SiS 900 10/100BaseTX" },
106 { PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7016, "SiS 7016 10/100BaseTX" },
107 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
111 static int sis_probe(device_t);
112 static int sis_attach(device_t);
113 static int sis_detach(device_t);
115 static int sis_newbuf(struct sis_softc *, int, int);
116 static void sis_setup_rxdesc(struct sis_softc *, int);
117 static int sis_encap(struct sis_softc *, struct mbuf **, uint32_t *);
118 static void sis_rxeof(struct sis_softc *);
119 static void sis_rxeoc(struct sis_softc *);
120 static void sis_txeof(struct sis_softc *);
121 static void sis_intr(void *);
122 static void sis_tick(void *);
123 static void sis_start(struct ifnet *);
124 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
125 static void sis_init(void *);
126 static void sis_stop(struct sis_softc *);
127 static void sis_watchdog(struct ifnet *);
128 static void sis_shutdown(device_t);
129 static int sis_ifmedia_upd(struct ifnet *);
130 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
132 static uint16_t sis_reverse(uint16_t);
133 static void sis_delay(struct sis_softc *);
134 static void sis_eeprom_idle(struct sis_softc *);
135 static void sis_eeprom_putbyte(struct sis_softc *, int);
136 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
137 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
139 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
140 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
141 static device_t sis_find_bridge(device_t);
144 static void sis_mii_sync(struct sis_softc *);
145 static void sis_mii_send(struct sis_softc *, uint32_t, int);
146 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
147 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
148 static int sis_miibus_readreg(device_t, int, int);
149 static int sis_miibus_writereg(device_t, int, int, int);
150 static void sis_miibus_statchg(device_t);
152 static void sis_setmulti_sis(struct sis_softc *);
153 static void sis_setmulti_ns(struct sis_softc *);
154 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
155 static void sis_reset(struct sis_softc *);
156 static int sis_list_rx_init(struct sis_softc *);
157 static int sis_list_tx_init(struct sis_softc *);
159 static int sis_dma_alloc(device_t dev);
160 static void sis_dma_free(device_t dev);
161 #ifdef DEVICE_POLLING
162 static poll_handler_t sis_poll;
164 #ifdef SIS_USEIOSPACE
165 #define SIS_RES SYS_RES_IOPORT
166 #define SIS_RID SIS_PCI_LOIO
168 #define SIS_RES SYS_RES_MEMORY
169 #define SIS_RID SIS_PCI_LOMEM
172 static device_method_t sis_methods[] = {
173 /* Device interface */
174 DEVMETHOD(device_probe, sis_probe),
175 DEVMETHOD(device_attach, sis_attach),
176 DEVMETHOD(device_detach, sis_detach),
177 DEVMETHOD(device_shutdown, sis_shutdown),
180 DEVMETHOD(bus_print_child, bus_generic_print_child),
181 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
184 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
185 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
186 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
191 static driver_t sis_driver = {
194 sizeof(struct sis_softc)
197 static devclass_t sis_devclass;
199 DECLARE_DUMMY_MODULE(if_sis);
200 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, NULL, NULL);
201 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, NULL, NULL);
203 #define SIS_SETBIT(sc, reg, x) \
204 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
206 #define SIS_CLRBIT(sc, reg, x) \
207 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
210 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
213 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
216 * Routine to reverse the bits in a word. Stolen almost
217 * verbatim from /usr/games/fortune.
220 sis_reverse(uint16_t n)
222 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
223 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
224 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
225 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
231 sis_delay(struct sis_softc *sc)
235 for (idx = (300 / 33) + 1; idx > 0; idx--)
236 CSR_READ_4(sc, SIS_CSR);
240 sis_eeprom_idle(struct sis_softc *sc)
244 SIO_SET(SIS_EECTL_CSEL);
246 SIO_SET(SIS_EECTL_CLK);
249 for (i = 0; i < 25; i++) {
250 SIO_CLR(SIS_EECTL_CLK);
252 SIO_SET(SIS_EECTL_CLK);
256 SIO_CLR(SIS_EECTL_CLK);
258 SIO_CLR(SIS_EECTL_CSEL);
260 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
264 * Send a read command and address to the EEPROM, check for ACK.
267 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
271 d = addr | SIS_EECMD_READ;
274 * Feed in each bit and stobe the clock.
276 for (i = 0x400; i; i >>= 1) {
278 SIO_SET(SIS_EECTL_DIN);
280 SIO_CLR(SIS_EECTL_DIN);
282 SIO_SET(SIS_EECTL_CLK);
284 SIO_CLR(SIS_EECTL_CLK);
290 * Read a word of data stored in the EEPROM at address 'addr.'
293 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
298 /* Force EEPROM to idle state. */
301 /* Enter EEPROM access mode. */
303 SIO_CLR(SIS_EECTL_CLK);
305 SIO_SET(SIS_EECTL_CSEL);
309 * Send address of word we want to read.
311 sis_eeprom_putbyte(sc, addr);
314 * Start reading bits from EEPROM.
316 for (i = 0x8000; i; i >>= 1) {
317 SIO_SET(SIS_EECTL_CLK);
319 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
322 SIO_CLR(SIS_EECTL_CLK);
326 /* Turn off EEPROM access mode. */
333 * Read a sequence of words from the EEPROM.
336 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
339 uint16_t word = 0, *ptr;
341 for (i = 0; i < cnt; i++) {
342 sis_eeprom_getword(sc, off + i, &word);
343 ptr = (uint16_t *)(dest + (i * 2));
353 sis_find_bridge(device_t dev)
355 devclass_t pci_devclass;
356 device_t *pci_devices;
358 device_t *pci_children;
359 int pci_childcount = 0;
360 device_t *busp, *childp;
361 device_t child = NULL;
364 if ((pci_devclass = devclass_find("pci")) == NULL)
367 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
369 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
371 device_get_children(*busp, &pci_children, &pci_childcount);
372 for (j = 0, childp = pci_children; j < pci_childcount;
374 if (pci_get_vendor(*childp) == PCI_VENDOR_SIS &&
375 pci_get_device(*childp) == 0x0008) {
383 kfree(pci_devices, M_TEMP);
384 kfree(pci_children, M_TEMP);
389 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
395 bus_space_tag_t btag;
397 bridge = sis_find_bridge(dev);
400 reg = pci_read_config(bridge, 0x48, 1);
401 pci_write_config(bridge, 0x48, reg|0x40, 1);
404 btag = I386_BUS_SPACE_IO;
406 for (i = 0; i < cnt; i++) {
407 bus_space_write_1(btag, 0x0, 0x70, i + off);
408 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
411 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
415 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
417 uint32_t filtsave, csrsave;
419 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
420 csrsave = CSR_READ_4(sc, SIS_CSR);
422 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
423 CSR_WRITE_4(sc, SIS_CSR, 0);
425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
428 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
429 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
430 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
431 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
432 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
434 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
435 CSR_WRITE_4(sc, SIS_CSR, csrsave);
440 * Sync the PHYs by setting data bit and strobing the clock 32 times.
443 sis_mii_sync(struct sis_softc *sc)
447 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
449 for (i = 0; i < 32; i++) {
450 SIO_SET(SIS_MII_CLK);
452 SIO_CLR(SIS_MII_CLK);
458 * Clock a series of bits through the MII.
461 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
465 SIO_CLR(SIS_MII_CLK);
467 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
469 SIO_SET(SIS_MII_DATA);
471 SIO_CLR(SIS_MII_DATA);
473 SIO_CLR(SIS_MII_CLK);
475 SIO_SET(SIS_MII_CLK);
480 * Read an PHY register through the MII.
483 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
488 * Set up frame for RX.
490 frame->mii_stdelim = SIS_MII_STARTDELIM;
491 frame->mii_opcode = SIS_MII_READOP;
492 frame->mii_turnaround = 0;
498 SIO_SET(SIS_MII_DIR);
503 * Send command/address info.
505 sis_mii_send(sc, frame->mii_stdelim, 2);
506 sis_mii_send(sc, frame->mii_opcode, 2);
507 sis_mii_send(sc, frame->mii_phyaddr, 5);
508 sis_mii_send(sc, frame->mii_regaddr, 5);
511 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
513 SIO_SET(SIS_MII_CLK);
517 SIO_CLR(SIS_MII_DIR);
520 SIO_CLR(SIS_MII_CLK);
522 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
523 SIO_SET(SIS_MII_CLK);
527 * Now try reading data bits. If the ack failed, we still
528 * need to clock through 16 cycles to keep the PHY(s) in sync.
531 for(i = 0; i < 16; i++) {
532 SIO_CLR(SIS_MII_CLK);
534 SIO_SET(SIS_MII_CLK);
540 for (i = 0x8000; i; i >>= 1) {
541 SIO_CLR(SIS_MII_CLK);
544 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
545 frame->mii_data |= i;
548 SIO_SET(SIS_MII_CLK);
554 SIO_CLR(SIS_MII_CLK);
556 SIO_SET(SIS_MII_CLK);
565 * Write to a PHY register through the MII.
568 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
571 * Set up frame for TX.
574 frame->mii_stdelim = SIS_MII_STARTDELIM;
575 frame->mii_opcode = SIS_MII_WRITEOP;
576 frame->mii_turnaround = SIS_MII_TURNAROUND;
579 * Turn on data output.
581 SIO_SET(SIS_MII_DIR);
585 sis_mii_send(sc, frame->mii_stdelim, 2);
586 sis_mii_send(sc, frame->mii_opcode, 2);
587 sis_mii_send(sc, frame->mii_phyaddr, 5);
588 sis_mii_send(sc, frame->mii_regaddr, 5);
589 sis_mii_send(sc, frame->mii_turnaround, 2);
590 sis_mii_send(sc, frame->mii_data, 16);
593 SIO_SET(SIS_MII_CLK);
595 SIO_CLR(SIS_MII_CLK);
601 SIO_CLR(SIS_MII_DIR);
607 sis_miibus_readreg(device_t dev, int phy, int reg)
609 struct sis_softc *sc;
610 struct sis_mii_frame frame;
612 sc = device_get_softc(dev);
614 if (sc->sis_type == SIS_TYPE_83815) {
618 * The NatSemi chip can take a while after
619 * a reset to come ready, during which the BMSR
620 * returns a value of 0. This is *never* supposed
621 * to happen: some of the BMSR bits are meant to
622 * be hardwired in the on position, and this can
623 * confuse the miibus code a bit during the probe
624 * and attach phase. So we make an effort to check
625 * for this condition and wait for it to clear.
627 if (!CSR_READ_4(sc, NS_BMSR))
629 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
632 * Chipsets < SIS_635 seem not to be able to read/write
633 * through mdio. Use the enhanced PHY access register
636 if (sc->sis_type == SIS_TYPE_900 &&
637 sc->sis_rev < SIS_REV_635) {
643 CSR_WRITE_4(sc, SIS_PHYCTL,
644 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
645 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
647 for (i = 0; i < SIS_TIMEOUT; i++) {
648 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
652 if (i == SIS_TIMEOUT) {
653 device_printf(dev, "PHY failed to come ready\n");
657 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
664 bzero((char *)&frame, sizeof(frame));
666 frame.mii_phyaddr = phy;
667 frame.mii_regaddr = reg;
668 sis_mii_readreg(sc, &frame);
670 return(frame.mii_data);
675 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
677 struct sis_softc *sc;
678 struct sis_mii_frame frame;
680 sc = device_get_softc(dev);
682 if (sc->sis_type == SIS_TYPE_83815) {
685 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
689 if (sc->sis_type == SIS_TYPE_900 &&
690 sc->sis_rev < SIS_REV_635) {
696 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
697 (reg << 6) | SIS_PHYOP_WRITE);
698 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
700 for (i = 0; i < SIS_TIMEOUT; i++) {
701 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
705 if (i == SIS_TIMEOUT)
706 device_printf(dev, "PHY failed to come ready\n");
708 bzero((char *)&frame, sizeof(frame));
710 frame.mii_phyaddr = phy;
711 frame.mii_regaddr = reg;
712 frame.mii_data = data;
713 sis_mii_writereg(sc, &frame);
719 sis_miibus_statchg(device_t dev)
721 struct sis_softc *sc;
723 sc = device_get_softc(dev);
728 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
734 /* Compute CRC for the address value. */
735 crc = 0xFFFFFFFF; /* initial value */
737 for (i = 0; i < 6; i++) {
739 for (j = 0; j < 8; j++) {
740 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
744 crc = (crc ^ 0x04c11db6) | carry;
749 * return the filter bit position
751 * The NatSemi chip has a 512-bit filter, which is
752 * different than the SiS, so we special-case it.
754 if (sc->sis_type == SIS_TYPE_83815)
756 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
763 sis_setmulti_ns(struct sis_softc *sc)
766 struct ifmultiaddr *ifma;
767 uint32_t h = 0, i, filtsave;
770 ifp = &sc->arpcom.ac_if;
772 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
773 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
774 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
779 * We have to explicitly enable the multicast hash table
780 * on the NatSemi chip if we want to use it, which we do.
782 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
783 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
785 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
787 /* first, zot all the existing hash bits */
788 for (i = 0; i < 32; i++) {
789 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
790 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
793 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
794 if (ifma->ifma_addr->sa_family != AF_LINK)
797 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
800 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
803 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
806 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
810 sis_setmulti_sis(struct sis_softc *sc)
813 struct ifmultiaddr *ifma;
814 uint32_t h, i, n, ctl;
817 ifp = &sc->arpcom.ac_if;
819 /* hash table size */
820 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
825 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
827 if (ifp->if_flags & IFF_BROADCAST)
828 ctl |= SIS_RXFILTCTL_BROAD;
830 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
831 ctl |= SIS_RXFILTCTL_ALLMULTI;
832 if (ifp->if_flags & IFF_PROMISC)
833 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
834 for (i = 0; i < n; i++)
837 for (i = 0; i < n; i++)
840 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
841 if (ifma->ifma_addr->sa_family != AF_LINK)
844 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
845 hashes[h >> 4] |= 1 << (h & 0xf);
849 ctl |= SIS_RXFILTCTL_ALLMULTI;
850 for (i = 0; i < n; i++)
855 for (i = 0; i < n; i++) {
856 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
857 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
860 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
864 sis_reset(struct sis_softc *sc)
866 struct ifnet *ifp = &sc->arpcom.ac_if;
869 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
871 for (i = 0; i < SIS_TIMEOUT; i++) {
872 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
876 if (i == SIS_TIMEOUT)
877 if_printf(ifp, "reset never completed\n");
879 /* Wait a little while for the chip to get its brains in order. */
883 * If this is a NetSemi chip, make sure to clear
886 if (sc->sis_type == SIS_TYPE_83815) {
887 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
888 CSR_WRITE_4(sc, NS_CLKRUN, 0);
893 * Probe for an SiS chip. Check the PCI vendor and device
894 * IDs against our list and return a device name if we find a match.
897 sis_probe(device_t dev)
903 while(t->sis_name != NULL) {
904 if ((pci_get_vendor(dev) == t->sis_vid) &&
905 (pci_get_device(dev) == t->sis_did)) {
906 device_set_desc(dev, t->sis_name);
916 * Attach the interface. Allocate softc structures, do ifmedia
917 * setup and ethernet/BPF attach.
920 sis_attach(device_t dev)
922 uint8_t eaddr[ETHER_ADDR_LEN];
924 struct sis_softc *sc;
926 int error, rid, waittime;
928 error = waittime = 0;
929 sc = device_get_softc(dev);
931 if (pci_get_device(dev) == PCI_PRODUCT_SIS_900)
932 sc->sis_type = SIS_TYPE_900;
933 if (pci_get_device(dev) == PCI_PRODUCT_SIS_7016)
934 sc->sis_type = SIS_TYPE_7016;
935 if (pci_get_vendor(dev) == PCI_VENDOR_NS)
936 sc->sis_type = SIS_TYPE_83815;
938 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
941 * Handle power management nonsense.
944 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
945 if (command == 0x01) {
947 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
948 if (command & SIS_PSTATE_MASK) {
949 uint32_t iobase, membase, irq;
951 /* Save important PCI config data. */
952 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
953 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
954 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
956 /* Reset the power state. */
957 device_printf(dev, "chip is in D%d power mode "
958 "-- setting to D0\n", command & SIS_PSTATE_MASK);
959 command &= 0xFFFFFFFC;
960 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
962 /* Restore PCI config data. */
963 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
964 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
965 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
970 * Map control/status registers.
972 command = pci_read_config(dev, PCIR_COMMAND, 4);
973 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
974 pci_write_config(dev, PCIR_COMMAND, command, 4);
975 command = pci_read_config(dev, PCIR_COMMAND, 4);
977 #ifdef SIS_USEIOSPACE
978 if (!(command & PCIM_CMD_PORTEN)) {
979 device_printf(dev, "failed to enable I/O ports!\n");
984 if (!(command & PCIM_CMD_MEMEN)) {
985 device_printf(dev, "failed to enable memory mapping!\n");
992 sc->sis_res = bus_alloc_resource_any(dev, SIS_RES, &rid, RF_ACTIVE);
994 if (sc->sis_res == NULL) {
995 device_printf(dev, "couldn't map ports/memory\n");
1000 sc->sis_btag = rman_get_bustag(sc->sis_res);
1001 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1003 /* Allocate interrupt */
1005 sc->sis_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1006 RF_SHAREABLE | RF_ACTIVE);
1008 if (sc->sis_irq == NULL) {
1009 device_printf(dev, "couldn't map interrupt\n");
1014 /* Reset the adapter. */
1017 if (sc->sis_type == SIS_TYPE_900 &&
1018 (sc->sis_rev == SIS_REV_635 ||
1019 sc->sis_rev == SIS_REV_900B)) {
1020 SIO_SET(SIS_CFG_RND_CNT);
1021 SIO_SET(SIS_CFG_PERR_DETECT);
1025 * Get station address from the EEPROM.
1027 switch (pci_get_vendor(dev)) {
1030 * Reading the MAC address out of the EEPROM on
1031 * the NatSemi chip takes a bit more work than
1032 * you'd expect. The address spans 4 16-bit words,
1033 * with the first word containing only a single bit.
1034 * You have to shift everything over one bit to
1035 * get it aligned properly. Also, the bits are
1036 * stored backwards (the LSB is really the MSB,
1037 * and so on) so you have to reverse them in order
1038 * to get the MAC address into the form we want.
1039 * Why? Who the hell knows.
1044 sis_read_eeprom(sc, (caddr_t)&tmp,
1045 NS_EE_NODEADDR, 4, 0);
1047 /* Shift everything over one bit. */
1048 tmp[3] = tmp[3] >> 1;
1049 tmp[3] |= tmp[2] << 15;
1050 tmp[2] = tmp[2] >> 1;
1051 tmp[2] |= tmp[1] << 15;
1052 tmp[1] = tmp[1] >> 1;
1053 tmp[1] |= tmp[0] << 15;
1055 /* Now reverse all the bits. */
1056 tmp[3] = sis_reverse(tmp[3]);
1057 tmp[2] = sis_reverse(tmp[2]);
1058 tmp[1] = sis_reverse(tmp[1]);
1060 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1063 case PCI_VENDOR_SIS:
1067 * If this is a SiS 630E chipset with an embedded
1068 * SiS 900 controller, we have to read the MAC address
1069 * from the APC CMOS RAM. Our method for doing this
1070 * is very ugly since we have to reach out and grab
1071 * ahold of hardware for which we cannot properly
1072 * allocate resources. This code is only compiled on
1073 * the i386 architecture since the SiS 630E chipset
1074 * is for x86 motherboards only. Note that there are
1075 * a lot of magic numbers in this hack. These are
1076 * taken from SiS's Linux driver. I'd like to replace
1077 * them with proper symbolic definitions, but that
1078 * requires some datasheets that I don't have access
1081 if (sc->sis_rev == SIS_REV_630S ||
1082 sc->sis_rev == SIS_REV_630E ||
1083 sc->sis_rev == SIS_REV_630EA1)
1084 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1086 else if (sc->sis_rev == SIS_REV_635 ||
1087 sc->sis_rev == SIS_REV_630ET)
1088 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1089 else if (sc->sis_rev == SIS_REV_96x) {
1091 * Allow to read EEPROM from LAN. It is shared
1092 * between a 1394 controller and the NIC and each
1093 * time we access it, we need to set SIS_EECMD_REQ.
1095 SIO_SET(SIS_EECMD_REQ);
1096 for (waittime = 0; waittime < SIS_TIMEOUT;
1098 /* Force EEPROM to idle state. */
1099 sis_eeprom_idle(sc);
1100 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1101 sis_read_eeprom(sc, (caddr_t)&eaddr,
1102 SIS_EE_NODEADDR, 3, 0);
1108 * Set SIS_EECTL_CLK to high, so a other master
1109 * can operate on the i2c bus.
1111 SIO_SET(SIS_EECTL_CLK);
1112 /* Refuse EEPROM access by LAN */
1113 SIO_SET(SIS_EECMD_DONE);
1116 sis_read_eeprom(sc, (caddr_t)&eaddr,
1117 SIS_EE_NODEADDR, 3, 0);
1121 callout_init(&sc->sis_timer);
1123 error = sis_dma_alloc(dev);
1127 ifp = &sc->arpcom.ac_if;
1129 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1130 ifp->if_mtu = ETHERMTU;
1131 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1132 ifp->if_ioctl = sis_ioctl;
1133 ifp->if_start = sis_start;
1134 ifp->if_watchdog = sis_watchdog;
1135 ifp->if_init = sis_init;
1136 ifp->if_baudrate = 10000000;
1137 ifq_set_maxlen(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
1138 ifq_set_ready(&ifp->if_snd);
1139 #ifdef DEVICE_POLLING
1140 ifp->if_poll = sis_poll;
1142 ifp->if_capenable = ifp->if_capabilities;
1147 if (mii_phy_probe(dev, &sc->sis_miibus,
1148 sis_ifmedia_upd, sis_ifmedia_sts)) {
1149 device_printf(dev, "MII without any PHY!\n");
1155 * Call MI attach routine.
1157 ether_ifattach(ifp, eaddr, NULL);
1160 * Tell the upper layer(s) we support long frames.
1162 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1164 error = bus_setup_intr(dev, sc->sis_irq, INTR_MPSAFE,
1167 ifp->if_serializer);
1170 device_printf(dev, "couldn't set up irq\n");
1171 ether_ifdetach(ifp);
1175 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sis_irq));
1176 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1186 * Shutdown hardware and free up resources. It is called in both the error case
1187 * and the normal detach case so it needs to be careful about only freeing
1188 * resources that have actually been allocated.
1191 sis_detach(device_t dev)
1193 struct sis_softc *sc = device_get_softc(dev);
1194 struct ifnet *ifp = &sc->arpcom.ac_if;
1197 if (device_is_attached(dev)) {
1198 lwkt_serialize_enter(ifp->if_serializer);
1201 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1202 lwkt_serialize_exit(ifp->if_serializer);
1204 ether_ifdetach(ifp);
1207 device_delete_child(dev, sc->sis_miibus);
1208 bus_generic_detach(dev);
1211 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1213 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1221 * Initialize the transmit descriptors.
1224 sis_list_tx_init(struct sis_softc *sc)
1226 struct sis_list_data *ld = &sc->sis_ldata;
1227 struct sis_chain_data *cd = &sc->sis_cdata;
1230 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1234 * Link the TX desc together
1236 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1237 paddr = ld->sis_tx_paddr + (nexti * sizeof(struct sis_desc));
1238 ld->sis_tx_list[i].sis_next = paddr;
1240 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1246 * Initialize the RX descriptors and allocate mbufs for them. Note that
1247 * we arrange the descriptors in a closed ring, so that the last descriptor
1248 * points back to the first.
1251 sis_list_rx_init(struct sis_softc *sc)
1253 struct sis_list_data *ld = &sc->sis_ldata;
1254 struct sis_chain_data *cd = &sc->sis_cdata;
1257 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1261 error = sis_newbuf(sc, i, 1);
1266 * Link the RX desc together
1268 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1269 paddr = ld->sis_rx_paddr + (nexti * sizeof(struct sis_desc));
1270 ld->sis_rx_list[i].sis_next = paddr;
1272 cd->sis_rx_prod = 0;
1278 * Initialize an RX descriptor and attach an MBUF cluster.
1281 sis_newbuf(struct sis_softc *sc, int idx, int init)
1283 struct sis_chain_data *cd = &sc->sis_cdata;
1284 struct sis_rx_data *rd = &cd->sis_rx_data[idx];
1285 bus_dma_segment_t seg;
1290 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1293 if_printf(&sc->arpcom.ac_if, "can't alloc RX mbuf\n");
1296 m->m_len = m->m_pkthdr.len = MCLBYTES;
1298 /* Try loading the mbuf into tmp DMA map */
1299 error = bus_dmamap_load_mbuf_segment(cd->sis_rxbuf_tag,
1300 cd->sis_rx_tmpmap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1304 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1308 /* Unload the currently loaded mbuf */
1309 if (rd->sis_mbuf != NULL) {
1310 bus_dmamap_sync(cd->sis_rxbuf_tag, rd->sis_map,
1311 BUS_DMASYNC_POSTREAD);
1312 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
1316 map = cd->sis_rx_tmpmap;
1317 cd->sis_rx_tmpmap = rd->sis_map;
1320 /* Save necessary information */
1322 rd->sis_paddr = seg.ds_addr;
1324 sis_setup_rxdesc(sc, idx);
1329 sis_setup_rxdesc(struct sis_softc *sc, int idx)
1331 struct sis_desc *c = &sc->sis_ldata.sis_rx_list[idx];
1333 /* Setup the RX desc */
1334 c->sis_ctl = SIS_RXLEN;
1335 c->sis_ptr = sc->sis_cdata.sis_rx_data[idx].sis_paddr;
1339 * A frame has been uploaded: pass the resulting mbuf chain up to
1340 * the higher level protocols.
1343 sis_rxeof(struct sis_softc *sc)
1345 struct ifnet *ifp = &sc->arpcom.ac_if;
1346 int i, total_len = 0;
1349 i = sc->sis_cdata.sis_rx_prod;
1350 while (SIS_OWNDESC(&sc->sis_ldata.sis_rx_list[i])) {
1351 struct sis_desc *cur_rx;
1352 struct sis_rx_data *rd;
1356 #ifdef DEVICE_POLLING
1357 if (ifp->if_flags & IFF_POLLING) {
1358 if (sc->rxcycles <= 0)
1362 #endif /* DEVICE_POLLING */
1364 cur_rx = &sc->sis_ldata.sis_rx_list[idx];
1365 rd = &sc->sis_cdata.sis_rx_data[idx];
1367 rxstat = cur_rx->sis_rxstat;
1368 total_len = SIS_RXBYTES(cur_rx);
1372 SIS_INC(i, SIS_RX_LIST_CNT);
1375 * If an error occurs, update stats, clear the
1376 * status word and leave the mbuf cluster in place:
1377 * it should simply get re-used next time this descriptor
1378 * comes up in the ring.
1380 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1382 if (rxstat & SIS_RXSTAT_COLL)
1383 ifp->if_collisions++;
1384 sis_setup_rxdesc(sc, idx);
1388 /* No errors; receive the packet. */
1389 if (sis_newbuf(sc, idx, 0) == 0) {
1390 m->m_pkthdr.len = m->m_len = total_len;
1391 m->m_pkthdr.rcvif = ifp;
1394 sis_setup_rxdesc(sc, idx);
1399 ifp->if_input(ifp, m);
1401 sc->sis_cdata.sis_rx_prod = i;
1405 sis_rxeoc(struct sis_softc *sc)
1412 * A frame was downloaded to the chip. It's safe for us to clean up
1417 sis_txeof(struct sis_softc *sc)
1419 struct ifnet *ifp = &sc->arpcom.ac_if;
1420 struct sis_chain_data *cd = &sc->sis_cdata;
1424 * Go through our tx list and free mbufs for those
1425 * frames that have been transmitted.
1427 for (idx = sc->sis_cdata.sis_tx_cons; sc->sis_cdata.sis_tx_cnt > 0;
1428 sc->sis_cdata.sis_tx_cnt--, SIS_INC(idx, SIS_TX_LIST_CNT) ) {
1429 struct sis_desc *cur_tx;
1430 struct sis_tx_data *td;
1432 cur_tx = &sc->sis_ldata.sis_tx_list[idx];
1433 td = &cd->sis_tx_data[idx];
1435 if (SIS_OWNDESC(cur_tx))
1438 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE)
1441 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1443 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1444 ifp->if_collisions++;
1445 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1446 ifp->if_collisions++;
1449 ifp->if_collisions +=
1450 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1453 if (td->sis_mbuf != NULL) {
1454 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
1455 m_freem(td->sis_mbuf);
1456 td->sis_mbuf = NULL;
1460 if (idx != sc->sis_cdata.sis_tx_cons) {
1461 /* we freed up some buffers */
1462 sc->sis_cdata.sis_tx_cons = idx;
1465 if (cd->sis_tx_cnt == 0)
1467 if (!SIS_IS_OACTIVE(sc))
1468 ifp->if_flags &= ~IFF_OACTIVE;
1474 struct sis_softc *sc = xsc;
1475 struct mii_data *mii;
1476 struct ifnet *ifp = &sc->arpcom.ac_if;
1478 lwkt_serialize_enter(ifp->if_serializer);
1480 mii = device_get_softc(sc->sis_miibus);
1483 if (!sc->sis_link) {
1485 if (mii->mii_media_status & IFM_ACTIVE &&
1486 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1488 if (!ifq_is_empty(&ifp->if_snd))
1492 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1493 lwkt_serialize_exit(ifp->if_serializer);
1496 #ifdef DEVICE_POLLING
1499 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1501 struct sis_softc *sc = ifp->if_softc;
1505 /* disable interrupts */
1506 CSR_WRITE_4(sc, SIS_IER, 0);
1508 case POLL_DEREGISTER:
1509 /* enable interrupts */
1510 CSR_WRITE_4(sc, SIS_IER, 1);
1514 * On the sis, reading the status register also clears it.
1515 * So before returning to intr mode we must make sure that all
1516 * possible pending sources of interrupts have been served.
1517 * In practice this means run to completion the *eof routines,
1518 * and then call the interrupt routine
1520 sc->rxcycles = count;
1523 if (!ifq_is_empty(&ifp->if_snd))
1526 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1529 /* Reading the ISR register clears all interrupts. */
1530 status = CSR_READ_4(sc, SIS_ISR);
1532 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1535 if (status & (SIS_ISR_RX_IDLE))
1536 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1538 if (status & SIS_ISR_SYSERR) {
1546 #endif /* DEVICE_POLLING */
1551 struct sis_softc *sc;
1556 ifp = &sc->arpcom.ac_if;
1558 /* Supress unwanted interrupts */
1559 if (!(ifp->if_flags & IFF_UP)) {
1564 /* Disable interrupts. */
1565 CSR_WRITE_4(sc, SIS_IER, 0);
1568 /* Reading the ISR register clears all interrupts. */
1569 status = CSR_READ_4(sc, SIS_ISR);
1571 if ((status & SIS_INTRS) == 0)
1575 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1580 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1583 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1586 if (status & (SIS_ISR_RX_IDLE))
1587 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1589 if (status & SIS_ISR_SYSERR) {
1595 /* Re-enable interrupts. */
1596 CSR_WRITE_4(sc, SIS_IER, 1);
1598 if (!ifq_is_empty(&ifp->if_snd))
1603 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1604 * pointers to the fragment pointers.
1607 sis_encap(struct sis_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1609 struct sis_chain_data *cd = &sc->sis_cdata;
1610 struct sis_list_data *ld = &sc->sis_ldata;
1611 bus_dma_segment_t segs[SIS_NSEGS];
1613 int frag, cur, maxsegs, nsegs, error, i;
1615 maxsegs = SIS_TX_LIST_CNT - SIS_NSEGS_RESERVED - cd->sis_tx_cnt;
1616 KASSERT(maxsegs >= 1, ("not enough TX descs\n"));
1617 if (maxsegs > SIS_NSEGS)
1618 maxsegs = SIS_NSEGS;
1620 map = cd->sis_tx_data[*txidx].sis_map;
1621 error = bus_dmamap_load_mbuf_defrag(cd->sis_txbuf_tag, map, m_head,
1622 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1628 bus_dmamap_sync(cd->sis_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1630 cur = frag = *txidx;
1631 for (i = 0; i < nsegs; ++i) {
1632 struct sis_desc *f = &ld->sis_tx_list[frag];
1634 f->sis_ctl = SIS_CMDSTS_MORE | segs[i].ds_len;
1635 f->sis_ptr = segs[i].ds_addr;
1637 f->sis_ctl |= SIS_CMDSTS_OWN;
1640 SIS_INC(frag, SIS_TX_LIST_CNT);
1642 ld->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1643 ld->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1646 cd->sis_tx_data[*txidx].sis_map = cd->sis_tx_data[cur].sis_map;
1647 cd->sis_tx_data[cur].sis_map = map;
1649 cd->sis_tx_data[cur].sis_mbuf = *m_head;
1651 cd->sis_tx_cnt += nsegs;
1658 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1659 * to the mbuf data regions directly in the transmit lists. We also save a
1660 * copy of the pointers since the transmit list fragment pointers are
1661 * physical addresses.
1665 sis_start(struct ifnet *ifp)
1667 struct sis_softc *sc = ifp->if_softc;
1668 int need_trans, error;
1671 if (!sc->sis_link) {
1672 ifq_purge(&ifp->if_snd);
1676 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1679 idx = sc->sis_cdata.sis_tx_prod;
1682 while (sc->sis_cdata.sis_tx_data[idx].sis_mbuf == NULL) {
1683 struct mbuf *m_head;
1686 * If there's no way we can send any packets, return now.
1688 if (SIS_IS_OACTIVE(sc)) {
1689 ifp->if_flags |= IFF_OACTIVE;
1693 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1697 error = sis_encap(sc, &m_head, &idx);
1700 if (sc->sis_cdata.sis_tx_cnt == 0) {
1703 ifp->if_flags |= IFF_OACTIVE;
1710 * If there's a BPF listener, bounce a copy of this frame
1713 BPF_MTAP(ifp, m_head);
1720 sc->sis_cdata.sis_tx_prod = idx;
1721 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1724 * Set a timeout in case the chip goes out to lunch.
1732 struct sis_softc *sc = xsc;
1733 struct ifnet *ifp = &sc->arpcom.ac_if;
1734 struct mii_data *mii;
1737 * Cancel pending I/O and free all RX/TX buffers.
1741 mii = device_get_softc(sc->sis_miibus);
1743 /* Set MAC address */
1744 if (sc->sis_type == SIS_TYPE_83815) {
1745 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1746 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1747 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1748 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1749 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1750 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1751 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1752 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1753 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1755 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1756 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1757 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1758 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1759 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1760 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1761 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1762 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1763 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1766 /* Init circular RX list. */
1767 if (sis_list_rx_init(sc)) {
1768 if_printf(ifp, "initialization failed: "
1769 "no memory for rx buffers\n");
1775 * Init tx descriptors.
1777 sis_list_tx_init(sc);
1780 * For the NatSemi chip, we have to explicitly enable the
1781 * reception of ARP frames, as well as turn on the 'perfect
1782 * match' filter where we store the station address, otherwise
1783 * we won't receive unicasts meant for this host.
1785 if (sc->sis_type == SIS_TYPE_83815) {
1786 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1787 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1790 /* If we want promiscuous mode, set the allframes bit. */
1791 if (ifp->if_flags & IFF_PROMISC)
1792 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1794 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1797 * Set the capture broadcast bit to capture broadcast frames.
1799 if (ifp->if_flags & IFF_BROADCAST)
1800 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1802 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1805 * Load the multicast filter.
1807 if (sc->sis_type == SIS_TYPE_83815)
1808 sis_setmulti_ns(sc);
1810 sis_setmulti_sis(sc);
1812 /* Turn the receive filter on */
1813 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1816 * Load the address of the RX and TX lists.
1818 CSR_WRITE_4(sc, SIS_RX_LISTPTR, sc->sis_ldata.sis_rx_paddr);
1819 CSR_WRITE_4(sc, SIS_TX_LISTPTR, sc->sis_ldata.sis_tx_paddr);
1821 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1822 * the PCI bus. When this bit is set, the Max DMA Burst Size
1823 * for TX/RX DMA should be no larger than 16 double words.
1825 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1826 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1828 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1830 /* Accept Long Packets for VLAN support */
1831 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1833 /* Set TX configuration */
1834 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1835 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1837 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1839 /* Set full/half duplex mode. */
1840 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1841 SIS_SETBIT(sc, SIS_TX_CFG,
1842 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1843 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1845 SIS_CLRBIT(sc, SIS_TX_CFG,
1846 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1847 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1851 * Enable interrupts.
1853 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1854 #ifdef DEVICE_POLLING
1856 * ... only enable interrupts if we are not polling, make sure
1857 * they are off otherwise.
1859 if (ifp->if_flags & IFF_POLLING)
1860 CSR_WRITE_4(sc, SIS_IER, 0);
1862 #endif /* DEVICE_POLLING */
1863 CSR_WRITE_4(sc, SIS_IER, 1);
1865 /* Enable receiver and transmitter. */
1866 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1867 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1874 * Page 75 of the DP83815 manual recommends the
1875 * following register settings "for optimum
1876 * performance." Note however that at least three
1877 * of the registers are listed as "reserved" in
1878 * the register map, so who knows what they do.
1880 if (sc->sis_type == SIS_TYPE_83815) {
1881 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1882 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1883 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1884 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1885 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1888 ifp->if_flags |= IFF_RUNNING;
1889 ifp->if_flags &= ~IFF_OACTIVE;
1891 callout_reset(&sc->sis_timer, hz, sis_tick, sc);
1895 * Set media options.
1898 sis_ifmedia_upd(struct ifnet *ifp)
1900 struct sis_softc *sc;
1901 struct mii_data *mii;
1905 mii = device_get_softc(sc->sis_miibus);
1907 if (mii->mii_instance) {
1908 struct mii_softc *miisc;
1909 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1910 mii_phy_reset(miisc);
1918 * Report current media status.
1921 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1923 struct sis_softc *sc;
1924 struct mii_data *mii;
1928 mii = device_get_softc(sc->sis_miibus);
1930 ifmr->ifm_active = mii->mii_media_active;
1931 ifmr->ifm_status = mii->mii_media_status;
1935 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1937 struct sis_softc *sc = ifp->if_softc;
1938 struct ifreq *ifr = (struct ifreq *) data;
1939 struct mii_data *mii;
1944 if (ifp->if_flags & IFF_UP) {
1947 if (ifp->if_flags & IFF_RUNNING)
1954 if (sc->sis_type == SIS_TYPE_83815)
1955 sis_setmulti_ns(sc);
1957 sis_setmulti_sis(sc);
1962 mii = device_get_softc(sc->sis_miibus);
1963 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1966 error = ether_ioctl(ifp, command, data);
1973 sis_watchdog(struct ifnet *ifp)
1975 struct sis_softc *sc;
1980 if_printf(ifp, "watchdog timeout\n");
1986 if (!ifq_is_empty(&ifp->if_snd))
1991 * Stop the adapter and free any mbufs allocated to the
1995 sis_stop(struct sis_softc *sc)
1997 struct ifnet *ifp = &sc->arpcom.ac_if;
1998 struct sis_list_data *ld = &sc->sis_ldata;
1999 struct sis_chain_data *cd = &sc->sis_cdata;
2002 callout_stop(&sc->sis_timer);
2004 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2007 CSR_WRITE_4(sc, SIS_IER, 0);
2008 CSR_WRITE_4(sc, SIS_IMR, 0);
2009 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2011 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2012 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2017 * Free data in the RX lists.
2019 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2020 struct sis_rx_data *rd = &cd->sis_rx_data[i];
2022 if (rd->sis_mbuf != NULL) {
2023 bus_dmamap_unload(cd->sis_rxbuf_tag, rd->sis_map);
2024 m_freem(rd->sis_mbuf);
2025 rd->sis_mbuf = NULL;
2028 bzero(ld->sis_rx_list, SIS_RX_LIST_SZ);
2031 * Free the TX list buffers.
2033 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2034 struct sis_tx_data *td = &cd->sis_tx_data[i];
2036 if (td->sis_mbuf != NULL) {
2037 bus_dmamap_unload(cd->sis_txbuf_tag, td->sis_map);
2038 m_freem(td->sis_mbuf);
2039 td->sis_mbuf = NULL;
2042 bzero(ld->sis_tx_list, SIS_TX_LIST_SZ);
2046 * Stop all chip I/O so that the kernel's probe routines don't
2047 * get confused by errant DMAs when rebooting.
2050 sis_shutdown(device_t dev)
2052 struct sis_softc *sc;
2055 sc = device_get_softc(dev);
2056 ifp = &sc->arpcom.ac_if;
2057 lwkt_serialize_enter(ifp->if_serializer);
2060 lwkt_serialize_exit(ifp->if_serializer);
2064 sis_dma_alloc(device_t dev)
2066 struct sis_softc *sc = device_get_softc(dev);
2067 struct sis_chain_data *cd = &sc->sis_cdata;
2068 struct sis_list_data *ld = &sc->sis_ldata;
2071 /* Create top level DMA tag */
2072 error = bus_dma_tag_create(NULL, /* parent */
2073 1, 0, /* alignment, boundary */
2074 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
2075 BUS_SPACE_MAXADDR, /* highaddr */
2076 NULL, NULL, /* filter, filterarg */
2077 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
2079 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
2081 &sc->sis_parent_tag);
2083 device_printf(dev, "could not create parent DMA tag\n");
2087 /* Allocate RX ring */
2088 ld->sis_rx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2089 SIS_RING_ALIGN, SIS_RX_LIST_SZ,
2090 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2091 &ld->sis_rx_tag, &ld->sis_rx_dmamap,
2093 if (ld->sis_rx_list == NULL) {
2094 device_printf(dev, "could not allocate RX ring\n");
2098 /* Allocate TX ring */
2099 ld->sis_tx_list = bus_dmamem_coherent_any(sc->sis_parent_tag,
2100 SIS_RING_ALIGN, SIS_TX_LIST_SZ,
2101 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2102 &ld->sis_tx_tag, &ld->sis_tx_dmamap,
2104 if (ld->sis_tx_list == NULL) {
2105 device_printf(dev, "could not allocate TX ring\n");
2109 /* Create DMA tag for TX mbuf */
2110 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2111 1, 0, /* alignment, boundary */
2112 BUS_SPACE_MAXADDR, /* lowaddr */
2113 BUS_SPACE_MAXADDR, /* highaddr */
2114 NULL, NULL, /* filter, filterarg */
2115 MCLBYTES, /* maxsize */
2116 SIS_NSEGS, /* nsegments */
2117 MCLBYTES, /* maxsegsize */
2118 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,/* flags */
2119 &cd->sis_txbuf_tag);
2121 device_printf(dev, "could not create TX buf DMA tag\n");
2125 /* Create DMA maps for TX mbufs */
2126 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2127 error = bus_dmamap_create(cd->sis_txbuf_tag, BUS_DMA_WAITOK,
2128 &cd->sis_tx_data[i].sis_map);
2132 for (j = 0; j < i; ++j) {
2133 bus_dmamap_destroy(cd->sis_txbuf_tag,
2134 cd->sis_tx_data[j].sis_map);
2136 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2137 cd->sis_txbuf_tag = NULL;
2139 device_printf(dev, "could not create %dth "
2140 "TX buf DMA map\n", i);
2145 /* Create DMA tag for RX mbuf */
2146 error = bus_dma_tag_create(sc->sis_parent_tag,/* parent */
2147 SIS_RXBUF_ALIGN, 0, /* alignment, boundary */
2148 BUS_SPACE_MAXADDR, /* lowaddr */
2149 BUS_SPACE_MAXADDR, /* highaddr */
2150 NULL, NULL, /* filter, filterarg */
2151 MCLBYTES, /* maxsize */
2153 MCLBYTES, /* maxsegsize */
2154 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2155 BUS_DMA_ALIGNED, /* flags */
2156 &cd->sis_rxbuf_tag);
2158 device_printf(dev, "could not create RX buf DMA tag\n");
2162 /* Create tmp DMA map for loading RX mbuf */
2163 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2164 &cd->sis_rx_tmpmap);
2166 device_printf(dev, "could not create RX buf tmp DMA map\n");
2167 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2168 cd->sis_rxbuf_tag = NULL;
2172 /* Create DMA maps for RX mbufs */
2173 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2174 error = bus_dmamap_create(cd->sis_rxbuf_tag, BUS_DMA_WAITOK,
2175 &cd->sis_rx_data[i].sis_map);
2179 for (j = 0; j < i; ++j) {
2180 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2181 cd->sis_rx_data[j].sis_map);
2183 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2185 bus_dma_tag_destroy(cd->sis_rxbuf_tag);
2186 cd->sis_rxbuf_tag = NULL;
2188 device_printf(dev, "could not create %dth "
2189 "RX buf DMA map\n", i);
2197 sis_dma_free(device_t dev)
2199 struct sis_softc *sc = device_get_softc(dev);
2200 struct sis_list_data *ld = &sc->sis_ldata;
2201 struct sis_chain_data *cd = &sc->sis_cdata;
2205 if (ld->sis_tx_list != NULL) {
2206 bus_dmamap_unload(ld->sis_tx_tag, ld->sis_tx_dmamap);
2207 bus_dmamem_free(ld->sis_tx_tag, ld->sis_tx_list,
2209 bus_dma_tag_destroy(ld->sis_tx_tag);
2213 if (ld->sis_rx_list != NULL) {
2214 bus_dmamap_unload(ld->sis_rx_tag, ld->sis_rx_dmamap);
2215 bus_dmamem_free(ld->sis_rx_tag, ld->sis_rx_list,
2217 bus_dma_tag_destroy(ld->sis_rx_tag);
2220 /* Destroy DMA stuffs for TX mbufs */
2221 if (cd->sis_txbuf_tag != NULL) {
2222 for (i = 0; i < SIS_TX_LIST_CNT; ++i) {
2223 KKASSERT(cd->sis_tx_data[i].sis_mbuf == NULL);
2224 bus_dmamap_destroy(cd->sis_txbuf_tag,
2225 cd->sis_tx_data[i].sis_map);
2227 bus_dma_tag_destroy(cd->sis_txbuf_tag);
2230 /* Destroy DMA stuffs for RX mbufs */
2231 if (cd->sis_rxbuf_tag != NULL) {
2232 for (i = 0; i < SIS_RX_LIST_CNT; ++i) {
2233 KKASSERT(cd->sis_rx_data[i].sis_mbuf == NULL);
2234 bus_dmamap_destroy(cd->sis_rxbuf_tag,
2235 cd->sis_rx_data[i].sis_map);
2237 bus_dmamap_destroy(cd->sis_rxbuf_tag, cd->sis_rx_tmpmap);
2238 bus_dma_tag_destroy(cd->sis_rxbuf_tag);