2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written consent.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
30 * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
34 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
48 * BCM5709S A0, A1, B0, B1, B2, C0
52 #include "opt_polling.h"
54 #include <sys/param.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
63 #include <sys/random.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
72 #include <net/ethernet.h>
74 #include <net/if_arp.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/ifq_var.h>
79 #include <net/vlan/if_vlan_var.h>
80 #include <net/vlan/if_vlan_ether.h>
82 #include <dev/netif/mii_layer/mii.h>
83 #include <dev/netif/mii_layer/miivar.h>
84 #include <dev/netif/mii_layer/brgphyreg.h>
86 #include <bus/pci/pcireg.h>
87 #include <bus/pci/pcivar.h>
89 #include "miibus_if.h"
91 #include <dev/netif/bce/if_bcereg.h>
92 #include <dev/netif/bce/if_bcefw.h>
94 /****************************************************************************/
95 /* BCE Debug Options */
96 /****************************************************************************/
99 static uint32_t bce_debug = BCE_WARN;
103 * 1 = 1 in 2,147,483,648
104 * 256 = 1 in 8,388,608
105 * 2048 = 1 in 1,048,576
106 * 65536 = 1 in 32,768
107 * 1048576 = 1 in 2,048
110 * 1073741824 = 1 in 2
112 * bce_debug_l2fhdr_status_check:
113 * How often the l2_fhdr frame error check will fail.
115 * bce_debug_unexpected_attention:
116 * How often the unexpected attention check will fail.
118 * bce_debug_mbuf_allocation_failure:
119 * How often to simulate an mbuf allocation failure.
121 * bce_debug_dma_map_addr_failure:
122 * How often to simulate a DMA mapping failure.
124 * bce_debug_bootcode_running_failure:
125 * How often to simulate a bootcode failure.
127 static int bce_debug_l2fhdr_status_check = 0;
128 static int bce_debug_unexpected_attention = 0;
129 static int bce_debug_mbuf_allocation_failure = 0;
130 static int bce_debug_dma_map_addr_failure = 0;
131 static int bce_debug_bootcode_running_failure = 0;
133 #endif /* BCE_DEBUG */
136 /****************************************************************************/
137 /* PCI Device ID Table */
139 /* Used by bce_probe() to identify the devices supported by this driver. */
140 /****************************************************************************/
141 #define BCE_DEVDESC_MAX 64
143 static struct bce_type bce_devs[] = {
144 /* BCM5706C Controllers and OEM boards. */
145 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
146 "HP NC370T Multifunction Gigabit Server Adapter" },
147 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
148 "HP NC370i Multifunction Gigabit Server Adapter" },
149 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
150 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
151 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
152 "HP NC371i Multifunction Gigabit Server Adapter" },
153 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
154 "Broadcom NetXtreme II BCM5706 1000Base-T" },
156 /* BCM5706S controllers and OEM boards. */
157 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
158 "HP NC370F Multifunction Gigabit Server Adapter" },
159 { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
160 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
162 /* BCM5708C controllers and OEM boards. */
163 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
164 "HP NC373T PCIe Multifunction Gig Server Adapter" },
165 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
166 "HP NC373i Multifunction Gigabit Server Adapter" },
167 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
168 "HP NC374m PCIe Multifunction Adapter" },
169 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
170 "Broadcom NetXtreme II BCM5708 1000Base-T" },
172 /* BCM5708S controllers and OEM boards. */
173 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
174 "HP NC373m Multifunction Gigabit Server Adapter" },
175 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
176 "HP NC373i Multifunction Gigabit Server Adapter" },
177 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
178 "HP NC373F PCIe Multifunc Giga Server Adapter" },
179 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
180 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
182 /* BCM5709C controllers and OEM boards. */
183 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
184 "HP NC382i DP Multifunction Gigabit Server Adapter" },
185 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
186 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
187 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
188 "Broadcom NetXtreme II BCM5709 1000Base-T" },
190 /* BCM5709S controllers and OEM boards. */
191 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
192 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
193 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
194 "HP NC382i DP Multifunction Gigabit Server Adapter" },
195 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
196 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
198 /* BCM5716 controllers and OEM boards. */
199 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
200 "Broadcom NetXtreme II BCM5716 1000Base-T" },
206 /****************************************************************************/
207 /* Supported Flash NVRAM device data. */
208 /****************************************************************************/
209 static const struct flash_spec flash_table[] =
211 #define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
212 #define NONBUFFERED_FLAGS (BCE_NV_WREN)
215 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
216 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
217 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
219 /* Expansion entry 0001 */
220 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
221 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
222 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
224 /* Saifun SA25F010 (non-buffered flash) */
225 /* strap, cfg1, & write1 need updates */
226 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
227 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
228 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
229 "Non-buffered flash (128kB)"},
230 /* Saifun SA25F020 (non-buffered flash) */
231 /* strap, cfg1, & write1 need updates */
232 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
233 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
234 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
235 "Non-buffered flash (256kB)"},
236 /* Expansion entry 0100 */
237 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
238 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
239 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
241 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
242 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
243 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
244 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
245 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
246 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
247 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
248 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
249 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
250 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
251 /* Saifun SA25F005 (non-buffered flash) */
252 /* strap, cfg1, & write1 need updates */
253 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
254 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
255 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
256 "Non-buffered flash (64kB)"},
258 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
259 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
260 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
262 /* Expansion entry 1001 */
263 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
264 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
265 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
267 /* Expansion entry 1010 */
268 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
269 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
270 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
272 /* ATMEL AT45DB011B (buffered flash) */
273 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
274 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
275 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
276 "Buffered flash (128kB)"},
277 /* Expansion entry 1100 */
278 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
279 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
280 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
282 /* Expansion entry 1101 */
283 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
284 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
285 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
287 /* Ateml Expansion entry 1110 */
288 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
289 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
290 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
291 "Entry 1110 (Atmel)"},
292 /* ATMEL AT45DB021B (buffered flash) */
293 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
294 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
295 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
296 "Buffered flash (256kB)"},
300 * The BCM5709 controllers transparently handle the
301 * differences between Atmel 264 byte pages and all
302 * flash devices which use 256 byte pages, so no
303 * logical-to-physical mapping is required in the
306 static struct flash_spec flash_5709 = {
307 .flags = BCE_NV_BUFFERED,
308 .page_bits = BCM5709_FLASH_PAGE_BITS,
309 .page_size = BCM5709_FLASH_PAGE_SIZE,
310 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
311 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
312 .name = "5709/5716 buffered flash (256kB)",
316 /****************************************************************************/
317 /* DragonFly device entry points. */
318 /****************************************************************************/
319 static int bce_probe(device_t);
320 static int bce_attach(device_t);
321 static int bce_detach(device_t);
322 static void bce_shutdown(device_t);
324 /****************************************************************************/
325 /* BCE Debug Data Structure Dump Routines */
326 /****************************************************************************/
328 static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
329 static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
330 static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
331 static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
332 static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
333 static void bce_dump_l2fhdr(struct bce_softc *, int,
334 struct l2_fhdr *) __unused;
335 static void bce_dump_tx_chain(struct bce_softc *, int, int);
336 static void bce_dump_rx_chain(struct bce_softc *, int, int);
337 static void bce_dump_status_block(struct bce_softc *);
338 static void bce_dump_driver_state(struct bce_softc *);
339 static void bce_dump_stats_block(struct bce_softc *) __unused;
340 static void bce_dump_hw_state(struct bce_softc *);
341 static void bce_dump_txp_state(struct bce_softc *);
342 static void bce_dump_rxp_state(struct bce_softc *) __unused;
343 static void bce_dump_tpat_state(struct bce_softc *) __unused;
344 static void bce_freeze_controller(struct bce_softc *) __unused;
345 static void bce_unfreeze_controller(struct bce_softc *) __unused;
346 static void bce_breakpoint(struct bce_softc *);
347 #endif /* BCE_DEBUG */
350 /****************************************************************************/
351 /* BCE Register/Memory Access Routines */
352 /****************************************************************************/
353 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
354 static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
355 static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
356 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
357 static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
358 static int bce_miibus_read_reg(device_t, int, int);
359 static int bce_miibus_write_reg(device_t, int, int, int);
360 static void bce_miibus_statchg(device_t);
363 /****************************************************************************/
364 /* BCE NVRAM Access Routines */
365 /****************************************************************************/
366 static int bce_acquire_nvram_lock(struct bce_softc *);
367 static int bce_release_nvram_lock(struct bce_softc *);
368 static void bce_enable_nvram_access(struct bce_softc *);
369 static void bce_disable_nvram_access(struct bce_softc *);
370 static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
372 static int bce_init_nvram(struct bce_softc *);
373 static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
374 static int bce_nvram_test(struct bce_softc *);
376 /****************************************************************************/
377 /* BCE DMA Allocate/Free Routines */
378 /****************************************************************************/
379 static int bce_dma_alloc(struct bce_softc *);
380 static void bce_dma_free(struct bce_softc *);
381 static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
383 /****************************************************************************/
384 /* BCE Firmware Synchronization and Load */
385 /****************************************************************************/
386 static int bce_fw_sync(struct bce_softc *, uint32_t);
387 static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
389 static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
391 static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
392 static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
393 static void bce_start_rxp_cpu(struct bce_softc *);
394 static void bce_init_rxp_cpu(struct bce_softc *);
395 static void bce_init_txp_cpu(struct bce_softc *);
396 static void bce_init_tpat_cpu(struct bce_softc *);
397 static void bce_init_cp_cpu(struct bce_softc *);
398 static void bce_init_com_cpu(struct bce_softc *);
399 static void bce_init_cpus(struct bce_softc *);
401 static void bce_stop(struct bce_softc *);
402 static int bce_reset(struct bce_softc *, uint32_t);
403 static int bce_chipinit(struct bce_softc *);
404 static int bce_blockinit(struct bce_softc *);
405 static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
407 static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
408 static void bce_probe_pci_caps(struct bce_softc *);
409 static void bce_print_adapter_info(struct bce_softc *);
410 static void bce_get_media(struct bce_softc *);
412 static void bce_init_tx_context(struct bce_softc *);
413 static int bce_init_tx_chain(struct bce_softc *);
414 static void bce_init_rx_context(struct bce_softc *);
415 static int bce_init_rx_chain(struct bce_softc *);
416 static void bce_free_rx_chain(struct bce_softc *);
417 static void bce_free_tx_chain(struct bce_softc *);
419 static int bce_encap(struct bce_softc *, struct mbuf **);
420 static void bce_start(struct ifnet *);
421 static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
422 static void bce_watchdog(struct ifnet *);
423 static int bce_ifmedia_upd(struct ifnet *);
424 static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
425 static void bce_init(void *);
426 static void bce_mgmt_init(struct bce_softc *);
428 static int bce_init_ctx(struct bce_softc *);
429 static void bce_get_mac_addr(struct bce_softc *);
430 static void bce_set_mac_addr(struct bce_softc *);
431 static void bce_phy_intr(struct bce_softc *);
432 static void bce_rx_intr(struct bce_softc *, int);
433 static void bce_tx_intr(struct bce_softc *);
434 static void bce_disable_intr(struct bce_softc *);
435 static void bce_enable_intr(struct bce_softc *, int);
437 #ifdef DEVICE_POLLING
438 static void bce_poll(struct ifnet *, enum poll_cmd, int);
440 static void bce_intr(struct bce_softc *);
441 static void bce_intr_legacy(void *);
442 static void bce_intr_msi(void *);
443 static void bce_intr_msi_oneshot(void *);
444 static void bce_set_rx_mode(struct bce_softc *);
445 static void bce_stats_update(struct bce_softc *);
446 static void bce_tick(void *);
447 static void bce_tick_serialized(struct bce_softc *);
448 static void bce_pulse(void *);
449 static void bce_pulse_check_msi(struct bce_softc *);
450 static void bce_add_sysctls(struct bce_softc *);
452 static void bce_coal_change(struct bce_softc *);
453 static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
454 static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
455 static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
456 static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
457 static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
458 static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
459 static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
460 static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
461 static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
462 uint32_t *, uint32_t);
466 * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
467 * takes 1023 as the TX ticks limit. However, using 1023 will
468 * cause 5708(B2) to generate extra interrupts (~2000/s) even when
469 * there is _no_ network activity on the NIC.
471 static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
472 static uint32_t bce_tx_bds = 255; /* bcm: 20 */
473 static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
474 static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
475 static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
476 static uint32_t bce_rx_bds = 128; /* bcm: 6 */
477 static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
478 static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
480 static int bce_msi_enable = 1;
482 static int bce_rx_pages = RX_PAGES_DEFAULT;
483 static int bce_tx_pages = TX_PAGES_DEFAULT;
485 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
486 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
487 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
488 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
489 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
490 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
491 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
492 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
493 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
494 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
495 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
497 /****************************************************************************/
498 /* DragonFly device dispatch table. */
499 /****************************************************************************/
500 static device_method_t bce_methods[] = {
501 /* Device interface */
502 DEVMETHOD(device_probe, bce_probe),
503 DEVMETHOD(device_attach, bce_attach),
504 DEVMETHOD(device_detach, bce_detach),
505 DEVMETHOD(device_shutdown, bce_shutdown),
508 DEVMETHOD(bus_print_child, bus_generic_print_child),
509 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
512 DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
513 DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
514 DEVMETHOD(miibus_statchg, bce_miibus_statchg),
519 static driver_t bce_driver = {
522 sizeof(struct bce_softc)
525 static devclass_t bce_devclass;
528 DECLARE_DUMMY_MODULE(if_bce);
529 MODULE_DEPEND(bce, miibus, 1, 1, 1);
530 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
531 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
534 /****************************************************************************/
535 /* Device probe function. */
537 /* Compares the device to the driver's list of supported devices and */
538 /* reports back to the OS whether this is the right driver for the device. */
541 /* BUS_PROBE_DEFAULT on success, positive value on failure. */
542 /****************************************************************************/
544 bce_probe(device_t dev)
547 uint16_t vid, did, svid, sdid;
549 /* Get the data for the device to be probed. */
550 vid = pci_get_vendor(dev);
551 did = pci_get_device(dev);
552 svid = pci_get_subvendor(dev);
553 sdid = pci_get_subdevice(dev);
555 /* Look through the list of known devices for a match. */
556 for (t = bce_devs; t->bce_name != NULL; ++t) {
557 if (vid == t->bce_vid && did == t->bce_did &&
558 (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
559 (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
560 uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
563 descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
565 /* Print out the device identity. */
566 ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
568 ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
570 device_set_desc_copy(dev, descbuf);
571 kfree(descbuf, M_TEMP);
579 /****************************************************************************/
580 /* PCI Capabilities Probe Function. */
582 /* Walks the PCI capabiites list for the device to find what features are */
587 /****************************************************************************/
589 bce_print_adapter_info(struct bce_softc *sc)
591 device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
593 kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
594 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
597 if (sc->bce_flags & BCE_PCIE_FLAG) {
598 kprintf("Bus (PCIe x%d, ", sc->link_width);
599 switch (sc->link_speed) {
601 kprintf("2.5Gbps); ");
607 kprintf("Unknown link speed); ");
611 kprintf("Bus (PCI%s, %s, %dMHz); ",
612 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
613 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
617 /* Firmware version and device features. */
618 kprintf("B/C (%s)", sc->bce_bc_ver);
620 if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
621 (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
623 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
624 kprintf("MFW[%s]", sc->bce_mfw_ver);
625 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
633 /****************************************************************************/
634 /* PCI Capabilities Probe Function. */
636 /* Walks the PCI capabiites list for the device to find what features are */
641 /****************************************************************************/
643 bce_probe_pci_caps(struct bce_softc *sc)
645 device_t dev = sc->bce_dev;
648 if (pci_is_pcix(dev))
649 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
651 ptr = pci_get_pciecap_ptr(dev);
653 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
655 sc->link_speed = link_status & 0xf;
656 sc->link_width = (link_status >> 4) & 0x3f;
657 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
658 sc->bce_flags |= BCE_PCIE_FLAG;
663 /****************************************************************************/
664 /* Device attach function. */
666 /* Allocates device resources, performs secondary chip identification, */
667 /* resets and initializes the hardware, and initializes driver instance */
671 /* 0 on success, positive value on failure. */
672 /****************************************************************************/
674 bce_attach(device_t dev)
676 struct bce_softc *sc = device_get_softc(dev);
677 struct ifnet *ifp = &sc->arpcom.ac_if;
680 void (*irq_handle)(void *);
683 struct mii_probe_args mii_args;
684 uintptr_t mii_priv = 0;
687 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
689 pci_enable_busmaster(dev);
691 bce_probe_pci_caps(sc);
693 /* Allocate PCI memory resources. */
695 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
696 RF_ACTIVE | PCI_RF_DENSE);
697 if (sc->bce_res_mem == NULL) {
698 device_printf(dev, "PCI memory allocation failed\n");
701 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
702 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
704 /* Allocate PCI IRQ resources. */
705 sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
706 &sc->bce_irq_rid, &irq_flags);
708 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
709 &sc->bce_irq_rid, irq_flags);
710 if (sc->bce_res_irq == NULL) {
711 device_printf(dev, "PCI map interrupt failed\n");
717 * Configure byte swap and enable indirect register access.
718 * Rely on CPU to do target byte swapping on big endian systems.
719 * Access to registers outside of PCI configurtion space are not
720 * valid until this is done.
722 pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
723 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
724 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
726 /* Save ASIC revsion info. */
727 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
729 /* Weed out any non-production controller revisions. */
730 switch (BCE_CHIP_ID(sc)) {
731 case BCE_CHIP_ID_5706_A0:
732 case BCE_CHIP_ID_5706_A1:
733 case BCE_CHIP_ID_5708_A0:
734 case BCE_CHIP_ID_5708_B0:
735 case BCE_CHIP_ID_5709_A0:
736 case BCE_CHIP_ID_5709_B0:
737 case BCE_CHIP_ID_5709_B1:
739 /* 5709C B2 seems to work fine */
740 case BCE_CHIP_ID_5709_B2:
742 device_printf(dev, "Unsupported chip id 0x%08x!\n",
748 mii_priv |= BRGPHY_FLAG_WIRESPEED;
749 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
750 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
751 BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
752 mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
754 mii_priv |= BRGPHY_FLAG_BER_BUG;
757 if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
758 irq_handle = bce_intr_legacy;
759 } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
760 irq_handle = bce_intr_msi;
761 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
762 irq_handle = bce_intr_msi_oneshot;
763 sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
766 panic("%s: unsupported intr type %d",
767 device_get_nameunit(dev), sc->bce_irq_type);
771 * Find the base address for shared memory access.
772 * Newer versions of bootcode use a signature and offset
773 * while older versions use a fixed address.
775 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
776 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
777 BCE_SHM_HDR_SIGNATURE_SIG) {
778 /* Multi-port devices use different offsets in shared memory. */
779 sc->bce_shmem_base = REG_RD_IND(sc,
780 BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
782 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
784 DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
786 /* Fetch the bootcode revision. */
787 val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
788 for (i = 0, j = 0; i < 3; i++) {
792 num = (uint8_t)(val >> (24 - (i * 8)));
793 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
794 if (num >= k || !skip0 || k == 1) {
795 sc->bce_bc_ver[j++] = (num / k) + '0';
800 sc->bce_bc_ver[j++] = '.';
803 /* Check if any management firwmare is running. */
804 val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
805 if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
806 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
808 /* Allow time for firmware to enter the running state. */
809 for (i = 0; i < 30; i++) {
810 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
811 if (val & BCE_CONDITION_MFW_RUN_MASK)
817 /* Check the current bootcode state. */
818 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
819 BCE_CONDITION_MFW_RUN_MASK;
820 if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
821 val != BCE_CONDITION_MFW_RUN_NONE) {
822 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
824 for (i = 0, j = 0; j < 3; j++) {
825 val = bce_reg_rd_ind(sc, addr + j * 4);
827 memcpy(&sc->bce_mfw_ver[i], &val, 4);
832 /* Get PCI bus information (speed and type). */
833 val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
834 if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
837 sc->bce_flags |= BCE_PCIX_FLAG;
839 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
840 BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
842 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
843 sc->bus_speed_mhz = 133;
846 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
847 sc->bus_speed_mhz = 100;
850 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
851 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
852 sc->bus_speed_mhz = 66;
855 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
856 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
857 sc->bus_speed_mhz = 50;
860 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
861 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
862 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
863 sc->bus_speed_mhz = 33;
867 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
868 sc->bus_speed_mhz = 66;
870 sc->bus_speed_mhz = 33;
873 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
874 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
876 /* Reset the controller. */
877 rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
881 /* Initialize the controller. */
882 rc = bce_chipinit(sc);
884 device_printf(dev, "Controller initialization failed!\n");
888 /* Perform NVRAM test. */
889 rc = bce_nvram_test(sc);
891 device_printf(dev, "NVRAM test failed!\n");
895 /* Fetch the permanent Ethernet MAC address. */
896 bce_get_mac_addr(sc);
899 * Trip points control how many BDs
900 * should be ready before generating an
901 * interrupt while ticks control how long
902 * a BD can sit in the chain before
903 * generating an interrupt. Set the default
904 * values for the RX and TX rings.
908 /* Force more frequent interrupts. */
909 sc->bce_tx_quick_cons_trip_int = 1;
910 sc->bce_tx_quick_cons_trip = 1;
911 sc->bce_tx_ticks_int = 0;
912 sc->bce_tx_ticks = 0;
914 sc->bce_rx_quick_cons_trip_int = 1;
915 sc->bce_rx_quick_cons_trip = 1;
916 sc->bce_rx_ticks_int = 0;
917 sc->bce_rx_ticks = 0;
919 sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
920 sc->bce_tx_quick_cons_trip = bce_tx_bds;
921 sc->bce_tx_ticks_int = bce_tx_ticks_int;
922 sc->bce_tx_ticks = bce_tx_ticks;
924 sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
925 sc->bce_rx_quick_cons_trip = bce_rx_bds;
926 sc->bce_rx_ticks_int = bce_rx_ticks_int;
927 sc->bce_rx_ticks = bce_rx_ticks;
930 /* Update statistics once every second. */
931 sc->bce_stats_ticks = 1000000 & 0xffff00;
933 /* Find the media type for the adapter. */
936 /* Allocate DMA memory resources. */
937 rc = bce_dma_alloc(sc);
939 device_printf(dev, "DMA resource allocation failed!\n");
943 /* Initialize the ifnet interface. */
945 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
946 ifp->if_ioctl = bce_ioctl;
947 ifp->if_start = bce_start;
948 ifp->if_init = bce_init;
949 ifp->if_watchdog = bce_watchdog;
950 #ifdef DEVICE_POLLING
951 ifp->if_poll = bce_poll;
953 ifp->if_mtu = ETHERMTU;
954 ifp->if_hwassist = BCE_IF_HWASSIST;
955 ifp->if_capabilities = BCE_IF_CAPABILITIES;
956 ifp->if_capenable = ifp->if_capabilities;
957 ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
958 ifq_set_ready(&ifp->if_snd);
960 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
961 ifp->if_baudrate = IF_Gbps(2.5);
963 ifp->if_baudrate = IF_Gbps(1);
965 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
966 sc->mbuf_alloc_size = MCLBYTES;
971 mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
972 mii_args.mii_probemask = 1 << sc->bce_phy_addr;
973 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
974 mii_args.mii_priv = mii_priv;
976 rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
978 device_printf(dev, "PHY probe failed!\n");
982 /* Attach to the Ethernet interface list. */
983 ether_ifattach(ifp, sc->eaddr, NULL);
985 callout_init_mp(&sc->bce_tick_callout);
986 callout_init_mp(&sc->bce_pulse_callout);
988 /* Hookup IRQ last. */
989 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
990 &sc->bce_intrhand, ifp->if_serializer);
992 device_printf(dev, "Failed to setup IRQ!\n");
997 ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
998 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1000 /* Print some important debugging info. */
1001 DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1003 /* Add the supported sysctls to the kernel. */
1004 bce_add_sysctls(sc);
1007 * The chip reset earlier notified the bootcode that
1008 * a driver is present. We now need to start our pulse
1009 * routine so that the bootcode is reminded that we're
1014 /* Get the firmware running so IPMI still works */
1018 bce_print_adapter_info(sc);
1027 /****************************************************************************/
1028 /* Device detach function. */
1030 /* Stops the controller, resets the controller, and releases resources. */
1033 /* 0 on success, positive value on failure. */
1034 /****************************************************************************/
1036 bce_detach(device_t dev)
1038 struct bce_softc *sc = device_get_softc(dev);
1040 if (device_is_attached(dev)) {
1041 struct ifnet *ifp = &sc->arpcom.ac_if;
1044 /* Stop and reset the controller. */
1045 lwkt_serialize_enter(ifp->if_serializer);
1046 callout_stop(&sc->bce_pulse_callout);
1048 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1049 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1051 msg = BCE_DRV_MSG_CODE_UNLOAD;
1053 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1054 lwkt_serialize_exit(ifp->if_serializer);
1056 ether_ifdetach(ifp);
1059 /* If we have a child device on the MII bus remove it too. */
1061 device_delete_child(dev, sc->bce_miibus);
1062 bus_generic_detach(dev);
1064 if (sc->bce_res_irq != NULL) {
1065 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1069 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1070 pci_release_msi(dev);
1072 if (sc->bce_res_mem != NULL) {
1073 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1079 if (sc->bce_sysctl_tree != NULL)
1080 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1086 /****************************************************************************/
1087 /* Device shutdown function. */
1089 /* Stops and resets the controller. */
1093 /****************************************************************************/
1095 bce_shutdown(device_t dev)
1097 struct bce_softc *sc = device_get_softc(dev);
1098 struct ifnet *ifp = &sc->arpcom.ac_if;
1101 lwkt_serialize_enter(ifp->if_serializer);
1103 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1104 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1106 msg = BCE_DRV_MSG_CODE_UNLOAD;
1108 lwkt_serialize_exit(ifp->if_serializer);
1112 /****************************************************************************/
1113 /* Indirect register read. */
1115 /* Reads NetXtreme II registers using an index/data register pair in PCI */
1116 /* configuration space. Using this mechanism avoids issues with posted */
1117 /* reads but is much slower than memory-mapped I/O. */
1120 /* The value of the register. */
1121 /****************************************************************************/
1123 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1125 device_t dev = sc->bce_dev;
1127 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1131 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1132 DBPRINT(sc, BCE_EXCESSIVE,
1133 "%s(); offset = 0x%08X, val = 0x%08X\n",
1134 __func__, offset, val);
1138 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1143 /****************************************************************************/
1144 /* Indirect register write. */
1146 /* Writes NetXtreme II registers using an index/data register pair in PCI */
1147 /* configuration space. Using this mechanism avoids issues with posted */
1148 /* writes but is muchh slower than memory-mapped I/O. */
1152 /****************************************************************************/
1154 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1156 device_t dev = sc->bce_dev;
1158 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1159 __func__, offset, val);
1161 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1162 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1166 /****************************************************************************/
1167 /* Shared memory write. */
1169 /* Writes NetXtreme II shared memory region. */
1173 /****************************************************************************/
1175 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1177 bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1181 /****************************************************************************/
1182 /* Shared memory read. */
1184 /* Reads NetXtreme II shared memory region. */
1187 /* The 32 bit value read. */
1188 /****************************************************************************/
1190 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1192 return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1196 /****************************************************************************/
1197 /* Context memory write. */
1199 /* The NetXtreme II controller uses context memory to track connection */
1200 /* information for L2 and higher network protocols. */
1204 /****************************************************************************/
1206 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1209 uint32_t idx, offset = ctx_offset + cid_addr;
1210 uint32_t val, retry_cnt = 5;
1212 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1213 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1214 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1215 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1217 for (idx = 0; idx < retry_cnt; idx++) {
1218 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1219 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1224 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1225 device_printf(sc->bce_dev,
1226 "Unable to write CTX memory: "
1227 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1228 cid_addr, ctx_offset);
1231 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1232 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1237 /****************************************************************************/
1238 /* PHY register read. */
1240 /* Implements register reads on the MII bus. */
1243 /* The value of the register. */
1244 /****************************************************************************/
1246 bce_miibus_read_reg(device_t dev, int phy, int reg)
1248 struct bce_softc *sc = device_get_softc(dev);
1252 /* Make sure we are accessing the correct PHY address. */
1253 KASSERT(phy == sc->bce_phy_addr,
1254 ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1256 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1257 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1258 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1260 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1261 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1266 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1267 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1268 BCE_EMAC_MDIO_COMM_START_BUSY;
1269 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1271 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1274 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1275 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1278 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1279 val &= BCE_EMAC_MDIO_COMM_DATA;
1284 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1285 if_printf(&sc->arpcom.ac_if,
1286 "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1290 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1293 DBPRINT(sc, BCE_EXCESSIVE,
1294 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1295 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1297 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1298 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1299 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1301 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1302 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1306 return (val & 0xffff);
1310 /****************************************************************************/
1311 /* PHY register write. */
1313 /* Implements register writes on the MII bus. */
1316 /* The value of the register. */
1317 /****************************************************************************/
1319 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1321 struct bce_softc *sc = device_get_softc(dev);
1325 /* Make sure we are accessing the correct PHY address. */
1326 KASSERT(phy == sc->bce_phy_addr,
1327 ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1329 DBPRINT(sc, BCE_EXCESSIVE,
1330 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1331 __func__, phy, (uint16_t)(reg & 0xffff),
1332 (uint16_t)(val & 0xffff));
1334 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1335 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1336 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1338 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1339 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1344 val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1345 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1346 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1347 REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1349 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1352 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1353 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1359 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1360 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1362 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1363 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1364 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1366 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1367 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1375 /****************************************************************************/
1376 /* MII bus status change. */
1378 /* Called by the MII bus driver when the PHY establishes link to set the */
1379 /* MAC interface registers. */
1383 /****************************************************************************/
1385 bce_miibus_statchg(device_t dev)
1387 struct bce_softc *sc = device_get_softc(dev);
1388 struct mii_data *mii = device_get_softc(sc->bce_miibus);
1390 DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1391 mii->mii_media_active);
1394 /* Decode the interface media flags. */
1395 if_printf(&sc->arpcom.ac_if, "Media: ( ");
1396 switch(IFM_TYPE(mii->mii_media_active)) {
1398 kprintf("Ethernet )");
1401 kprintf("Unknown )");
1405 kprintf(" Media Options: ( ");
1406 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1408 kprintf("Autoselect )");
1411 kprintf("Manual )");
1417 kprintf("10Base-T )");
1420 kprintf("100Base-TX )");
1423 kprintf("1000Base-SX )");
1426 kprintf("1000Base-T )");
1433 kprintf(" Global Options: (");
1434 if (mii->mii_media_active & IFM_FDX)
1435 kprintf(" FullDuplex");
1436 if (mii->mii_media_active & IFM_HDX)
1437 kprintf(" HalfDuplex");
1438 if (mii->mii_media_active & IFM_LOOP)
1439 kprintf(" Loopback");
1440 if (mii->mii_media_active & IFM_FLAG0)
1442 if (mii->mii_media_active & IFM_FLAG1)
1444 if (mii->mii_media_active & IFM_FLAG2)
1449 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1452 * Set MII or GMII interface based on the speed negotiated
1455 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1456 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1457 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1458 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1460 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1461 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1465 * Set half or full duplex based on the duplicity negotiated
1468 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1469 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1470 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1472 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1473 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1478 /****************************************************************************/
1479 /* Acquire NVRAM lock. */
1481 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1482 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1483 /* for use by the driver. */
1486 /* 0 on success, positive value on failure. */
1487 /****************************************************************************/
1489 bce_acquire_nvram_lock(struct bce_softc *sc)
1494 DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1496 /* Request access to the flash interface. */
1497 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1498 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1499 val = REG_RD(sc, BCE_NVM_SW_ARB);
1500 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1506 if (j >= NVRAM_TIMEOUT_COUNT) {
1507 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1514 /****************************************************************************/
1515 /* Release NVRAM lock. */
1517 /* When the caller is finished accessing NVRAM the lock must be released. */
1518 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1519 /* for use by the driver. */
1522 /* 0 on success, positive value on failure. */
1523 /****************************************************************************/
1525 bce_release_nvram_lock(struct bce_softc *sc)
1530 DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1533 * Relinquish nvram interface.
1535 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1537 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1538 val = REG_RD(sc, BCE_NVM_SW_ARB);
1539 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1545 if (j >= NVRAM_TIMEOUT_COUNT) {
1546 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1553 /****************************************************************************/
1554 /* Enable NVRAM access. */
1556 /* Before accessing NVRAM for read or write operations the caller must */
1557 /* enabled NVRAM access. */
1561 /****************************************************************************/
1563 bce_enable_nvram_access(struct bce_softc *sc)
1567 DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1569 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1570 /* Enable both bits, even on read. */
1571 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1572 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1576 /****************************************************************************/
1577 /* Disable NVRAM access. */
1579 /* When the caller is finished accessing NVRAM access must be disabled. */
1583 /****************************************************************************/
1585 bce_disable_nvram_access(struct bce_softc *sc)
1589 DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1591 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1593 /* Disable both bits, even after read. */
1594 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1595 val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1599 /****************************************************************************/
1600 /* Read a dword (32 bits) from NVRAM. */
1602 /* Read a 32 bit word from NVRAM. The caller is assumed to have already */
1603 /* obtained the NVRAM lock and enabled the controller for NVRAM access. */
1606 /* 0 on success and the 32 bit value read, positive value on failure. */
1607 /****************************************************************************/
1609 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1615 /* Build the command word. */
1616 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1618 /* Calculate the offset for buffered flash. */
1619 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1620 offset = ((offset / sc->bce_flash_info->page_size) <<
1621 sc->bce_flash_info->page_bits) +
1622 (offset % sc->bce_flash_info->page_size);
1626 * Clear the DONE bit separately, set the address to read,
1627 * and issue the read.
1629 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1630 REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1631 REG_WR(sc, BCE_NVM_COMMAND, cmd);
1633 /* Wait for completion. */
1634 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1639 val = REG_RD(sc, BCE_NVM_COMMAND);
1640 if (val & BCE_NVM_COMMAND_DONE) {
1641 val = REG_RD(sc, BCE_NVM_READ);
1644 memcpy(ret_val, &val, 4);
1649 /* Check for errors. */
1650 if (i >= NVRAM_TIMEOUT_COUNT) {
1651 if_printf(&sc->arpcom.ac_if,
1652 "Timeout error reading NVRAM at offset 0x%08X!\n",
1660 /****************************************************************************/
1661 /* Initialize NVRAM access. */
1663 /* Identify the NVRAM device in use and prepare the NVRAM interface to */
1664 /* access that device. */
1667 /* 0 on success, positive value on failure. */
1668 /****************************************************************************/
1670 bce_init_nvram(struct bce_softc *sc)
1673 int j, entry_count, rc = 0;
1674 const struct flash_spec *flash;
1676 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1678 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1679 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1680 sc->bce_flash_info = &flash_5709;
1681 goto bce_init_nvram_get_flash_size;
1684 /* Determine the selected interface. */
1685 val = REG_RD(sc, BCE_NVM_CFG1);
1687 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1690 * Flash reconfiguration is required to support additional
1691 * NVRAM devices not directly supported in hardware.
1692 * Check if the flash interface was reconfigured
1696 if (val & 0x40000000) {
1697 /* Flash interface reconfigured by bootcode. */
1699 DBPRINT(sc, BCE_INFO_LOAD,
1700 "%s(): Flash WAS reconfigured.\n", __func__);
1702 for (j = 0, flash = flash_table; j < entry_count;
1704 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1705 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1706 sc->bce_flash_info = flash;
1711 /* Flash interface not yet reconfigured. */
1714 DBPRINT(sc, BCE_INFO_LOAD,
1715 "%s(): Flash was NOT reconfigured.\n", __func__);
1717 if (val & (1 << 23))
1718 mask = FLASH_BACKUP_STRAP_MASK;
1720 mask = FLASH_STRAP_MASK;
1722 /* Look for the matching NVRAM device configuration data. */
1723 for (j = 0, flash = flash_table; j < entry_count;
1725 /* Check if the device matches any of the known devices. */
1726 if ((val & mask) == (flash->strapping & mask)) {
1727 /* Found a device match. */
1728 sc->bce_flash_info = flash;
1730 /* Request access to the flash interface. */
1731 rc = bce_acquire_nvram_lock(sc);
1735 /* Reconfigure the flash interface. */
1736 bce_enable_nvram_access(sc);
1737 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1738 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1739 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1740 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1741 bce_disable_nvram_access(sc);
1742 bce_release_nvram_lock(sc);
1748 /* Check if a matching device was found. */
1749 if (j == entry_count) {
1750 sc->bce_flash_info = NULL;
1751 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1755 bce_init_nvram_get_flash_size:
1756 /* Write the flash config data to the shared memory interface. */
1757 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1758 BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1760 sc->bce_flash_size = val;
1762 sc->bce_flash_size = sc->bce_flash_info->total_size;
1764 DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1765 __func__, sc->bce_flash_info->total_size);
1767 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1773 /****************************************************************************/
1774 /* Read an arbitrary range of data from NVRAM. */
1776 /* Prepares the NVRAM interface for access and reads the requested data */
1777 /* into the supplied buffer. */
1780 /* 0 on success and the data read, positive value on failure. */
1781 /****************************************************************************/
1783 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1786 uint32_t cmd_flags, offset32, len32, extra;
1792 /* Request access to the flash interface. */
1793 rc = bce_acquire_nvram_lock(sc);
1797 /* Enable access to flash interface */
1798 bce_enable_nvram_access(sc);
1806 /* XXX should we release nvram lock if read_dword() fails? */
1812 pre_len = 4 - (offset & 3);
1814 if (pre_len >= len32) {
1816 cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1818 cmd_flags = BCE_NVM_COMMAND_FIRST;
1821 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1825 memcpy(ret_buf, buf + (offset & 3), pre_len);
1833 extra = 4 - (len32 & 3);
1834 len32 = (len32 + 4) & ~3;
1841 cmd_flags = BCE_NVM_COMMAND_LAST;
1843 cmd_flags = BCE_NVM_COMMAND_FIRST |
1844 BCE_NVM_COMMAND_LAST;
1846 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1848 memcpy(ret_buf, buf, 4 - extra);
1849 } else if (len32 > 0) {
1852 /* Read the first word. */
1856 cmd_flags = BCE_NVM_COMMAND_FIRST;
1858 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1860 /* Advance to the next dword. */
1865 while (len32 > 4 && rc == 0) {
1866 rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1868 /* Advance to the next dword. */
1875 goto bce_nvram_read_locked_exit;
1877 cmd_flags = BCE_NVM_COMMAND_LAST;
1878 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1880 memcpy(ret_buf, buf, 4 - extra);
1883 bce_nvram_read_locked_exit:
1884 /* Disable access to flash interface and release the lock. */
1885 bce_disable_nvram_access(sc);
1886 bce_release_nvram_lock(sc);
1892 /****************************************************************************/
1893 /* Verifies that NVRAM is accessible and contains valid data. */
1895 /* Reads the configuration data from NVRAM and verifies that the CRC is */
1899 /* 0 on success, positive value on failure. */
1900 /****************************************************************************/
1902 bce_nvram_test(struct bce_softc *sc)
1904 uint32_t buf[BCE_NVRAM_SIZE / 4];
1905 uint32_t magic, csum;
1906 uint8_t *data = (uint8_t *)buf;
1910 * Check that the device NVRAM is valid by reading
1911 * the magic value at offset 0.
1913 rc = bce_nvram_read(sc, 0, data, 4);
1917 magic = be32toh(buf[0]);
1918 if (magic != BCE_NVRAM_MAGIC) {
1919 if_printf(&sc->arpcom.ac_if,
1920 "Invalid NVRAM magic value! Expected: 0x%08X, "
1921 "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1926 * Verify that the device NVRAM includes valid
1927 * configuration data.
1929 rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1933 csum = ether_crc32_le(data, 0x100);
1934 if (csum != BCE_CRC32_RESIDUAL) {
1935 if_printf(&sc->arpcom.ac_if,
1936 "Invalid Manufacturing Information NVRAM CRC! "
1937 "Expected: 0x%08X, Found: 0x%08X\n",
1938 BCE_CRC32_RESIDUAL, csum);
1942 csum = ether_crc32_le(data + 0x100, 0x100);
1943 if (csum != BCE_CRC32_RESIDUAL) {
1944 if_printf(&sc->arpcom.ac_if,
1945 "Invalid Feature Configuration Information "
1946 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1947 BCE_CRC32_RESIDUAL, csum);
1954 /****************************************************************************/
1955 /* Identifies the current media type of the controller and sets the PHY */
1960 /****************************************************************************/
1962 bce_get_media(struct bce_softc *sc)
1966 sc->bce_phy_addr = 1;
1968 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1969 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1970 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1971 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1975 * The BCM5709S is software configurable
1976 * for Copper or SerDes operation.
1978 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1980 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1981 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1985 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1986 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1989 (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1992 if (pci_get_function(sc->bce_dev) == 0) {
1997 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2005 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2009 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2010 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2013 if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2014 sc->bce_flags |= BCE_NO_WOL_FLAG;
2015 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2016 sc->bce_phy_addr = 2;
2017 val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2018 if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2019 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2021 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2022 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2023 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2028 /****************************************************************************/
2029 /* Free any DMA memory owned by the driver. */
2031 /* Scans through each data structre that requires DMA memory and frees */
2032 /* the memory if allocated. */
2036 /****************************************************************************/
2038 bce_dma_free(struct bce_softc *sc)
2042 /* Destroy the status block. */
2043 if (sc->status_tag != NULL) {
2044 if (sc->status_block != NULL) {
2045 bus_dmamap_unload(sc->status_tag, sc->status_map);
2046 bus_dmamem_free(sc->status_tag, sc->status_block,
2049 bus_dma_tag_destroy(sc->status_tag);
2052 /* Destroy the statistics block. */
2053 if (sc->stats_tag != NULL) {
2054 if (sc->stats_block != NULL) {
2055 bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2056 bus_dmamem_free(sc->stats_tag, sc->stats_block,
2059 bus_dma_tag_destroy(sc->stats_tag);
2062 /* Destroy the CTX DMA stuffs. */
2063 if (sc->ctx_tag != NULL) {
2064 for (i = 0; i < sc->ctx_pages; i++) {
2065 if (sc->ctx_block[i] != NULL) {
2066 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2067 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2071 bus_dma_tag_destroy(sc->ctx_tag);
2074 /* Destroy the TX buffer descriptor DMA stuffs. */
2075 if (sc->tx_bd_chain_tag != NULL) {
2076 for (i = 0; i < sc->tx_pages; i++) {
2077 if (sc->tx_bd_chain[i] != NULL) {
2078 bus_dmamap_unload(sc->tx_bd_chain_tag,
2079 sc->tx_bd_chain_map[i]);
2080 bus_dmamem_free(sc->tx_bd_chain_tag,
2082 sc->tx_bd_chain_map[i]);
2085 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2088 /* Destroy the RX buffer descriptor DMA stuffs. */
2089 if (sc->rx_bd_chain_tag != NULL) {
2090 for (i = 0; i < sc->rx_pages; i++) {
2091 if (sc->rx_bd_chain[i] != NULL) {
2092 bus_dmamap_unload(sc->rx_bd_chain_tag,
2093 sc->rx_bd_chain_map[i]);
2094 bus_dmamem_free(sc->rx_bd_chain_tag,
2096 sc->rx_bd_chain_map[i]);
2099 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2102 /* Destroy the TX mbuf DMA stuffs. */
2103 if (sc->tx_mbuf_tag != NULL) {
2104 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2105 /* Must have been unloaded in bce_stop() */
2106 KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2107 bus_dmamap_destroy(sc->tx_mbuf_tag,
2108 sc->tx_mbuf_map[i]);
2110 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2113 /* Destroy the RX mbuf DMA stuffs. */
2114 if (sc->rx_mbuf_tag != NULL) {
2115 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2116 /* Must have been unloaded in bce_stop() */
2117 KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2118 bus_dmamap_destroy(sc->rx_mbuf_tag,
2119 sc->rx_mbuf_map[i]);
2121 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2122 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2125 /* Destroy the parent tag */
2126 if (sc->parent_tag != NULL)
2127 bus_dma_tag_destroy(sc->parent_tag);
2129 if (sc->tx_bd_chain_map != NULL)
2130 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2131 if (sc->tx_bd_chain != NULL)
2132 kfree(sc->tx_bd_chain, M_DEVBUF);
2133 if (sc->tx_bd_chain_paddr != NULL)
2134 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2136 if (sc->rx_bd_chain_map != NULL)
2137 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2138 if (sc->rx_bd_chain != NULL)
2139 kfree(sc->rx_bd_chain, M_DEVBUF);
2140 if (sc->rx_bd_chain_paddr != NULL)
2141 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2143 if (sc->tx_mbuf_map != NULL)
2144 kfree(sc->tx_mbuf_map, M_DEVBUF);
2145 if (sc->tx_mbuf_ptr != NULL)
2146 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2148 if (sc->rx_mbuf_map != NULL)
2149 kfree(sc->rx_mbuf_map, M_DEVBUF);
2150 if (sc->rx_mbuf_ptr != NULL)
2151 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2152 if (sc->rx_mbuf_paddr != NULL)
2153 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2157 /****************************************************************************/
2158 /* Get DMA memory from the OS. */
2160 /* Validates that the OS has provided DMA buffers in response to a */
2161 /* bus_dmamap_load() call and saves the physical address of those buffers. */
2162 /* When the callback is used the OS will return 0 for the mapping function */
2163 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any */
2164 /* failures back to the caller. */
2168 /****************************************************************************/
2170 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2172 bus_addr_t *busaddr = arg;
2175 * Simulate a mapping failure.
2178 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2179 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2180 __FILE__, __LINE__);
2183 /* Check for an error and signal the caller that an error occurred. */
2187 KASSERT(nseg == 1, ("only one segment is allowed"));
2188 *busaddr = segs->ds_addr;
2192 /****************************************************************************/
2193 /* Allocate any DMA memory needed by the driver. */
2195 /* Allocates DMA memory needed for the various global structures needed by */
2198 /* Memory alignment requirements: */
2199 /* -----------------+----------+----------+----------+----------+ */
2200 /* Data Structure | 5706 | 5708 | 5709 | 5716 | */
2201 /* -----------------+----------+----------+----------+----------+ */
2202 /* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2203 /* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2204 /* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2205 /* PG Buffers | none | none | none | none | */
2206 /* TX Buffers | none | none | none | none | */
2207 /* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2208 /* Context Pages(1) | N/A | N/A | 4KiB | 4KiB | */
2209 /* -----------------+----------+----------+----------+----------+ */
2211 /* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2214 /* 0 for success, positive value for failure. */
2215 /****************************************************************************/
2217 bce_dma_alloc(struct bce_softc *sc)
2219 struct ifnet *ifp = &sc->arpcom.ac_if;
2220 int i, j, rc = 0, pages;
2221 bus_addr_t busaddr, max_busaddr;
2222 bus_size_t status_align, stats_align;
2224 pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2225 if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2226 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2227 pages = RX_PAGES_DEFAULT;
2229 sc->rx_pages = pages;
2231 pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2232 if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2233 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2234 pages = TX_PAGES_DEFAULT;
2236 sc->tx_pages = pages;
2238 sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2239 M_DEVBUF, M_WAITOK | M_ZERO);
2240 sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2241 M_DEVBUF, M_WAITOK | M_ZERO);
2242 sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2243 M_DEVBUF, M_WAITOK | M_ZERO);
2245 sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2246 M_DEVBUF, M_WAITOK | M_ZERO);
2247 sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2248 M_DEVBUF, M_WAITOK | M_ZERO);
2249 sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2250 M_DEVBUF, M_WAITOK | M_ZERO);
2252 sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2253 M_DEVBUF, M_WAITOK | M_ZERO);
2254 sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2255 M_DEVBUF, M_WAITOK | M_ZERO);
2257 sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2258 M_DEVBUF, M_WAITOK | M_ZERO);
2259 sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2260 M_DEVBUF, M_WAITOK | M_ZERO);
2261 sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2262 M_DEVBUF, M_WAITOK | M_ZERO);
2265 * The embedded PCIe to PCI-X bridge (EPB)
2266 * in the 5708 cannot address memory above
2267 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2269 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2270 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2272 max_busaddr = BUS_SPACE_MAXADDR;
2275 * BCM5709 and BCM5716 uses host memory as cache for context memory.
2277 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2278 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2279 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2280 if (sc->ctx_pages == 0)
2282 if (sc->ctx_pages > BCE_CTX_PAGES) {
2283 device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2295 * Allocate the parent bus DMA tag appropriate for PCI.
2297 rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2298 max_busaddr, BUS_SPACE_MAXADDR,
2300 BUS_SPACE_MAXSIZE_32BIT, 0,
2301 BUS_SPACE_MAXSIZE_32BIT,
2302 0, &sc->parent_tag);
2304 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2309 * Allocate status block.
2311 sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2312 status_align, BCE_STATUS_BLK_SZ,
2313 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2314 &sc->status_tag, &sc->status_map,
2315 &sc->status_block_paddr);
2316 if (sc->status_block == NULL) {
2317 if_printf(ifp, "Could not allocate status block!\n");
2322 * Allocate statistics block.
2324 sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2325 stats_align, BCE_STATS_BLK_SZ,
2326 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2327 &sc->stats_tag, &sc->stats_map,
2328 &sc->stats_block_paddr);
2329 if (sc->stats_block == NULL) {
2330 if_printf(ifp, "Could not allocate statistics block!\n");
2335 * Allocate context block, if needed
2337 if (sc->ctx_pages != 0) {
2338 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2339 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2341 BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2344 if_printf(ifp, "Could not allocate "
2345 "context block DMA tag!\n");
2349 for (i = 0; i < sc->ctx_pages; i++) {
2350 rc = bus_dmamem_alloc(sc->ctx_tag,
2351 (void **)&sc->ctx_block[i],
2352 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2356 if_printf(ifp, "Could not allocate %dth context "
2357 "DMA memory!\n", i);
2361 rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2362 sc->ctx_block[i], BCM_PAGE_SIZE,
2363 bce_dma_map_addr, &busaddr,
2366 if (rc == EINPROGRESS) {
2367 panic("%s coherent memory loading "
2368 "is still in progress!", ifp->if_xname);
2370 if_printf(ifp, "Could not map %dth context "
2371 "DMA memory!\n", i);
2372 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2374 sc->ctx_block[i] = NULL;
2377 sc->ctx_paddr[i] = busaddr;
2382 * Create a DMA tag for the TX buffer descriptor chain,
2383 * allocate and clear the memory, and fetch the
2384 * physical address of the block.
2386 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2387 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2389 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2390 0, &sc->tx_bd_chain_tag);
2392 if_printf(ifp, "Could not allocate "
2393 "TX descriptor chain DMA tag!\n");
2397 for (i = 0; i < sc->tx_pages; i++) {
2398 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2399 (void **)&sc->tx_bd_chain[i],
2400 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2402 &sc->tx_bd_chain_map[i]);
2404 if_printf(ifp, "Could not allocate %dth TX descriptor "
2405 "chain DMA memory!\n", i);
2409 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2410 sc->tx_bd_chain_map[i],
2411 sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2412 bce_dma_map_addr, &busaddr,
2415 if (rc == EINPROGRESS) {
2416 panic("%s coherent memory loading "
2417 "is still in progress!", ifp->if_xname);
2419 if_printf(ifp, "Could not map %dth TX descriptor "
2420 "chain DMA memory!\n", i);
2421 bus_dmamem_free(sc->tx_bd_chain_tag,
2423 sc->tx_bd_chain_map[i]);
2424 sc->tx_bd_chain[i] = NULL;
2428 sc->tx_bd_chain_paddr[i] = busaddr;
2429 /* DRC - Fix for 64 bit systems. */
2430 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2431 i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2434 /* Create a DMA tag for TX mbufs. */
2435 rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2436 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2438 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2439 BCE_MAX_SEGMENTS, MCLBYTES,
2440 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2444 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2448 /* Create DMA maps for the TX mbufs clusters. */
2449 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2450 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2451 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2452 &sc->tx_mbuf_map[i]);
2454 for (j = 0; j < i; ++j) {
2455 bus_dmamap_destroy(sc->tx_mbuf_tag,
2456 sc->tx_mbuf_map[i]);
2458 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2459 sc->tx_mbuf_tag = NULL;
2461 if_printf(ifp, "Unable to create "
2462 "%dth TX mbuf DMA map!\n", i);
2468 * Create a DMA tag for the RX buffer descriptor chain,
2469 * allocate and clear the memory, and fetch the physical
2470 * address of the blocks.
2472 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2473 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2475 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2476 0, &sc->rx_bd_chain_tag);
2478 if_printf(ifp, "Could not allocate "
2479 "RX descriptor chain DMA tag!\n");
2483 for (i = 0; i < sc->rx_pages; i++) {
2484 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2485 (void **)&sc->rx_bd_chain[i],
2486 BUS_DMA_WAITOK | BUS_DMA_ZERO |
2488 &sc->rx_bd_chain_map[i]);
2490 if_printf(ifp, "Could not allocate %dth RX descriptor "
2491 "chain DMA memory!\n", i);
2495 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2496 sc->rx_bd_chain_map[i],
2497 sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2498 bce_dma_map_addr, &busaddr,
2501 if (rc == EINPROGRESS) {
2502 panic("%s coherent memory loading "
2503 "is still in progress!", ifp->if_xname);
2505 if_printf(ifp, "Could not map %dth RX descriptor "
2506 "chain DMA memory!\n", i);
2507 bus_dmamem_free(sc->rx_bd_chain_tag,
2509 sc->rx_bd_chain_map[i]);
2510 sc->rx_bd_chain[i] = NULL;
2514 sc->rx_bd_chain_paddr[i] = busaddr;
2515 /* DRC - Fix for 64 bit systems. */
2516 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2517 i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2520 /* Create a DMA tag for RX mbufs. */
2521 rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2522 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2524 MCLBYTES, 1, MCLBYTES,
2525 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2529 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2533 /* Create tmp DMA map for RX mbuf clusters. */
2534 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2535 &sc->rx_mbuf_tmpmap);
2537 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2538 sc->rx_mbuf_tag = NULL;
2540 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2544 /* Create DMA maps for the RX mbuf clusters. */
2545 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2546 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2547 &sc->rx_mbuf_map[i]);
2549 for (j = 0; j < i; ++j) {
2550 bus_dmamap_destroy(sc->rx_mbuf_tag,
2551 sc->rx_mbuf_map[j]);
2553 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2554 sc->rx_mbuf_tag = NULL;
2556 if_printf(ifp, "Unable to create "
2557 "%dth RX mbuf DMA map!\n", i);
2565 /****************************************************************************/
2566 /* Firmware synchronization. */
2568 /* Before performing certain events such as a chip reset, synchronize with */
2569 /* the firmware first. */
2572 /* 0 for success, positive value for failure. */
2573 /****************************************************************************/
2575 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2580 /* Don't waste any time if we've timed out before. */
2581 if (sc->bce_fw_timed_out)
2584 /* Increment the message sequence number. */
2585 sc->bce_fw_wr_seq++;
2586 msg_data |= sc->bce_fw_wr_seq;
2588 DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2590 /* Send the message to the bootcode driver mailbox. */
2591 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2593 /* Wait for the bootcode to acknowledge the message. */
2594 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2595 /* Check for a response in the bootcode firmware mailbox. */
2596 val = bce_shmem_rd(sc, BCE_FW_MB);
2597 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2602 /* If we've timed out, tell the bootcode that we've stopped waiting. */
2603 if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2604 (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2605 if_printf(&sc->arpcom.ac_if,
2606 "Firmware synchronization timeout! "
2607 "msg_data = 0x%08X\n", msg_data);
2609 msg_data &= ~BCE_DRV_MSG_CODE;
2610 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2612 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2614 sc->bce_fw_timed_out = 1;
2621 /****************************************************************************/
2622 /* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2626 /****************************************************************************/
2628 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2629 uint32_t rv2p_code_len, uint32_t rv2p_proc)
2634 for (i = 0; i < rv2p_code_len; i += 8) {
2635 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2637 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2640 if (rv2p_proc == RV2P_PROC1) {
2641 val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2642 REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2644 val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2645 REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2649 /* Reset the processor, un-stall is done later. */
2650 if (rv2p_proc == RV2P_PROC1)
2651 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2653 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2657 /****************************************************************************/
2658 /* Load RISC processor firmware. */
2660 /* Loads firmware from the file if_bcefw.h into the scratchpad memory */
2661 /* associated with a particular processor. */
2665 /****************************************************************************/
2667 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2673 bce_halt_cpu(sc, cpu_reg);
2675 /* Load the Text area. */
2676 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2678 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2679 REG_WR_IND(sc, offset, fw->text[j]);
2682 /* Load the Data area. */
2683 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2685 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2686 REG_WR_IND(sc, offset, fw->data[j]);
2689 /* Load the SBSS area. */
2690 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2692 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2693 REG_WR_IND(sc, offset, fw->sbss[j]);
2696 /* Load the BSS area. */
2697 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2699 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2700 REG_WR_IND(sc, offset, fw->bss[j]);
2703 /* Load the Read-Only area. */
2704 offset = cpu_reg->spad_base +
2705 (fw->rodata_addr - cpu_reg->mips_view_base);
2707 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2708 REG_WR_IND(sc, offset, fw->rodata[j]);
2711 /* Clear the pre-fetch instruction and set the FW start address. */
2712 REG_WR_IND(sc, cpu_reg->inst, 0);
2713 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2717 /****************************************************************************/
2718 /* Starts the RISC processor. */
2720 /* Assumes the CPU starting address has already been set. */
2724 /****************************************************************************/
2726 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2730 /* Start the CPU. */
2731 val = REG_RD_IND(sc, cpu_reg->mode);
2732 val &= ~cpu_reg->mode_value_halt;
2733 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2734 REG_WR_IND(sc, cpu_reg->mode, val);
2738 /****************************************************************************/
2739 /* Halts the RISC processor. */
2743 /****************************************************************************/
2745 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2750 val = REG_RD_IND(sc, cpu_reg->mode);
2751 val |= cpu_reg->mode_value_halt;
2752 REG_WR_IND(sc, cpu_reg->mode, val);
2753 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2757 /****************************************************************************/
2758 /* Start the RX CPU. */
2762 /****************************************************************************/
2764 bce_start_rxp_cpu(struct bce_softc *sc)
2766 struct cpu_reg cpu_reg;
2768 cpu_reg.mode = BCE_RXP_CPU_MODE;
2769 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2770 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2771 cpu_reg.state = BCE_RXP_CPU_STATE;
2772 cpu_reg.state_value_clear = 0xffffff;
2773 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2774 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2775 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2776 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2777 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2778 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2779 cpu_reg.mips_view_base = 0x8000000;
2781 bce_start_cpu(sc, &cpu_reg);
2785 /****************************************************************************/
2786 /* Initialize the RX CPU. */
2790 /****************************************************************************/
2792 bce_init_rxp_cpu(struct bce_softc *sc)
2794 struct cpu_reg cpu_reg;
2797 cpu_reg.mode = BCE_RXP_CPU_MODE;
2798 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2799 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2800 cpu_reg.state = BCE_RXP_CPU_STATE;
2801 cpu_reg.state_value_clear = 0xffffff;
2802 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2803 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2804 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2805 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2806 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2807 cpu_reg.spad_base = BCE_RXP_SCRATCH;
2808 cpu_reg.mips_view_base = 0x8000000;
2810 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2811 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2812 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2813 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2814 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2815 fw.start_addr = bce_RXP_b09FwStartAddr;
2817 fw.text_addr = bce_RXP_b09FwTextAddr;
2818 fw.text_len = bce_RXP_b09FwTextLen;
2820 fw.text = bce_RXP_b09FwText;
2822 fw.data_addr = bce_RXP_b09FwDataAddr;
2823 fw.data_len = bce_RXP_b09FwDataLen;
2825 fw.data = bce_RXP_b09FwData;
2827 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2828 fw.sbss_len = bce_RXP_b09FwSbssLen;
2830 fw.sbss = bce_RXP_b09FwSbss;
2832 fw.bss_addr = bce_RXP_b09FwBssAddr;
2833 fw.bss_len = bce_RXP_b09FwBssLen;
2835 fw.bss = bce_RXP_b09FwBss;
2837 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2838 fw.rodata_len = bce_RXP_b09FwRodataLen;
2839 fw.rodata_index = 0;
2840 fw.rodata = bce_RXP_b09FwRodata;
2842 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2843 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2844 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2845 fw.start_addr = bce_RXP_b06FwStartAddr;
2847 fw.text_addr = bce_RXP_b06FwTextAddr;
2848 fw.text_len = bce_RXP_b06FwTextLen;
2850 fw.text = bce_RXP_b06FwText;
2852 fw.data_addr = bce_RXP_b06FwDataAddr;
2853 fw.data_len = bce_RXP_b06FwDataLen;
2855 fw.data = bce_RXP_b06FwData;
2857 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2858 fw.sbss_len = bce_RXP_b06FwSbssLen;
2860 fw.sbss = bce_RXP_b06FwSbss;
2862 fw.bss_addr = bce_RXP_b06FwBssAddr;
2863 fw.bss_len = bce_RXP_b06FwBssLen;
2865 fw.bss = bce_RXP_b06FwBss;
2867 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2868 fw.rodata_len = bce_RXP_b06FwRodataLen;
2869 fw.rodata_index = 0;
2870 fw.rodata = bce_RXP_b06FwRodata;
2873 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2874 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2875 /* Delay RXP start until initialization is complete. */
2879 /****************************************************************************/
2880 /* Initialize the TX CPU. */
2884 /****************************************************************************/
2886 bce_init_txp_cpu(struct bce_softc *sc)
2888 struct cpu_reg cpu_reg;
2891 cpu_reg.mode = BCE_TXP_CPU_MODE;
2892 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2893 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2894 cpu_reg.state = BCE_TXP_CPU_STATE;
2895 cpu_reg.state_value_clear = 0xffffff;
2896 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2897 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2898 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2899 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2900 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2901 cpu_reg.spad_base = BCE_TXP_SCRATCH;
2902 cpu_reg.mips_view_base = 0x8000000;
2904 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2905 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2906 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2907 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2908 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2909 fw.start_addr = bce_TXP_b09FwStartAddr;
2911 fw.text_addr = bce_TXP_b09FwTextAddr;
2912 fw.text_len = bce_TXP_b09FwTextLen;
2914 fw.text = bce_TXP_b09FwText;
2916 fw.data_addr = bce_TXP_b09FwDataAddr;
2917 fw.data_len = bce_TXP_b09FwDataLen;
2919 fw.data = bce_TXP_b09FwData;
2921 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2922 fw.sbss_len = bce_TXP_b09FwSbssLen;
2924 fw.sbss = bce_TXP_b09FwSbss;
2926 fw.bss_addr = bce_TXP_b09FwBssAddr;
2927 fw.bss_len = bce_TXP_b09FwBssLen;
2929 fw.bss = bce_TXP_b09FwBss;
2931 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2932 fw.rodata_len = bce_TXP_b09FwRodataLen;
2933 fw.rodata_index = 0;
2934 fw.rodata = bce_TXP_b09FwRodata;
2936 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2937 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2938 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2939 fw.start_addr = bce_TXP_b06FwStartAddr;
2941 fw.text_addr = bce_TXP_b06FwTextAddr;
2942 fw.text_len = bce_TXP_b06FwTextLen;
2944 fw.text = bce_TXP_b06FwText;
2946 fw.data_addr = bce_TXP_b06FwDataAddr;
2947 fw.data_len = bce_TXP_b06FwDataLen;
2949 fw.data = bce_TXP_b06FwData;
2951 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2952 fw.sbss_len = bce_TXP_b06FwSbssLen;
2954 fw.sbss = bce_TXP_b06FwSbss;
2956 fw.bss_addr = bce_TXP_b06FwBssAddr;
2957 fw.bss_len = bce_TXP_b06FwBssLen;
2959 fw.bss = bce_TXP_b06FwBss;
2961 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2962 fw.rodata_len = bce_TXP_b06FwRodataLen;
2963 fw.rodata_index = 0;
2964 fw.rodata = bce_TXP_b06FwRodata;
2967 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2968 bce_load_cpu_fw(sc, &cpu_reg, &fw);
2969 bce_start_cpu(sc, &cpu_reg);
2973 /****************************************************************************/
2974 /* Initialize the TPAT CPU. */
2978 /****************************************************************************/
2980 bce_init_tpat_cpu(struct bce_softc *sc)
2982 struct cpu_reg cpu_reg;
2985 cpu_reg.mode = BCE_TPAT_CPU_MODE;
2986 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2987 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2988 cpu_reg.state = BCE_TPAT_CPU_STATE;
2989 cpu_reg.state_value_clear = 0xffffff;
2990 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2991 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2992 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2993 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2994 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2995 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2996 cpu_reg.mips_view_base = 0x8000000;
2998 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2999 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3000 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3001 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3002 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3003 fw.start_addr = bce_TPAT_b09FwStartAddr;
3005 fw.text_addr = bce_TPAT_b09FwTextAddr;
3006 fw.text_len = bce_TPAT_b09FwTextLen;
3008 fw.text = bce_TPAT_b09FwText;
3010 fw.data_addr = bce_TPAT_b09FwDataAddr;
3011 fw.data_len = bce_TPAT_b09FwDataLen;
3013 fw.data = bce_TPAT_b09FwData;
3015 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3016 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3018 fw.sbss = bce_TPAT_b09FwSbss;
3020 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3021 fw.bss_len = bce_TPAT_b09FwBssLen;
3023 fw.bss = bce_TPAT_b09FwBss;
3025 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3026 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3027 fw.rodata_index = 0;
3028 fw.rodata = bce_TPAT_b09FwRodata;
3030 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3031 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3032 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3033 fw.start_addr = bce_TPAT_b06FwStartAddr;
3035 fw.text_addr = bce_TPAT_b06FwTextAddr;
3036 fw.text_len = bce_TPAT_b06FwTextLen;
3038 fw.text = bce_TPAT_b06FwText;
3040 fw.data_addr = bce_TPAT_b06FwDataAddr;
3041 fw.data_len = bce_TPAT_b06FwDataLen;
3043 fw.data = bce_TPAT_b06FwData;
3045 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3046 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3048 fw.sbss = bce_TPAT_b06FwSbss;
3050 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3051 fw.bss_len = bce_TPAT_b06FwBssLen;
3053 fw.bss = bce_TPAT_b06FwBss;
3055 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3056 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3057 fw.rodata_index = 0;
3058 fw.rodata = bce_TPAT_b06FwRodata;
3061 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3062 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3063 bce_start_cpu(sc, &cpu_reg);
3067 /****************************************************************************/
3068 /* Initialize the CP CPU. */
3072 /****************************************************************************/
3074 bce_init_cp_cpu(struct bce_softc *sc)
3076 struct cpu_reg cpu_reg;
3079 cpu_reg.mode = BCE_CP_CPU_MODE;
3080 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3081 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3082 cpu_reg.state = BCE_CP_CPU_STATE;
3083 cpu_reg.state_value_clear = 0xffffff;
3084 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3085 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3086 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3087 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3088 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3089 cpu_reg.spad_base = BCE_CP_SCRATCH;
3090 cpu_reg.mips_view_base = 0x8000000;
3092 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3093 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3094 fw.ver_major = bce_CP_b09FwReleaseMajor;
3095 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3096 fw.ver_fix = bce_CP_b09FwReleaseFix;
3097 fw.start_addr = bce_CP_b09FwStartAddr;
3099 fw.text_addr = bce_CP_b09FwTextAddr;
3100 fw.text_len = bce_CP_b09FwTextLen;
3102 fw.text = bce_CP_b09FwText;
3104 fw.data_addr = bce_CP_b09FwDataAddr;
3105 fw.data_len = bce_CP_b09FwDataLen;
3107 fw.data = bce_CP_b09FwData;
3109 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3110 fw.sbss_len = bce_CP_b09FwSbssLen;
3112 fw.sbss = bce_CP_b09FwSbss;
3114 fw.bss_addr = bce_CP_b09FwBssAddr;
3115 fw.bss_len = bce_CP_b09FwBssLen;
3117 fw.bss = bce_CP_b09FwBss;
3119 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3120 fw.rodata_len = bce_CP_b09FwRodataLen;
3121 fw.rodata_index = 0;
3122 fw.rodata = bce_CP_b09FwRodata;
3124 fw.ver_major = bce_CP_b06FwReleaseMajor;
3125 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3126 fw.ver_fix = bce_CP_b06FwReleaseFix;
3127 fw.start_addr = bce_CP_b06FwStartAddr;
3129 fw.text_addr = bce_CP_b06FwTextAddr;
3130 fw.text_len = bce_CP_b06FwTextLen;
3132 fw.text = bce_CP_b06FwText;
3134 fw.data_addr = bce_CP_b06FwDataAddr;
3135 fw.data_len = bce_CP_b06FwDataLen;
3137 fw.data = bce_CP_b06FwData;
3139 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3140 fw.sbss_len = bce_CP_b06FwSbssLen;
3142 fw.sbss = bce_CP_b06FwSbss;
3144 fw.bss_addr = bce_CP_b06FwBssAddr;
3145 fw.bss_len = bce_CP_b06FwBssLen;
3147 fw.bss = bce_CP_b06FwBss;
3149 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3150 fw.rodata_len = bce_CP_b06FwRodataLen;
3151 fw.rodata_index = 0;
3152 fw.rodata = bce_CP_b06FwRodata;
3155 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3156 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3157 bce_start_cpu(sc, &cpu_reg);
3161 /****************************************************************************/
3162 /* Initialize the COM CPU. */
3166 /****************************************************************************/
3168 bce_init_com_cpu(struct bce_softc *sc)
3170 struct cpu_reg cpu_reg;
3173 cpu_reg.mode = BCE_COM_CPU_MODE;
3174 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3175 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3176 cpu_reg.state = BCE_COM_CPU_STATE;
3177 cpu_reg.state_value_clear = 0xffffff;
3178 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3179 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3180 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3181 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3182 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3183 cpu_reg.spad_base = BCE_COM_SCRATCH;
3184 cpu_reg.mips_view_base = 0x8000000;
3186 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3187 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3188 fw.ver_major = bce_COM_b09FwReleaseMajor;
3189 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3190 fw.ver_fix = bce_COM_b09FwReleaseFix;
3191 fw.start_addr = bce_COM_b09FwStartAddr;
3193 fw.text_addr = bce_COM_b09FwTextAddr;
3194 fw.text_len = bce_COM_b09FwTextLen;
3196 fw.text = bce_COM_b09FwText;
3198 fw.data_addr = bce_COM_b09FwDataAddr;
3199 fw.data_len = bce_COM_b09FwDataLen;
3201 fw.data = bce_COM_b09FwData;
3203 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3204 fw.sbss_len = bce_COM_b09FwSbssLen;
3206 fw.sbss = bce_COM_b09FwSbss;
3208 fw.bss_addr = bce_COM_b09FwBssAddr;
3209 fw.bss_len = bce_COM_b09FwBssLen;
3211 fw.bss = bce_COM_b09FwBss;
3213 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3214 fw.rodata_len = bce_COM_b09FwRodataLen;
3215 fw.rodata_index = 0;
3216 fw.rodata = bce_COM_b09FwRodata;
3218 fw.ver_major = bce_COM_b06FwReleaseMajor;
3219 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3220 fw.ver_fix = bce_COM_b06FwReleaseFix;
3221 fw.start_addr = bce_COM_b06FwStartAddr;
3223 fw.text_addr = bce_COM_b06FwTextAddr;
3224 fw.text_len = bce_COM_b06FwTextLen;
3226 fw.text = bce_COM_b06FwText;
3228 fw.data_addr = bce_COM_b06FwDataAddr;
3229 fw.data_len = bce_COM_b06FwDataLen;
3231 fw.data = bce_COM_b06FwData;
3233 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3234 fw.sbss_len = bce_COM_b06FwSbssLen;
3236 fw.sbss = bce_COM_b06FwSbss;
3238 fw.bss_addr = bce_COM_b06FwBssAddr;
3239 fw.bss_len = bce_COM_b06FwBssLen;
3241 fw.bss = bce_COM_b06FwBss;
3243 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3244 fw.rodata_len = bce_COM_b06FwRodataLen;
3245 fw.rodata_index = 0;
3246 fw.rodata = bce_COM_b06FwRodata;
3249 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3250 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3251 bce_start_cpu(sc, &cpu_reg);
3255 /****************************************************************************/
3256 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
3258 /* Loads the firmware for each CPU and starts the CPU. */
3262 /****************************************************************************/
3264 bce_init_cpus(struct bce_softc *sc)
3266 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3267 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3268 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3269 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3270 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3271 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3272 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3274 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3275 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3276 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3277 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3280 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3281 sizeof(bce_rv2p_proc1), RV2P_PROC1);
3282 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3283 sizeof(bce_rv2p_proc2), RV2P_PROC2);
3286 bce_init_rxp_cpu(sc);
3287 bce_init_txp_cpu(sc);
3288 bce_init_tpat_cpu(sc);
3289 bce_init_com_cpu(sc);
3290 bce_init_cp_cpu(sc);
3294 /****************************************************************************/
3295 /* Initialize context memory. */
3297 /* Clears the memory associated with each Context ID (CID). */
3301 /****************************************************************************/
3303 bce_init_ctx(struct bce_softc *sc)
3305 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3306 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3307 /* DRC: Replace this constant value with a #define. */
3308 int i, retry_cnt = 10;
3312 * BCM5709 context memory may be cached
3313 * in host memory so prepare the host memory
3316 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3318 val |= (BCM_PAGE_BITS - 8) << 16;
3319 REG_WR(sc, BCE_CTX_COMMAND, val);
3321 /* Wait for mem init command to complete. */
3322 for (i = 0; i < retry_cnt; i++) {
3323 val = REG_RD(sc, BCE_CTX_COMMAND);
3324 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3328 if (i == retry_cnt) {
3329 device_printf(sc->bce_dev,
3330 "Context memory initialization failed!\n");
3334 for (i = 0; i < sc->ctx_pages; i++) {
3338 * Set the physical address of the context
3341 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3342 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3343 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3344 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3345 BCE_ADDR_HI(sc->ctx_paddr[i]));
3346 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3347 i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3350 * Verify that the context memory write was successful.
3352 for (j = 0; j < retry_cnt; j++) {
3353 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3355 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3359 if (j == retry_cnt) {
3360 device_printf(sc->bce_dev,
3361 "Failed to initialize context page!\n");
3366 uint32_t vcid_addr, offset;
3369 * For the 5706/5708, context memory is local to
3370 * the controller, so initialize the controller
3374 vcid_addr = GET_CID_ADDR(96);
3376 vcid_addr -= PHY_CTX_SIZE;
3378 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3379 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3381 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3382 CTX_WR(sc, 0x00, offset, 0);
3384 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3385 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3392 /****************************************************************************/
3393 /* Fetch the permanent MAC address of the controller. */
3397 /****************************************************************************/
3399 bce_get_mac_addr(struct bce_softc *sc)
3401 uint32_t mac_lo = 0, mac_hi = 0;
3404 * The NetXtreme II bootcode populates various NIC
3405 * power-on and runtime configuration items in a
3406 * shared memory area. The factory configured MAC
3407 * address is available from both NVRAM and the
3408 * shared memory area so we'll read the value from
3409 * shared memory for speed.
3412 mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
3413 mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3415 if (mac_lo == 0 && mac_hi == 0) {
3416 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3418 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3419 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3420 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3421 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3422 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3423 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3426 DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3430 /****************************************************************************/
3431 /* Program the MAC address. */
3435 /****************************************************************************/
3437 bce_set_mac_addr(struct bce_softc *sc)
3439 const uint8_t *mac_addr = sc->eaddr;
3442 DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3445 val = (mac_addr[0] << 8) | mac_addr[1];
3446 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3448 val = (mac_addr[2] << 24) |
3449 (mac_addr[3] << 16) |
3450 (mac_addr[4] << 8) |
3452 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3456 /****************************************************************************/
3457 /* Stop the controller. */
3461 /****************************************************************************/
3463 bce_stop(struct bce_softc *sc)
3465 struct ifnet *ifp = &sc->arpcom.ac_if;
3467 ASSERT_SERIALIZED(ifp->if_serializer);
3469 callout_stop(&sc->bce_tick_callout);
3471 /* Disable the transmit/receive blocks. */
3472 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3473 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3476 bce_disable_intr(sc);
3478 /* Free the RX lists. */
3479 bce_free_rx_chain(sc);
3481 /* Free TX buffers. */
3482 bce_free_tx_chain(sc);
3485 sc->bce_coalchg_mask = 0;
3487 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3493 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3498 /* Wait for pending PCI transactions to complete. */
3499 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3500 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3501 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3502 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3503 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3504 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3508 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3509 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3510 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3511 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3512 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3515 /* Assume bootcode is running. */
3516 sc->bce_fw_timed_out = 0;
3517 sc->bce_drv_cardiac_arrest = 0;
3519 /* Give the firmware a chance to prepare for the reset. */
3520 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3522 if_printf(&sc->arpcom.ac_if,
3523 "Firmware is not ready for reset\n");
3527 /* Set a firmware reminder that this is a soft reset. */
3528 bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3529 BCE_DRV_RESET_SIGNATURE_MAGIC);
3531 /* Dummy read to force the chip to complete all current transactions. */
3532 val = REG_RD(sc, BCE_MISC_ID);
3535 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3536 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3537 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3538 REG_RD(sc, BCE_MISC_COMMAND);
3541 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3542 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3544 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3546 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3547 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3548 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3549 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3551 /* Allow up to 30us for reset to complete. */
3552 for (i = 0; i < 10; i++) {
3553 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3554 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3555 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3560 /* Check that reset completed successfully. */
3561 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3562 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3563 if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3568 /* Make sure byte swapping is properly configured. */
3569 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3570 if (val != 0x01020304) {
3571 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3575 /* Just completed a reset, assume that firmware is running again. */
3576 sc->bce_fw_timed_out = 0;
3577 sc->bce_drv_cardiac_arrest = 0;
3579 /* Wait for the firmware to finish its initialization. */
3580 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3582 if_printf(&sc->arpcom.ac_if,
3583 "Firmware did not complete initialization!\n");
3590 bce_chipinit(struct bce_softc *sc)
3595 /* Make sure the interrupt is not active. */
3596 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3597 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3600 * Initialize DMA byte/word swapping, configure the number of DMA
3601 * channels and PCI clock compensation delay.
3603 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3604 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3605 #if BYTE_ORDER == BIG_ENDIAN
3606 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3608 BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3609 DMA_READ_CHANS << 12 |
3610 DMA_WRITE_CHANS << 16;
3612 val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3614 if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3615 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3618 * This setting resolves a problem observed on certain Intel PCI
3619 * chipsets that cannot handle multiple outstanding DMA operations.
3620 * See errata E9_5706A1_65.
3622 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3623 BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3624 !(sc->bce_flags & BCE_PCIX_FLAG))
3625 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3627 REG_WR(sc, BCE_DMA_CONFIG, val);
3629 /* Enable the RX_V2P and Context state machines before access. */
3630 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3631 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3632 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3633 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3635 /* Initialize context mapping and zero out the quick contexts. */
3636 rc = bce_init_ctx(sc);
3640 /* Initialize the on-boards CPUs */
3643 /* Enable management frames (NC-SI) to flow to the MCP. */
3644 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3645 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3646 BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3647 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3650 /* Prepare NVRAM for access. */
3651 rc = bce_init_nvram(sc);
3655 /* Set the kernel bypass block size */
3656 val = REG_RD(sc, BCE_MQ_CONFIG);
3657 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3658 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3660 /* Enable bins used on the 5709/5716. */
3661 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3662 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3663 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3664 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3665 val |= BCE_MQ_CONFIG_HALT_DIS;
3668 REG_WR(sc, BCE_MQ_CONFIG, val);
3670 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3671 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3672 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3674 /* Set the page size and clear the RV2P processor stall bits. */
3675 val = (BCM_PAGE_BITS - 8) << 24;
3676 REG_WR(sc, BCE_RV2P_CONFIG, val);
3678 /* Configure page size. */
3679 val = REG_RD(sc, BCE_TBDR_CONFIG);
3680 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3681 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3682 REG_WR(sc, BCE_TBDR_CONFIG, val);
3684 /* Set the perfect match control register to default. */
3685 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3691 /****************************************************************************/
3692 /* Initialize the controller in preparation to send/receive traffic. */
3695 /* 0 for success, positive value for failure. */
3696 /****************************************************************************/
3698 bce_blockinit(struct bce_softc *sc)
3703 /* Load the hardware default MAC address. */
3704 bce_set_mac_addr(sc);
3706 /* Set the Ethernet backoff seed value */
3707 val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3708 sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3709 REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3711 sc->last_status_idx = 0;
3712 sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3714 sc->pulse_check_status_idx = 0xffff;
3716 /* Set up link change interrupt generation. */
3717 REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3719 /* Program the physical address of the status block. */
3720 REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3721 REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3723 /* Program the physical address of the statistics block. */
3724 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3725 BCE_ADDR_LO(sc->stats_block_paddr));
3726 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3727 BCE_ADDR_HI(sc->stats_block_paddr));
3729 /* Program various host coalescing parameters. */
3730 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3731 (sc->bce_tx_quick_cons_trip_int << 16) |
3732 sc->bce_tx_quick_cons_trip);
3733 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3734 (sc->bce_rx_quick_cons_trip_int << 16) |
3735 sc->bce_rx_quick_cons_trip);
3736 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3737 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3738 REG_WR(sc, BCE_HC_TX_TICKS,
3739 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3740 REG_WR(sc, BCE_HC_RX_TICKS,
3741 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3742 REG_WR(sc, BCE_HC_COM_TICKS,
3743 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3744 REG_WR(sc, BCE_HC_CMD_TICKS,
3745 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3746 REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3747 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3749 val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3750 if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3752 if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3753 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3755 REG_WR(sc, BCE_HC_CONFIG, val);
3757 /* Clear the internal statistics counters. */
3758 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3760 /* Verify that bootcode is running. */
3761 reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3763 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3764 if_printf(&sc->arpcom.ac_if,
3765 "%s(%d): Simulating bootcode failure.\n",
3766 __FILE__, __LINE__);
3769 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3770 BCE_DEV_INFO_SIGNATURE_MAGIC) {
3771 if_printf(&sc->arpcom.ac_if,
3772 "Bootcode not running! Found: 0x%08X, "
3773 "Expected: 08%08X\n",
3774 reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3775 BCE_DEV_INFO_SIGNATURE_MAGIC);
3780 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3781 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3782 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3783 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3784 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3787 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3788 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3790 /* Enable link state change interrupt generation. */
3791 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3793 /* Enable the RXP. */
3794 bce_start_rxp_cpu(sc);
3796 /* Disable management frames (NC-SI) from flowing to the MCP. */
3797 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3798 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3799 ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3800 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3803 /* Enable all remaining blocks in the MAC. */
3804 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3805 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3806 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3807 BCE_MISC_ENABLE_DEFAULT_XI);
3809 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3811 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3814 /* Save the current host coalescing block settings. */
3815 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3821 /****************************************************************************/
3822 /* Encapsulate an mbuf cluster into the rx_bd chain. */
3824 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's. */
3825 /* This routine will map an mbuf cluster into 1 or more rx_bd's as */
3829 /* 0 for success, positive value for failure. */
3830 /****************************************************************************/
3832 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3833 uint32_t *prod_bseq, int init)
3836 bus_dma_segment_t seg;
3840 uint16_t debug_chain_prod = *chain_prod;
3843 /* Make sure the inputs are valid. */
3844 DBRUNIF((*chain_prod > MAX_RX_BD(sc)),
3845 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3846 "RX producer out of range: 0x%04X > 0x%04X\n",
3848 *chain_prod, (uint16_t)MAX_RX_BD(sc)));
3850 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3851 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3853 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3854 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3855 "Simulating mbuf allocation failure.\n",
3856 __FILE__, __LINE__);
3857 sc->mbuf_alloc_failed++;
3860 /* This is a new mbuf allocation. */
3861 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3864 DBRUNIF(1, sc->rx_mbuf_alloc++);
3866 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3868 /* Map the mbuf cluster into device memory. */
3869 error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3870 sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3875 if_printf(&sc->arpcom.ac_if,
3876 "Error mapping mbuf into RX chain!\n");
3878 DBRUNIF(1, sc->rx_mbuf_alloc--);
3882 if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3883 bus_dmamap_unload(sc->rx_mbuf_tag,
3884 sc->rx_mbuf_map[*chain_prod]);
3887 map = sc->rx_mbuf_map[*chain_prod];
3888 sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3889 sc->rx_mbuf_tmpmap = map;
3891 /* Watch for overflow. */
3892 DBRUNIF((sc->free_rx_bd > USABLE_RX_BD(sc)),
3893 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3894 "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3895 __FILE__, __LINE__, sc->free_rx_bd,
3896 (uint16_t)USABLE_RX_BD(sc)));
3898 /* Update some debug statistic counters */
3899 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3900 sc->rx_low_watermark = sc->free_rx_bd);
3901 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3903 /* Save the mbuf and update our counter. */
3904 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3905 sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3908 bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3910 DBRUN(BCE_VERBOSE_RECV,
3911 bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3913 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3914 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3921 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3927 paddr = sc->rx_mbuf_paddr[chain_prod];
3928 len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3930 /* Setup the rx_bd for the first segment. */
3931 rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3933 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3934 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3935 rxbd->rx_bd_len = htole32(len);
3936 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3939 rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3943 /****************************************************************************/
3944 /* Initialize the TX context memory. */
3948 /****************************************************************************/
3950 bce_init_tx_context(struct bce_softc *sc)
3954 /* Initialize the context ID for an L2 TX chain. */
3955 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3956 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3957 /* Set the CID type to support an L2 connection. */
3958 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3959 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3960 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3961 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3963 /* Point the hardware to the first page in the chain. */
3964 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3965 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3966 BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3967 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3968 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3969 BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3971 /* Set the CID type to support an L2 connection. */
3972 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3973 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3974 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3975 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3977 /* Point the hardware to the first page in the chain. */
3978 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3979 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3980 BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3981 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3982 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3983 BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3988 /****************************************************************************/
3989 /* Allocate memory and initialize the TX data structures. */
3992 /* 0 for success, positive value for failure. */
3993 /****************************************************************************/
3995 bce_init_tx_chain(struct bce_softc *sc)
4000 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4002 /* Set the initial TX producer/consumer indices. */
4005 sc->tx_prod_bseq = 0;
4007 sc->max_tx_bd = USABLE_TX_BD(sc);
4008 DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD(sc));
4009 DBRUNIF(1, sc->tx_full_count = 0);
4012 * The NetXtreme II supports a linked-list structre called
4013 * a Buffer Descriptor Chain (or BD chain). A BD chain
4014 * consists of a series of 1 or more chain pages, each of which
4015 * consists of a fixed number of BD entries.
4016 * The last BD entry on each page is a pointer to the next page
4017 * in the chain, and the last pointer in the BD chain
4018 * points back to the beginning of the chain.
4021 /* Set the TX next pointer chain entries. */
4022 for (i = 0; i < sc->tx_pages; i++) {
4025 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
4027 /* Check if we've reached the last page. */
4028 if (i == (sc->tx_pages - 1))
4033 txbd->tx_bd_haddr_hi =
4034 htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4035 txbd->tx_bd_haddr_lo =
4036 htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4038 bce_init_tx_context(sc);
4044 /****************************************************************************/
4045 /* Free memory and clear the TX data structures. */
4049 /****************************************************************************/
4051 bce_free_tx_chain(struct bce_softc *sc)
4055 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4057 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4058 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
4059 if (sc->tx_mbuf_ptr[i] != NULL) {
4060 bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
4061 m_freem(sc->tx_mbuf_ptr[i]);
4062 sc->tx_mbuf_ptr[i] = NULL;
4063 DBRUNIF(1, sc->tx_mbuf_alloc--);
4067 /* Clear each TX chain page. */
4068 for (i = 0; i < sc->tx_pages; i++)
4069 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4072 /* Check if we lost any mbufs in the process. */
4073 DBRUNIF((sc->tx_mbuf_alloc),
4074 if_printf(&sc->arpcom.ac_if,
4075 "%s(%d): Memory leak! "
4076 "Lost %d mbufs from tx chain!\n",
4077 __FILE__, __LINE__, sc->tx_mbuf_alloc));
4079 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4083 /****************************************************************************/
4084 /* Initialize the RX context memory. */
4088 /****************************************************************************/
4090 bce_init_rx_context(struct bce_softc *sc)
4094 /* Initialize the context ID for an L2 RX chain. */
4095 val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4096 BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4099 * Set the level for generating pause frames
4100 * when the number of available rx_bd's gets
4101 * too low (the low watermark) and the level
4102 * when pause frames can be stopped (the high
4105 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4106 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4107 uint32_t lo_water, hi_water;
4109 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4110 hi_water = USABLE_RX_BD(sc) / 4;
4112 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4113 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4117 else if (hi_water == 0)
4120 (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4123 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4125 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4126 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4127 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4128 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4129 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4132 /* Point the hardware to the first page in the chain. */
4133 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4134 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4135 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4136 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4140 /****************************************************************************/
4141 /* Allocate memory and initialize the RX data structures. */
4144 /* 0 for success, positive value for failure. */
4145 /****************************************************************************/
4147 bce_init_rx_chain(struct bce_softc *sc)
4151 uint16_t prod, chain_prod;
4154 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4156 /* Initialize the RX producer and consumer indices. */
4159 sc->rx_prod_bseq = 0;
4160 sc->free_rx_bd = USABLE_RX_BD(sc);
4161 sc->max_rx_bd = USABLE_RX_BD(sc);
4162 DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD(sc));
4163 DBRUNIF(1, sc->rx_empty_count = 0);
4165 /* Initialize the RX next pointer chain entries. */
4166 for (i = 0; i < sc->rx_pages; i++) {
4169 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4171 /* Check if we've reached the last page. */
4172 if (i == (sc->rx_pages - 1))
4177 /* Setup the chain page pointers. */
4178 rxbd->rx_bd_haddr_hi =
4179 htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4180 rxbd->rx_bd_haddr_lo =
4181 htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4184 /* Allocate mbuf clusters for the rx_bd chain. */
4185 prod = prod_bseq = 0;
4186 while (prod < TOTAL_RX_BD(sc)) {
4187 chain_prod = RX_CHAIN_IDX(sc, prod);
4188 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4189 if_printf(&sc->arpcom.ac_if,
4190 "Error filling RX chain: rx_bd[0x%04X]!\n",
4195 prod = NEXT_RX_BD(prod);
4198 /* Save the RX chain producer index. */
4200 sc->rx_prod_bseq = prod_bseq;
4202 /* Tell the chip about the waiting rx_bd's. */
4203 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4205 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4208 bce_init_rx_context(sc);
4214 /****************************************************************************/
4215 /* Free memory and clear the RX data structures. */
4219 /****************************************************************************/
4221 bce_free_rx_chain(struct bce_softc *sc)
4225 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4227 /* Free any mbufs still in the RX mbuf chain. */
4228 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
4229 if (sc->rx_mbuf_ptr[i] != NULL) {
4230 bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4231 m_freem(sc->rx_mbuf_ptr[i]);
4232 sc->rx_mbuf_ptr[i] = NULL;
4233 DBRUNIF(1, sc->rx_mbuf_alloc--);
4237 /* Clear each RX chain page. */
4238 for (i = 0; i < sc->rx_pages; i++)
4239 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4241 /* Check if we lost any mbufs in the process. */
4242 DBRUNIF((sc->rx_mbuf_alloc),
4243 if_printf(&sc->arpcom.ac_if,
4244 "%s(%d): Memory leak! "
4245 "Lost %d mbufs from rx chain!\n",
4246 __FILE__, __LINE__, sc->rx_mbuf_alloc));
4248 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4252 /****************************************************************************/
4253 /* Set media options. */
4256 /* 0 for success, positive value for failure. */
4257 /****************************************************************************/
4259 bce_ifmedia_upd(struct ifnet *ifp)
4261 struct bce_softc *sc = ifp->if_softc;
4262 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4266 * 'mii' will be NULL, when this function is called on following
4267 * code path: bce_attach() -> bce_mgmt_init()
4270 /* Make sure the MII bus has been enumerated. */
4272 if (mii->mii_instance) {
4273 struct mii_softc *miisc;
4275 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4276 mii_phy_reset(miisc);
4278 error = mii_mediachg(mii);
4284 /****************************************************************************/
4285 /* Reports current media status. */
4289 /****************************************************************************/
4291 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4293 struct bce_softc *sc = ifp->if_softc;
4294 struct mii_data *mii = device_get_softc(sc->bce_miibus);
4297 ifmr->ifm_active = mii->mii_media_active;
4298 ifmr->ifm_status = mii->mii_media_status;
4302 /****************************************************************************/
4303 /* Handles PHY generated interrupt events. */
4307 /****************************************************************************/
4309 bce_phy_intr(struct bce_softc *sc)
4311 uint32_t new_link_state, old_link_state;
4312 struct ifnet *ifp = &sc->arpcom.ac_if;
4314 ASSERT_SERIALIZED(ifp->if_serializer);
4316 new_link_state = sc->status_block->status_attn_bits &
4317 STATUS_ATTN_BITS_LINK_STATE;
4318 old_link_state = sc->status_block->status_attn_bits_ack &
4319 STATUS_ATTN_BITS_LINK_STATE;
4321 /* Handle any changes if the link state has changed. */
4322 if (new_link_state != old_link_state) { /* XXX redundant? */
4323 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4325 /* Update the status_attn_bits_ack field in the status block. */
4326 if (new_link_state) {
4327 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4328 STATUS_ATTN_BITS_LINK_STATE);
4330 if_printf(ifp, "Link is now UP.\n");
4332 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4333 STATUS_ATTN_BITS_LINK_STATE);
4335 if_printf(ifp, "Link is now DOWN.\n");
4339 * Assume link is down and allow tick routine to
4340 * update the state based on the actual media state.
4343 callout_stop(&sc->bce_tick_callout);
4344 bce_tick_serialized(sc);
4347 /* Acknowledge the link change interrupt. */
4348 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4352 /****************************************************************************/
4353 /* Reads the receive consumer value from the status block (skipping over */
4354 /* chain page pointer if necessary). */
4358 /****************************************************************************/
4359 static __inline uint16_t
4360 bce_get_hw_rx_cons(struct bce_softc *sc)
4362 uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4364 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4370 /****************************************************************************/
4371 /* Handles received frame interrupt events. */
4375 /****************************************************************************/
4377 bce_rx_intr(struct bce_softc *sc, int count)
4379 struct ifnet *ifp = &sc->arpcom.ac_if;
4380 uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4381 uint32_t sw_prod_bseq;
4383 ASSERT_SERIALIZED(ifp->if_serializer);
4385 DBRUNIF(1, sc->rx_interrupts++);
4387 /* Get the hardware's view of the RX consumer index. */
4388 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4390 /* Get working copies of the driver's view of the RX indices. */
4391 sw_cons = sc->rx_cons;
4392 sw_prod = sc->rx_prod;
4393 sw_prod_bseq = sc->rx_prod_bseq;
4395 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4396 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4397 __func__, sw_prod, sw_cons, sw_prod_bseq);
4399 /* Prevent speculative reads from getting ahead of the status block. */
4400 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4401 BUS_SPACE_BARRIER_READ);
4403 /* Update some debug statistics counters */
4404 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4405 sc->rx_low_watermark = sc->free_rx_bd);
4406 DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4408 /* Scan through the receive chain as long as there is work to do. */
4409 while (sw_cons != hw_cons) {
4410 struct mbuf *m = NULL;
4411 struct l2_fhdr *l2fhdr = NULL;
4414 uint32_t status = 0;
4416 #ifdef DEVICE_POLLING
4417 if (count >= 0 && count-- == 0) {
4418 sc->hw_rx_cons = sw_cons;
4424 * Convert the producer/consumer indices
4425 * to an actual rx_bd index.
4427 sw_chain_cons = RX_CHAIN_IDX(sc, sw_cons);
4428 sw_chain_prod = RX_CHAIN_IDX(sc, sw_prod);
4430 /* Get the used rx_bd. */
4431 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4432 [RX_IDX(sw_chain_cons)];
4435 DBRUN(BCE_VERBOSE_RECV,
4436 if_printf(ifp, "%s(): ", __func__);
4437 bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4439 /* The mbuf is stored with the last rx_bd entry of a packet. */
4440 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4441 /* Validate that this is the last rx_bd. */
4442 DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4443 if_printf(ifp, "%s(%d): "
4444 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4445 __FILE__, __LINE__, sw_chain_cons);
4446 bce_breakpoint(sc));
4448 if (sw_chain_cons != sw_chain_prod) {
4449 if_printf(ifp, "RX cons(%d) != prod(%d), "
4450 "drop!\n", sw_chain_cons,
4454 bce_setup_rxdesc_std(sc, sw_chain_cons,
4457 goto bce_rx_int_next_rx;
4460 /* Unmap the mbuf from DMA space. */
4461 bus_dmamap_sync(sc->rx_mbuf_tag,
4462 sc->rx_mbuf_map[sw_chain_cons],
4463 BUS_DMASYNC_POSTREAD);
4465 /* Save the mbuf from the driver's chain. */
4466 m = sc->rx_mbuf_ptr[sw_chain_cons];
4469 * Frames received on the NetXteme II are prepended
4470 * with an l2_fhdr structure which provides status
4471 * information about the received frame (including
4472 * VLAN tags and checksum info). The frames are also
4473 * automatically adjusted to align the IP header
4474 * (i.e. two null bytes are inserted before the
4475 * Ethernet header). As a result the data DMA'd by
4476 * the controller into the mbuf is as follows:
4478 * +---------+-----+---------------------+-----+
4479 * | l2_fhdr | pad | packet data | FCS |
4480 * +---------+-----+---------------------+-----+
4482 * The l2_fhdr needs to be checked and skipped and the
4483 * FCS needs to be stripped before sending the packet
4486 l2fhdr = mtod(m, struct l2_fhdr *);
4488 len = l2fhdr->l2_fhdr_pkt_len;
4489 status = l2fhdr->l2_fhdr_status;
4491 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4493 "Simulating l2_fhdr status error.\n");
4494 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4496 /* Watch for unusual sized frames. */
4497 DBRUNIF((len < BCE_MIN_MTU ||
4498 len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4500 "%s(%d): Unusual frame size found. "
4501 "Min(%d), Actual(%d), Max(%d)\n",
4503 (int)BCE_MIN_MTU, len,
4504 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4505 bce_dump_mbuf(sc, m);
4506 bce_breakpoint(sc));
4508 len -= ETHER_CRC_LEN;
4510 /* Check the received frame for errors. */
4511 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4512 L2_FHDR_ERRORS_PHY_DECODE |
4513 L2_FHDR_ERRORS_ALIGNMENT |
4514 L2_FHDR_ERRORS_TOO_SHORT |
4515 L2_FHDR_ERRORS_GIANT_FRAME)) {
4517 DBRUNIF(1, sc->l2fhdr_status_errors++);
4519 /* Reuse the mbuf for a new frame. */
4520 bce_setup_rxdesc_std(sc, sw_chain_prod,
4523 goto bce_rx_int_next_rx;
4527 * Get a new mbuf for the rx_bd. If no new
4528 * mbufs are available then reuse the current mbuf,
4529 * log an ierror on the interface, and generate
4530 * an error in the system log.
4532 if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4533 &sw_prod_bseq, 0)) {
4536 "%s(%d): Failed to allocate new mbuf, "
4537 "incoming frame dropped!\n",
4538 __FILE__, __LINE__));
4542 /* Try and reuse the exisitng mbuf. */
4543 bce_setup_rxdesc_std(sc, sw_chain_prod,
4546 goto bce_rx_int_next_rx;
4550 * Skip over the l2_fhdr when passing
4551 * the data up the stack.
4553 m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4555 m->m_pkthdr.len = m->m_len = len;
4556 m->m_pkthdr.rcvif = ifp;
4558 DBRUN(BCE_VERBOSE_RECV,
4559 struct ether_header *eh;
4560 eh = mtod(m, struct ether_header *);
4561 if_printf(ifp, "%s(): to: %6D, from: %6D, "
4562 "type: 0x%04X\n", __func__,
4563 eh->ether_dhost, ":",
4564 eh->ether_shost, ":",
4565 htons(eh->ether_type)));
4567 /* Validate the checksum if offload enabled. */
4568 if (ifp->if_capenable & IFCAP_RXCSUM) {
4569 /* Check for an IP datagram. */
4570 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4571 m->m_pkthdr.csum_flags |=
4574 /* Check if the IP checksum is valid. */
4575 if ((l2fhdr->l2_fhdr_ip_xsum ^
4577 m->m_pkthdr.csum_flags |=
4580 DBPRINT(sc, BCE_WARN_RECV,
4581 "%s(): Invalid IP checksum = 0x%04X!\n",
4582 __func__, l2fhdr->l2_fhdr_ip_xsum);
4586 /* Check for a valid TCP/UDP frame. */
4587 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4588 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4590 /* Check for a good TCP/UDP checksum. */
4592 (L2_FHDR_ERRORS_TCP_XSUM |
4593 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4594 m->m_pkthdr.csum_data =
4595 l2fhdr->l2_fhdr_tcp_udp_xsum;
4596 m->m_pkthdr.csum_flags |=
4600 DBPRINT(sc, BCE_WARN_RECV,
4601 "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4602 __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4609 sw_prod = NEXT_RX_BD(sw_prod);
4612 sw_cons = NEXT_RX_BD(sw_cons);
4614 /* If we have a packet, pass it up the stack */
4616 DBPRINT(sc, BCE_VERBOSE_RECV,
4617 "%s(): Passing received frame up.\n", __func__);
4619 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4620 m->m_flags |= M_VLANTAG;
4621 m->m_pkthdr.ether_vlantag =
4622 l2fhdr->l2_fhdr_vlan_tag;
4624 ifp->if_input(ifp, m);
4626 DBRUNIF(1, sc->rx_mbuf_alloc--);
4630 * If polling(4) is not enabled, refresh hw_cons to see
4631 * whether there's new work.
4633 * If polling(4) is enabled, i.e count >= 0, refreshing
4634 * should not be performed, so that we would not spend
4635 * too much time in RX processing.
4637 if (count < 0 && sw_cons == hw_cons)
4638 hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4641 * Prevent speculative reads from getting ahead
4642 * of the status block.
4644 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4645 BUS_SPACE_BARRIER_READ);
4648 sc->rx_cons = sw_cons;
4649 sc->rx_prod = sw_prod;
4650 sc->rx_prod_bseq = sw_prod_bseq;
4652 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4654 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4657 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4658 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4659 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4663 /****************************************************************************/
4664 /* Reads the transmit consumer value from the status block (skipping over */
4665 /* chain page pointer if necessary). */
4669 /****************************************************************************/
4670 static __inline uint16_t
4671 bce_get_hw_tx_cons(struct bce_softc *sc)
4673 uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4675 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4681 /****************************************************************************/
4682 /* Handles transmit completion interrupt events. */
4686 /****************************************************************************/
4688 bce_tx_intr(struct bce_softc *sc)
4690 struct ifnet *ifp = &sc->arpcom.ac_if;
4691 uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4693 ASSERT_SERIALIZED(ifp->if_serializer);
4695 DBRUNIF(1, sc->tx_interrupts++);
4697 /* Get the hardware's view of the TX consumer index. */
4698 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4699 sw_tx_cons = sc->tx_cons;
4701 /* Prevent speculative reads from getting ahead of the status block. */
4702 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4703 BUS_SPACE_BARRIER_READ);
4705 /* Cycle through any completed TX chain page entries. */
4706 while (sw_tx_cons != hw_tx_cons) {
4708 struct tx_bd *txbd = NULL;
4710 sw_tx_chain_cons = TX_CHAIN_IDX(sc, sw_tx_cons);
4712 DBPRINT(sc, BCE_INFO_SEND,
4713 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4714 "sw_tx_chain_cons = 0x%04X\n",
4715 __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4717 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD(sc)),
4718 if_printf(ifp, "%s(%d): "
4719 "TX chain consumer out of range! "
4720 " 0x%04X > 0x%04X\n",
4721 __FILE__, __LINE__, sw_tx_chain_cons,
4722 (int)MAX_TX_BD(sc));
4723 bce_breakpoint(sc));
4725 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4726 [TX_IDX(sw_tx_chain_cons)]);
4728 DBRUNIF((txbd == NULL),
4729 if_printf(ifp, "%s(%d): "
4730 "Unexpected NULL tx_bd[0x%04X]!\n",
4731 __FILE__, __LINE__, sw_tx_chain_cons);
4732 bce_breakpoint(sc));
4734 DBRUN(BCE_INFO_SEND,
4735 if_printf(ifp, "%s(): ", __func__);
4736 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4739 * Free the associated mbuf. Remember
4740 * that only the last tx_bd of a packet
4741 * has an mbuf pointer and DMA map.
4743 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4744 /* Validate that this is the last tx_bd. */
4745 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4746 if_printf(ifp, "%s(%d): "
4747 "tx_bd END flag not set but "
4748 "txmbuf == NULL!\n", __FILE__, __LINE__);
4749 bce_breakpoint(sc));
4751 DBRUN(BCE_INFO_SEND,
4752 if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4753 "from tx_bd[0x%04X]\n", __func__,
4756 /* Unmap the mbuf. */
4757 bus_dmamap_unload(sc->tx_mbuf_tag,
4758 sc->tx_mbuf_map[sw_tx_chain_cons]);
4760 /* Free the mbuf. */
4761 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4762 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4763 DBRUNIF(1, sc->tx_mbuf_alloc--);
4769 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4771 if (sw_tx_cons == hw_tx_cons) {
4772 /* Refresh hw_cons to see if there's new work. */
4773 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4777 * Prevent speculative reads from getting
4778 * ahead of the status block.
4780 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4781 BUS_SPACE_BARRIER_READ);
4784 if (sc->used_tx_bd == 0) {
4785 /* Clear the TX timeout timer. */
4789 /* Clear the tx hardware queue full flag. */
4790 if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4791 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4792 DBPRINT(sc, BCE_WARN_SEND,
4793 "%s(): Open TX chain! %d/%d (used/total)\n",
4794 __func__, sc->used_tx_bd, sc->max_tx_bd));
4795 ifp->if_flags &= ~IFF_OACTIVE;
4797 sc->tx_cons = sw_tx_cons;
4801 /****************************************************************************/
4802 /* Disables interrupt generation. */
4806 /****************************************************************************/
4808 bce_disable_intr(struct bce_softc *sc)
4810 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4811 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4812 lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4816 /****************************************************************************/
4817 /* Enables interrupt generation. */
4821 /****************************************************************************/
4823 bce_enable_intr(struct bce_softc *sc, int coal_now)
4825 lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4827 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4828 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4829 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4831 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4832 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4835 REG_WR(sc, BCE_HC_COMMAND,
4836 sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4841 /****************************************************************************/
4842 /* Handles controller initialization. */
4846 /****************************************************************************/
4850 struct bce_softc *sc = xsc;
4851 struct ifnet *ifp = &sc->arpcom.ac_if;
4855 ASSERT_SERIALIZED(ifp->if_serializer);
4857 /* Check if the driver is still running and bail out if it is. */
4858 if (ifp->if_flags & IFF_RUNNING)
4863 error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4865 if_printf(ifp, "Controller reset failed!\n");
4869 error = bce_chipinit(sc);
4871 if_printf(ifp, "Controller initialization failed!\n");
4875 error = bce_blockinit(sc);
4877 if_printf(ifp, "Block initialization failed!\n");
4881 /* Load our MAC address. */
4882 bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4883 bce_set_mac_addr(sc);
4885 /* Calculate and program the Ethernet MTU size. */
4886 ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4888 DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4891 * Program the mtu, enabling jumbo frame
4892 * support if necessary. Also set the mbuf
4893 * allocation count for RX frames.
4895 if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4897 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4898 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4899 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4900 sc->mbuf_alloc_size = MJUM9BYTES;
4902 panic("jumbo buffer is not supported yet");
4905 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4906 sc->mbuf_alloc_size = MCLBYTES;
4909 /* Calculate the RX Ethernet frame size for rx_bd's. */
4910 sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4912 DBPRINT(sc, BCE_INFO,
4913 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4914 "max_frame_size = %d\n",
4915 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4916 sc->max_frame_size);
4918 /* Program appropriate promiscuous/multicast filtering. */
4919 bce_set_rx_mode(sc);
4921 /* Init RX buffer descriptor chain. */
4922 bce_init_rx_chain(sc); /* XXX return value */
4924 /* Init TX buffer descriptor chain. */
4925 bce_init_tx_chain(sc); /* XXX return value */
4927 #ifdef DEVICE_POLLING
4928 /* Disable interrupts if we are polling. */
4929 if (ifp->if_flags & IFF_POLLING) {
4930 bce_disable_intr(sc);
4932 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4933 (1 << 16) | sc->bce_rx_quick_cons_trip);
4934 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4935 (1 << 16) | sc->bce_tx_quick_cons_trip);
4938 /* Enable host interrupts. */
4939 bce_enable_intr(sc, 1);
4941 bce_ifmedia_upd(ifp);
4943 ifp->if_flags |= IFF_RUNNING;
4944 ifp->if_flags &= ~IFF_OACTIVE;
4946 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4953 /****************************************************************************/
4954 /* Initialize the controller just enough so that any management firmware */
4955 /* running on the device will continue to operate corectly. */
4959 /****************************************************************************/
4961 bce_mgmt_init(struct bce_softc *sc)
4963 struct ifnet *ifp = &sc->arpcom.ac_if;
4965 /* Bail out if management firmware is not running. */
4966 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4969 /* Enable all critical blocks in the MAC. */
4970 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4971 BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4972 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4973 BCE_MISC_ENABLE_DEFAULT_XI);
4975 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4977 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4980 bce_ifmedia_upd(ifp);
4984 /****************************************************************************/
4985 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4986 /* memory visible to the controller. */
4989 /* 0 for success, positive value for failure. */
4990 /****************************************************************************/
4992 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4994 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4995 bus_dmamap_t map, tmp_map;
4996 struct mbuf *m0 = *m_head;
4997 struct tx_bd *txbd = NULL;
4998 uint16_t vlan_tag = 0, flags = 0;
4999 uint16_t chain_prod, chain_prod_start, prod;
5001 int i, error, maxsegs, nsegs;
5003 uint16_t debug_prod;
5006 /* Transfer any checksum offload flags to the bd. */
5007 if (m0->m_pkthdr.csum_flags) {
5008 if (m0->m_pkthdr.csum_flags & CSUM_IP)
5009 flags |= TX_BD_FLAGS_IP_CKSUM;
5010 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
5011 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5014 /* Transfer any VLAN tags to the bd. */
5015 if (m0->m_flags & M_VLANTAG) {
5016 flags |= TX_BD_FLAGS_VLAN_TAG;
5017 vlan_tag = m0->m_pkthdr.ether_vlantag;
5021 chain_prod_start = chain_prod = TX_CHAIN_IDX(sc, prod);
5023 /* Map the mbuf into DMAable memory. */
5024 map = sc->tx_mbuf_map[chain_prod_start];
5026 maxsegs = sc->max_tx_bd - sc->used_tx_bd;
5027 KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
5028 ("not enough segments %d", maxsegs));
5029 if (maxsegs > BCE_MAX_SEGMENTS)
5030 maxsegs = BCE_MAX_SEGMENTS;
5032 /* Map the mbuf into our DMA address space. */
5033 error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
5034 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
5037 bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
5042 /* prod points to an empty tx_bd at this point. */
5043 prod_bseq = sc->tx_prod_bseq;
5046 debug_prod = chain_prod;
5049 DBPRINT(sc, BCE_INFO_SEND,
5050 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
5051 "prod_bseq = 0x%08X\n",
5052 __func__, prod, chain_prod, prod_bseq);
5055 * Cycle through each mbuf segment that makes up
5056 * the outgoing frame, gathering the mapping info
5057 * for that segment and creating a tx_bd to for
5060 for (i = 0; i < nsegs; i++) {
5061 chain_prod = TX_CHAIN_IDX(sc, prod);
5062 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
5064 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
5065 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
5066 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
5067 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
5068 txbd->tx_bd_flags = htole16(flags);
5069 prod_bseq += segs[i].ds_len;
5071 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
5072 prod = NEXT_TX_BD(prod);
5075 /* Set the END flag on the last TX buffer descriptor. */
5076 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
5078 DBRUN(BCE_EXCESSIVE_SEND,
5079 bce_dump_tx_chain(sc, debug_prod, nsegs));
5081 DBPRINT(sc, BCE_INFO_SEND,
5082 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
5083 "prod_bseq = 0x%08X\n",
5084 __func__, prod, chain_prod, prod_bseq);
5087 * Ensure that the mbuf pointer for this transmission
5088 * is placed at the array index of the last
5089 * descriptor in this chain. This is done
5090 * because a single map is used for all
5091 * segments of the mbuf and we don't want to
5092 * unload the map before all of the segments
5095 sc->tx_mbuf_ptr[chain_prod] = m0;
5097 tmp_map = sc->tx_mbuf_map[chain_prod];
5098 sc->tx_mbuf_map[chain_prod] = map;
5099 sc->tx_mbuf_map[chain_prod_start] = tmp_map;
5101 sc->used_tx_bd += nsegs;
5103 /* Update some debug statistic counters */
5104 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5105 sc->tx_hi_watermark = sc->used_tx_bd);
5106 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5107 DBRUNIF(1, sc->tx_mbuf_alloc++);
5109 DBRUN(BCE_VERBOSE_SEND,
5110 bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5112 /* prod points to the next free tx_bd at this point. */
5114 sc->tx_prod_bseq = prod_bseq;
5124 /****************************************************************************/
5125 /* Main transmit routine when called from another routine with a lock. */
5129 /****************************************************************************/
5131 bce_start(struct ifnet *ifp)
5133 struct bce_softc *sc = ifp->if_softc;
5136 ASSERT_SERIALIZED(ifp->if_serializer);
5138 /* If there's no link or the transmit queue is empty then just exit. */
5139 if (!sc->bce_link) {
5140 ifq_purge(&ifp->if_snd);
5144 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5147 DBPRINT(sc, BCE_INFO_SEND,
5148 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5149 "tx_prod_bseq = 0x%08X\n",
5151 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5154 struct mbuf *m_head;
5157 * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5160 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5161 ifp->if_flags |= IFF_OACTIVE;
5165 /* Check for any frames to send. */
5166 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5171 * Pack the data into the transmit ring. If we
5172 * don't have room, place the mbuf back at the
5173 * head of the queue and set the OACTIVE flag
5174 * to wait for the NIC to drain the chain.
5176 if (bce_encap(sc, &m_head)) {
5178 if (sc->used_tx_bd == 0) {
5181 ifp->if_flags |= IFF_OACTIVE;
5188 /* Send a copy of the frame to any BPF listeners. */
5189 ETHER_BPF_MTAP(ifp, m_head);
5193 /* no packets were dequeued */
5194 DBPRINT(sc, BCE_VERBOSE_SEND,
5195 "%s(): No packets were dequeued\n", __func__);
5199 DBPRINT(sc, BCE_INFO_SEND,
5200 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5201 "tx_prod_bseq = 0x%08X\n",
5203 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5205 REG_WR(sc, BCE_MQ_COMMAND,
5206 REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5208 /* Start the transmit. */
5209 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5210 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5212 /* Set the tx timeout. */
5213 ifp->if_timer = BCE_TX_TIMEOUT;
5217 /****************************************************************************/
5218 /* Handles any IOCTL calls from the operating system. */
5221 /* 0 for success, positive value for failure. */
5222 /****************************************************************************/
5224 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5226 struct bce_softc *sc = ifp->if_softc;
5227 struct ifreq *ifr = (struct ifreq *)data;
5228 struct mii_data *mii;
5229 int mask, error = 0;
5231 ASSERT_SERIALIZED(ifp->if_serializer);
5235 /* Check that the MTU setting is supported. */
5236 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5238 ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5240 ifr->ifr_mtu > ETHERMTU
5247 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5249 ifp->if_mtu = ifr->ifr_mtu;
5250 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5255 if (ifp->if_flags & IFF_UP) {
5256 if (ifp->if_flags & IFF_RUNNING) {
5257 mask = ifp->if_flags ^ sc->bce_if_flags;
5259 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5260 bce_set_rx_mode(sc);
5264 } else if (ifp->if_flags & IFF_RUNNING) {
5267 /* If MFW is running, restart the controller a bit. */
5268 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5269 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5274 sc->bce_if_flags = ifp->if_flags;
5279 if (ifp->if_flags & IFF_RUNNING)
5280 bce_set_rx_mode(sc);
5285 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5287 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5289 mii = device_get_softc(sc->bce_miibus);
5290 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5294 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5295 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5298 if (mask & IFCAP_HWCSUM) {
5299 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5300 if (IFCAP_HWCSUM & ifp->if_capenable)
5301 ifp->if_hwassist = BCE_IF_HWASSIST;
5303 ifp->if_hwassist = 0;
5308 error = ether_ioctl(ifp, command, data);
5315 /****************************************************************************/
5316 /* Transmit timeout handler. */
5320 /****************************************************************************/
5322 bce_watchdog(struct ifnet *ifp)
5324 struct bce_softc *sc = ifp->if_softc;
5326 ASSERT_SERIALIZED(ifp->if_serializer);
5328 DBRUN(BCE_VERBOSE_SEND,
5329 bce_dump_driver_state(sc);
5330 bce_dump_status_block(sc));
5333 * If we are in this routine because of pause frames, then
5334 * don't reset the hardware.
5336 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5339 if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5341 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5343 ifp->if_flags &= ~IFF_RUNNING; /* Force reinitialize */
5348 if (!ifq_is_empty(&ifp->if_snd))
5353 #ifdef DEVICE_POLLING
5356 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5358 struct bce_softc *sc = ifp->if_softc;
5359 struct status_block *sblk = sc->status_block;
5360 uint16_t hw_tx_cons, hw_rx_cons;
5362 ASSERT_SERIALIZED(ifp->if_serializer);
5366 bce_disable_intr(sc);
5368 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5369 (1 << 16) | sc->bce_rx_quick_cons_trip);
5370 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5371 (1 << 16) | sc->bce_tx_quick_cons_trip);
5373 case POLL_DEREGISTER:
5374 bce_enable_intr(sc, 1);
5376 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5377 (sc->bce_tx_quick_cons_trip_int << 16) |
5378 sc->bce_tx_quick_cons_trip);
5379 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5380 (sc->bce_rx_quick_cons_trip_int << 16) |
5381 sc->bce_rx_quick_cons_trip);
5387 if (cmd == POLL_AND_CHECK_STATUS) {
5388 uint32_t status_attn_bits;
5390 status_attn_bits = sblk->status_attn_bits;
5392 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5394 "Simulating unexpected status attention bit set.");
5395 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5397 /* Was it a link change interrupt? */
5398 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5399 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5402 /* Clear any transient status updates during link state change. */
5403 REG_WR(sc, BCE_HC_COMMAND,
5404 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5405 REG_RD(sc, BCE_HC_COMMAND);
5408 * If any other attention is asserted then
5409 * the chip is toast.
5411 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5412 (sblk->status_attn_bits_ack &
5413 ~STATUS_ATTN_BITS_LINK_STATE)) {
5414 DBRUN(1, sc->unexpected_attentions++);
5416 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5417 sblk->status_attn_bits);
5420 if (bce_debug_unexpected_attention == 0)
5421 bce_breakpoint(sc));
5428 hw_rx_cons = bce_get_hw_rx_cons(sc);
5429 hw_tx_cons = bce_get_hw_tx_cons(sc);
5431 /* Check for any completed RX frames. */
5432 if (hw_rx_cons != sc->hw_rx_cons)
5433 bce_rx_intr(sc, count);
5435 /* Check for any completed TX frames. */
5436 if (hw_tx_cons != sc->hw_tx_cons)
5439 /* Check for new frames to transmit. */
5440 if (!ifq_is_empty(&ifp->if_snd))
5444 #endif /* DEVICE_POLLING */
5448 * Interrupt handler.
5450 /****************************************************************************/
5451 /* Main interrupt entry point. Verifies that the controller generated the */
5452 /* interrupt and then calls a separate routine for handle the various */
5453 /* interrupt causes (PHY, TX, RX). */
5456 /* 0 for success, positive value for failure. */
5457 /****************************************************************************/
5459 bce_intr(struct bce_softc *sc)
5461 struct ifnet *ifp = &sc->arpcom.ac_if;
5462 struct status_block *sblk;
5463 uint16_t hw_rx_cons, hw_tx_cons;
5465 ASSERT_SERIALIZED(ifp->if_serializer);
5467 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5468 DBRUNIF(1, sc->interrupts_generated++);
5470 sblk = sc->status_block;
5472 /* Check if the hardware has finished any work. */
5473 hw_rx_cons = bce_get_hw_rx_cons(sc);
5474 hw_tx_cons = bce_get_hw_tx_cons(sc);
5476 /* Keep processing data as long as there is work to do. */
5478 uint32_t status_attn_bits;
5480 status_attn_bits = sblk->status_attn_bits;
5482 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5484 "Simulating unexpected status attention bit set.");
5485 status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5487 /* Was it a link change interrupt? */
5488 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5489 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5493 * Clear any transient status updates during link state
5496 REG_WR(sc, BCE_HC_COMMAND,
5497 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5498 REG_RD(sc, BCE_HC_COMMAND);
5502 * If any other attention is asserted then
5503 * the chip is toast.
5505 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5506 (sblk->status_attn_bits_ack &
5507 ~STATUS_ATTN_BITS_LINK_STATE)) {
5508 DBRUN(1, sc->unexpected_attentions++);
5510 if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5511 sblk->status_attn_bits);
5514 if (bce_debug_unexpected_attention == 0)
5515 bce_breakpoint(sc));
5521 /* Check for any completed RX frames. */
5522 if (hw_rx_cons != sc->hw_rx_cons)
5523 bce_rx_intr(sc, -1);
5525 /* Check for any completed TX frames. */
5526 if (hw_tx_cons != sc->hw_tx_cons)
5530 * Save the status block index value
5531 * for use during the next interrupt.
5533 sc->last_status_idx = sblk->status_idx;
5536 * Prevent speculative reads from getting
5537 * ahead of the status block.
5539 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5540 BUS_SPACE_BARRIER_READ);
5543 * If there's no work left then exit the
5544 * interrupt service routine.
5546 hw_rx_cons = bce_get_hw_rx_cons(sc);
5547 hw_tx_cons = bce_get_hw_tx_cons(sc);
5548 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5552 /* Re-enable interrupts. */
5553 bce_enable_intr(sc, 0);
5555 if (sc->bce_coalchg_mask)
5556 bce_coal_change(sc);
5558 /* Handle any frames that arrived while handling the interrupt. */
5559 if (!ifq_is_empty(&ifp->if_snd))
5564 bce_intr_legacy(void *xsc)
5566 struct bce_softc *sc = xsc;
5567 struct status_block *sblk;
5569 sblk = sc->status_block;
5572 * If the hardware status block index matches the last value
5573 * read by the driver and we haven't asserted our interrupt
5574 * then there's nothing to do.
5576 if (sblk->status_idx == sc->last_status_idx &&
5577 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5578 BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5581 /* Ack the interrupt and stop others from occuring. */
5582 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5583 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5584 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5587 * Read back to deassert IRQ immediately to avoid too
5588 * many spurious interrupts.
5590 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5596 bce_intr_msi(void *xsc)
5598 struct bce_softc *sc = xsc;
5600 /* Ack the interrupt and stop others from occuring. */
5601 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5602 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5603 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5609 bce_intr_msi_oneshot(void *xsc)
5615 /****************************************************************************/
5616 /* Programs the various packet receive modes (broadcast and multicast). */
5620 /****************************************************************************/
5622 bce_set_rx_mode(struct bce_softc *sc)
5624 struct ifnet *ifp = &sc->arpcom.ac_if;
5625 struct ifmultiaddr *ifma;
5626 uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5627 uint32_t rx_mode, sort_mode;
5630 ASSERT_SERIALIZED(ifp->if_serializer);
5632 /* Initialize receive mode default settings. */
5633 rx_mode = sc->rx_mode &
5634 ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5635 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5636 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5639 * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5642 if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5643 !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5644 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5647 * Check for promiscuous, all multicast, or selected
5648 * multicast address filtering.
5650 if (ifp->if_flags & IFF_PROMISC) {
5651 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5653 /* Enable promiscuous mode. */
5654 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5655 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5656 } else if (ifp->if_flags & IFF_ALLMULTI) {
5657 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5659 /* Enable all multicast addresses. */
5660 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5661 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5664 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5666 /* Accept one or more multicast(s). */
5667 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5669 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5670 if (ifma->ifma_addr->sa_family != AF_LINK)
5673 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5674 ETHER_ADDR_LEN) & 0xFF;
5675 hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5678 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5679 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5682 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5685 /* Only make changes if the recive mode has actually changed. */
5686 if (rx_mode != sc->rx_mode) {
5687 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5690 sc->rx_mode = rx_mode;
5691 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5694 /* Disable and clear the exisitng sort before enabling a new sort. */
5695 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5696 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5697 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5701 /****************************************************************************/
5702 /* Called periodically to updates statistics from the controllers */
5703 /* statistics block. */
5707 /****************************************************************************/
5709 bce_stats_update(struct bce_softc *sc)
5711 struct ifnet *ifp = &sc->arpcom.ac_if;
5712 struct statistics_block *stats = sc->stats_block;
5714 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5716 ASSERT_SERIALIZED(ifp->if_serializer);
5719 * Certain controllers don't report carrier sense errors correctly.
5720 * See errata E11_5708CA0_1165.
5722 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5723 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5725 (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5729 * Update the sysctl statistics from the hardware statistics.
5731 sc->stat_IfHCInOctets =
5732 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5733 (uint64_t)stats->stat_IfHCInOctets_lo;
5735 sc->stat_IfHCInBadOctets =
5736 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5737 (uint64_t)stats->stat_IfHCInBadOctets_lo;
5739 sc->stat_IfHCOutOctets =
5740 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5741 (uint64_t)stats->stat_IfHCOutOctets_lo;
5743 sc->stat_IfHCOutBadOctets =
5744 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5745 (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5747 sc->stat_IfHCInUcastPkts =
5748 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5749 (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5751 sc->stat_IfHCInMulticastPkts =
5752 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5753 (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5755 sc->stat_IfHCInBroadcastPkts =
5756 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5757 (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5759 sc->stat_IfHCOutUcastPkts =
5760 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5761 (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5763 sc->stat_IfHCOutMulticastPkts =
5764 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5765 (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5767 sc->stat_IfHCOutBroadcastPkts =
5768 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5769 (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5771 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5772 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5774 sc->stat_Dot3StatsCarrierSenseErrors =
5775 stats->stat_Dot3StatsCarrierSenseErrors;
5777 sc->stat_Dot3StatsFCSErrors =
5778 stats->stat_Dot3StatsFCSErrors;
5780 sc->stat_Dot3StatsAlignmentErrors =
5781 stats->stat_Dot3StatsAlignmentErrors;
5783 sc->stat_Dot3StatsSingleCollisionFrames =
5784 stats->stat_Dot3StatsSingleCollisionFrames;
5786 sc->stat_Dot3StatsMultipleCollisionFrames =
5787 stats->stat_Dot3StatsMultipleCollisionFrames;
5789 sc->stat_Dot3StatsDeferredTransmissions =
5790 stats->stat_Dot3StatsDeferredTransmissions;
5792 sc->stat_Dot3StatsExcessiveCollisions =
5793 stats->stat_Dot3StatsExcessiveCollisions;
5795 sc->stat_Dot3StatsLateCollisions =
5796 stats->stat_Dot3StatsLateCollisions;
5798 sc->stat_EtherStatsCollisions =
5799 stats->stat_EtherStatsCollisions;
5801 sc->stat_EtherStatsFragments =
5802 stats->stat_EtherStatsFragments;
5804 sc->stat_EtherStatsJabbers =
5805 stats->stat_EtherStatsJabbers;
5807 sc->stat_EtherStatsUndersizePkts =
5808 stats->stat_EtherStatsUndersizePkts;
5810 sc->stat_EtherStatsOverrsizePkts =
5811 stats->stat_EtherStatsOverrsizePkts;
5813 sc->stat_EtherStatsPktsRx64Octets =
5814 stats->stat_EtherStatsPktsRx64Octets;
5816 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5817 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5819 sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5820 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5822 sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5823 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5825 sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5826 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5828 sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5829 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5831 sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5832 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5834 sc->stat_EtherStatsPktsTx64Octets =
5835 stats->stat_EtherStatsPktsTx64Octets;
5837 sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5838 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5840 sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5841 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5843 sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5844 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5846 sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5847 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5849 sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5850 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5852 sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5853 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5855 sc->stat_XonPauseFramesReceived =
5856 stats->stat_XonPauseFramesReceived;
5858 sc->stat_XoffPauseFramesReceived =
5859 stats->stat_XoffPauseFramesReceived;
5861 sc->stat_OutXonSent =
5862 stats->stat_OutXonSent;
5864 sc->stat_OutXoffSent =
5865 stats->stat_OutXoffSent;
5867 sc->stat_FlowControlDone =
5868 stats->stat_FlowControlDone;
5870 sc->stat_MacControlFramesReceived =
5871 stats->stat_MacControlFramesReceived;
5873 sc->stat_XoffStateEntered =
5874 stats->stat_XoffStateEntered;
5876 sc->stat_IfInFramesL2FilterDiscards =
5877 stats->stat_IfInFramesL2FilterDiscards;
5879 sc->stat_IfInRuleCheckerDiscards =
5880 stats->stat_IfInRuleCheckerDiscards;
5882 sc->stat_IfInFTQDiscards =
5883 stats->stat_IfInFTQDiscards;
5885 sc->stat_IfInMBUFDiscards =
5886 stats->stat_IfInMBUFDiscards;
5888 sc->stat_IfInRuleCheckerP4Hit =
5889 stats->stat_IfInRuleCheckerP4Hit;
5891 sc->stat_CatchupInRuleCheckerDiscards =
5892 stats->stat_CatchupInRuleCheckerDiscards;
5894 sc->stat_CatchupInFTQDiscards =
5895 stats->stat_CatchupInFTQDiscards;
5897 sc->stat_CatchupInMBUFDiscards =
5898 stats->stat_CatchupInMBUFDiscards;
5900 sc->stat_CatchupInRuleCheckerP4Hit =
5901 stats->stat_CatchupInRuleCheckerP4Hit;
5903 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5906 * Update the interface statistics from the
5907 * hardware statistics.
5909 ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5911 ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5912 (u_long)sc->stat_EtherStatsOverrsizePkts +
5913 (u_long)sc->stat_IfInMBUFDiscards +
5914 (u_long)sc->stat_Dot3StatsAlignmentErrors +
5915 (u_long)sc->stat_Dot3StatsFCSErrors +
5916 (u_long)sc->stat_IfInRuleCheckerDiscards +
5917 (u_long)sc->stat_IfInFTQDiscards +
5918 (u_long)sc->com_no_buffers;
5921 (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5922 (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5923 (u_long)sc->stat_Dot3StatsLateCollisions;
5925 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5929 /****************************************************************************/
5930 /* Periodic function to notify the bootcode that the driver is still */
5935 /****************************************************************************/
5937 bce_pulse(void *xsc)
5939 struct bce_softc *sc = xsc;
5940 struct ifnet *ifp = &sc->arpcom.ac_if;
5943 lwkt_serialize_enter(ifp->if_serializer);
5945 if (ifp->if_flags & IFF_RUNNING) {
5946 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI &&
5947 (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) == 0)
5948 bce_pulse_check_msi(sc);
5951 /* Tell the firmware that the driver is still running. */
5952 msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5953 bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5955 /* Update the bootcode condition. */
5956 sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5958 /* Report whether the bootcode still knows the driver is running. */
5959 if (!sc->bce_drv_cardiac_arrest) {
5960 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5961 sc->bce_drv_cardiac_arrest = 1;
5962 if_printf(ifp, "Bootcode lost the driver pulse! "
5963 "(bc_state = 0x%08X)\n", sc->bc_state);
5967 * Not supported by all bootcode versions.
5968 * (v5.0.11+ and v5.2.1+) Older bootcode
5969 * will require the driver to reset the
5970 * controller to clear this condition.
5972 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5973 sc->bce_drv_cardiac_arrest = 0;
5974 if_printf(ifp, "Bootcode found the driver pulse! "
5975 "(bc_state = 0x%08X)\n", sc->bc_state);
5979 /* Schedule the next pulse. */
5980 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5982 lwkt_serialize_exit(ifp->if_serializer);
5986 bce_pulse_check_msi(struct bce_softc *sc)
5990 if (bce_get_hw_rx_cons(sc) != sc->hw_rx_cons) {
5992 } else if (bce_get_hw_tx_cons(sc) != sc->hw_tx_cons) {
5995 struct status_block *sblk = sc->status_block;
5997 if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5998 (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
6005 msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
6006 if ((msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) == 0)
6009 if (sc->pulse_check_status_idx == sc->last_status_idx) {
6010 if_printf(&sc->arpcom.ac_if, "missing MSI\n");
6012 REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
6013 msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
6014 REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
6019 sc->pulse_check_status_idx = sc->last_status_idx;
6022 /****************************************************************************/
6023 /* Periodic function to perform maintenance tasks. */
6027 /****************************************************************************/
6029 bce_tick_serialized(struct bce_softc *sc)
6031 struct ifnet *ifp = &sc->arpcom.ac_if;
6032 struct mii_data *mii;
6034 ASSERT_SERIALIZED(ifp->if_serializer);
6036 /* Update the statistics from the hardware statistics block. */
6037 bce_stats_update(sc);
6039 /* Schedule the next tick. */
6040 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6042 /* If link is up already up then we're done. */
6046 mii = device_get_softc(sc->bce_miibus);
6049 /* Check if the link has come up. */
6050 if ((mii->mii_media_status & IFM_ACTIVE) &&
6051 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6053 /* Now that link is up, handle any outstanding TX traffic. */
6054 if (!ifq_is_empty(&ifp->if_snd))
6063 struct bce_softc *sc = xsc;
6064 struct ifnet *ifp = &sc->arpcom.ac_if;
6066 lwkt_serialize_enter(ifp->if_serializer);
6067 bce_tick_serialized(sc);
6068 lwkt_serialize_exit(ifp->if_serializer);
6073 /****************************************************************************/
6074 /* Allows the driver state to be dumped through the sysctl interface. */
6077 /* 0 for success, positive value for failure. */
6078 /****************************************************************************/
6080 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
6084 struct bce_softc *sc;
6087 error = sysctl_handle_int(oidp, &result, 0, req);
6089 if (error || !req->newptr)
6093 sc = (struct bce_softc *)arg1;
6094 bce_dump_driver_state(sc);
6101 /****************************************************************************/
6102 /* Allows the hardware state to be dumped through the sysctl interface. */
6105 /* 0 for success, positive value for failure. */
6106 /****************************************************************************/
6108 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
6112 struct bce_softc *sc;
6115 error = sysctl_handle_int(oidp, &result, 0, req);
6117 if (error || !req->newptr)
6121 sc = (struct bce_softc *)arg1;
6122 bce_dump_hw_state(sc);
6129 /****************************************************************************/
6130 /* Provides a sysctl interface to allows dumping the RX chain. */
6133 /* 0 for success, positive value for failure. */
6134 /****************************************************************************/
6136 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
6140 struct bce_softc *sc;
6143 error = sysctl_handle_int(oidp, &result, 0, req);
6145 if (error || !req->newptr)
6149 sc = (struct bce_softc *)arg1;
6150 bce_dump_rx_chain(sc, 0, USABLE_RX_BD(sc));
6157 /****************************************************************************/
6158 /* Provides a sysctl interface to allows dumping the TX chain. */
6161 /* 0 for success, positive value for failure. */
6162 /****************************************************************************/
6164 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
6168 struct bce_softc *sc;
6171 error = sysctl_handle_int(oidp, &result, 0, req);
6173 if (error || !req->newptr)
6177 sc = (struct bce_softc *)arg1;
6178 bce_dump_tx_chain(sc, 0, USABLE_TX_BD(sc));
6185 /****************************************************************************/
6186 /* Provides a sysctl interface to allow reading arbitrary registers in the */
6187 /* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6190 /* 0 for success, positive value for failure. */
6191 /****************************************************************************/
6193 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6195 struct bce_softc *sc;
6197 uint32_t val, result;
6200 error = sysctl_handle_int(oidp, &result, 0, req);
6201 if (error || (req->newptr == NULL))
6204 /* Make sure the register is accessible. */
6205 if (result < 0x8000) {
6206 sc = (struct bce_softc *)arg1;
6207 val = REG_RD(sc, result);
6208 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6210 } else if (result < 0x0280000) {
6211 sc = (struct bce_softc *)arg1;
6212 val = REG_RD_IND(sc, result);
6213 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6220 /****************************************************************************/
6221 /* Provides a sysctl interface to allow reading arbitrary PHY registers in */
6222 /* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6225 /* 0 for success, positive value for failure. */
6226 /****************************************************************************/
6228 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6230 struct bce_softc *sc;
6236 error = sysctl_handle_int(oidp, &result, 0, req);
6237 if (error || (req->newptr == NULL))
6240 /* Make sure the register is accessible. */
6241 if (result < 0x20) {
6242 sc = (struct bce_softc *)arg1;
6244 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6245 if_printf(&sc->arpcom.ac_if,
6246 "phy 0x%02X = 0x%04X\n", result, val);
6252 /****************************************************************************/
6253 /* Provides a sysctl interface to forcing the driver to dump state and */
6254 /* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6257 /* 0 for success, positive value for failure. */
6258 /****************************************************************************/
6260 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6264 struct bce_softc *sc;
6267 error = sysctl_handle_int(oidp, &result, 0, req);
6269 if (error || !req->newptr)
6273 sc = (struct bce_softc *)arg1;
6282 /****************************************************************************/
6283 /* Adds any sysctl parameters for tuning or debugging purposes. */
6286 /* 0 for success, positive value for failure. */
6287 /****************************************************************************/
6289 bce_add_sysctls(struct bce_softc *sc)
6291 struct sysctl_ctx_list *ctx;
6292 struct sysctl_oid_list *children;
6294 sysctl_ctx_init(&sc->bce_sysctl_ctx);
6295 sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6296 SYSCTL_STATIC_CHILDREN(_hw),
6298 device_get_nameunit(sc->bce_dev),
6300 if (sc->bce_sysctl_tree == NULL) {
6301 device_printf(sc->bce_dev, "can't add sysctl node\n");
6305 ctx = &sc->bce_sysctl_ctx;
6306 children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6308 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6309 CTLTYPE_INT | CTLFLAG_RW,
6310 sc, 0, bce_sysctl_tx_bds_int, "I",
6311 "Send max coalesced BD count during interrupt");
6312 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6313 CTLTYPE_INT | CTLFLAG_RW,
6314 sc, 0, bce_sysctl_tx_bds, "I",
6315 "Send max coalesced BD count");
6316 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6317 CTLTYPE_INT | CTLFLAG_RW,
6318 sc, 0, bce_sysctl_tx_ticks_int, "I",
6319 "Send coalescing ticks during interrupt");
6320 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6321 CTLTYPE_INT | CTLFLAG_RW,
6322 sc, 0, bce_sysctl_tx_ticks, "I",
6323 "Send coalescing ticks");
6325 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6326 CTLTYPE_INT | CTLFLAG_RW,
6327 sc, 0, bce_sysctl_rx_bds_int, "I",
6328 "Receive max coalesced BD count during interrupt");
6329 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6330 CTLTYPE_INT | CTLFLAG_RW,
6331 sc, 0, bce_sysctl_rx_bds, "I",
6332 "Receive max coalesced BD count");
6333 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6334 CTLTYPE_INT | CTLFLAG_RW,
6335 sc, 0, bce_sysctl_rx_ticks_int, "I",
6336 "Receive coalescing ticks during interrupt");
6337 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6338 CTLTYPE_INT | CTLFLAG_RW,
6339 sc, 0, bce_sysctl_rx_ticks, "I",
6340 "Receive coalescing ticks");
6342 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
6343 CTLFLAG_RD, &sc->rx_pages, 0, "# of RX pages");
6344 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
6345 CTLFLAG_RD, &sc->tx_pages, 0, "# of TX pages");
6348 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6350 CTLFLAG_RD, &sc->rx_low_watermark,
6351 0, "Lowest level of free rx_bd's");
6353 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6355 CTLFLAG_RD, &sc->rx_empty_count,
6356 0, "Number of times the RX chain was empty");
6358 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6360 CTLFLAG_RD, &sc->tx_hi_watermark,
6361 0, "Highest level of used tx_bd's");
6363 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6365 CTLFLAG_RD, &sc->tx_full_count,
6366 0, "Number of times the TX chain was full");
6368 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6369 "l2fhdr_status_errors",
6370 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6371 0, "l2_fhdr status errors");
6373 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6374 "unexpected_attentions",
6375 CTLFLAG_RD, &sc->unexpected_attentions,
6376 0, "unexpected attentions");
6378 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6379 "lost_status_block_updates",
6380 CTLFLAG_RD, &sc->lost_status_block_updates,
6381 0, "lost status block updates");
6383 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6384 "mbuf_alloc_failed",
6385 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6386 0, "mbuf cluster allocation failures");
6389 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6390 "stat_IfHCInOctets",
6391 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6394 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6395 "stat_IfHCInBadOctets",
6396 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6397 "Bad bytes received");
6399 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6400 "stat_IfHCOutOctets",
6401 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6404 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6405 "stat_IfHCOutBadOctets",
6406 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6409 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6410 "stat_IfHCInUcastPkts",
6411 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6412 "Unicast packets received");
6414 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6415 "stat_IfHCInMulticastPkts",
6416 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6417 "Multicast packets received");
6419 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6420 "stat_IfHCInBroadcastPkts",
6421 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6422 "Broadcast packets received");
6424 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6425 "stat_IfHCOutUcastPkts",
6426 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6427 "Unicast packets sent");
6429 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6430 "stat_IfHCOutMulticastPkts",
6431 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6432 "Multicast packets sent");
6434 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6435 "stat_IfHCOutBroadcastPkts",
6436 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6437 "Broadcast packets sent");
6439 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6440 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6441 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6442 0, "Internal MAC transmit errors");
6444 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6445 "stat_Dot3StatsCarrierSenseErrors",
6446 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6447 0, "Carrier sense errors");
6449 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6450 "stat_Dot3StatsFCSErrors",
6451 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6452 0, "Frame check sequence errors");
6454 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6455 "stat_Dot3StatsAlignmentErrors",
6456 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6457 0, "Alignment errors");
6459 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6460 "stat_Dot3StatsSingleCollisionFrames",
6461 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6462 0, "Single Collision Frames");
6464 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6465 "stat_Dot3StatsMultipleCollisionFrames",
6466 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6467 0, "Multiple Collision Frames");
6469 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6470 "stat_Dot3StatsDeferredTransmissions",
6471 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6472 0, "Deferred Transmissions");
6474 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6475 "stat_Dot3StatsExcessiveCollisions",
6476 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6477 0, "Excessive Collisions");
6479 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6480 "stat_Dot3StatsLateCollisions",
6481 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6482 0, "Late Collisions");
6484 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6485 "stat_EtherStatsCollisions",
6486 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6489 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6490 "stat_EtherStatsFragments",
6491 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6494 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6495 "stat_EtherStatsJabbers",
6496 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6499 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6500 "stat_EtherStatsUndersizePkts",
6501 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6502 0, "Undersize packets");
6504 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6505 "stat_EtherStatsOverrsizePkts",
6506 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6507 0, "stat_EtherStatsOverrsizePkts");
6509 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6510 "stat_EtherStatsPktsRx64Octets",
6511 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6512 0, "Bytes received in 64 byte packets");
6514 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6515 "stat_EtherStatsPktsRx65Octetsto127Octets",
6516 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6517 0, "Bytes received in 65 to 127 byte packets");
6519 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6520 "stat_EtherStatsPktsRx128Octetsto255Octets",
6521 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6522 0, "Bytes received in 128 to 255 byte packets");
6524 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6525 "stat_EtherStatsPktsRx256Octetsto511Octets",
6526 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6527 0, "Bytes received in 256 to 511 byte packets");
6529 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6530 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6531 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6532 0, "Bytes received in 512 to 1023 byte packets");
6534 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6535 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6536 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6537 0, "Bytes received in 1024 t0 1522 byte packets");
6539 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6540 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6541 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6542 0, "Bytes received in 1523 to 9022 byte packets");
6544 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6545 "stat_EtherStatsPktsTx64Octets",
6546 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6547 0, "Bytes sent in 64 byte packets");
6549 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6550 "stat_EtherStatsPktsTx65Octetsto127Octets",
6551 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6552 0, "Bytes sent in 65 to 127 byte packets");
6554 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6555 "stat_EtherStatsPktsTx128Octetsto255Octets",
6556 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6557 0, "Bytes sent in 128 to 255 byte packets");
6559 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6560 "stat_EtherStatsPktsTx256Octetsto511Octets",
6561 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6562 0, "Bytes sent in 256 to 511 byte packets");
6564 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6565 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6566 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6567 0, "Bytes sent in 512 to 1023 byte packets");
6569 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6570 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6571 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6572 0, "Bytes sent in 1024 to 1522 byte packets");
6574 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6575 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6576 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6577 0, "Bytes sent in 1523 to 9022 byte packets");
6579 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6580 "stat_XonPauseFramesReceived",
6581 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6582 0, "XON pause frames receved");
6584 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6585 "stat_XoffPauseFramesReceived",
6586 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6587 0, "XOFF pause frames received");
6589 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6591 CTLFLAG_RD, &sc->stat_OutXonSent,
6592 0, "XON pause frames sent");
6594 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6596 CTLFLAG_RD, &sc->stat_OutXoffSent,
6597 0, "XOFF pause frames sent");
6599 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6600 "stat_FlowControlDone",
6601 CTLFLAG_RD, &sc->stat_FlowControlDone,
6602 0, "Flow control done");
6604 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6605 "stat_MacControlFramesReceived",
6606 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6607 0, "MAC control frames received");
6609 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6610 "stat_XoffStateEntered",
6611 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6612 0, "XOFF state entered");
6614 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6615 "stat_IfInFramesL2FilterDiscards",
6616 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6617 0, "Received L2 packets discarded");
6619 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6620 "stat_IfInRuleCheckerDiscards",
6621 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6622 0, "Received packets discarded by rule");
6624 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6625 "stat_IfInFTQDiscards",
6626 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6627 0, "Received packet FTQ discards");
6629 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6630 "stat_IfInMBUFDiscards",
6631 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6632 0, "Received packets discarded due to lack of controller buffer memory");
6634 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6635 "stat_IfInRuleCheckerP4Hit",
6636 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6637 0, "Received packets rule checker hits");
6639 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6640 "stat_CatchupInRuleCheckerDiscards",
6641 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6642 0, "Received packets discarded in Catchup path");
6644 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6645 "stat_CatchupInFTQDiscards",
6646 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6647 0, "Received packets discarded in FTQ in Catchup path");
6649 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6650 "stat_CatchupInMBUFDiscards",
6651 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6652 0, "Received packets discarded in controller buffer memory in Catchup path");
6654 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6655 "stat_CatchupInRuleCheckerP4Hit",
6656 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6657 0, "Received packets rule checker hits in Catchup path");
6659 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6661 CTLFLAG_RD, &sc->com_no_buffers,
6662 0, "Valid packets received but no RX buffers available");
6665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6666 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6668 bce_sysctl_driver_state, "I", "Drive state information");
6670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6671 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6673 bce_sysctl_hw_state, "I", "Hardware state information");
6675 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6676 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6678 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6680 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6681 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6683 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6686 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6688 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6691 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6693 bce_sysctl_reg_read, "I", "Register read");
6695 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6696 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6698 bce_sysctl_phy_read, "I", "PHY register read");
6705 /****************************************************************************/
6706 /* BCE Debug Routines */
6707 /****************************************************************************/
6710 /****************************************************************************/
6711 /* Freezes the controller to allow for a cohesive state dump. */
6715 /****************************************************************************/
6717 bce_freeze_controller(struct bce_softc *sc)
6721 val = REG_RD(sc, BCE_MISC_COMMAND);
6722 val |= BCE_MISC_COMMAND_DISABLE_ALL;
6723 REG_WR(sc, BCE_MISC_COMMAND, val);
6727 /****************************************************************************/
6728 /* Unfreezes the controller after a freeze operation. This may not always */
6729 /* work and the controller will require a reset! */
6733 /****************************************************************************/
6735 bce_unfreeze_controller(struct bce_softc *sc)
6739 val = REG_RD(sc, BCE_MISC_COMMAND);
6740 val |= BCE_MISC_COMMAND_ENABLE_ALL;
6741 REG_WR(sc, BCE_MISC_COMMAND, val);
6745 /****************************************************************************/
6746 /* Prints out information about an mbuf. */
6750 /****************************************************************************/
6752 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6754 struct ifnet *ifp = &sc->arpcom.ac_if;
6755 uint32_t val_hi, val_lo;
6756 struct mbuf *mp = m;
6759 /* Index out of range. */
6760 if_printf(ifp, "mbuf: null pointer\n");
6765 val_hi = BCE_ADDR_HI(mp);
6766 val_lo = BCE_ADDR_LO(mp);
6767 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6768 "m_flags = ( ", val_hi, val_lo, mp->m_len);
6770 if (mp->m_flags & M_EXT)
6772 if (mp->m_flags & M_PKTHDR)
6773 kprintf("M_PKTHDR ");
6774 if (mp->m_flags & M_EOR)
6777 if (mp->m_flags & M_RDONLY)
6778 kprintf("M_RDONLY ");
6781 val_hi = BCE_ADDR_HI(mp->m_data);
6782 val_lo = BCE_ADDR_LO(mp->m_data);
6783 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6785 if (mp->m_flags & M_PKTHDR) {
6786 if_printf(ifp, "- m_pkthdr: flags = ( ");
6787 if (mp->m_flags & M_BCAST)
6788 kprintf("M_BCAST ");
6789 if (mp->m_flags & M_MCAST)
6790 kprintf("M_MCAST ");
6791 if (mp->m_flags & M_FRAG)
6793 if (mp->m_flags & M_FIRSTFRAG)
6794 kprintf("M_FIRSTFRAG ");
6795 if (mp->m_flags & M_LASTFRAG)
6796 kprintf("M_LASTFRAG ");
6798 if (mp->m_flags & M_VLANTAG)
6799 kprintf("M_VLANTAG ");
6802 if (mp->m_flags & M_PROMISC)
6803 kprintf("M_PROMISC ");
6805 kprintf(") csum_flags = ( ");
6806 if (mp->m_pkthdr.csum_flags & CSUM_IP)
6807 kprintf("CSUM_IP ");
6808 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6809 kprintf("CSUM_TCP ");
6810 if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6811 kprintf("CSUM_UDP ");
6812 if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6813 kprintf("CSUM_IP_FRAGS ");
6814 if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6815 kprintf("CSUM_FRAGMENT ");
6817 if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6818 kprintf("CSUM_TSO ");
6820 if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6821 kprintf("CSUM_IP_CHECKED ");
6822 if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6823 kprintf("CSUM_IP_VALID ");
6824 if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6825 kprintf("CSUM_DATA_VALID ");
6829 if (mp->m_flags & M_EXT) {
6830 val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6831 val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6832 if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6834 val_hi, val_lo, mp->m_ext.ext_size);
6841 /****************************************************************************/
6842 /* Prints out the mbufs in the TX mbuf chain. */
6846 /****************************************************************************/
6848 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6850 struct ifnet *ifp = &sc->arpcom.ac_if;
6854 "----------------------------"
6856 "----------------------------\n");
6858 for (i = 0; i < count; i++) {
6859 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6860 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6861 chain_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(chain_prod));
6865 "----------------------------"
6867 "----------------------------\n");
6871 /****************************************************************************/
6872 /* Prints out the mbufs in the RX mbuf chain. */
6876 /****************************************************************************/
6878 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6880 struct ifnet *ifp = &sc->arpcom.ac_if;
6884 "----------------------------"
6886 "----------------------------\n");
6888 for (i = 0; i < count; i++) {
6889 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6890 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6891 chain_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(chain_prod));
6895 "----------------------------"
6897 "----------------------------\n");
6901 /****************************************************************************/
6902 /* Prints out a tx_bd structure. */
6906 /****************************************************************************/
6908 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6910 struct ifnet *ifp = &sc->arpcom.ac_if;
6912 if (idx > MAX_TX_BD(sc)) {
6913 /* Index out of range. */
6914 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6915 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6916 /* TX Chain page pointer. */
6917 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6918 "chain page pointer\n",
6919 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6921 /* Normal tx_bd entry. */
6922 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6924 "vlan tag= 0x%04X, flags = 0x%04X (",
6925 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6926 txbd->tx_bd_mss_nbytes,
6927 txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6929 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6930 kprintf(" CONN_FAULT");
6932 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6933 kprintf(" TCP_UDP_CKSUM");
6935 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6936 kprintf(" IP_CKSUM");
6938 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6941 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6942 kprintf(" COAL_NOW");
6944 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6945 kprintf(" DONT_GEN_CRC");
6947 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6950 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6953 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6956 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6957 kprintf(" OPTION_WORD");
6959 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6962 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6970 /****************************************************************************/
6971 /* Prints out a rx_bd structure. */
6975 /****************************************************************************/
6977 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6979 struct ifnet *ifp = &sc->arpcom.ac_if;
6981 if (idx > MAX_RX_BD(sc)) {
6982 /* Index out of range. */
6983 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6984 } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6985 /* TX Chain page pointer. */
6986 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6987 "chain page pointer\n",
6988 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6990 /* Normal tx_bd entry. */
6991 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6992 "nbytes = 0x%08X, flags = 0x%08X\n",
6993 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6994 rxbd->rx_bd_len, rxbd->rx_bd_flags);
6999 /****************************************************************************/
7000 /* Prints out a l2_fhdr structure. */
7004 /****************************************************************************/
7006 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
7008 if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
7009 "pkt_len = 0x%04X, vlan = 0x%04x, "
7010 "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
7011 idx, l2fhdr->l2_fhdr_status,
7012 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
7013 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
7017 /****************************************************************************/
7018 /* Prints out the tx chain. */
7022 /****************************************************************************/
7024 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
7026 struct ifnet *ifp = &sc->arpcom.ac_if;
7029 /* First some info about the tx_bd chain structure. */
7031 "----------------------------"
7033 "----------------------------\n");
7035 if_printf(ifp, "page size = 0x%08X, "
7036 "tx chain pages = 0x%08X\n",
7037 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->tx_pages);
7039 if_printf(ifp, "tx_bd per page = 0x%08X, "
7040 "usable tx_bd per page = 0x%08X\n",
7041 (uint32_t)TOTAL_TX_BD_PER_PAGE,
7042 (uint32_t)USABLE_TX_BD_PER_PAGE);
7044 if_printf(ifp, "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD(sc));
7047 "----------------------------"
7049 "----------------------------\n");
7051 /* Now print out the tx_bd's themselves. */
7052 for (i = 0; i < count; i++) {
7055 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
7056 bce_dump_txbd(sc, tx_prod, txbd);
7057 tx_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(tx_prod));
7061 "----------------------------"
7063 "----------------------------\n");
7067 /****************************************************************************/
7068 /* Prints out the rx chain. */
7072 /****************************************************************************/
7074 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
7076 struct ifnet *ifp = &sc->arpcom.ac_if;
7079 /* First some info about the tx_bd chain structure. */
7081 "----------------------------"
7083 "----------------------------\n");
7085 if_printf(ifp, "page size = 0x%08X, "
7086 "rx chain pages = 0x%08X\n",
7087 (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->rx_pages);
7089 if_printf(ifp, "rx_bd per page = 0x%08X, "
7090 "usable rx_bd per page = 0x%08X\n",
7091 (uint32_t)TOTAL_RX_BD_PER_PAGE,
7092 (uint32_t)USABLE_RX_BD_PER_PAGE);
7094 if_printf(ifp, "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD(sc));
7097 "----------------------------"
7099 "----------------------------\n");
7101 /* Now print out the rx_bd's themselves. */
7102 for (i = 0; i < count; i++) {
7105 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
7106 bce_dump_rxbd(sc, rx_prod, rxbd);
7107 rx_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(rx_prod));
7111 "----------------------------"
7113 "----------------------------\n");
7117 /****************************************************************************/
7118 /* Prints out the status block from host memory. */
7122 /****************************************************************************/
7124 bce_dump_status_block(struct bce_softc *sc)
7126 struct status_block *sblk = sc->status_block;
7127 struct ifnet *ifp = &sc->arpcom.ac_if;
7130 "----------------------------"
7132 "----------------------------\n");
7134 if_printf(ifp, " 0x%08X - attn_bits\n", sblk->status_attn_bits);
7136 if_printf(ifp, " 0x%08X - attn_bits_ack\n",
7137 sblk->status_attn_bits_ack);
7139 if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
7140 sblk->status_rx_quick_consumer_index0,
7141 (uint16_t)RX_CHAIN_IDX(sc, sblk->status_rx_quick_consumer_index0));
7143 if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
7144 sblk->status_tx_quick_consumer_index0,
7145 (uint16_t)TX_CHAIN_IDX(sc, sblk->status_tx_quick_consumer_index0));
7147 if_printf(ifp, " 0x%04X - status_idx\n", sblk->status_idx);
7149 /* Theses indices are not used for normal L2 drivers. */
7150 if (sblk->status_rx_quick_consumer_index1) {
7151 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
7152 sblk->status_rx_quick_consumer_index1,
7153 (uint16_t)RX_CHAIN_IDX(sc,
7154 sblk->status_rx_quick_consumer_index1));
7157 if (sblk->status_tx_quick_consumer_index1) {
7158 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
7159 sblk->status_tx_quick_consumer_index1,
7160 (uint16_t)TX_CHAIN_IDX(sc,
7161 sblk->status_tx_quick_consumer_index1));
7164 if (sblk->status_rx_quick_consumer_index2) {
7165 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
7166 sblk->status_rx_quick_consumer_index2,
7167 (uint16_t)RX_CHAIN_IDX(sc,
7168 sblk->status_rx_quick_consumer_index2));
7171 if (sblk->status_tx_quick_consumer_index2) {
7172 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
7173 sblk->status_tx_quick_consumer_index2,
7174 (uint16_t)TX_CHAIN_IDX(sc,
7175 sblk->status_tx_quick_consumer_index2));
7178 if (sblk->status_rx_quick_consumer_index3) {
7179 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7180 sblk->status_rx_quick_consumer_index3,
7181 (uint16_t)RX_CHAIN_IDX(sc,
7182 sblk->status_rx_quick_consumer_index3));
7185 if (sblk->status_tx_quick_consumer_index3) {
7186 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7187 sblk->status_tx_quick_consumer_index3,
7188 (uint16_t)TX_CHAIN_IDX(sc,
7189 sblk->status_tx_quick_consumer_index3));
7192 if (sblk->status_rx_quick_consumer_index4 ||
7193 sblk->status_rx_quick_consumer_index5) {
7194 if_printf(ifp, "rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
7195 sblk->status_rx_quick_consumer_index4,
7196 sblk->status_rx_quick_consumer_index5);
7199 if (sblk->status_rx_quick_consumer_index6 ||
7200 sblk->status_rx_quick_consumer_index7) {
7201 if_printf(ifp, "rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
7202 sblk->status_rx_quick_consumer_index6,
7203 sblk->status_rx_quick_consumer_index7);
7206 if (sblk->status_rx_quick_consumer_index8 ||
7207 sblk->status_rx_quick_consumer_index9) {
7208 if_printf(ifp, "rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
7209 sblk->status_rx_quick_consumer_index8,
7210 sblk->status_rx_quick_consumer_index9);
7213 if (sblk->status_rx_quick_consumer_index10 ||
7214 sblk->status_rx_quick_consumer_index11) {
7215 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
7216 sblk->status_rx_quick_consumer_index10,
7217 sblk->status_rx_quick_consumer_index11);
7220 if (sblk->status_rx_quick_consumer_index12 ||
7221 sblk->status_rx_quick_consumer_index13) {
7222 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
7223 sblk->status_rx_quick_consumer_index12,
7224 sblk->status_rx_quick_consumer_index13);
7227 if (sblk->status_rx_quick_consumer_index14 ||
7228 sblk->status_rx_quick_consumer_index15) {
7229 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
7230 sblk->status_rx_quick_consumer_index14,
7231 sblk->status_rx_quick_consumer_index15);
7234 if (sblk->status_completion_producer_index ||
7235 sblk->status_cmd_consumer_index) {
7236 if_printf(ifp, "com_prod = 0x%08X, cmd_cons = 0x%08X\n",
7237 sblk->status_completion_producer_index,
7238 sblk->status_cmd_consumer_index);
7242 "----------------------------"
7244 "----------------------------\n");
7248 /****************************************************************************/
7249 /* Prints out the statistics block. */
7253 /****************************************************************************/
7255 bce_dump_stats_block(struct bce_softc *sc)
7257 struct statistics_block *sblk = sc->stats_block;
7258 struct ifnet *ifp = &sc->arpcom.ac_if;
7262 " Stats Block (All Stats Not Shown Are 0) "
7263 "---------------\n");
7265 if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7266 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7267 sblk->stat_IfHCInOctets_hi,
7268 sblk->stat_IfHCInOctets_lo);
7271 if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7272 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7273 sblk->stat_IfHCInBadOctets_hi,
7274 sblk->stat_IfHCInBadOctets_lo);
7277 if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7278 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7279 sblk->stat_IfHCOutOctets_hi,
7280 sblk->stat_IfHCOutOctets_lo);
7283 if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7284 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7285 sblk->stat_IfHCOutBadOctets_hi,
7286 sblk->stat_IfHCOutBadOctets_lo);
7289 if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7290 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7291 sblk->stat_IfHCInUcastPkts_hi,
7292 sblk->stat_IfHCInUcastPkts_lo);
7295 if (sblk->stat_IfHCInBroadcastPkts_hi ||
7296 sblk->stat_IfHCInBroadcastPkts_lo) {
7297 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7298 sblk->stat_IfHCInBroadcastPkts_hi,
7299 sblk->stat_IfHCInBroadcastPkts_lo);
7302 if (sblk->stat_IfHCInMulticastPkts_hi ||
7303 sblk->stat_IfHCInMulticastPkts_lo) {
7304 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7305 sblk->stat_IfHCInMulticastPkts_hi,
7306 sblk->stat_IfHCInMulticastPkts_lo);
7309 if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7310 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7311 sblk->stat_IfHCOutUcastPkts_hi,
7312 sblk->stat_IfHCOutUcastPkts_lo);
7315 if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7316 sblk->stat_IfHCOutBroadcastPkts_lo) {
7317 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7318 sblk->stat_IfHCOutBroadcastPkts_hi,
7319 sblk->stat_IfHCOutBroadcastPkts_lo);
7322 if (sblk->stat_IfHCOutMulticastPkts_hi ||
7323 sblk->stat_IfHCOutMulticastPkts_lo) {
7324 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7325 sblk->stat_IfHCOutMulticastPkts_hi,
7326 sblk->stat_IfHCOutMulticastPkts_lo);
7329 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7330 if_printf(ifp, " 0x%08X : "
7331 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7332 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7335 if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7336 if_printf(ifp, " 0x%08X : "
7337 "Dot3StatsCarrierSenseErrors\n",
7338 sblk->stat_Dot3StatsCarrierSenseErrors);
7341 if (sblk->stat_Dot3StatsFCSErrors) {
7342 if_printf(ifp, " 0x%08X : Dot3StatsFCSErrors\n",
7343 sblk->stat_Dot3StatsFCSErrors);
7346 if (sblk->stat_Dot3StatsAlignmentErrors) {
7347 if_printf(ifp, " 0x%08X : Dot3StatsAlignmentErrors\n",
7348 sblk->stat_Dot3StatsAlignmentErrors);
7351 if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7352 if_printf(ifp, " 0x%08X : "
7353 "Dot3StatsSingleCollisionFrames\n",
7354 sblk->stat_Dot3StatsSingleCollisionFrames);
7357 if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7358 if_printf(ifp, " 0x%08X : "
7359 "Dot3StatsMultipleCollisionFrames\n",
7360 sblk->stat_Dot3StatsMultipleCollisionFrames);
7363 if (sblk->stat_Dot3StatsDeferredTransmissions) {
7364 if_printf(ifp, " 0x%08X : "
7365 "Dot3StatsDeferredTransmissions\n",
7366 sblk->stat_Dot3StatsDeferredTransmissions);
7369 if (sblk->stat_Dot3StatsExcessiveCollisions) {
7370 if_printf(ifp, " 0x%08X : "
7371 "Dot3StatsExcessiveCollisions\n",
7372 sblk->stat_Dot3StatsExcessiveCollisions);
7375 if (sblk->stat_Dot3StatsLateCollisions) {
7376 if_printf(ifp, " 0x%08X : Dot3StatsLateCollisions\n",
7377 sblk->stat_Dot3StatsLateCollisions);
7380 if (sblk->stat_EtherStatsCollisions) {
7381 if_printf(ifp, " 0x%08X : EtherStatsCollisions\n",
7382 sblk->stat_EtherStatsCollisions);
7385 if (sblk->stat_EtherStatsFragments) {
7386 if_printf(ifp, " 0x%08X : EtherStatsFragments\n",
7387 sblk->stat_EtherStatsFragments);
7390 if (sblk->stat_EtherStatsJabbers) {
7391 if_printf(ifp, " 0x%08X : EtherStatsJabbers\n",
7392 sblk->stat_EtherStatsJabbers);
7395 if (sblk->stat_EtherStatsUndersizePkts) {
7396 if_printf(ifp, " 0x%08X : EtherStatsUndersizePkts\n",
7397 sblk->stat_EtherStatsUndersizePkts);
7400 if (sblk->stat_EtherStatsOverrsizePkts) {
7401 if_printf(ifp, " 0x%08X : EtherStatsOverrsizePkts\n",
7402 sblk->stat_EtherStatsOverrsizePkts);
7405 if (sblk->stat_EtherStatsPktsRx64Octets) {
7406 if_printf(ifp, " 0x%08X : EtherStatsPktsRx64Octets\n",
7407 sblk->stat_EtherStatsPktsRx64Octets);
7410 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7411 if_printf(ifp, " 0x%08X : "
7412 "EtherStatsPktsRx65Octetsto127Octets\n",
7413 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7416 if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7417 if_printf(ifp, " 0x%08X : "
7418 "EtherStatsPktsRx128Octetsto255Octets\n",
7419 sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7422 if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7423 if_printf(ifp, " 0x%08X : "
7424 "EtherStatsPktsRx256Octetsto511Octets\n",
7425 sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7428 if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7429 if_printf(ifp, " 0x%08X : "
7430 "EtherStatsPktsRx512Octetsto1023Octets\n",
7431 sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7434 if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7435 if_printf(ifp, " 0x%08X : "
7436 "EtherStatsPktsRx1024Octetsto1522Octets\n",
7437 sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7440 if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7441 if_printf(ifp, " 0x%08X : "
7442 "EtherStatsPktsRx1523Octetsto9022Octets\n",
7443 sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7446 if (sblk->stat_EtherStatsPktsTx64Octets) {
7447 if_printf(ifp, " 0x%08X : EtherStatsPktsTx64Octets\n",
7448 sblk->stat_EtherStatsPktsTx64Octets);
7451 if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7452 if_printf(ifp, " 0x%08X : "
7453 "EtherStatsPktsTx65Octetsto127Octets\n",
7454 sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7457 if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7458 if_printf(ifp, " 0x%08X : "
7459 "EtherStatsPktsTx128Octetsto255Octets\n",
7460 sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7463 if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7464 if_printf(ifp, " 0x%08X : "
7465 "EtherStatsPktsTx256Octetsto511Octets\n",
7466 sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7469 if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7470 if_printf(ifp, " 0x%08X : "
7471 "EtherStatsPktsTx512Octetsto1023Octets\n",
7472 sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7475 if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7476 if_printf(ifp, " 0x%08X : "
7477 "EtherStatsPktsTx1024Octetsto1522Octets\n",
7478 sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7481 if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7482 if_printf(ifp, " 0x%08X : "
7483 "EtherStatsPktsTx1523Octetsto9022Octets\n",
7484 sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7487 if (sblk->stat_XonPauseFramesReceived) {
7488 if_printf(ifp, " 0x%08X : XonPauseFramesReceived\n",
7489 sblk->stat_XonPauseFramesReceived);
7492 if (sblk->stat_XoffPauseFramesReceived) {
7493 if_printf(ifp, " 0x%08X : XoffPauseFramesReceived\n",
7494 sblk->stat_XoffPauseFramesReceived);
7497 if (sblk->stat_OutXonSent) {
7498 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7499 sblk->stat_OutXonSent);
7502 if (sblk->stat_OutXoffSent) {
7503 if_printf(ifp, " 0x%08X : OutXoffSent\n",
7504 sblk->stat_OutXoffSent);
7507 if (sblk->stat_FlowControlDone) {
7508 if_printf(ifp, " 0x%08X : FlowControlDone\n",
7509 sblk->stat_FlowControlDone);
7512 if (sblk->stat_MacControlFramesReceived) {
7513 if_printf(ifp, " 0x%08X : MacControlFramesReceived\n",
7514 sblk->stat_MacControlFramesReceived);
7517 if (sblk->stat_XoffStateEntered) {
7518 if_printf(ifp, " 0x%08X : XoffStateEntered\n",
7519 sblk->stat_XoffStateEntered);
7522 if (sblk->stat_IfInFramesL2FilterDiscards) {
7523 if_printf(ifp, " 0x%08X : IfInFramesL2FilterDiscards\n", sblk->stat_IfInFramesL2FilterDiscards);
7526 if (sblk->stat_IfInRuleCheckerDiscards) {
7527 if_printf(ifp, " 0x%08X : IfInRuleCheckerDiscards\n",
7528 sblk->stat_IfInRuleCheckerDiscards);
7531 if (sblk->stat_IfInFTQDiscards) {
7532 if_printf(ifp, " 0x%08X : IfInFTQDiscards\n",
7533 sblk->stat_IfInFTQDiscards);
7536 if (sblk->stat_IfInMBUFDiscards) {
7537 if_printf(ifp, " 0x%08X : IfInMBUFDiscards\n",
7538 sblk->stat_IfInMBUFDiscards);
7541 if (sblk->stat_IfInRuleCheckerP4Hit) {
7542 if_printf(ifp, " 0x%08X : IfInRuleCheckerP4Hit\n",
7543 sblk->stat_IfInRuleCheckerP4Hit);
7546 if (sblk->stat_CatchupInRuleCheckerDiscards) {
7547 if_printf(ifp, " 0x%08X : "
7548 "CatchupInRuleCheckerDiscards\n",
7549 sblk->stat_CatchupInRuleCheckerDiscards);
7552 if (sblk->stat_CatchupInFTQDiscards) {
7553 if_printf(ifp, " 0x%08X : CatchupInFTQDiscards\n",
7554 sblk->stat_CatchupInFTQDiscards);
7557 if (sblk->stat_CatchupInMBUFDiscards) {
7558 if_printf(ifp, " 0x%08X : CatchupInMBUFDiscards\n",
7559 sblk->stat_CatchupInMBUFDiscards);
7562 if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7563 if_printf(ifp, " 0x%08X : CatchupInRuleCheckerP4Hit\n",
7564 sblk->stat_CatchupInRuleCheckerP4Hit);
7568 "----------------------------"
7570 "----------------------------\n");
7574 /****************************************************************************/
7575 /* Prints out a summary of the driver state. */
7579 /****************************************************************************/
7581 bce_dump_driver_state(struct bce_softc *sc)
7583 struct ifnet *ifp = &sc->arpcom.ac_if;
7584 uint32_t val_hi, val_lo;
7587 "-----------------------------"
7589 "-----------------------------\n");
7591 val_hi = BCE_ADDR_HI(sc);
7592 val_lo = BCE_ADDR_LO(sc);
7593 if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7594 "virtual address\n", val_hi, val_lo);
7596 val_hi = BCE_ADDR_HI(sc->status_block);
7597 val_lo = BCE_ADDR_LO(sc->status_block);
7598 if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7599 "virtual address\n", val_hi, val_lo);
7601 val_hi = BCE_ADDR_HI(sc->stats_block);
7602 val_lo = BCE_ADDR_LO(sc->stats_block);
7603 if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7604 "virtual address\n", val_hi, val_lo);
7606 val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7607 val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7608 if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7609 "virtual adddress\n", val_hi, val_lo);
7611 val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7612 val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7613 if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7614 "virtual address\n", val_hi, val_lo);
7616 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7617 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7618 if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7619 "virtual address\n", val_hi, val_lo);
7621 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7622 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7623 if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7624 "virtual address\n", val_hi, val_lo);
7626 if_printf(ifp, " 0x%08X - (sc->interrupts_generated) "
7627 "h/w intrs\n", sc->interrupts_generated);
7629 if_printf(ifp, " 0x%08X - (sc->rx_interrupts) "
7630 "rx interrupts handled\n", sc->rx_interrupts);
7632 if_printf(ifp, " 0x%08X - (sc->tx_interrupts) "
7633 "tx interrupts handled\n", sc->tx_interrupts);
7635 if_printf(ifp, " 0x%08X - (sc->last_status_idx) "
7636 "status block index\n", sc->last_status_idx);
7638 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_prod) "
7639 "tx producer index\n",
7640 sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_prod));
7642 if_printf(ifp, " 0x%04X(0x%04X) - (sc->tx_cons) "
7643 "tx consumer index\n",
7644 sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_cons));
7646 if_printf(ifp, " 0x%08X - (sc->tx_prod_bseq) "
7647 "tx producer bseq index\n", sc->tx_prod_bseq);
7649 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_prod) "
7650 "rx producer index\n",
7651 sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_prod));
7653 if_printf(ifp, " 0x%04X(0x%04X) - (sc->rx_cons) "
7654 "rx consumer index\n",
7655 sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_cons));
7657 if_printf(ifp, " 0x%08X - (sc->rx_prod_bseq) "
7658 "rx producer bseq index\n", sc->rx_prod_bseq);
7660 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7661 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7663 if_printf(ifp, " 0x%08X - (sc->free_rx_bd) "
7664 "free rx_bd's\n", sc->free_rx_bd);
7666 if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7667 "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7669 if_printf(ifp, " 0x%08X - (sc->txmbuf_alloc) "
7670 "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7672 if_printf(ifp, " 0x%08X - (sc->rx_mbuf_alloc) "
7673 "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7675 if_printf(ifp, " 0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7678 if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7679 sc->tx_hi_watermark, sc->max_tx_bd);
7681 if_printf(ifp, " 0x%08X - (sc->mbuf_alloc_failed) "
7682 "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7685 "----------------------------"
7687 "----------------------------\n");
7691 /****************************************************************************/
7692 /* Prints out the hardware state through a summary of important registers, */
7693 /* followed by a complete register dump. */
7697 /****************************************************************************/
7699 bce_dump_hw_state(struct bce_softc *sc)
7701 struct ifnet *ifp = &sc->arpcom.ac_if;
7706 "----------------------------"
7708 "----------------------------\n");
7710 if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7712 val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7713 if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7714 val1, BCE_MISC_ENABLE_STATUS_BITS);
7716 val1 = REG_RD(sc, BCE_DMA_STATUS);
7717 if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7719 val1 = REG_RD(sc, BCE_CTX_STATUS);
7720 if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7722 val1 = REG_RD(sc, BCE_EMAC_STATUS);
7723 if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7724 val1, BCE_EMAC_STATUS);
7726 val1 = REG_RD(sc, BCE_RPM_STATUS);
7727 if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7729 val1 = REG_RD(sc, BCE_TBDR_STATUS);
7730 if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7731 val1, BCE_TBDR_STATUS);
7733 val1 = REG_RD(sc, BCE_TDMA_STATUS);
7734 if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7735 val1, BCE_TDMA_STATUS);
7737 val1 = REG_RD(sc, BCE_HC_STATUS);
7738 if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7740 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7741 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7742 val1, BCE_TXP_CPU_STATE);
7744 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7745 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7746 val1, BCE_TPAT_CPU_STATE);
7748 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7749 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7750 val1, BCE_RXP_CPU_STATE);
7752 val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7753 if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7754 val1, BCE_COM_CPU_STATE);
7756 val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7757 if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7758 val1, BCE_MCP_CPU_STATE);
7760 val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7761 if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7762 val1, BCE_CP_CPU_STATE);
7765 "----------------------------"
7767 "----------------------------\n");
7770 "----------------------------"
7772 "----------------------------\n");
7774 for (i = 0x400; i < 0x8000; i += 0x10) {
7775 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7777 REG_RD(sc, i + 0x4),
7778 REG_RD(sc, i + 0x8),
7779 REG_RD(sc, i + 0xc));
7783 "----------------------------"
7785 "----------------------------\n");
7789 /****************************************************************************/
7790 /* Prints out the TXP state. */
7794 /****************************************************************************/
7796 bce_dump_txp_state(struct bce_softc *sc)
7798 struct ifnet *ifp = &sc->arpcom.ac_if;
7803 "----------------------------"
7805 "----------------------------\n");
7807 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7808 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7809 val1, BCE_TXP_CPU_MODE);
7811 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7812 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7813 val1, BCE_TXP_CPU_STATE);
7815 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7816 if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7817 val1, BCE_TXP_CPU_EVENT_MASK);
7820 "----------------------------"
7822 "----------------------------\n");
7824 for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7825 /* Skip the big blank spaces */
7826 if (i < 0x454000 && i > 0x5ffff) {
7827 if_printf(ifp, "0x%04X: "
7828 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7830 REG_RD_IND(sc, i + 0x4),
7831 REG_RD_IND(sc, i + 0x8),
7832 REG_RD_IND(sc, i + 0xc));
7837 "----------------------------"
7839 "----------------------------\n");
7843 /****************************************************************************/
7844 /* Prints out the RXP state. */
7848 /****************************************************************************/
7850 bce_dump_rxp_state(struct bce_softc *sc)
7852 struct ifnet *ifp = &sc->arpcom.ac_if;
7857 "----------------------------"
7859 "----------------------------\n");
7861 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7862 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7863 val1, BCE_RXP_CPU_MODE);
7865 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7866 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7867 val1, BCE_RXP_CPU_STATE);
7869 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7870 if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7871 val1, BCE_RXP_CPU_EVENT_MASK);
7874 "----------------------------"
7876 "----------------------------\n");
7878 for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7879 /* Skip the big blank sapces */
7880 if (i < 0xc5400 && i > 0xdffff) {
7881 if_printf(ifp, "0x%04X: "
7882 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7884 REG_RD_IND(sc, i + 0x4),
7885 REG_RD_IND(sc, i + 0x8),
7886 REG_RD_IND(sc, i + 0xc));
7891 "----------------------------"
7893 "----------------------------\n");
7897 /****************************************************************************/
7898 /* Prints out the TPAT state. */
7902 /****************************************************************************/
7904 bce_dump_tpat_state(struct bce_softc *sc)
7906 struct ifnet *ifp = &sc->arpcom.ac_if;
7911 "----------------------------"
7913 "----------------------------\n");
7915 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7916 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7917 val1, BCE_TPAT_CPU_MODE);
7919 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7920 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7921 val1, BCE_TPAT_CPU_STATE);
7923 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7924 if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7925 val1, BCE_TPAT_CPU_EVENT_MASK);
7928 "----------------------------"
7930 "----------------------------\n");
7932 for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7933 /* Skip the big blank spaces */
7934 if (i < 0x854000 && i > 0x9ffff) {
7935 if_printf(ifp, "0x%04X: "
7936 "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7938 REG_RD_IND(sc, i + 0x4),
7939 REG_RD_IND(sc, i + 0x8),
7940 REG_RD_IND(sc, i + 0xc));
7945 "----------------------------"
7947 "----------------------------\n");
7951 /****************************************************************************/
7952 /* Prints out the driver state and then enters the debugger. */
7956 /****************************************************************************/
7958 bce_breakpoint(struct bce_softc *sc)
7961 bce_freeze_controller(sc);
7964 bce_dump_driver_state(sc);
7965 bce_dump_status_block(sc);
7966 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD(sc));
7967 bce_dump_hw_state(sc);
7968 bce_dump_txp_state(sc);
7971 bce_unfreeze_controller(sc);
7974 /* Call the debugger. */
7978 #endif /* BCE_DEBUG */
7981 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7983 struct bce_softc *sc = arg1;
7985 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7986 &sc->bce_tx_quick_cons_trip_int,
7987 BCE_COALMASK_TX_BDS_INT);
7991 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7993 struct bce_softc *sc = arg1;
7995 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7996 &sc->bce_tx_quick_cons_trip,
7997 BCE_COALMASK_TX_BDS);
8001 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
8003 struct bce_softc *sc = arg1;
8005 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8006 &sc->bce_tx_ticks_int,
8007 BCE_COALMASK_TX_TICKS_INT);
8011 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
8013 struct bce_softc *sc = arg1;
8015 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8017 BCE_COALMASK_TX_TICKS);
8021 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
8023 struct bce_softc *sc = arg1;
8025 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8026 &sc->bce_rx_quick_cons_trip_int,
8027 BCE_COALMASK_RX_BDS_INT);
8031 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
8033 struct bce_softc *sc = arg1;
8035 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8036 &sc->bce_rx_quick_cons_trip,
8037 BCE_COALMASK_RX_BDS);
8041 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
8043 struct bce_softc *sc = arg1;
8045 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8046 &sc->bce_rx_ticks_int,
8047 BCE_COALMASK_RX_TICKS_INT);
8051 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
8053 struct bce_softc *sc = arg1;
8055 return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8057 BCE_COALMASK_RX_TICKS);
8061 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
8062 uint32_t coalchg_mask)
8064 struct bce_softc *sc = arg1;
8065 struct ifnet *ifp = &sc->arpcom.ac_if;
8068 lwkt_serialize_enter(ifp->if_serializer);
8071 error = sysctl_handle_int(oidp, &v, 0, req);
8072 if (!error && req->newptr != NULL) {
8077 sc->bce_coalchg_mask |= coalchg_mask;
8081 lwkt_serialize_exit(ifp->if_serializer);
8086 bce_coal_change(struct bce_softc *sc)
8088 struct ifnet *ifp = &sc->arpcom.ac_if;
8090 ASSERT_SERIALIZED(ifp->if_serializer);
8092 if ((ifp->if_flags & IFF_RUNNING) == 0) {
8093 sc->bce_coalchg_mask = 0;
8097 if (sc->bce_coalchg_mask &
8098 (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
8099 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
8100 (sc->bce_tx_quick_cons_trip_int << 16) |
8101 sc->bce_tx_quick_cons_trip);
8103 if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
8104 sc->bce_tx_quick_cons_trip,
8105 sc->bce_tx_quick_cons_trip_int);
8109 if (sc->bce_coalchg_mask &
8110 (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
8111 REG_WR(sc, BCE_HC_TX_TICKS,
8112 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
8114 if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
8115 sc->bce_tx_ticks, sc->bce_tx_ticks_int);
8119 if (sc->bce_coalchg_mask &
8120 (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
8121 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
8122 (sc->bce_rx_quick_cons_trip_int << 16) |
8123 sc->bce_rx_quick_cons_trip);
8125 if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
8126 sc->bce_rx_quick_cons_trip,
8127 sc->bce_rx_quick_cons_trip_int);
8131 if (sc->bce_coalchg_mask &
8132 (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
8133 REG_WR(sc, BCE_HC_RX_TICKS,
8134 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
8136 if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
8137 sc->bce_rx_ticks, sc->bce_rx_ticks_int);
8141 sc->bce_coalchg_mask = 0;