2 * Copyright (c) 2004 Martin V\xe9giard.
3 * Copyright (c) 2004-2005 Bruno Ducrot
4 * Copyright (c) 2004 FUKUDA Nobuhiko <nfukuda@spa.is.uec.ac.jp>
5 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc.
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Juan Romero Pardines and Martin Vegiard.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <machine/cpufunc.h>
35 #include <machine/cpufreq.h>
37 #define AMD0F_MSR_FIDVID_CTL 0xc0010041
38 #define AMD0F_MSR_FIDVID_STATUS 0xc0010042
40 /* AMD0F_MSR_FIDVID_STATUS */
41 #define AMD0F_STA_CFID(x) ((x) & 0x3f)
42 #define AMD0F_STA_SFID(x) (((x) >> 8) & 0x3f)
43 #define AMD0F_STA_MFID(x) (((x) >> 16) & 0x3f)
44 #define AMD0F_STA_PENDING(x) (((x) >> 31) & 0x01)
45 #define AMD0F_STA_CVID(x) (((x) >> 32) & 0x1f)
46 #define AMD0F_STA_SVID(x) (((x) >> 40) & 0x1f)
47 #define AMD0F_STA_MVID(x) (((x) >> 48) & 0x1f)
49 #define AMD0F_WRITE_FIDVID(fid, vid, ctrl) \
50 wrmsr(AMD0F_MSR_FIDVID_CTL, \
51 (((ctrl) << 32) | (1ULL << 16) | ((vid) << 8) | (fid)))
53 #define AMD0F_WAIT_FIDVID_CHG(status) \
55 (status) = rdmsr(AMD0F_MSR_FIDVID_STATUS); \
56 } while (AMD0F_STA_PENDING(status))
58 #define AMD0F_FID2VCO(fid) \
59 (((fid) < 8) ? (8 + ((fid) << 1)) : (fid))
61 #define AMD0F_DELAY_VST(vst) DELAY(20 * (vst))
62 #define AMD0F_DELAY_IRT(irt) DELAY(10 * (1 << (irt)))
65 #define abs(x) ((x) < 0 ? -(x) : (x))
68 amd0f_set_fidvid(const struct amd0f_fidvid *fv, const struct amd0f_xsit *xsit)
70 uint32_t val, cfid, cvid;
75 * We don't wait change pending bit here, need to ensure
76 * that it isn't stuck.
78 status = rdmsr(AMD0F_MSR_FIDVID_STATUS);
79 if (AMD0F_STA_PENDING(status))
82 cfid = AMD0F_STA_CFID(status);
83 cvid = AMD0F_STA_CVID(status);
84 if (fv->fid == cfid && fv->vid == cvid)
88 * Phase 1: Raise core voltage to requested VID if frequency is
91 if ((fv->fid & ~0x1) > (cfid & ~0x1) || cvid > fv->vid) {
92 KKASSERT(fv->vid >= xsit->rvo);
94 KKASSERT(cvid >= xsit->rvo);
96 while (cvid > fv->vid) {
97 if (cvid > (1 << xsit->mvs))
98 val = cvid - (1 << xsit->mvs);
101 AMD0F_WRITE_FIDVID(cfid, val, 0ULL);
102 AMD0F_WAIT_FIDVID_CHG(status);
103 cvid = AMD0F_STA_CVID(status);
104 AMD0F_DELAY_VST(xsit->vst);
106 /* ... then raise to voltage + RVO (if required) */
107 for (rvo = xsit->rvo; rvo > 0 && cvid > 0; --rvo) {
108 /* XXX It's not clear from spec if we have to do that
109 * in 0.25 step or in MVS. Therefore do it as it's done
111 AMD0F_WRITE_FIDVID(cfid, cvid - 1, 0ULL);
112 AMD0F_WAIT_FIDVID_CHG(status);
113 cvid = AMD0F_STA_CVID(status);
114 AMD0F_DELAY_VST(xsit->vst);
118 * Phase 2: Change to requested core frequency
120 if (cfid != fv->fid) {
121 /* NOTE: Keep type as int, else following 'abs' will break */
122 int vco_fid, vco_cfid;
124 vco_fid = AMD0F_FID2VCO(fv->fid);
125 vco_cfid = AMD0F_FID2VCO(cfid);
126 while (abs(vco_fid - vco_cfid) > 2) {
127 if (fv->fid > cfid) {
131 val = AMD0F_FID2VCO(cfid) + 2;
136 AMD0F_WRITE_FIDVID(val, cvid,
137 (uint64_t)xsit->pll_time * 1000 / 5);
138 AMD0F_WAIT_FIDVID_CHG(status);
139 cfid = AMD0F_STA_CFID(status);
140 AMD0F_DELAY_IRT(xsit->irt);
141 vco_cfid = AMD0F_FID2VCO(cfid);
143 if (cfid != fv->fid) {
144 AMD0F_WRITE_FIDVID(fv->fid, cvid,
145 (uint64_t)xsit->pll_time * 1000 / 5);
146 AMD0F_WAIT_FIDVID_CHG(status);
147 cfid = AMD0F_STA_CFID(status);
148 AMD0F_DELAY_IRT(xsit->irt);
153 * Phase 3: Change to requested voltage
155 if (cvid != fv->vid) {
156 AMD0F_WRITE_FIDVID(cfid, fv->vid, 0ULL);
157 AMD0F_WAIT_FIDVID_CHG(status);
158 cvid = AMD0F_STA_CVID(status);
159 AMD0F_DELAY_VST(xsit->vst);
165 amd0f_get_fidvid(struct amd0f_fidvid *fv)
169 status = rdmsr(AMD0F_MSR_FIDVID_STATUS);
170 if (AMD0F_STA_PENDING(status))
173 fv->fid = AMD0F_STA_CFID(status);
174 fv->vid = AMD0F_STA_CVID(status);
179 amd0f_fidvid_limit(struct amd0f_fidvid *fv_min, struct amd0f_fidvid *fv_max)
181 uint32_t max_fid, max_vid, start_fid, start_vid;
184 status = rdmsr(AMD0F_MSR_FIDVID_STATUS);
186 start_fid = AMD0F_STA_SFID(status);
187 max_fid = AMD0F_STA_MFID(status);
188 start_vid = AMD0F_STA_SVID(status);
189 max_vid = AMD0F_STA_MVID(status);
191 if (max_fid == 0x2a && max_vid != 0) {
192 fv_max->fid = start_fid + 0xa;
193 fv_max->vid = max_vid + 0x2;
195 fv_min->vid = start_vid;
197 fv_max->fid = max_fid;
198 fv_max->vid = max_vid + 0x2;
199 fv_min->fid = start_fid;
200 fv_min->vid = start_vid;