2 * Copyright (c) 2003-2011 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * pmap invalidation support code. Certain hardware requirements must
37 * be dealt with when manipulating page table entries and page directory
38 * entries within a pmap. In particular, we cannot safely manipulate
39 * page tables which are in active use by another cpu (even if it is
40 * running in userland) for two reasons: First, TLB writebacks will
41 * race against our own modifications and tests. Second, even if we
42 * were to use bus-locked instruction we can still screw up the
43 * target cpu's instruction pipeline due to Intel cpu errata.
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
50 #include <sys/vmmeter.h>
51 #include <sys/thread2.h>
55 #include <vm/vm_object.h>
57 #include <machine/cputypes.h>
58 #include <machine/md_var.h>
59 #include <machine/specialreg.h>
60 #include <machine/smp.h>
61 #include <machine/globaldata.h>
62 #include <machine/pmap.h>
63 #include <machine/pmap_inval.h>
65 static void pmap_inval_callback(void *arg);
68 * Initialize for add or flush
71 pmap_inval_init(pmap_inval_info_t info)
74 crit_enter_id("inval");
78 * Add a (pmap, va) pair to the invalidation list and protect access
81 * CPULOCK_EXCL is used to interlock thread switchins
84 pmap_inval_interlock(pmap_inval_info_t info, pmap_t pmap, vm_offset_t va)
89 DEBUG_PUSH_INFO("pmap_inval_interlock");
91 olock = pmap->pm_active_lock & ~CPULOCK_EXCL;
92 nlock = olock | CPULOCK_EXCL;
93 if (atomic_cmpset_int(&pmap->pm_active_lock, olock, nlock))
99 KKASSERT((info->pir_flags & PIRF_CPUSYNC) == 0);
101 info->pir_flags = PIRF_CPUSYNC;
102 lwkt_cpusync_init(&info->pir_cpusync, pmap->pm_active,
103 pmap_inval_callback, info);
104 lwkt_cpusync_interlock(&info->pir_cpusync);
108 pmap_inval_deinterlock(pmap_inval_info_t info, pmap_t pmap)
110 KKASSERT(info->pir_flags & PIRF_CPUSYNC);
111 atomic_clear_int(&pmap->pm_active_lock, CPULOCK_EXCL);
112 lwkt_cpusync_deinterlock(&info->pir_cpusync);
117 pmap_inval_callback(void *arg)
119 pmap_inval_info_t info = arg;
121 if (info->pir_va == (vm_offset_t)-1)
124 cpu_invlpg((void *)info->pir_va);
128 pmap_inval_done(pmap_inval_info_t info)
130 KKASSERT((info->pir_flags & PIRF_CPUSYNC) == 0);
131 crit_exit_id("inval");