2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
27 * $DragonFly: src/sys/dev/netif/tx/if_tx.c,v 1.43 2008/08/17 04:32:35 sephe Exp $
31 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
33 * These cards are based on SMC83c17x (EPIC) chip and one of the various
34 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
35 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
36 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
37 * supports fibre optics.
39 * Thanks are going to Steve Bauer and Jason Wright.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/sockio.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/queue.h>
50 #include <sys/serialize.h>
53 #include <sys/thread2.h>
54 #include <sys/interrupt.h>
57 #include <net/ifq_var.h>
58 #include <net/if_arp.h>
59 #include <net/ethernet.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
65 #include <net/vlan/if_vlan_var.h>
67 #include <vm/vm.h> /* for vtophys */
68 #include <vm/pmap.h> /* for vtophys */
70 #include <bus/pci/pcireg.h>
71 #include <bus/pci/pcivar.h>
72 #include <bus/pci/pcidevs.h>
74 #include <dev/netif/mii_layer/mii.h>
75 #include <dev/netif/mii_layer/miivar.h>
76 #include <dev/netif/mii_layer/miidevs.h>
77 #include <dev/netif/mii_layer/lxtphyreg.h>
79 #include "miibus_if.h"
81 #include <dev/netif/tx/if_txreg.h>
82 #include <dev/netif/tx/if_txvar.h>
84 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
85 static void epic_intr(void *);
86 static void epic_tx_underrun(epic_softc_t *);
87 static int epic_common_attach(epic_softc_t *);
88 static void epic_ifstart(struct ifnet *);
89 static void epic_ifwatchdog(struct ifnet *);
90 static void epic_stats_update(void *);
91 static int epic_init(epic_softc_t *);
92 static void epic_stop(epic_softc_t *);
93 static void epic_rx_done(epic_softc_t *);
94 static void epic_tx_done(epic_softc_t *);
95 static int epic_init_rings(epic_softc_t *);
96 static void epic_free_rings(epic_softc_t *);
97 static void epic_stop_activity(epic_softc_t *);
98 static int epic_queue_last_packet(epic_softc_t *);
99 static void epic_start_activity(epic_softc_t *);
100 static void epic_set_rx_mode(epic_softc_t *);
101 static void epic_set_tx_mode(epic_softc_t *);
102 static void epic_set_mc_table(epic_softc_t *);
103 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
104 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
105 static u_int16_t epic_input_eepromw(epic_softc_t *);
106 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
107 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
108 static u_int8_t epic_read_eepromreg(epic_softc_t *);
110 static int epic_read_phy_reg(epic_softc_t *, int, int);
111 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
113 static int epic_miibus_readreg(device_t, int, int);
114 static int epic_miibus_writereg(device_t, int, int, int);
115 static void epic_miibus_statchg(device_t);
116 static void epic_miibus_mediainit(device_t);
118 static int epic_ifmedia_upd(struct ifnet *);
119 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
121 static int epic_probe(device_t);
122 static int epic_attach(device_t);
123 static void epic_shutdown(device_t);
124 static int epic_detach(device_t);
126 static device_method_t epic_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, epic_probe),
129 DEVMETHOD(device_attach, epic_attach),
130 DEVMETHOD(device_detach, epic_detach),
131 DEVMETHOD(device_shutdown, epic_shutdown),
134 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
135 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
136 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
137 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
142 static driver_t epic_driver = {
148 static devclass_t epic_devclass;
150 DECLARE_DUMMY_MODULE(if_tx);
151 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
152 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
153 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
155 static struct epic_type epic_devs[] = {
156 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170,
157 "SMC EtherPower II 10/100" },
162 epic_probe(device_t dev)
167 vid = pci_get_vendor(dev);
168 did = pci_get_device(dev);
169 for (t = epic_devs; t->name != NULL; ++t) {
170 if (vid == t->ven_id && did == t->dev_id) {
171 device_set_desc(dev, t->name);
178 #if defined(EPIC_USEIOSPACE)
179 #define EPIC_RES SYS_RES_IOPORT
180 #define EPIC_RID PCIR_BAR(0)
182 #define EPIC_RES SYS_RES_MEMORY
183 #define EPIC_RID PCIR_BAR(1)
187 * Attach routine: map registers, allocate softc, rings and descriptors.
188 * Reset to known state.
191 epic_attach(device_t dev)
198 sc = device_get_softc(dev);
200 /* Preinitialize softc structure */
202 callout_init(&sc->tx_stat_timer);
204 /* Fill ifnet structure */
206 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
208 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
209 ifp->if_ioctl = epic_ifioctl;
210 ifp->if_start = epic_ifstart;
211 ifp->if_watchdog = epic_ifwatchdog;
212 ifp->if_init = (if_init_f_t*)epic_init;
214 ifp->if_baudrate = 10000000;
215 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
216 ifq_set_ready(&ifp->if_snd);
218 pci_enable_busmaster(dev);
221 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
223 if (sc->res == NULL) {
224 device_printf(dev, "couldn't map ports/memory\n");
229 sc->sc_st = rman_get_bustag(sc->res);
230 sc->sc_sh = rman_get_bushandle(sc->res);
232 /* Allocate interrupt */
234 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
235 RF_SHAREABLE | RF_ACTIVE);
237 if (sc->irq == NULL) {
238 device_printf(dev, "couldn't map interrupt\n");
243 /* Do OS independent part, including chip wakeup and reset */
244 error = epic_common_attach(sc);
250 /* Do ifmedia setup */
251 if (mii_phy_probe(dev, &sc->miibus,
252 epic_ifmedia_upd, epic_ifmedia_sts)) {
253 device_printf(dev, "ERROR! MII without any PHY!?\n");
258 /* board type and ... */
260 for(i=0x2c;i<0x32;i++) {
261 tmp = epic_read_eeprom(sc, i);
262 if (' ' == (u_int8_t)tmp) break;
263 kprintf("%c", (u_int8_t)tmp);
265 if (' ' == (u_int8_t)tmp) break;
266 kprintf("%c", (u_int8_t)tmp);
270 /* Attach to OS's managers */
271 ether_ifattach(ifp, sc->sc_macaddr, NULL);
272 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
274 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
275 epic_intr, sc, &sc->sc_ih,
279 device_printf(dev, "couldn't set up irq\n");
284 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->irq));
285 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
295 * Detach driver and free resources
298 epic_detach(device_t dev)
300 epic_softc_t *sc = device_get_softc(dev);
301 struct ifnet *ifp = &sc->arpcom.ac_if;
303 if (device_is_attached(dev)) {
304 lwkt_serialize_enter(ifp->if_serializer);
306 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
307 lwkt_serialize_exit(ifp->if_serializer);
313 device_delete_child(dev, sc->miibus);
314 bus_generic_detach(dev);
317 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
319 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
322 kfree(sc->tx_flist, M_DEVBUF);
324 kfree(sc->tx_desc, M_DEVBUF);
326 kfree(sc->rx_desc, M_DEVBUF);
335 * Stop all chip I/O so that the kernel's probe routines don't
336 * get confused by errant DMAs when rebooting.
339 epic_shutdown(device_t dev)
344 sc = device_get_softc(dev);
345 ifp = &sc->arpcom.ac_if;
346 lwkt_serialize_enter(ifp->if_serializer);
348 lwkt_serialize_exit(ifp->if_serializer);
352 * This is if_ioctl handler.
355 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
357 epic_softc_t *sc = ifp->if_softc;
358 struct mii_data *mii;
359 struct ifreq *ifr = (struct ifreq *) data;
364 if (ifp->if_mtu == ifr->ifr_mtu)
367 /* XXX Though the datasheet doesn't imply any
368 * limitations on RX and TX sizes beside max 64Kb
369 * DMA transfer, seems we can't send more then 1600
370 * data bytes per ethernet packet. (Transmitter hangs
371 * up if more data is sent)
373 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
374 ifp->if_mtu = ifr->ifr_mtu;
383 * If the interface is marked up and stopped, then start it.
384 * If it is marked down and running, then stop it.
386 if (ifp->if_flags & IFF_UP) {
387 if ((ifp->if_flags & IFF_RUNNING) == 0) {
392 if (ifp->if_flags & IFF_RUNNING) {
398 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
399 epic_stop_activity(sc);
400 epic_set_mc_table(sc);
401 epic_set_rx_mode(sc);
402 epic_start_activity(sc);
407 epic_set_mc_table(sc);
413 mii = device_get_softc(sc->miibus);
414 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
418 error = ether_ioctl(ifp, command, data);
425 * OS-independed part of attach process. allocate memory for descriptors
426 * and frag lists, wake up chip, read MAC address and PHY identyfier.
427 * Return -1 on failure.
430 epic_common_attach(epic_softc_t *sc)
435 sc->tx_flist = kmalloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
436 M_DEVBUF, M_WAITOK | M_ZERO);
437 sc->tx_desc = kmalloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
438 M_DEVBUF, M_WAITOK | M_ZERO);
439 sc->rx_desc = kmalloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
440 M_DEVBUF, M_WAITOK | M_ZERO);
442 /* Bring the chip out of low-power mode. */
443 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
446 /* Workaround for Application Note 7-15 */
447 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
449 /* Read mac address from EEPROM */
450 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
451 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
453 /* Set Non-Volatile Control Register from EEPROM */
454 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
457 sc->tx_threshold = TRANSMIT_THRESHOLD;
458 sc->txcon = TXCON_DEFAULT;
459 sc->miicfg = MIICFG_SMI_ENABLE;
460 sc->phyid = EPIC_UNKN_PHY;
464 sub_vid = pci_get_subvendor(sc->dev);
465 sc->cardid = pci_get_subdevice(sc->dev);
467 if (sub_vid != PCI_VENDOR_SMC)
468 device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid);
474 * This is if_start handler. It takes mbufs from if_snd queue
475 * and queue them for transmit, one by one, until TX ring become full
476 * or queue become empty.
479 epic_ifstart(struct ifnet *ifp)
481 epic_softc_t *sc = ifp->if_softc;
482 struct epic_tx_buffer *buf;
483 struct epic_tx_desc *desc;
484 struct epic_frag_list *flist;
489 while (sc->pending_txs < TX_RING_SIZE) {
490 buf = sc->tx_buffer + sc->cur_tx;
491 desc = sc->tx_desc + sc->cur_tx;
492 flist = sc->tx_flist + sc->cur_tx;
494 /* Get next packet to send */
495 m0 = ifq_dequeue(&ifp->if_snd, NULL);
497 /* If nothing to send, return */
501 /* Fill fragments list */
503 (NULL != m) && (i < EPIC_MAX_FRAGS);
504 m = m->m_next, i++) {
505 flist->frag[i].fraglen = m->m_len;
506 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
510 /* If packet was more than EPIC_MAX_FRAGS parts, */
511 /* recopy packet to new allocated mbuf cluster */
513 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
520 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
521 flist->frag[0].fraglen =
522 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
523 m->m_pkthdr.rcvif = ifp;
526 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
533 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
534 desc->control = 0x01;
536 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
537 desc->status = 0x8000;
538 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
540 /* Set watchdog timer */
546 ifp->if_flags |= IFF_OACTIVE;
553 * Synopsis: Finish all received frames.
556 epic_rx_done(epic_softc_t *sc)
559 struct ifnet *ifp = &sc->sc_if;
560 struct epic_rx_buffer *buf;
561 struct epic_rx_desc *desc;
564 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
565 buf = sc->rx_buffer + sc->cur_rx;
566 desc = sc->rx_desc + sc->cur_rx;
568 /* Switch to next descriptor */
569 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
572 * Check for RX errors. This should only happen if
573 * SAVE_ERRORED_PACKETS is set. RX errors generate
574 * RXE interrupt usually.
576 if ((desc->status & 1) == 0) {
577 sc->sc_if.if_ierrors++;
578 desc->status = 0x8000;
582 /* Save packet length and mbuf contained packet */
583 len = desc->rxlength - ETHER_CRC_LEN;
586 /* Try to get mbuf cluster */
587 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
588 if (NULL == buf->mbuf) {
590 desc->status = 0x8000;
595 /* Point to new mbuf, and give descriptor to chip */
596 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
597 desc->status = 0x8000;
599 /* First mbuf in packet holds the ethernet and packet headers */
600 m->m_pkthdr.rcvif = ifp;
601 m->m_pkthdr.len = m->m_len = len;
603 /* Give mbuf to OS */
604 ifp->if_input(ifp, m);
606 /* Successfuly received frame */
614 * Synopsis: Do last phase of transmission. I.e. if desc is
615 * transmitted, decrease pending_txs counter, free mbuf contained
616 * packet, switch to next descriptor and repeat until no packets
617 * are pending or descriptor is not transmitted yet.
620 epic_tx_done(epic_softc_t *sc)
622 struct epic_tx_buffer *buf;
623 struct epic_tx_desc *desc;
626 while (sc->pending_txs > 0) {
627 buf = sc->tx_buffer + sc->dirty_tx;
628 desc = sc->tx_desc + sc->dirty_tx;
629 status = desc->status;
631 /* If packet is not transmitted, thou followed */
632 /* packets are not transmitted too */
633 if (status & 0x8000) break;
635 /* Packet is transmitted. Switch to next and */
638 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
642 /* Check for errors and collisions */
643 if (status & 0x0001) sc->sc_if.if_opackets++;
644 else sc->sc_if.if_oerrors++;
645 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
646 #if defined(EPIC_DIAG)
647 if ((status & 0x1001) == 0x1001) {
648 if_printf(&sc->sc_if,
649 "Tx ERROR: excessive coll. number\n");
654 if (sc->pending_txs < TX_RING_SIZE)
655 sc->sc_if.if_flags &= ~IFF_OACTIVE;
664 epic_softc_t * sc = (epic_softc_t *) arg;
667 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
668 CSR_WRITE_4(sc, INTSTAT, status);
670 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
672 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
673 #if defined(EPIC_DIAG)
674 if (status & INTSTAT_OVW)
675 if_printf(&sc->sc_if, "RX buffer overflow\n");
676 if (status & INTSTAT_RQE)
677 if_printf(&sc->sc_if, "RX FIFO overflow\n");
679 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
680 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
681 sc->sc_if.if_ierrors++;
685 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
687 if (!ifq_is_empty(&sc->sc_if.if_snd))
688 if_devstart(&sc->sc_if);
691 /* Check for rare errors */
692 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
693 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
694 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
695 INTSTAT_APE|INTSTAT_DPE)) {
696 if_printf(&sc->sc_if, "PCI fatal errors occurred: %s%s%s%s\n",
697 (status&INTSTAT_PMA)?"PMA ":"",
698 (status&INTSTAT_PTA)?"PTA ":"",
699 (status&INTSTAT_APE)?"APE ":"",
700 (status&INTSTAT_DPE)?"DPE":""
709 if (status & INTSTAT_RXE) {
710 #if defined(EPIC_DIAG)
711 if_printf(sc->sc_if, "CRC/Alignment error\n");
713 sc->sc_if.if_ierrors++;
716 if (status & INTSTAT_TXU) {
717 epic_tx_underrun(sc);
718 sc->sc_if.if_oerrors++;
723 /* If no packets are pending, then no timeouts */
724 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
730 * Handle the TX underrun error: increase the TX threshold
731 * and restart the transmitter.
734 epic_tx_underrun(epic_softc_t *sc)
736 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
737 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
738 #if defined(EPIC_DIAG)
739 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
742 sc->tx_threshold += 0x40;
743 #if defined(EPIC_DIAG)
744 if_printf(&sc->sc_if, "Tx UNDERRUN: "
745 "TX threshold increased to %d\n", sc->tx_threshold);
749 /* We must set TXUGO to reset the stuck transmitter */
750 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
752 /* Update the TX threshold */
753 epic_stop_activity(sc);
754 epic_set_tx_mode(sc);
755 epic_start_activity(sc);
761 * Synopsis: This one is called if packets wasn't transmitted
762 * during timeout. Try to deallocate transmitted packets, and
763 * if success continue to work.
766 epic_ifwatchdog(struct ifnet *ifp)
768 epic_softc_t *sc = ifp->if_softc;
770 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
772 /* Try to finish queued packets */
775 /* If not successful */
776 if (sc->pending_txs > 0) {
778 ifp->if_oerrors+=sc->pending_txs;
780 /* Reinitialize board */
781 if_printf(ifp, "reinitialization\n");
786 if_printf(ifp, "seems we can continue normally\n");
789 if (!ifq_is_empty(&ifp->if_snd))
794 * Despite the name of this function, it doesn't update statistics, it only
795 * helps in autonegotiation process.
798 epic_stats_update(void *xsc)
800 epic_softc_t *sc = xsc;
801 struct ifnet *ifp = &sc->sc_if;
802 struct mii_data * mii;
804 lwkt_serialize_enter(ifp->if_serializer);
806 mii = device_get_softc(sc->miibus);
809 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
811 lwkt_serialize_exit(ifp->if_serializer);
818 epic_ifmedia_upd(struct ifnet *ifp)
821 struct mii_data *mii;
823 struct mii_softc *miisc;
827 mii = device_get_softc(sc->miibus);
828 ifm = &mii->mii_media;
829 media = ifm->ifm_cur->ifm_media;
831 /* Do not do anything if interface is not up */
832 if ((ifp->if_flags & IFF_UP) == 0)
836 * Lookup current selected PHY
838 if (IFM_INST(media) == sc->serinst) {
839 sc->phyid = EPIC_SERIAL;
842 /* If we're not selecting serial interface, select MII mode */
843 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
844 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
846 /* Default to unknown PHY */
847 sc->phyid = EPIC_UNKN_PHY;
849 /* Lookup selected PHY */
850 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
851 miisc = LIST_NEXT(miisc, mii_list)) {
852 if (IFM_INST(media) == miisc->mii_inst) {
858 /* Identify selected PHY */
860 int id1, id2, model, oui;
862 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
863 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
865 oui = MII_OUI(id1, id2);
866 model = MII_MODEL(id2);
868 case MII_OUI_QUALSEMI:
869 if (model == MII_MODEL_QUALSEMI_QS6612)
870 sc->phyid = EPIC_QS6612_PHY;
872 case MII_OUI_xxALTIMA:
873 if (model == MII_MODEL_xxALTIMA_AC101)
874 sc->phyid = EPIC_AC101_PHY;
876 case MII_OUI_xxLEVEL1:
877 if (model == MII_MODEL_xxLEVEL1_LXT970)
878 sc->phyid = EPIC_LXT970_PHY;
885 * Do PHY specific card setup
888 /* Call this, to isolate all not selected PHYs and
893 /* Do our own setup */
895 case EPIC_QS6612_PHY:
898 /* We have to powerup fiber tranceivers */
899 if (IFM_SUBTYPE(media) == IFM_100_FX)
900 sc->miicfg |= MIICFG_694_ENABLE;
902 sc->miicfg &= ~MIICFG_694_ENABLE;
903 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
906 case EPIC_LXT970_PHY:
907 /* We have to powerup fiber tranceivers */
908 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
909 if (IFM_SUBTYPE(media) == IFM_100_FX)
910 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
912 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
913 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
917 /* Select serial PHY, (10base2/BNC usually) */
918 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
919 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
921 /* There is no driver to fill this */
922 mii->mii_media_active = media;
923 mii->mii_media_status = 0;
925 /* We need to call this manualy as i wasn't called
928 epic_miibus_statchg(sc->dev);
932 if_printf(ifp, "ERROR! Unknown PHY selected\n");
940 * Report current media status.
943 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
946 struct mii_data *mii;
950 mii = device_get_softc(sc->miibus);
951 ifm = &mii->mii_media;
953 /* Nothing should be selected if interface is down */
954 if ((ifp->if_flags & IFF_UP) == 0) {
955 ifmr->ifm_active = IFM_NONE;
956 ifmr->ifm_status = 0;
961 /* Call underlying pollstat, if not serial PHY */
962 if (sc->phyid != EPIC_SERIAL)
965 /* Simply copy media info */
966 ifmr->ifm_active = mii->mii_media_active;
967 ifmr->ifm_status = mii->mii_media_status;
973 * Callback routine, called on media change.
976 epic_miibus_statchg(device_t dev)
979 struct mii_data *mii;
982 sc = device_get_softc(dev);
983 mii = device_get_softc(sc->miibus);
984 media = mii->mii_media_active;
986 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
988 /* If we are in full-duplex mode or loopback operation,
989 * we need to decouple receiver and transmitter.
991 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
992 sc->txcon |= TXCON_FULL_DUPLEX;
994 /* On some cards we need manualy set fullduplex led */
995 if (sc->cardid == SMC9432FTX ||
996 sc->cardid == SMC9432FTX_SC) {
997 if (IFM_OPTIONS(media) & IFM_FDX)
998 sc->miicfg |= MIICFG_694_ENABLE;
1000 sc->miicfg &= ~MIICFG_694_ENABLE;
1002 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1005 /* Update baudrate */
1006 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1007 IFM_SUBTYPE(media) == IFM_100_FX)
1008 sc->sc_if.if_baudrate = 100000000;
1010 sc->sc_if.if_baudrate = 10000000;
1012 epic_stop_activity(sc);
1013 epic_set_tx_mode(sc);
1014 epic_start_activity(sc);
1020 epic_miibus_mediainit(device_t dev)
1023 struct mii_data *mii;
1024 struct ifmedia *ifm;
1027 sc = device_get_softc(dev);
1028 mii = device_get_softc(sc->miibus);
1029 ifm = &mii->mii_media;
1031 /* Add Serial Media Interface if present, this applies to
1034 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1035 /* Store its instance */
1036 sc->serinst = mii->mii_instance++;
1038 /* Add as 10base2/BNC media */
1039 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1040 ifmedia_add(ifm, media, 0, NULL);
1042 /* Report to user */
1043 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
1050 * Reset chip, allocate rings, and update media.
1053 epic_init(epic_softc_t *sc)
1055 struct ifnet *ifp = &sc->sc_if;
1058 /* If interface is already running, then we need not do anything */
1059 if (ifp->if_flags & IFF_RUNNING) {
1063 /* Soft reset the chip (we have to power up card before) */
1064 CSR_WRITE_4(sc, GENCTL, 0);
1065 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1068 * Reset takes 15 pci ticks which depends on PCI bus speed.
1069 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1074 CSR_WRITE_4(sc, GENCTL, 0);
1076 /* Workaround for Application Note 7-15 */
1077 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1079 /* Initialize rings */
1080 if (epic_init_rings(sc)) {
1081 if_printf(ifp, "failed to init rings\n");
1085 /* Give rings to EPIC */
1086 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1087 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1089 /* Put node address to EPIC */
1090 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1091 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1092 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1094 /* Set tx mode, includeing transmit threshold */
1095 epic_set_tx_mode(sc);
1097 /* Compute and set RXCON. */
1098 epic_set_rx_mode(sc);
1100 /* Set multicast table */
1101 epic_set_mc_table(sc);
1103 /* Enable interrupts by setting the interrupt mask. */
1104 CSR_WRITE_4(sc, INTMASK,
1105 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1106 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1109 /* Acknowledge all pending interrupts */
1110 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1112 /* Enable interrupts, set for PCI read multiple and etc */
1113 CSR_WRITE_4(sc, GENCTL,
1114 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1115 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1117 /* Mark interface running ... */
1118 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1119 else ifp->if_flags &= ~IFF_RUNNING;
1122 ifp->if_flags &= ~IFF_OACTIVE;
1124 /* Start Rx process */
1125 epic_start_activity(sc);
1127 /* Set appropriate media */
1128 epic_ifmedia_upd(ifp);
1130 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1136 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1140 epic_set_rx_mode(epic_softc_t *sc)
1142 u_int32_t flags = sc->sc_if.if_flags;
1143 u_int32_t rxcon = RXCON_DEFAULT;
1145 #if defined(EPIC_EARLY_RX)
1146 rxcon |= RXCON_EARLY_RX;
1149 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1151 CSR_WRITE_4(sc, RXCON, rxcon);
1157 * Synopsis: Set transmit control register. Chip must be in idle state to
1161 epic_set_tx_mode(epic_softc_t *sc)
1163 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1164 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1166 CSR_WRITE_4(sc, TXCON, sc->txcon);
1170 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1171 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1172 * individual frames, multicast filter must be manually programmed)
1174 * Note: EPIC must be in idle state.
1177 epic_set_mc_table(epic_softc_t *sc)
1179 struct ifnet *ifp = &sc->sc_if;
1180 struct ifmultiaddr *ifma;
1181 u_int16_t filter[4];
1184 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1185 CSR_WRITE_4(sc, MC0, 0xFFFF);
1186 CSR_WRITE_4(sc, MC1, 0xFFFF);
1187 CSR_WRITE_4(sc, MC2, 0xFFFF);
1188 CSR_WRITE_4(sc, MC3, 0xFFFF);
1198 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1199 if (ifma->ifma_addr->sa_family != AF_LINK)
1201 h = (ether_crc32_be(
1202 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1203 ETHER_ADDR_LEN) >> 26) & 0x3f;
1204 filter[h >> 4] |= 1 << (h & 0xF);
1207 CSR_WRITE_4(sc, MC0, filter[0]);
1208 CSR_WRITE_4(sc, MC1, filter[1]);
1209 CSR_WRITE_4(sc, MC2, filter[2]);
1210 CSR_WRITE_4(sc, MC3, filter[3]);
1216 * Synopsis: Start receive process and transmit one, if they need.
1219 epic_start_activity(epic_softc_t *sc)
1221 /* Start rx process */
1222 CSR_WRITE_4(sc, COMMAND,
1223 COMMAND_RXQUEUED | COMMAND_START_RX |
1224 (sc->pending_txs?COMMAND_TXQUEUED:0));
1228 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1229 * packet needs to be queued to stop Tx DMA.
1232 epic_stop_activity(epic_softc_t *sc)
1236 /* Stop Tx and Rx DMA */
1237 CSR_WRITE_4(sc, COMMAND,
1238 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1240 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1241 for (i=0; i<0x1000; i++) {
1242 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1243 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1248 /* Catch all finished packets */
1252 status = CSR_READ_4(sc, INTSTAT);
1254 if ((status & INTSTAT_RXIDLE) == 0)
1255 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
1257 if ((status & INTSTAT_TXIDLE) == 0)
1258 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
1261 * May need to queue one more packet if TQE, this is rare
1262 * but existing case.
1264 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1265 epic_queue_last_packet(sc);
1270 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1271 * a packet from current descriptor will be copied to internal RAM. We
1272 * compose a dummy packet here and queue it for transmission.
1274 * XXX the packet will then be actually sent over network...
1277 epic_queue_last_packet(epic_softc_t *sc)
1279 struct epic_tx_desc *desc;
1280 struct epic_frag_list *flist;
1281 struct epic_tx_buffer *buf;
1285 if_printf(&sc->sc_if, "queue last packet\n");
1287 desc = sc->tx_desc + sc->cur_tx;
1288 flist = sc->tx_flist + sc->cur_tx;
1289 buf = sc->tx_buffer + sc->cur_tx;
1291 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1294 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1299 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1300 flist->frag[0].fraglen = m0->m_len;
1301 m0->m_pkthdr.len = m0->m_len;
1302 m0->m_pkthdr.rcvif = &sc->sc_if;
1303 bzero(mtod(m0,caddr_t), m0->m_len);
1305 /* Fill fragments list */
1306 flist->frag[0].fraglen = m0->m_len;
1307 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1308 flist->numfrags = 1;
1310 /* Fill in descriptor */
1313 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1314 desc->control = 0x01;
1315 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1316 desc->status = 0x8000;
1318 /* Launch transmition */
1319 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1321 /* Wait Tx DMA to stop (for how long??? XXX) */
1322 for (i=0; i<1000; i++) {
1323 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1328 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1329 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
1337 * Synopsis: Shut down board and deallocates rings.
1340 epic_stop(epic_softc_t *sc)
1342 sc->sc_if.if_timer = 0;
1344 callout_stop(&sc->tx_stat_timer);
1346 /* Disable interrupts */
1347 CSR_WRITE_4(sc, INTMASK, 0);
1348 CSR_WRITE_4(sc, GENCTL, 0);
1350 /* Try to stop Rx and TX processes */
1351 epic_stop_activity(sc);
1354 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1357 /* Make chip go to bed */
1358 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1360 /* Free memory allocated for rings */
1361 epic_free_rings(sc);
1363 /* Mark as stoped */
1364 sc->sc_if.if_flags &= ~IFF_RUNNING;
1368 * Synopsis: This function should free all memory allocated for rings.
1371 epic_free_rings(epic_softc_t *sc)
1375 for (i=0; i<RX_RING_SIZE; i++) {
1376 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1377 struct epic_rx_desc *desc = sc->rx_desc + i;
1380 desc->buflength = 0;
1383 if (buf->mbuf) m_freem(buf->mbuf);
1387 for (i=0; i<TX_RING_SIZE; i++) {
1388 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1389 struct epic_tx_desc *desc = sc->tx_desc + i;
1392 desc->buflength = 0;
1395 if (buf->mbuf) m_freem(buf->mbuf);
1401 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1402 * Point Tx descs to fragment lists. Check that all descs and fraglists
1403 * are bounded and aligned properly.
1406 epic_init_rings(epic_softc_t *sc)
1410 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1412 for (i = 0; i < RX_RING_SIZE; i++) {
1413 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1414 struct epic_rx_desc *desc = sc->rx_desc + i;
1416 desc->status = 0; /* Owned by driver */
1417 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1419 if ((desc->next & 3) ||
1420 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1421 epic_free_rings(sc);
1425 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1426 if (NULL == buf->mbuf) {
1427 epic_free_rings(sc);
1430 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1432 desc->buflength = MCLBYTES; /* Max RX buffer length */
1433 desc->status = 0x8000; /* Set owner bit to NIC */
1436 for (i = 0; i < TX_RING_SIZE; i++) {
1437 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1438 struct epic_tx_desc *desc = sc->tx_desc + i;
1441 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1443 if ((desc->next & 3) ||
1444 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1445 epic_free_rings(sc);
1450 desc->bufaddr = vtophys(sc->tx_flist + i);
1452 if ((desc->bufaddr & 3) ||
1453 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1454 epic_free_rings(sc);
1463 * EEPROM operation functions
1466 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
1470 CSR_WRITE_1(sc, EECTL, val);
1472 for (i=0; i<0xFF; i++)
1473 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1479 epic_read_eepromreg(epic_softc_t *sc)
1481 return CSR_READ_1(sc, EECTL);
1485 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
1487 epic_write_eepromreg(sc, val);
1488 epic_write_eepromreg(sc, (val | 0x4));
1489 epic_write_eepromreg(sc, val);
1491 return epic_read_eepromreg(sc);
1495 epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
1499 for (i = 0xF; i >= 0; i--) {
1501 epic_eeprom_clock(sc, 0x0B);
1503 epic_eeprom_clock(sc, 0x03);
1508 epic_input_eepromw(epic_softc_t *sc)
1510 u_int16_t retval = 0;
1513 for (i = 0xF; i >= 0; i--) {
1514 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1522 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
1527 epic_write_eepromreg(sc, 3);
1529 if (epic_read_eepromreg(sc) & 0x40)
1530 read_cmd = (loc & 0x3F) | 0x180;
1532 read_cmd = (loc & 0xFF) | 0x600;
1534 epic_output_eepromw(sc, read_cmd);
1536 dataval = epic_input_eepromw(sc);
1538 epic_write_eepromreg(sc, 1);
1544 * Here goes MII read/write routines
1547 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
1551 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1553 for (i = 0; i < 0x100; i++) {
1554 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1558 return (CSR_READ_4(sc, MIIDATA));
1562 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
1566 CSR_WRITE_4(sc, MIIDATA, val);
1567 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1569 for(i=0;i<0x100;i++) {
1570 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1578 epic_miibus_readreg(device_t dev, int phy, int reg)
1582 sc = device_get_softc(dev);
1584 return (PHY_READ_2(sc, phy, reg));
1588 epic_miibus_writereg(device_t dev, int phy, int reg, int data)
1592 sc = device_get_softc(dev);
1594 PHY_WRITE_2(sc, phy, reg, data);