sys/dev/netif/re/if_re.c

   1 /*
   2  * Copyright (c) 2004
   3  *      Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
   4  *
   5  * Copyright (c) 1997, 1998-2003
   6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Bill Paul.
  19  * 4. Neither the name of the author nor the names of any co-contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  33  * THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
  36  */
  37
  38 /*
  39  * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Networking Software Engineer
  43  * Wind River Systems
  44  */
  45
  46 /*
  47  * This driver is designed to support RealTek's next generation of
  48  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
  49  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
  50  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
  51  *
  52  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
  53  * with the older 8139 family, however it also supports a special
  54  * C+ mode of operation that provides several new performance enhancing
  55  * features. These include:
  56  *
  57  *      o Descriptor based DMA mechanism. Each descriptor represents
  58  *        a single packet fragment. Data buffers may be aligned on
  59  *        any byte boundary.
  60  *
  61  *      o 64-bit DMA
  62  *
  63  *      o TCP/IP checksum offload for both RX and TX
  64  *
  65  *      o High and normal priority transmit DMA rings
  66  *
  67  *      o VLAN tag insertion and extraction
  68  *
  69  *      o TCP large send (segmentation offload)
  70  *
  71  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
  72  * programming API is fairly straightforward. The RX filtering, EEPROM
  73  * access and PHY access is the same as it is on the older 8139 series
  74  * chips.
  75  *
  76  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
  77  * same programming API and feature set as the 8139C+ with the following
  78  * differences and additions:
  79  *
  80  *      o 1000Mbps mode
  81  *
  82  *      o Jumbo frames
  83  *
  84  *      o GMII and TBI ports/registers for interfacing with copper
  85  *        or fiber PHYs
  86  *
  87  *      o RX and TX DMA rings can have up to 1024 descriptors
  88  *        (the 8139C+ allows a maximum of 64)
  89  *
  90  *      o Slight differences in register layout from the 8139C+
  91  *
  92  * The TX start and timer interrupt registers are at different locations
  93  * on the 8169 than they are on the 8139C+. Also, the status word in the
  94  * RX descriptor has a slightly different bit layout. The 8169 does not
  95  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
  96  * copper gigE PHY.
  97  *
  98  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
  99  * (the 'S' stands for 'single-chip'). These devices have the same
 100  * programming API as the older 8169, but also have some vendor-specific
 101  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
 102  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
 103  *
 104  * This driver takes advantage of the RX and TX checksum offload and
 105  * VLAN tag insertion/extraction features. It also implements TX
 106  * interrupt moderation using the timer interrupt registers, which
 107  * significantly reduces TX interrupt load. There is also support
 108  * for jumbo frames, however the 8169/8169S/8110S can not transmit
 109  * jumbo frames larger than 7440, so the max MTU possible with this
 110  * driver is 7422 bytes.
 111  */
 112
 113 #define _IP_VHL
 114
 115 #include "opt_ifpoll.h"
 116
 117 #include <sys/param.h>
 118 #include <sys/bus.h>
 119 #include <sys/endian.h>
 120 #include <sys/kernel.h>
 121 #include <sys/in_cksum.h>
 122 #include <sys/interrupt.h>
 123 #include <sys/malloc.h>
 124 #include <sys/mbuf.h>
 125 #include <sys/rman.h>
 126 #include <sys/serialize.h>
 127 #include <sys/socket.h>
 128 #include <sys/sockio.h>
 129 #include <sys/sysctl.h>
 130
 131 #include <net/bpf.h>
 132 #include <net/ethernet.h>
 133 #include <net/if.h>
 134 #include <net/ifq_var.h>
 135 #include <net/if_arp.h>
 136 #include <net/if_dl.h>
 137 #include <net/if_media.h>
 138 #include <net/if_poll.h>
 139 #include <net/if_types.h>
 140 #include <net/vlan/if_vlan_var.h>
 141 #include <net/vlan/if_vlan_ether.h>
 142
 143 #include <netinet/ip.h>
 144
 145 #include <dev/netif/mii_layer/mii.h>
 146 #include <dev/netif/mii_layer/miivar.h>
 147
 148 #include <bus/pci/pcidevs.h>
 149 #include <bus/pci/pcireg.h>
 150 #include <bus/pci/pcivar.h>
 151
 152 /* "device miibus" required.  See GENERIC if you get errors here. */
 153 #include "miibus_if.h"
 154
 155 #include <dev/netif/re/if_rereg.h>
 156 #include <dev/netif/re/if_revar.h>
 157
 158 #define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
 159
 160 /*
 161  * Various supported device vendors/types and their names.
 162  */
 163 static const struct re_type {
 164         uint16_t        re_vid;
 165         uint16_t        re_did;
 166         const char      *re_name;
 167 } re_devs[] = {
 168         { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
 169           "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
 170
 171         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
 172           "RealTek 8139C+ 10/100BaseTX" },
 173
 174         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
 175           "RealTek 810x PCIe 10/100baseTX" },
 176
 177         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
 178           "RealTek 8111/8168 PCIe Gigabit Ethernet" },
 179
 180         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
 181           "RealTek 8110/8169 Gigabit Ethernet" },
 182
 183         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
 184           "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
 185
 186         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
 187           "Corega CG-LAPCIGT Gigabit Ethernet" },
 188
 189         { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
 190           "Linksys EG1032 Gigabit Ethernet" },
 191
 192         { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
 193           "US Robotics 997902 Gigabit Ethernet" },
 194
 195         { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322,
 196           "TTTech MC322 Gigabit Ethernet" },
 197
 198         { 0, 0, NULL }
 199 };
 200
 201 static const struct re_hwrev re_hwrevs[] = {
 202         { RE_HWREV_8139CPLUS,   RE_MACVER_UNKN,         ETHERMTU,
 203           RE_C_HWCSUM | RE_C_8139CP | RE_C_FASTE },
 204
 205         { RE_HWREV_8169,        RE_MACVER_UNKN,         ETHERMTU,
 206           RE_C_HWCSUM | RE_C_8169 },
 207
 208         { RE_HWREV_8110S,       RE_MACVER_03,           RE_MTU_6K,
 209           RE_C_HWCSUM | RE_C_8169 },
 210
 211         { RE_HWREV_8169S,       RE_MACVER_03,           RE_MTU_6K,
 212           RE_C_HWCSUM | RE_C_8169 },
 213
 214         { RE_HWREV_8169SB,      RE_MACVER_04,           RE_MTU_6K,
 215           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 216
 217         { RE_HWREV_8169SC1,     RE_MACVER_05,           RE_MTU_6K,
 218           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 219
 220         { RE_HWREV_8169SC2,     RE_MACVER_06,           RE_MTU_6K,
 221           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 222
 223         { RE_HWREV_8168B1,      RE_MACVER_21,           RE_MTU_6K,
 224           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
 225
 226         { RE_HWREV_8168B2,      RE_MACVER_23,           RE_MTU_6K,
 227           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
 228
 229         { RE_HWREV_8168B3,      RE_MACVER_23,           RE_MTU_6K,
 230           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
 231
 232         { RE_HWREV_8168C,       RE_MACVER_29,           RE_MTU_6K,
 233           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 234           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 235
 236         { RE_HWREV_8168CP,      RE_MACVER_2B,           RE_MTU_6K,
 237           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 238           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 239
 240         { RE_HWREV_8168D,       RE_MACVER_2A,           RE_MTU_9K,
 241           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 242           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 243
 244         { RE_HWREV_8168DP,      RE_MACVER_2D,           RE_MTU_9K,
 245           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 246           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 247
 248         { RE_HWREV_8168E,       RE_MACVER_UNKN,         RE_MTU_9K,
 249           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 250           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 251
 252         { RE_HWREV_8168F,       RE_MACVER_UNKN,         RE_MTU_9K,
 253           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 254           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 255
 256         { RE_HWREV_8111F,       RE_MACVER_UNKN,         RE_MTU_9K,
 257           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 258           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 259
 260         { RE_HWREV_8100E,       RE_MACVER_UNKN,         ETHERMTU,
 261           RE_C_HWCSUM | RE_C_FASTE },
 262
 263         { RE_HWREV_8101E1,      RE_MACVER_16,           ETHERMTU,
 264           RE_C_HWCSUM | RE_C_FASTE },
 265
 266         { RE_HWREV_8101E2,      RE_MACVER_16,           ETHERMTU,
 267           RE_C_HWCSUM | RE_C_FASTE },
 268
 269         { RE_HWREV_8102E,       RE_MACVER_15,           ETHERMTU,
 270           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
 271           RE_C_FASTE },
 272
 273         { RE_HWREV_8102EL,      RE_MACVER_15,           ETHERMTU,
 274           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX |
 275           RE_C_FASTE },
 276
 277         { RE_HWREV_8105E,       RE_MACVER_UNKN,         ETHERMTU,
 278           RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT | RE_C_AUTOPAD |
 279           RE_C_STOP_RXTX | RE_C_FASTE },
 280
 281         { RE_HWREV_NULL, 0, 0, 0 }
 282 };
 283
 284 static int      re_probe(device_t);
 285 static int      re_attach(device_t);
 286 static int      re_detach(device_t);
 287 static int      re_suspend(device_t);
 288 static int      re_resume(device_t);
 289 static void     re_shutdown(device_t);
 290
 291 static int      re_allocmem(device_t);
 292 static void     re_freemem(device_t);
 293 static void     re_freebufmem(struct re_softc *, int, int);
 294 static int      re_encap(struct re_softc *, struct mbuf **, int *);
 295 static int      re_newbuf_std(struct re_softc *, int, int);
 296 static int      re_newbuf_jumbo(struct re_softc *, int, int);
 297 static void     re_setup_rxdesc(struct re_softc *, int);
 298 static int      re_rx_list_init(struct re_softc *);
 299 static int      re_tx_list_init(struct re_softc *);
 300 static int      re_rxeof(struct re_softc *);
 301 static int      re_txeof(struct re_softc *);
 302 static int      re_tx_collect(struct re_softc *);
 303 static void     re_intr(void *);
 304 static void     re_tick(void *);
 305 static void     re_tick_serialized(void *);
 306
 307 static void     re_start(struct ifnet *);
 308 static int      re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 309 static void     re_init(void *);
 310 static void     re_stop(struct re_softc *);
 311 static void     re_watchdog(struct ifnet *);
 312 static int      re_ifmedia_upd(struct ifnet *);
 313 static void     re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 314
 315 static void     re_eeprom_putbyte(struct re_softc *, int);
 316 static void     re_eeprom_getword(struct re_softc *, int, u_int16_t *);
 317 static void     re_read_eeprom(struct re_softc *, caddr_t, int, int);
 318 static void     re_get_eewidth(struct re_softc *);
 319
 320 static int      re_gmii_readreg(device_t, int, int);
 321 static int      re_gmii_writereg(device_t, int, int, int);
 322
 323 static int      re_miibus_readreg(device_t, int, int);
 324 static int      re_miibus_writereg(device_t, int, int, int);
 325 static void     re_miibus_statchg(device_t);
 326
 327 static void     re_setmulti(struct re_softc *);
 328 static void     re_reset(struct re_softc *, int);
 329 static void     re_get_eaddr(struct re_softc *, uint8_t *);
 330
 331 static void     re_setup_hw_im(struct re_softc *);
 332 static void     re_setup_sim_im(struct re_softc *);
 333 static void     re_disable_hw_im(struct re_softc *);
 334 static void     re_disable_sim_im(struct re_softc *);
 335 static void     re_config_imtype(struct re_softc *, int);
 336 static void     re_setup_intr(struct re_softc *, int, int);
 337
 338 static int      re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
 339 static int      re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
 340 static int      re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
 341 static int      re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
 342 static int      re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
 343
 344 static int      re_jpool_alloc(struct re_softc *);
 345 static void     re_jpool_free(struct re_softc *);
 346 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
 347 static void     re_jbuf_free(void *);
 348 static void     re_jbuf_ref(void *);
 349
 350 #ifdef RE_DIAG
 351 static int      re_diag(struct re_softc *);
 352 #endif
 353
 354 #ifdef IFPOLL_ENABLE
 355 static void     re_npoll(struct ifnet *, struct ifpoll_info *);
 356 static void     re_npoll_compat(struct ifnet *, void *, int);
 357 #endif
 358
 359 static device_method_t re_methods[] = {
 360         /* Device interface */
 361         DEVMETHOD(device_probe,         re_probe),
 362         DEVMETHOD(device_attach,        re_attach),
 363         DEVMETHOD(device_detach,        re_detach),
 364         DEVMETHOD(device_suspend,       re_suspend),
 365         DEVMETHOD(device_resume,        re_resume),
 366         DEVMETHOD(device_shutdown,      re_shutdown),
 367
 368         /* bus interface */
 369         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 370         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 371
 372         /* MII interface */
 373         DEVMETHOD(miibus_readreg,       re_miibus_readreg),
 374         DEVMETHOD(miibus_writereg,      re_miibus_writereg),
 375         DEVMETHOD(miibus_statchg,       re_miibus_statchg),
 376
 377         { 0, 0 }
 378 };
 379
 380 static driver_t re_driver = {
 381         "re",
 382         re_methods,
 383         sizeof(struct re_softc)
 384 };
 385
 386 static devclass_t re_devclass;
 387
 388 DECLARE_DUMMY_MODULE(if_re);
 389 MODULE_DEPEND(if_re, miibus, 1, 1, 1);
 390 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, NULL, NULL);
 391 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, NULL, NULL);
 392 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, NULL, NULL);
 393
 394 static int      re_rx_desc_count = RE_RX_DESC_CNT_DEF;
 395 static int      re_tx_desc_count = RE_TX_DESC_CNT_DEF;
 396 static int      re_msi_enable = 0;
 397
 398 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
 399 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
 400 TUNABLE_INT("hw.re.msi.enable", &re_msi_enable);
 401
 402 #define EE_SET(x)       \
 403         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
 404
 405 #define EE_CLR(x)       \
 406         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
 407
 408 static __inline void
 409 re_free_rxchain(struct re_softc *sc)
 410 {
 411         if (sc->re_head != NULL) {
 412                 m_freem(sc->re_head);
 413                 sc->re_head = sc->re_tail = NULL;
 414         }
 415 }
 416
 417 /*
 418  * Send a read command and address to the EEPROM, check for ACK.
 419  */
 420 static void
 421 re_eeprom_putbyte(struct re_softc *sc, int addr)
 422 {
 423         int d, i;
 424
 425         d = addr | (RE_9346_READ << sc->re_eewidth);
 426
 427         /*
 428          * Feed in each bit and strobe the clock.
 429          */
 430         for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
 431                 if (d & i)
 432                         EE_SET(RE_EE_DATAIN);
 433                 else
 434                         EE_CLR(RE_EE_DATAIN);
 435                 DELAY(100);
 436                 EE_SET(RE_EE_CLK);
 437                 DELAY(150);
 438                 EE_CLR(RE_EE_CLK);
 439                 DELAY(100);
 440         }
 441 }
 442
 443 /*
 444  * Read a word of data stored in the EEPROM at address 'addr.'
 445  */
 446 static void
 447 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
 448 {
 449         int i;
 450         uint16_t word = 0;
 451
 452         /*
 453          * Send address of word we want to read.
 454          */
 455         re_eeprom_putbyte(sc, addr);
 456
 457         /*
 458          * Start reading bits from EEPROM.
 459          */
 460         for (i = 0x8000; i != 0; i >>= 1) {
 461                 EE_SET(RE_EE_CLK);
 462                 DELAY(100);
 463                 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
 464                         word |= i;
 465                 EE_CLR(RE_EE_CLK);
 466                 DELAY(100);
 467         }
 468
 469         *dest = word;
 470 }
 471
 472 /*
 473  * Read a sequence of words from the EEPROM.
 474  */
 475 static void
 476 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
 477 {
 478         int i;
 479         uint16_t word = 0, *ptr;
 480
 481         CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
 482         DELAY(100);
 483
 484         for (i = 0; i < cnt; i++) {
 485                 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
 486                 re_eeprom_getword(sc, off + i, &word);
 487                 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
 488                 ptr = (uint16_t *)(dest + (i * 2));
 489                 *ptr = word;
 490         }
 491
 492         CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
 493 }
 494
 495 static void
 496 re_get_eewidth(struct re_softc *sc)
 497 {
 498         uint16_t re_did = 0;
 499
 500         sc->re_eewidth = 6;
 501         re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
 502         if (re_did != 0x8129)
 503                 sc->re_eewidth = 8;
 504 }
 505
 506 static int
 507 re_gmii_readreg(device_t dev, int phy, int reg)
 508 {
 509         struct re_softc *sc = device_get_softc(dev);
 510         u_int32_t rval;
 511         int i;
 512
 513         if (phy != 1)
 514                 return(0);
 515
 516         /* Let the rgephy driver read the GMEDIASTAT register */
 517
 518         if (reg == RE_GMEDIASTAT)
 519                 return(CSR_READ_1(sc, RE_GMEDIASTAT));
 520
 521         CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
 522         DELAY(1000);
 523
 524         for (i = 0; i < RE_TIMEOUT; i++) {
 525                 rval = CSR_READ_4(sc, RE_PHYAR);
 526                 if (rval & RE_PHYAR_BUSY)
 527                         break;
 528                 DELAY(100);
 529         }
 530
 531         if (i == RE_TIMEOUT) {
 532                 device_printf(dev, "PHY read failed\n");
 533                 return(0);
 534         }
 535
 536         return(rval & RE_PHYAR_PHYDATA);
 537 }
 538
 539 static int
 540 re_gmii_writereg(device_t dev, int phy, int reg, int data)
 541 {
 542         struct re_softc *sc = device_get_softc(dev);
 543         uint32_t rval;
 544         int i;
 545
 546         CSR_WRITE_4(sc, RE_PHYAR,
 547                     (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
 548         DELAY(1000);
 549
 550         for (i = 0; i < RE_TIMEOUT; i++) {
 551                 rval = CSR_READ_4(sc, RE_PHYAR);
 552                 if ((rval & RE_PHYAR_BUSY) == 0)
 553                         break;
 554                 DELAY(100);
 555         }
 556
 557         if (i == RE_TIMEOUT)
 558                 device_printf(dev, "PHY write failed\n");
 559
 560         return(0);
 561 }
 562
 563 static int
 564 re_miibus_readreg(device_t dev, int phy, int reg)
 565 {
 566         struct re_softc *sc = device_get_softc(dev);
 567         uint16_t rval = 0;
 568         uint16_t re8139_reg = 0;
 569
 570         if (!RE_IS_8139CP(sc)) {
 571                 rval = re_gmii_readreg(dev, phy, reg);
 572                 return(rval);
 573         }
 574
 575         /* Pretend the internal PHY is only at address 0 */
 576         if (phy)
 577                 return(0);
 578
 579         switch(reg) {
 580         case MII_BMCR:
 581                 re8139_reg = RE_BMCR;
 582                 break;
 583         case MII_BMSR:
 584                 re8139_reg = RE_BMSR;
 585                 break;
 586         case MII_ANAR:
 587                 re8139_reg = RE_ANAR;
 588                 break;
 589         case MII_ANER:
 590                 re8139_reg = RE_ANER;
 591                 break;
 592         case MII_ANLPAR:
 593                 re8139_reg = RE_LPAR;
 594                 break;
 595         case MII_PHYIDR1:
 596         case MII_PHYIDR2:
 597                 return(0);
 598         /*
 599          * Allow the rlphy driver to read the media status
 600          * register. If we have a link partner which does not
 601          * support NWAY, this is the register which will tell
 602          * us the results of parallel detection.
 603          */
 604         case RE_MEDIASTAT:
 605                 return(CSR_READ_1(sc, RE_MEDIASTAT));
 606         default:
 607                 device_printf(dev, "bad phy register\n");
 608                 return(0);
 609         }
 610         rval = CSR_READ_2(sc, re8139_reg);
 611         if (re8139_reg == RE_BMCR) {
 612                 /* 8139C+ has different bit layout. */
 613                 rval &= ~(BMCR_LOOP | BMCR_ISO);
 614         }
 615         return(rval);
 616 }
 617
 618 static int
 619 re_miibus_writereg(device_t dev, int phy, int reg, int data)
 620 {
 621         struct re_softc *sc= device_get_softc(dev);
 622         u_int16_t re8139_reg = 0;
 623
 624         if (!RE_IS_8139CP(sc))
 625                 return(re_gmii_writereg(dev, phy, reg, data));
 626
 627         /* Pretend the internal PHY is only at address 0 */
 628         if (phy)
 629                 return(0);
 630
 631         switch(reg) {
 632         case MII_BMCR:
 633                 re8139_reg = RE_BMCR;
 634                 /* 8139C+ has different bit layout. */
 635                 data &= ~(BMCR_LOOP | BMCR_ISO);
 636                 break;
 637         case MII_BMSR:
 638                 re8139_reg = RE_BMSR;
 639                 break;
 640         case MII_ANAR:
 641                 re8139_reg = RE_ANAR;
 642                 break;
 643         case MII_ANER:
 644                 re8139_reg = RE_ANER;
 645                 break;
 646         case MII_ANLPAR:
 647                 re8139_reg = RE_LPAR;
 648                 break;
 649         case MII_PHYIDR1:
 650         case MII_PHYIDR2:
 651                 return(0);
 652         default:
 653                 device_printf(dev, "bad phy register\n");
 654                 return(0);
 655         }
 656         CSR_WRITE_2(sc, re8139_reg, data);
 657         return(0);
 658 }
 659
 660 static void
 661 re_miibus_statchg(device_t dev)
 662 {
 663 }
 664
 665 /*
 666  * Program the 64-bit multicast hash filter.
 667  */
 668 static void
 669 re_setmulti(struct re_softc *sc)
 670 {
 671         struct ifnet *ifp = &sc->arpcom.ac_if;
 672         int h = 0;
 673         uint32_t hashes[2] = { 0, 0 };
 674         struct ifmultiaddr *ifma;
 675         uint32_t rxfilt;
 676         int mcnt = 0;
 677
 678         rxfilt = CSR_READ_4(sc, RE_RXCFG);
 679
 680         /* Set the individual bit to receive frames for this host only. */
 681         rxfilt |= RE_RXCFG_RX_INDIV;
 682         /* Set capture broadcast bit to capture broadcast frames. */
 683         rxfilt |= RE_RXCFG_RX_BROAD;
 684
 685         rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
 686         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
 687                 rxfilt |= RE_RXCFG_RX_MULTI;
 688
 689                 /* If we want promiscuous mode, set the allframes bit. */
 690                 if (ifp->if_flags & IFF_PROMISC)
 691                         rxfilt |= RE_RXCFG_RX_ALLPHYS;
 692
 693                 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
 694                 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
 695                 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
 696                 return;
 697         }
 698
 699         /* first, zot all the existing hash bits */
 700         CSR_WRITE_4(sc, RE_MAR0, 0);
 701         CSR_WRITE_4(sc, RE_MAR4, 0);
 702
 703         /* now program new ones */
 704         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 705                 if (ifma->ifma_addr->sa_family != AF_LINK)
 706                         continue;
 707                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 708                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 709                 if (h < 32)
 710                         hashes[0] |= (1 << h);
 711                 else
 712                         hashes[1] |= (1 << (h - 32));
 713                 mcnt++;
 714         }
 715
 716         if (mcnt)
 717                 rxfilt |= RE_RXCFG_RX_MULTI;
 718         else
 719                 rxfilt &= ~RE_RXCFG_RX_MULTI;
 720
 721         CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
 722
 723         /*
 724          * For some unfathomable reason, RealTek decided to reverse
 725          * the order of the multicast hash registers in the PCI Express
 726          * parts. This means we have to write the hash pattern in reverse
 727          * order for those devices.
 728          */
 729         if (sc->re_caps & RE_C_PCIE) {
 730                 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[1]));
 731                 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[0]));
 732         } else {
 733                 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
 734                 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
 735         }
 736 }
 737
 738 static void
 739 re_reset(struct re_softc *sc, int running)
 740 {
 741         int i;
 742
 743         if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
 744                 CSR_WRITE_1(sc, RE_COMMAND,
 745                             RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
 746                 DELAY(100);
 747         }
 748
 749         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
 750
 751         for (i = 0; i < RE_TIMEOUT; i++) {
 752                 DELAY(10);
 753                 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
 754                         break;
 755         }
 756         if (i == RE_TIMEOUT)
 757                 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
 758 }
 759
 760 #ifdef RE_DIAG
 761 /*
 762  * The following routine is designed to test for a defect on some
 763  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
 764  * lines connected to the bus, however for a 32-bit only card, they
 765  * should be pulled high. The result of this defect is that the
 766  * NIC will not work right if you plug it into a 64-bit slot: DMA
 767  * operations will be done with 64-bit transfers, which will fail
 768  * because the 64-bit data lines aren't connected.
 769  *
 770  * There's no way to work around this (short of talking a soldering
 771  * iron to the board), however we can detect it. The method we use
 772  * here is to put the NIC into digital loopback mode, set the receiver
 773  * to promiscuous mode, and then try to send a frame. We then compare
 774  * the frame data we sent to what was received. If the data matches,
 775  * then the NIC is working correctly, otherwise we know the user has
 776  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
 777  * slot. In the latter case, there's no way the NIC can work correctly,
 778  * so we print out a message on the console and abort the device attach.
 779  */
 780
 781 static int
 782 re_diag(struct re_softc *sc)
 783 {
 784         struct ifnet *ifp = &sc->arpcom.ac_if;
 785         struct mbuf *m0;
 786         struct ether_header *eh;
 787         struct re_desc *cur_rx;
 788         uint16_t status;
 789         uint32_t rxstat;
 790         int total_len, i, error = 0, phyaddr;
 791         uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
 792         uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
 793
 794         /* Allocate a single mbuf */
 795
 796         MGETHDR(m0, MB_DONTWAIT, MT_DATA);
 797         if (m0 == NULL)
 798                 return(ENOBUFS);
 799
 800         /*
 801          * Initialize the NIC in test mode. This sets the chip up
 802          * so that it can send and receive frames, but performs the
 803          * following special functions:
 804          * - Puts receiver in promiscuous mode
 805          * - Enables digital loopback mode
 806          * - Leaves interrupts turned off
 807          */
 808
 809         ifp->if_flags |= IFF_PROMISC;
 810         sc->re_flags |= RE_F_TESTMODE;
 811         re_init(sc);
 812         sc->re_flags |= RE_F_LINKED;
 813         if (!RE_IS_8139CP(sc))
 814                 phyaddr = 1;
 815         else
 816                 phyaddr = 0;
 817
 818         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
 819         for (i = 0; i < RE_TIMEOUT; i++) {
 820                 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
 821                 if (!(status & BMCR_RESET))
 822                         break;
 823         }
 824
 825         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
 826         CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
 827
 828         DELAY(100000);
 829
 830         /* Put some data in the mbuf */
 831
 832         eh = mtod(m0, struct ether_header *);
 833         bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
 834         bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
 835         eh->ether_type = htons(ETHERTYPE_IP);
 836         m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
 837
 838         /*
 839          * Queue the packet, start transmission.
 840          * Note: ifq_handoff() ultimately calls re_start() for us.
 841          */
 842
 843         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
 844         error = ifq_handoff(ifp, m0, NULL);
 845         if (error) {
 846                 m0 = NULL;
 847                 goto done;
 848         }
 849         m0 = NULL;
 850
 851         /* Wait for it to propagate through the chip */
 852
 853         DELAY(100000);
 854         for (i = 0; i < RE_TIMEOUT; i++) {
 855                 status = CSR_READ_2(sc, RE_ISR);
 856                 CSR_WRITE_2(sc, RE_ISR, status);
 857                 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
 858                     (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
 859                         break;
 860                 DELAY(10);
 861         }
 862
 863         if (i == RE_TIMEOUT) {
 864                 if_printf(ifp, "diagnostic failed to receive packet "
 865                           "in loopback mode\n");
 866                 error = EIO;
 867                 goto done;
 868         }
 869
 870         /*
 871          * The packet should have been dumped into the first
 872          * entry in the RX DMA ring. Grab it from there.
 873          */
 874
 875         bus_dmamap_sync(sc->re_ldata.re_rx_mtag, sc->re_ldata.re_rx_dmamap[0],
 876                         BUS_DMASYNC_POSTREAD);
 877         bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
 878                           sc->re_ldata.re_rx_dmamap[0]);
 879
 880         m0 = sc->re_ldata.re_rx_mbuf[0];
 881         sc->re_ldata.re_rx_mbuf[0] = NULL;
 882         eh = mtod(m0, struct ether_header *);
 883
 884         cur_rx = &sc->re_ldata.re_rx_list[0];
 885         total_len = RE_RXBYTES(cur_rx);
 886         rxstat = le32toh(cur_rx->re_cmdstat);
 887
 888         if (total_len != ETHER_MIN_LEN) {
 889                 if_printf(ifp, "diagnostic failed, received short packet\n");
 890                 error = EIO;
 891                 goto done;
 892         }
 893
 894         /* Test that the received packet data matches what we sent. */
 895
 896         if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
 897             bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
 898             be16toh(eh->ether_type) != ETHERTYPE_IP) {
 899                 if_printf(ifp, "WARNING, DMA FAILURE!\n");
 900                 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
 901                     dst, ":", src, ":", ETHERTYPE_IP);
 902                 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
 903                     eh->ether_dhost, ":",  eh->ether_shost, ":",
 904                     ntohs(eh->ether_type));
 905                 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
 906                     "into a 64-bit PCI slot.\n");
 907                 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
 908                     "for proper operation.\n");
 909                 if_printf(ifp, "Read the re(4) man page for more details.\n");
 910                 error = EIO;
 911         }
 912
 913 done:
 914         /* Turn interface off, release resources */
 915
 916         sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
 917         ifp->if_flags &= ~IFF_PROMISC;
 918         re_stop(sc);
 919         if (m0 != NULL)
 920                 m_freem(m0);
 921
 922         return (error);
 923 }
 924 #endif  /* RE_DIAG */
 925
 926 /*
 927  * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
 928  * IDs against our list and return a device name if we find a match.
 929  */
 930 static int
 931 re_probe(device_t dev)
 932 {
 933         const struct re_type *t;
 934         const struct re_hwrev *hw_rev;
 935         struct re_softc *sc;
 936         int rid;
 937         uint32_t hwrev, macmode, txcfg;
 938         uint16_t vendor, product;
 939
 940         vendor = pci_get_vendor(dev);
 941         product = pci_get_device(dev);
 942
 943         /*
 944          * Only attach to rev.3 of the Linksys EG1032 adapter.
 945          * Rev.2 is supported by sk(4).
 946          */
 947         if (vendor == PCI_VENDOR_LINKSYS &&
 948             product == PCI_PRODUCT_LINKSYS_EG1032 &&
 949             pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
 950                 return ENXIO;
 951
 952         if (vendor == PCI_VENDOR_REALTEK &&
 953             product == PCI_PRODUCT_REALTEK_RT8139 &&
 954             pci_get_revid(dev) != PCI_REVID_REALTEK_RT8139CP) {
 955                 /* Poor 8139 */
 956                 return ENXIO;
 957         }
 958
 959         for (t = re_devs; t->re_name != NULL; t++) {
 960                 if (product == t->re_did && vendor == t->re_vid)
 961                         break;
 962         }
 963
 964         /*
 965          * Check if we found a RealTek device.
 966          */
 967         if (t->re_name == NULL)
 968                 return ENXIO;
 969
 970         /*
 971          * Temporarily map the I/O space so we can read the chip ID register.
 972          */
 973         sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
 974         rid = RE_PCI_LOIO;
 975         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
 976                                             RF_ACTIVE);
 977         if (sc->re_res == NULL) {
 978                 device_printf(dev, "couldn't map ports/memory\n");
 979                 kfree(sc, M_TEMP);
 980                 return ENXIO;
 981         }
 982
 983         sc->re_btag = rman_get_bustag(sc->re_res);
 984         sc->re_bhandle = rman_get_bushandle(sc->re_res);
 985
 986         txcfg = CSR_READ_4(sc, RE_TXCFG);
 987         hwrev = txcfg & RE_TXCFG_HWREV;
 988         macmode = txcfg & RE_TXCFG_MACMODE;
 989         bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
 990         kfree(sc, M_TEMP);
 991
 992         /*
 993          * and continue matching for the specific chip...
 994          */
 995         for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
 996                 if (hw_rev->re_hwrev == hwrev) {
 997                         sc = device_get_softc(dev);
 998
 999                         sc->re_hwrev = hw_rev->re_hwrev;
1000                         sc->re_macver = hw_rev->re_macver;
1001                         sc->re_caps = hw_rev->re_caps;
1002                         sc->re_maxmtu = hw_rev->re_maxmtu;
1003
1004                         /*
1005                          * Apply chip property fixup
1006                          */
1007                         switch (sc->re_hwrev) {
1008                         case RE_HWREV_8101E1:
1009                         case RE_HWREV_8101E2:
1010                                 if (macmode == 0)
1011                                         sc->re_macver = RE_MACVER_11;
1012                                 else if (macmode == 0x200000)
1013                                         sc->re_macver = RE_MACVER_12;
1014                                 break;
1015                         case RE_HWREV_8102E:
1016                         case RE_HWREV_8102EL:
1017                                 if (macmode == 0)
1018                                         sc->re_macver = RE_MACVER_13;
1019                                 else if (macmode == 0x100000)
1020                                         sc->re_macver = RE_MACVER_14;
1021                                 break;
1022                         case RE_HWREV_8168B2:
1023                         case RE_HWREV_8168B3:
1024                                 if (macmode == 0)
1025                                         sc->re_macver = RE_MACVER_22;
1026                                 break;
1027                         case RE_HWREV_8168C:
1028                                 if (macmode == 0)
1029                                         sc->re_macver = RE_MACVER_24;
1030                                 else if (macmode == 0x200000)
1031                                         sc->re_macver = RE_MACVER_25;
1032                                 else if (macmode == 0x300000)
1033                                         sc->re_macver = RE_MACVER_27;
1034                                 break;
1035                         case RE_HWREV_8168CP:
1036                                 if (macmode == 0)
1037                                         sc->re_macver = RE_MACVER_26;
1038                                 else if (macmode == 0x100000)
1039                                         sc->re_macver = RE_MACVER_28;
1040                                 break;
1041                         case RE_HWREV_8168DP:
1042                                 if (macmode == 0)
1043                                         sc->re_macver = RE_MACVER_2B;
1044                                 else if (macmode == 0x200000)
1045                                         sc->re_macver = RE_MACVER_2C;
1046                                 break;
1047                         case RE_HWREV_8168E:
1048                                 if (macmode == 0x100000)
1049                                         sc->re_macver = RE_MACVER_2E;
1050                                 else if (macmode == 0x200000)
1051                                         sc->re_macver = RE_MACVER_2F;
1052                                 break;
1053                         case RE_HWREV_8168F:
1054                         case RE_HWREV_8111F:
1055                                 if (macmode == 0x000000)
1056                                         sc->re_macver = RE_MACVER_30;
1057                                 else if (macmode == 0x100000)
1058                                         sc->re_macver = RE_MACVER_31;
1059                                 break;
1060                         }
1061                         if (pci_is_pcie(dev))
1062                                 sc->re_caps |= RE_C_PCIE;
1063
1064                         device_set_desc(dev, t->re_name);
1065                         return 0;
1066                 }
1067         }
1068
1069         if (bootverbose) {
1070                 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1071                               hwrev, macmode);
1072         }
1073         return ENXIO;
1074 }
1075
1076 static int
1077 re_allocmem(device_t dev)
1078 {
1079         struct re_softc *sc = device_get_softc(dev);
1080         bus_dmamem_t dmem;
1081         int error, i;
1082
1083         /*
1084          * Allocate list data
1085          */
1086         sc->re_ldata.re_tx_mbuf =
1087         kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1088                 M_DEVBUF, M_ZERO | M_WAITOK);
1089
1090         sc->re_ldata.re_rx_mbuf =
1091         kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1092                 M_DEVBUF, M_ZERO | M_WAITOK);
1093
1094         sc->re_ldata.re_rx_paddr =
1095         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1096                 M_DEVBUF, M_ZERO | M_WAITOK);
1097
1098         sc->re_ldata.re_tx_dmamap =
1099         kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1100                 M_DEVBUF, M_ZERO | M_WAITOK);
1101
1102         sc->re_ldata.re_rx_dmamap =
1103         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1104                 M_DEVBUF, M_ZERO | M_WAITOK);
1105
1106         /*
1107          * Allocate the parent bus DMA tag appropriate for PCI.
1108          */
1109         error = bus_dma_tag_create(NULL,        /* parent */
1110                         1, 0,                   /* alignment, boundary */
1111                         BUS_SPACE_MAXADDR,      /* lowaddr */
1112                         BUS_SPACE_MAXADDR,      /* highaddr */
1113                         NULL, NULL,             /* filter, filterarg */
1114                         BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
1115                         0,                      /* nsegments */
1116                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1117                         0,                      /* flags */
1118                         &sc->re_parent_tag);
1119         if (error) {
1120                 device_printf(dev, "could not allocate parent dma tag\n");
1121                 return error;
1122         }
1123
1124         /* Allocate TX descriptor list. */
1125         error = bus_dmamem_coherent(sc->re_parent_tag,
1126                         RE_RING_ALIGN, 0,
1127                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1128                         RE_TX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1129                         &dmem);
1130         if (error) {
1131                 device_printf(dev, "could not allocate TX ring\n");
1132                 return error;
1133         }
1134         sc->re_ldata.re_tx_list_tag = dmem.dmem_tag;
1135         sc->re_ldata.re_tx_list_map = dmem.dmem_map;
1136         sc->re_ldata.re_tx_list = dmem.dmem_addr;
1137         sc->re_ldata.re_tx_list_addr = dmem.dmem_busaddr;
1138
1139         /* Allocate RX descriptor list. */
1140         error = bus_dmamem_coherent(sc->re_parent_tag,
1141                         RE_RING_ALIGN, 0,
1142                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1143                         RE_RX_LIST_SZ(sc), BUS_DMA_WAITOK | BUS_DMA_ZERO,
1144                         &dmem);
1145         if (error) {
1146                 device_printf(dev, "could not allocate RX ring\n");
1147                 return error;
1148         }
1149         sc->re_ldata.re_rx_list_tag = dmem.dmem_tag;
1150         sc->re_ldata.re_rx_list_map = dmem.dmem_map;
1151         sc->re_ldata.re_rx_list = dmem.dmem_addr;
1152         sc->re_ldata.re_rx_list_addr = dmem.dmem_busaddr;
1153
1154         /* Allocate maps for TX mbufs. */
1155         error = bus_dma_tag_create(sc->re_parent_tag,
1156                         1, 0,
1157                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1158                         NULL, NULL,
1159                         RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1160                         BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1161                         &sc->re_ldata.re_tx_mtag);
1162         if (error) {
1163                 device_printf(dev, "could not allocate TX buf dma tag\n");
1164                 return(error);
1165         }
1166
1167         /* Create DMA maps for TX buffers */
1168         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1169                 error = bus_dmamap_create(sc->re_ldata.re_tx_mtag,
1170                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1171                                 &sc->re_ldata.re_tx_dmamap[i]);
1172                 if (error) {
1173                         device_printf(dev, "can't create DMA map for TX buf\n");
1174                         re_freebufmem(sc, i, 0);
1175                         return(error);
1176                 }
1177         }
1178
1179         /* Allocate maps for RX mbufs. */
1180         error = bus_dma_tag_create(sc->re_parent_tag,
1181                         RE_RXBUF_ALIGN, 0,
1182                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1183                         NULL, NULL,
1184                         MCLBYTES, 1, MCLBYTES,
1185                         BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,
1186                         &sc->re_ldata.re_rx_mtag);
1187         if (error) {
1188                 device_printf(dev, "could not allocate RX buf dma tag\n");
1189                 return(error);
1190         }
1191
1192         /* Create spare DMA map for RX */
1193         error = bus_dmamap_create(sc->re_ldata.re_rx_mtag, BUS_DMA_WAITOK,
1194                         &sc->re_ldata.re_rx_spare);
1195         if (error) {
1196                 device_printf(dev, "can't create spare DMA map for RX\n");
1197                 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1198                 sc->re_ldata.re_rx_mtag = NULL;
1199                 return error;
1200         }
1201
1202         /* Create DMA maps for RX buffers */
1203         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1204                 error = bus_dmamap_create(sc->re_ldata.re_rx_mtag,
1205                                 BUS_DMA_WAITOK, &sc->re_ldata.re_rx_dmamap[i]);
1206                 if (error) {
1207                         device_printf(dev, "can't create DMA map for RX buf\n");
1208                         re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1209                         return(error);
1210                 }
1211         }
1212
1213         /* Create jumbo buffer pool for RX if required */
1214         if (sc->re_caps & RE_C_CONTIGRX) {
1215                 error = re_jpool_alloc(sc);
1216                 if (error) {
1217                         re_jpool_free(sc);
1218                         /* Disable jumbo frame support */
1219                         sc->re_maxmtu = ETHERMTU;
1220                 }
1221         }
1222         return(0);
1223 }
1224
1225 static void
1226 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1227 {
1228         int i;
1229
1230         /* Destroy all the RX and TX buffer maps */
1231         if (sc->re_ldata.re_tx_mtag) {
1232                 for (i = 0; i < tx_cnt; i++) {
1233                         bus_dmamap_destroy(sc->re_ldata.re_tx_mtag,
1234                                            sc->re_ldata.re_tx_dmamap[i]);
1235                 }
1236                 bus_dma_tag_destroy(sc->re_ldata.re_tx_mtag);
1237                 sc->re_ldata.re_tx_mtag = NULL;
1238         }
1239
1240         if (sc->re_ldata.re_rx_mtag) {
1241                 for (i = 0; i < rx_cnt; i++) {
1242                         bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1243                                            sc->re_ldata.re_rx_dmamap[i]);
1244                 }
1245                 bus_dmamap_destroy(sc->re_ldata.re_rx_mtag,
1246                                    sc->re_ldata.re_rx_spare);
1247                 bus_dma_tag_destroy(sc->re_ldata.re_rx_mtag);
1248                 sc->re_ldata.re_rx_mtag = NULL;
1249         }
1250 }
1251
1252 static void
1253 re_freemem(device_t dev)
1254 {
1255         struct re_softc *sc = device_get_softc(dev);
1256
1257         /* Unload and free the RX DMA ring memory and map */
1258         if (sc->re_ldata.re_rx_list_tag) {
1259                 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1260                                   sc->re_ldata.re_rx_list_map);
1261                 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1262                                 sc->re_ldata.re_rx_list,
1263                                 sc->re_ldata.re_rx_list_map);
1264                 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1265         }
1266
1267         /* Unload and free the TX DMA ring memory and map */
1268         if (sc->re_ldata.re_tx_list_tag) {
1269                 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1270                                   sc->re_ldata.re_tx_list_map);
1271                 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1272                                 sc->re_ldata.re_tx_list,
1273                                 sc->re_ldata.re_tx_list_map);
1274                 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1275         }
1276
1277         /* Free RX/TX buf DMA stuffs */
1278         re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1279
1280         /* Unload and free the stats buffer and map */
1281         if (sc->re_ldata.re_stag) {
1282                 bus_dmamap_unload(sc->re_ldata.re_stag, sc->re_ldata.re_smap);
1283                 bus_dmamem_free(sc->re_ldata.re_stag,
1284                                 sc->re_ldata.re_stats,
1285                                 sc->re_ldata.re_smap);
1286                 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1287         }
1288
1289         if (sc->re_caps & RE_C_CONTIGRX)
1290                 re_jpool_free(sc);
1291
1292         if (sc->re_parent_tag)
1293                 bus_dma_tag_destroy(sc->re_parent_tag);
1294
1295         if (sc->re_ldata.re_tx_mbuf != NULL)
1296                 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1297         if (sc->re_ldata.re_rx_mbuf != NULL)
1298                 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1299         if (sc->re_ldata.re_rx_paddr != NULL)
1300                 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1301         if (sc->re_ldata.re_tx_dmamap != NULL)
1302                 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1303         if (sc->re_ldata.re_rx_dmamap != NULL)
1304                 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1305 }
1306
1307 /*
1308  * Attach the interface. Allocate softc structures, do ifmedia
1309  * setup and ethernet/BPF attach.
1310  */
1311 static int
1312 re_attach(device_t dev)
1313 {
1314         struct re_softc *sc = device_get_softc(dev);
1315         struct ifnet *ifp;
1316         uint8_t eaddr[ETHER_ADDR_LEN];
1317         int error = 0, rid, qlen;
1318         u_int irq_flags;
1319
1320         callout_init(&sc->re_timer);
1321         sc->re_dev = dev;
1322
1323         if (RE_IS_8139CP(sc)) {
1324                 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1325                 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1326         } else {
1327                 sc->re_rx_desc_cnt = re_rx_desc_count;
1328                 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1329                         sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1330
1331                 sc->re_tx_desc_cnt = re_tx_desc_count;
1332                 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1333                         sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1334         }
1335
1336         qlen = RE_IFQ_MAXLEN;
1337         if (sc->re_tx_desc_cnt > qlen)
1338                 qlen = sc->re_tx_desc_cnt;
1339
1340         sc->re_rxbuf_size = MCLBYTES;
1341         sc->re_newbuf = re_newbuf_std;
1342
1343         sc->re_tx_time = 5;             /* 125us */
1344         sc->re_rx_time = 2;             /* 50us */
1345         if (sc->re_caps & RE_C_PCIE)
1346                 sc->re_sim_time = 75;   /* 75us */
1347         else
1348                 sc->re_sim_time = 125;  /* 125us */
1349         if (!RE_IS_8139CP(sc)) {
1350                 /* simulated interrupt moderation */
1351                 sc->re_imtype = RE_IMTYPE_SIM;
1352         } else {
1353                 sc->re_imtype = RE_IMTYPE_NONE;
1354         }
1355         re_config_imtype(sc, sc->re_imtype);
1356
1357         sysctl_ctx_init(&sc->re_sysctl_ctx);
1358         sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1359                                              SYSCTL_STATIC_CHILDREN(_hw),
1360                                              OID_AUTO,
1361                                              device_get_nameunit(dev),
1362                                              CTLFLAG_RD, 0, "");
1363         if (sc->re_sysctl_tree == NULL) {
1364                 device_printf(dev, "can't add sysctl node\n");
1365                 error = ENXIO;
1366                 goto fail;
1367         }
1368         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1369                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1370                        "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1371                        0, "RX desc count");
1372         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1373                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1374                        "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1375                        0, "TX desc count");
1376         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1377                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1378                         OID_AUTO, "sim_time",
1379                         CTLTYPE_INT | CTLFLAG_RW,
1380                         sc, 0, re_sysctl_simtime, "I",
1381                         "Simulated interrupt moderation time (usec).");
1382         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1383                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1384                         OID_AUTO, "imtype",
1385                         CTLTYPE_INT | CTLFLAG_RW,
1386                         sc, 0, re_sysctl_imtype, "I",
1387                         "Interrupt moderation type -- "
1388                         "0:disable, 1:simulated, "
1389                         "2:hardware(if supported)");
1390         if (sc->re_caps & RE_C_HWIM) {
1391                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1392                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1393                                 OID_AUTO, "hw_rxtime",
1394                                 CTLTYPE_INT | CTLFLAG_RW,
1395                                 sc, 0, re_sysctl_rxtime, "I",
1396                                 "Hardware interrupt moderation time "
1397                                 "(unit: 25usec).");
1398                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1399                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1400                                 OID_AUTO, "hw_txtime",
1401                                 CTLTYPE_INT | CTLFLAG_RW,
1402                                 sc, 0, re_sysctl_txtime, "I",
1403                                 "Hardware interrupt moderation time "
1404                                 "(unit: 25usec).");
1405         }
1406
1407 #ifndef BURN_BRIDGES
1408         /*
1409          * Handle power management nonsense.
1410          */
1411
1412         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1413                 uint32_t membase, irq;
1414
1415                 /* Save important PCI config data. */
1416                 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1417                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1418
1419                 /* Reset the power state. */
1420                 device_printf(dev, "chip is in D%d power mode "
1421                     "-- setting to D0\n", pci_get_powerstate(dev));
1422
1423                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1424
1425                 /* Restore PCI config data. */
1426                 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1427                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1428         }
1429 #endif
1430         /*
1431          * Map control/status registers.
1432          */
1433         pci_enable_busmaster(dev);
1434
1435         rid = RE_PCI_LOIO;
1436         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1437                                             RF_ACTIVE);
1438
1439         if (sc->re_res == NULL) {
1440                 device_printf(dev, "couldn't map ports\n");
1441                 error = ENXIO;
1442                 goto fail;
1443         }
1444
1445         sc->re_btag = rman_get_bustag(sc->re_res);
1446         sc->re_bhandle = rman_get_bushandle(sc->re_res);
1447
1448         /* Allocate interrupt */
1449         sc->re_irq_type = pci_alloc_1intr(dev, re_msi_enable,
1450                                            &sc->re_irq_rid, &irq_flags);
1451
1452         sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->re_irq_rid,
1453                                             irq_flags);
1454         if (sc->re_irq == NULL) {
1455                 device_printf(dev, "couldn't map interrupt\n");
1456                 error = ENXIO;
1457                 goto fail;
1458         }
1459
1460         /* Reset the adapter. */
1461         re_reset(sc, 0);
1462
1463         if (RE_IS_8139CP(sc)) {
1464                 sc->re_bus_speed = 33; /* XXX */
1465         } else if (sc->re_caps & RE_C_PCIE) {
1466                 sc->re_bus_speed = 125;
1467         } else {
1468                 uint8_t cfg2;
1469
1470                 cfg2 = CSR_READ_1(sc, RE_CFG2);
1471                 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1472                 case RE_CFG2_PCICLK_33MHZ:
1473                         sc->re_bus_speed = 33;
1474                         break;
1475                 case RE_CFG2_PCICLK_66MHZ:
1476                         sc->re_bus_speed = 66;
1477                         break;
1478                 default:
1479                         device_printf(dev, "unknown bus speed, assume 33MHz\n");
1480                         sc->re_bus_speed = 33;
1481                         break;
1482                 }
1483                 if (cfg2 & RE_CFG2_PCI64)
1484                         sc->re_caps |= RE_C_PCI64;
1485         }
1486         device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1487                       "PCI%s %dMHz\n",
1488                       sc->re_hwrev, sc->re_macver,
1489                       (sc->re_caps & RE_C_PCIE) ?
1490                       "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1491                       sc->re_bus_speed);
1492
1493         /*
1494          * NOTE:
1495          * DO NOT try to adjust config1 and config5 which was spotted in
1496          * Realtek's Linux drivers.  It will _permanently_ damage certain
1497          * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1498          */
1499
1500         re_get_eaddr(sc, eaddr);
1501
1502         if (!RE_IS_8139CP(sc)) {
1503                 /* Set RX length mask */
1504                 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1505                 sc->re_txstart = RE_GTXSTART;
1506         } else {
1507                 /* Set RX length mask */
1508                 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1509                 sc->re_txstart = RE_TXSTART;
1510         }
1511
1512         /* Allocate DMA stuffs */
1513         error = re_allocmem(dev);
1514         if (error)
1515                 goto fail;
1516
1517         /*
1518          * Apply some magic PCI settings from Realtek ...
1519          */
1520         if (RE_IS_8169(sc)) {
1521                 CSR_WRITE_1(sc, 0x82, 1);
1522                 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1523         }
1524         pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1525
1526         if (sc->re_caps & RE_C_MAC2) {
1527                 /*
1528                  * Following part is extracted from Realtek BSD driver v176.
1529                  * However, this does _not_ make much/any sense:
1530                  * 8168C's PCI Express device control is located at 0x78,
1531                  * so the reading from 0x79 (higher part of 0x78) and setting
1532                  * the 4~6bits intend to enlarge the "max read request size"
1533                  * (we will do it).  The content of the rest part of this
1534                  * register is not meaningful to other PCI registers, so
1535                  * writing the value to 0x54 could be completely wrong.
1536                  * 0x80 is the lower part of PCI Express device status, non-
1537                  * reserved bits are RW1C, writing 0 to them will not have
1538                  * any effect at all.
1539                  */
1540 #ifdef foo
1541                 uint8_t val;
1542
1543                 val = pci_read_config(dev, 0x79, 1);
1544                 val = (val & ~0x70) | 0x50;
1545                 pci_write_config(dev, 0x54, val, 1);
1546                 pci_write_config(dev, 0x80, 0, 1);
1547 #endif
1548         }
1549
1550         /*
1551          * Apply some PHY fixup from Realtek ...
1552          */
1553         if (sc->re_hwrev == RE_HWREV_8110S) {
1554                 CSR_WRITE_1(sc, 0x82, 1);
1555                 re_miibus_writereg(dev, 1, 0xb, 0);
1556         }
1557         if (sc->re_caps & RE_C_PHYPMGT) {
1558                 /* Power up PHY */
1559                 re_miibus_writereg(dev, 1, 0x1f, 0);
1560                 re_miibus_writereg(dev, 1, 0xe, 0);
1561         }
1562
1563         /* Do MII setup */
1564         if (mii_phy_probe(dev, &sc->re_miibus,
1565             re_ifmedia_upd, re_ifmedia_sts)) {
1566                 device_printf(dev, "MII without any phy!\n");
1567                 error = ENXIO;
1568                 goto fail;
1569         }
1570
1571         ifp = &sc->arpcom.ac_if;
1572         ifp->if_softc = sc;
1573         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1574         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1575         ifp->if_ioctl = re_ioctl;
1576         ifp->if_start = re_start;
1577 #ifdef IFPOLL_ENABLE
1578         ifp->if_npoll = re_npoll;
1579 #endif
1580         ifp->if_watchdog = re_watchdog;
1581         ifp->if_init = re_init;
1582         if (!RE_IS_8139CP(sc)) /* XXX */
1583                 ifp->if_baudrate = 1000000000;
1584         else
1585                 ifp->if_baudrate = 100000000;
1586         ifq_set_maxlen(&ifp->if_snd, qlen);
1587         ifq_set_ready(&ifp->if_snd);
1588
1589         ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1590         if (sc->re_caps & RE_C_HWCSUM)
1591                 ifp->if_capabilities |= IFCAP_HWCSUM;
1592
1593         ifp->if_capenable = ifp->if_capabilities;
1594         if (ifp->if_capabilities & IFCAP_HWCSUM)
1595                 ifp->if_hwassist = RE_CSUM_FEATURES;
1596         else
1597                 ifp->if_hwassist = 0;
1598
1599         /*
1600          * Call MI attach routine.
1601          */
1602         ether_ifattach(ifp, eaddr, NULL);
1603
1604 #ifdef IFPOLL_ENABLE
1605         ifpoll_compat_setup(&sc->re_npoll,
1606             &sc->re_sysctl_ctx, sc->re_sysctl_tree, device_get_unit(dev),
1607             ifp->if_serializer);
1608 #endif
1609
1610 #ifdef RE_DIAG
1611         /*
1612          * Perform hardware diagnostic on the original RTL8169.
1613          * Some 32-bit cards were incorrectly wired and would
1614          * malfunction if plugged into a 64-bit slot.
1615          */
1616         if (sc->re_hwrev == RE_HWREV_8169) {
1617                 lwkt_serialize_enter(ifp->if_serializer);
1618                 error = re_diag(sc);
1619                 lwkt_serialize_exit(ifp->if_serializer);
1620
1621                 if (error) {
1622                         device_printf(dev, "hardware diagnostic failure\n");
1623                         ether_ifdetach(ifp);
1624                         goto fail;
1625                 }
1626         }
1627 #endif  /* RE_DIAG */
1628
1629         /* Hook interrupt last to avoid having to lock softc */
1630         error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1631                                &sc->re_intrhand, ifp->if_serializer);
1632
1633         if (error) {
1634                 device_printf(dev, "couldn't set up irq\n");
1635                 ether_ifdetach(ifp);
1636                 goto fail;
1637         }
1638
1639         ifp->if_cpuid = rman_get_cpuid(sc->re_irq);
1640         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1641
1642 fail:
1643         if (error)
1644                 re_detach(dev);
1645
1646         return (error);
1647 }
1648
1649 /*
1650  * Shutdown hardware and free up resources. This can be called any
1651  * time after the mutex has been initialized. It is called in both
1652  * the error case in attach and the normal detach case so it needs
1653  * to be careful about only freeing resources that have actually been
1654  * allocated.
1655  */
1656 static int
1657 re_detach(device_t dev)
1658 {
1659         struct re_softc *sc = device_get_softc(dev);
1660         struct ifnet *ifp = &sc->arpcom.ac_if;
1661
1662         /* These should only be active if attach succeeded */
1663         if (device_is_attached(dev)) {
1664                 lwkt_serialize_enter(ifp->if_serializer);
1665                 re_stop(sc);
1666                 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1667                 lwkt_serialize_exit(ifp->if_serializer);
1668
1669                 ether_ifdetach(ifp);
1670         }
1671         if (sc->re_miibus)
1672                 device_delete_child(dev, sc->re_miibus);
1673         bus_generic_detach(dev);
1674
1675         if (sc->re_sysctl_tree != NULL)
1676                 sysctl_ctx_free(&sc->re_sysctl_ctx);
1677
1678         if (sc->re_irq)
1679                 bus_release_resource(dev, SYS_RES_IRQ, sc->re_irq_rid,
1680                                      sc->re_irq);
1681
1682         if (sc->re_irq_type == PCI_INTR_TYPE_MSI)
1683                 pci_release_msi(dev);
1684
1685         if (sc->re_res) {
1686                 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1687                                      sc->re_res);
1688         }
1689
1690         /* Free DMA stuffs */
1691         re_freemem(dev);
1692
1693         return(0);
1694 }
1695
1696 static void
1697 re_setup_rxdesc(struct re_softc *sc, int idx)
1698 {
1699         bus_addr_t paddr;
1700         uint32_t cmdstat;
1701         struct re_desc *d;
1702
1703         paddr = sc->re_ldata.re_rx_paddr[idx];
1704         d = &sc->re_ldata.re_rx_list[idx];
1705
1706         d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1707         d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1708
1709         cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1710         if (idx == (sc->re_rx_desc_cnt - 1))
1711                 cmdstat |= RE_RDESC_CMD_EOR;
1712         d->re_cmdstat = htole32(cmdstat);
1713 }
1714
1715 static int
1716 re_newbuf_std(struct re_softc *sc, int idx, int init)
1717 {
1718         bus_dma_segment_t seg;
1719         bus_dmamap_t map;
1720         struct mbuf *m;
1721         int error, nsegs;
1722
1723         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1724         if (m == NULL) {
1725                 error = ENOBUFS;
1726
1727                 if (init) {
1728                         if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1729                         return error;
1730                 } else {
1731                         goto back;
1732                 }
1733         }
1734         m->m_len = m->m_pkthdr.len = MCLBYTES;
1735
1736         /*
1737          * NOTE:
1738          * re(4) chips need address of the receive buffer to be 8-byte
1739          * aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1740          */
1741
1742         error = bus_dmamap_load_mbuf_segment(sc->re_ldata.re_rx_mtag,
1743                         sc->re_ldata.re_rx_spare, m,
1744                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1745         if (error) {
1746                 m_freem(m);
1747                 if (init) {
1748                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1749                         return error;
1750                 } else {
1751                         goto back;
1752                 }
1753         }
1754
1755         if (!init) {
1756                 bus_dmamap_sync(sc->re_ldata.re_rx_mtag,
1757                                 sc->re_ldata.re_rx_dmamap[idx],
1758                                 BUS_DMASYNC_POSTREAD);
1759                 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
1760                                   sc->re_ldata.re_rx_dmamap[idx]);
1761         }
1762         sc->re_ldata.re_rx_mbuf[idx] = m;
1763         sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1764
1765         map = sc->re_ldata.re_rx_dmamap[idx];
1766         sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1767         sc->re_ldata.re_rx_spare = map;
1768 back:
1769         re_setup_rxdesc(sc, idx);
1770         return error;
1771 }
1772
1773 static int
1774 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1775 {
1776         struct mbuf *m;
1777         struct re_jbuf *jbuf;
1778         int error = 0;
1779
1780         MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1781         if (m == NULL) {
1782                 error = ENOBUFS;
1783                 if (init) {
1784                         if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1785                         return error;
1786                 } else {
1787                         goto back;
1788                 }
1789         }
1790
1791         jbuf = re_jbuf_alloc(sc);
1792         if (jbuf == NULL) {
1793                 m_freem(m);
1794
1795                 error = ENOBUFS;
1796                 if (init) {
1797                         if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1798                         return error;
1799                 } else {
1800                         goto back;
1801                 }
1802         }
1803
1804         m->m_ext.ext_arg = jbuf;
1805         m->m_ext.ext_buf = jbuf->re_buf;
1806         m->m_ext.ext_free = re_jbuf_free;
1807         m->m_ext.ext_ref = re_jbuf_ref;
1808         m->m_ext.ext_size = sc->re_rxbuf_size;
1809
1810         m->m_data = m->m_ext.ext_buf;
1811         m->m_flags |= M_EXT;
1812         m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1813
1814         /*
1815          * NOTE:
1816          * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1817          * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1818          */
1819
1820         sc->re_ldata.re_rx_mbuf[idx] = m;
1821         sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1822 back:
1823         re_setup_rxdesc(sc, idx);
1824         return error;
1825 }
1826
1827 static int
1828 re_tx_list_init(struct re_softc *sc)
1829 {
1830         bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1831
1832         sc->re_ldata.re_tx_prodidx = 0;
1833         sc->re_ldata.re_tx_considx = 0;
1834         sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1835
1836         return(0);
1837 }
1838
1839 static int
1840 re_rx_list_init(struct re_softc *sc)
1841 {
1842         int i, error;
1843
1844         bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1845
1846         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1847                 error = sc->re_newbuf(sc, i, 1);
1848                 if (error)
1849                         return(error);
1850         }
1851
1852         sc->re_ldata.re_rx_prodidx = 0;
1853         sc->re_head = sc->re_tail = NULL;
1854
1855         return(0);
1856 }
1857
1858 #define RE_IP4_PACKET   0x1
1859 #define RE_TCP_PACKET   0x2
1860 #define RE_UDP_PACKET   0x4
1861
1862 static __inline uint8_t
1863 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1864 {
1865         uint8_t packet_type = 0;
1866
1867         if (sc->re_caps & RE_C_MAC2) {
1868                 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1869                         packet_type |= RE_IP4_PACKET;
1870         } else {
1871                 if (rxstat & RE_RDESC_STAT_PROTOID)
1872                         packet_type |= RE_IP4_PACKET;
1873         }
1874         if (RE_TCPPKT(rxstat))
1875                 packet_type |= RE_TCP_PACKET;
1876         else if (RE_UDPPKT(rxstat))
1877                 packet_type |= RE_UDP_PACKET;
1878         return packet_type;
1879 }
1880
1881 /*
1882  * RX handler for C+ and 8169. For the gigE chips, we support
1883  * the reception of jumbo frames that have been fragmented
1884  * across multiple 2K mbuf cluster buffers.
1885  */
1886 static int
1887 re_rxeof(struct re_softc *sc)
1888 {
1889         struct ifnet *ifp = &sc->arpcom.ac_if;
1890         struct mbuf *m;
1891         struct re_desc  *cur_rx;
1892         uint32_t rxstat, rxctrl;
1893         int i, total_len, rx = 0;
1894
1895         for (i = sc->re_ldata.re_rx_prodidx;
1896              RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1897                 cur_rx = &sc->re_ldata.re_rx_list[i];
1898                 m = sc->re_ldata.re_rx_mbuf[i];
1899                 total_len = RE_RXBYTES(cur_rx);
1900                 rxstat = le32toh(cur_rx->re_cmdstat);
1901                 rxctrl = le32toh(cur_rx->re_control);
1902
1903                 rx = 1;
1904
1905 #ifdef INVARIANTS
1906                 if (sc->re_flags & RE_F_USE_JPOOL)
1907                         KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1908 #endif
1909
1910                 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1911                         if (sc->re_flags & RE_F_DROP_RXFRAG) {
1912                                 re_setup_rxdesc(sc, i);
1913                                 continue;
1914                         }
1915
1916                         if (sc->re_newbuf(sc, i, 0)) {
1917                                 /* Drop upcoming fragments */
1918                                 sc->re_flags |= RE_F_DROP_RXFRAG;
1919                                 continue;
1920                         }
1921
1922                         m->m_len = MCLBYTES;
1923                         if (sc->re_head == NULL) {
1924                                 sc->re_head = sc->re_tail = m;
1925                         } else {
1926                                 sc->re_tail->m_next = m;
1927                                 sc->re_tail = m;
1928                         }
1929                         continue;
1930                 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1931                         /*
1932                          * Last fragment of a multi-fragment packet.
1933                          *
1934                          * Since error already happened, this fragment
1935                          * must be dropped as well as the fragment chain.
1936                          */
1937                         re_setup_rxdesc(sc, i);
1938                         re_free_rxchain(sc);
1939                         sc->re_flags &= ~RE_F_DROP_RXFRAG;
1940                         continue;
1941                 }
1942
1943                 /*
1944                  * NOTE: for the 8139C+, the frame length field
1945                  * is always 12 bits in size, but for the gigE chips,
1946                  * it is 13 bits (since the max RX frame length is 16K).
1947                  * Unfortunately, all 32 bits in the status word
1948                  * were already used, so to make room for the extra
1949                  * length bit, RealTek took out the 'frame alignment
1950                  * error' bit and shifted the other status bits
1951                  * over one slot. The OWN, EOR, FS and LS bits are
1952                  * still in the same places. We have already extracted
1953                  * the frame length and checked the OWN bit, so rather
1954                  * than using an alternate bit mapping, we shift the
1955                  * status bits one space to the right so we can evaluate
1956                  * them using the 8169 status as though it was in the
1957                  * same format as that of the 8139C+.
1958                  */
1959                 if (!RE_IS_8139CP(sc))
1960                         rxstat >>= 1;
1961
1962                 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1963                         ifp->if_ierrors++;
1964                         /*
1965                          * If this is part of a multi-fragment packet,
1966                          * discard all the pieces.
1967                          */
1968                         re_free_rxchain(sc);
1969                         re_setup_rxdesc(sc, i);
1970                         continue;
1971                 }
1972
1973                 /*
1974                  * If allocating a replacement mbuf fails,
1975                  * reload the current one.
1976                  */
1977
1978                 if (sc->re_newbuf(sc, i, 0)) {
1979                         ifp->if_ierrors++;
1980                         continue;
1981                 }
1982
1983                 if (sc->re_head != NULL) {
1984                         m->m_len = total_len % MCLBYTES;
1985                         /*
1986                          * Special case: if there's 4 bytes or less
1987                          * in this buffer, the mbuf can be discarded:
1988                          * the last 4 bytes is the CRC, which we don't
1989                          * care about anyway.
1990                          */
1991                         if (m->m_len <= ETHER_CRC_LEN) {
1992                                 sc->re_tail->m_len -=
1993                                     (ETHER_CRC_LEN - m->m_len);
1994                                 m_freem(m);
1995                         } else {
1996                                 m->m_len -= ETHER_CRC_LEN;
1997                                 sc->re_tail->m_next = m;
1998                         }
1999                         m = sc->re_head;
2000                         sc->re_head = sc->re_tail = NULL;
2001                         m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2002                 } else {
2003                         m->m_pkthdr.len = m->m_len =
2004                             (total_len - ETHER_CRC_LEN);
2005                 }
2006
2007                 ifp->if_ipackets++;
2008                 m->m_pkthdr.rcvif = ifp;
2009
2010                 /* Do RX checksumming if enabled */
2011
2012                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2013                         uint8_t packet_type;
2014
2015                         packet_type = re_packet_type(sc, rxstat, rxctrl);
2016
2017                         /* Check IP header checksum */
2018                         if (packet_type & RE_IP4_PACKET) {
2019                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2020                                 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
2021                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2022                         }
2023
2024                         /* Check TCP/UDP checksum */
2025                         if (((packet_type & RE_TCP_PACKET) &&
2026                              (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
2027                             ((packet_type & RE_UDP_PACKET) &&
2028                              (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
2029                                 m->m_pkthdr.csum_flags |=
2030                                     CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2031                                     CSUM_FRAG_NOT_CHECKED;
2032                                 m->m_pkthdr.csum_data = 0xffff;
2033                         }
2034                 }
2035
2036                 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2037                         m->m_flags |= M_VLANTAG;
2038                         m->m_pkthdr.ether_vlantag =
2039                                 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2040                 }
2041                 ifp->if_input(ifp, m);
2042         }
2043
2044         sc->re_ldata.re_rx_prodidx = i;
2045
2046         return rx;
2047 }
2048
2049 #undef RE_IP4_PACKET
2050 #undef RE_TCP_PACKET
2051 #undef RE_UDP_PACKET
2052
2053 static int
2054 re_tx_collect(struct re_softc *sc)
2055 {
2056         struct ifnet *ifp = &sc->arpcom.ac_if;
2057         uint32_t txstat;
2058         int idx, tx = 0;
2059
2060         for (idx = sc->re_ldata.re_tx_considx;
2061              sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2062              RE_TXDESC_INC(sc, idx)) {
2063                 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2064                 if (txstat & RE_TDESC_CMD_OWN)
2065                         break;
2066
2067                 tx = 1;
2068
2069                 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2070
2071                 /*
2072                  * We only stash mbufs in the last descriptor
2073                  * in a fragment chain, which also happens to
2074                  * be the only place where the TX status bits
2075                  * are valid.
2076                  */
2077                 if (txstat & RE_TDESC_CMD_EOF) {
2078                         bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2079                             sc->re_ldata.re_tx_dmamap[idx]);
2080                         m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2081                         sc->re_ldata.re_tx_mbuf[idx] = NULL;
2082                         if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2083                             RE_TDESC_STAT_COLCNT))
2084                                 ifp->if_collisions++;
2085                         if (txstat & RE_TDESC_STAT_TXERRSUM)
2086                                 ifp->if_oerrors++;
2087                         else
2088                                 ifp->if_opackets++;
2089                 }
2090                 sc->re_ldata.re_tx_free++;
2091         }
2092         sc->re_ldata.re_tx_considx = idx;
2093
2094         return tx;
2095 }
2096
2097 static int
2098 re_txeof(struct re_softc *sc)
2099 {
2100         struct ifnet *ifp = &sc->arpcom.ac_if;
2101         int tx;
2102
2103         tx = re_tx_collect(sc);
2104
2105         /* There is enough free TX descs */
2106         if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2107                 ifp->if_flags &= ~IFF_OACTIVE;
2108
2109         /*
2110          * Some chips will ignore a second TX request issued while an
2111          * existing transmission is in progress. If the transmitter goes
2112          * idle but there are still packets waiting to be sent, we need
2113          * to restart the channel here to flush them out. This only seems
2114          * to be required with the PCIe devices.
2115          */
2116         if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2117                 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2118         else
2119                 ifp->if_timer = 0;
2120
2121         return tx;
2122 }
2123
2124 static void
2125 re_tick(void *xsc)
2126 {
2127         struct re_softc *sc = xsc;
2128
2129         lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2130         re_tick_serialized(xsc);
2131         lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2132 }
2133
2134 static void
2135 re_tick_serialized(void *xsc)
2136 {
2137         struct re_softc *sc = xsc;
2138         struct ifnet *ifp = &sc->arpcom.ac_if;
2139         struct mii_data *mii;
2140
2141         ASSERT_SERIALIZED(ifp->if_serializer);
2142
2143         mii = device_get_softc(sc->re_miibus);
2144         mii_tick(mii);
2145         if (sc->re_flags & RE_F_LINKED) {
2146                 if (!(mii->mii_media_status & IFM_ACTIVE))
2147                         sc->re_flags &= ~RE_F_LINKED;
2148         } else {
2149                 if (mii->mii_media_status & IFM_ACTIVE &&
2150                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2151                         sc->re_flags |= RE_F_LINKED;
2152                         if (!ifq_is_empty(&ifp->if_snd))
2153                                 if_devstart(ifp);
2154                 }
2155         }
2156
2157         callout_reset(&sc->re_timer, hz, re_tick, sc);
2158 }
2159
2160 #ifdef IFPOLL_ENABLE
2161
2162 static void
2163 re_npoll_compat(struct ifnet *ifp, void *arg __unused, int count)
2164 {
2165         struct re_softc *sc = ifp->if_softc;
2166
2167         ASSERT_SERIALIZED(ifp->if_serializer);
2168
2169         if (sc->re_npoll.ifpc_stcount-- == 0) {
2170                 uint16_t       status;
2171
2172                 sc->re_npoll.ifpc_stcount = sc->re_npoll.ifpc_stfrac;
2173
2174                 status = CSR_READ_2(sc, RE_ISR);
2175                 if (status == 0xffff)
2176                         return;
2177                 if (status)
2178                         CSR_WRITE_2(sc, RE_ISR, status);
2179
2180                 /*
2181                  * XXX check behaviour on receiver stalls.
2182                  */
2183
2184                 if (status & RE_ISR_SYSTEM_ERR)
2185                         re_init(sc);
2186         }
2187
2188         sc->rxcycles = count;
2189         re_rxeof(sc);
2190         re_txeof(sc);
2191
2192         if (!ifq_is_empty(&ifp->if_snd))
2193                 if_devstart(ifp);
2194 }
2195
2196 static void
2197 re_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2198 {
2199         struct re_softc *sc = ifp->if_softc;
2200
2201         ASSERT_SERIALIZED(ifp->if_serializer);
2202
2203         if (info != NULL) {
2204                 int cpuid = sc->re_npoll.ifpc_cpuid;
2205
2206                 info->ifpi_rx[cpuid].poll_func = re_npoll_compat;
2207                 info->ifpi_rx[cpuid].arg = NULL;
2208                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2209
2210                 if (ifp->if_flags & IFF_RUNNING)
2211                         re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2212                 ifp->if_npoll_cpuid = cpuid;
2213         } else {
2214                 if (ifp->if_flags & IFF_RUNNING)
2215                         re_setup_intr(sc, 1, sc->re_imtype);
2216                 ifp->if_npoll_cpuid = -1;
2217         }
2218 }
2219 #endif /* IFPOLL_ENABLE */
2220
2221 static void
2222 re_intr(void *arg)
2223 {
2224         struct re_softc *sc = arg;
2225         struct ifnet *ifp = &sc->arpcom.ac_if;
2226         uint16_t status;
2227         int rx, tx;
2228
2229         ASSERT_SERIALIZED(ifp->if_serializer);
2230
2231         if ((sc->re_flags & RE_F_SUSPENDED) ||
2232             (ifp->if_flags & IFF_RUNNING) == 0)
2233                 return;
2234
2235         rx = tx = 0;
2236         for (;;) {
2237                 status = CSR_READ_2(sc, RE_ISR);
2238                 /* If the card has gone away the read returns 0xffff. */
2239                 if (status == 0xffff)
2240                         break;
2241                 if (status)
2242                         CSR_WRITE_2(sc, RE_ISR, status);
2243
2244                 if ((status & sc->re_intrs) == 0)
2245                         break;
2246
2247                 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2248                         rx |= re_rxeof(sc);
2249
2250                 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2251                         tx |= re_txeof(sc);
2252
2253                 if (status & RE_ISR_SYSTEM_ERR)
2254                         re_init(sc);
2255
2256                 if (status & RE_ISR_LINKCHG) {
2257                         callout_stop(&sc->re_timer);
2258                         re_tick_serialized(sc);
2259                 }
2260         }
2261
2262         if (sc->re_imtype == RE_IMTYPE_SIM) {
2263                 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2264                         if ((tx | rx) == 0) {
2265                                 /*
2266                                  * Nothing needs to be processed, fallback
2267                                  * to use TX/RX interrupts.
2268                                  */
2269                                 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2270
2271                                 /*
2272                                  * Recollect, mainly to avoid the possible
2273                                  * race introduced by changing interrupt
2274                                  * masks.
2275                                  */
2276                                 re_rxeof(sc);
2277                                 tx = re_txeof(sc);
2278                         } else {
2279                                 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2280                         }
2281                 } else if (tx | rx) {
2282                         /*
2283                          * Assume that using simulated interrupt moderation
2284                          * (hardware timer based) could reduce the interript
2285                          * rate.
2286                          */
2287                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2288                 }
2289         }
2290
2291         if (tx && !ifq_is_empty(&ifp->if_snd))
2292                 if_devstart(ifp);
2293 }
2294
2295 static int
2296 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2297 {
2298         struct mbuf *m = *m_head;
2299         bus_dma_segment_t segs[RE_MAXSEGS];
2300         bus_dmamap_t map;
2301         int error, maxsegs, idx, i, nsegs;
2302         struct re_desc *d, *tx_ring;
2303         uint32_t cmd_csum, ctl_csum, vlantag;
2304
2305         KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2306                 ("not enough free TX desc"));
2307
2308         map = sc->re_ldata.re_tx_dmamap[*idx0];
2309
2310         /*
2311          * Set up checksum offload. Note: checksum offload bits must
2312          * appear in all descriptors of a multi-descriptor transmit
2313          * attempt. (This is according to testing done with an 8169
2314          * chip. I'm not sure if this is a requirement or a bug.)
2315          */
2316         cmd_csum = ctl_csum = 0;
2317         if (m->m_pkthdr.csum_flags & CSUM_IP) {
2318                 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2319                 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2320         }
2321         if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2322                 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2323                 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2324         }
2325         if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2326                 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2327                 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2328         }
2329
2330         /* For MAC2 chips, csum flags are set on re_control */
2331         if (sc->re_caps & RE_C_MAC2)
2332                 cmd_csum = 0;
2333         else
2334                 ctl_csum = 0;
2335
2336         if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2337                 /*
2338                  * With some of the RealTek chips, using the checksum offload
2339                  * support in conjunction with the autopadding feature results
2340                  * in the transmission of corrupt frames. For example, if we
2341                  * need to send a really small IP fragment that's less than 60
2342                  * bytes in size, and IP header checksumming is enabled, the
2343                  * resulting ethernet frame that appears on the wire will
2344                  * have garbled payload. To work around this, if TX checksum
2345                  * offload is enabled, we always manually pad short frames out
2346                  * to the minimum ethernet frame size.
2347                  *
2348                  * Note: this appears unnecessary for TCP, and doing it for TCP
2349                  * with PCIe adapters seems to result in bad checksums.
2350                  */
2351                 if ((m->m_pkthdr.csum_flags &
2352                      (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2353                     (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2354                     m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2355                         error = m_devpad(m, RE_MIN_FRAMELEN);
2356                         if (error)
2357                                 goto back;
2358                 }
2359         }
2360
2361         vlantag = 0;
2362         if (m->m_flags & M_VLANTAG) {
2363                 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2364                           RE_TDESC_CTL_INSTAG;
2365         }
2366
2367         maxsegs = sc->re_ldata.re_tx_free;
2368         if (maxsegs > RE_MAXSEGS)
2369                 maxsegs = RE_MAXSEGS;
2370
2371         error = bus_dmamap_load_mbuf_defrag(sc->re_ldata.re_tx_mtag, map,
2372                         m_head, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2373         if (error)
2374                 goto back;
2375
2376         m = *m_head;
2377         bus_dmamap_sync(sc->re_ldata.re_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2378
2379         /*
2380          * Map the segment array into descriptors.  We also keep track
2381          * of the end of the ring and set the end-of-ring bits as needed,
2382          * and we set the ownership bits in all except the very first
2383          * descriptor, whose ownership bits will be turned on later.
2384          */
2385         tx_ring = sc->re_ldata.re_tx_list;
2386         idx = *idx0;
2387         i = 0;
2388         for (;;) {
2389                 uint32_t cmdstat;
2390
2391                 d = &tx_ring[idx];
2392
2393                 cmdstat = segs[i].ds_len;
2394                 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2395                 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2396                 if (i == 0)
2397                         cmdstat |= RE_TDESC_CMD_SOF;
2398                 else
2399                         cmdstat |= RE_TDESC_CMD_OWN;
2400                 if (idx == (sc->re_tx_desc_cnt - 1))
2401                         cmdstat |= RE_TDESC_CMD_EOR;
2402                 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2403                 d->re_control = htole32(ctl_csum | vlantag);
2404
2405                 i++;
2406                 if (i == nsegs)
2407                         break;
2408                 RE_TXDESC_INC(sc, idx);
2409         }
2410         d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2411
2412         /* Transfer ownership of packet to the chip. */
2413         d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2414         if (*idx0 != idx)
2415                 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2416
2417         /*
2418          * Insure that the map for this transmission
2419          * is placed at the array index of the last descriptor
2420          * in this chain.
2421          */
2422         sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2423         sc->re_ldata.re_tx_dmamap[idx] = map;
2424
2425         sc->re_ldata.re_tx_mbuf[idx] = m;
2426         sc->re_ldata.re_tx_free -= nsegs;
2427
2428         RE_TXDESC_INC(sc, idx);
2429         *idx0 = idx;
2430 back:
2431         if (error) {
2432                 m_freem(*m_head);
2433                 *m_head = NULL;
2434         }
2435         return error;
2436 }
2437
2438 /*
2439  * Main transmit routine for C+ and gigE NICs.
2440  */
2441
2442 static void
2443 re_start(struct ifnet *ifp)
2444 {
2445         struct re_softc *sc = ifp->if_softc;
2446         struct mbuf *m_head;
2447         int idx, need_trans, oactive, error;
2448
2449         ASSERT_SERIALIZED(ifp->if_serializer);
2450
2451         if ((sc->re_flags & RE_F_LINKED) == 0) {
2452                 ifq_purge(&ifp->if_snd);
2453                 return;
2454         }
2455
2456         if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2457                 return;
2458
2459         idx = sc->re_ldata.re_tx_prodidx;
2460
2461         need_trans = 0;
2462         oactive = 0;
2463         while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2464                 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2465                         if (!oactive) {
2466                                 if (re_tx_collect(sc)) {
2467                                         oactive = 1;
2468                                         continue;
2469                                 }
2470                         }
2471                         ifp->if_flags |= IFF_OACTIVE;
2472                         break;
2473                 }
2474
2475                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2476                 if (m_head == NULL)
2477                         break;
2478
2479                 error = re_encap(sc, &m_head, &idx);
2480                 if (error) {
2481                         /* m_head is freed by re_encap(), if we reach here */
2482                         ifp->if_oerrors++;
2483
2484                         if (error == EFBIG && !oactive) {
2485                                 if (re_tx_collect(sc)) {
2486                                         oactive = 1;
2487                                         continue;
2488                                 }
2489                         }
2490                         ifp->if_flags |= IFF_OACTIVE;
2491                         break;
2492                 }
2493
2494                 oactive = 0;
2495                 need_trans = 1;
2496
2497                 /*
2498                  * If there's a BPF listener, bounce a copy of this frame
2499                  * to him.
2500                  */
2501                 ETHER_BPF_MTAP(ifp, m_head);
2502         }
2503
2504         /*
2505          * If sc->re_ldata.re_tx_mbuf[idx] is not NULL it is possible
2506          * for IFF_OACTIVE to not be properly set when we also do not
2507          * have sufficient free tx descriptors, leaving packet in
2508          * ifp->if_send.  This can cause if_start_dispatch() to loop
2509          * infinitely so make sure IFF_OACTIVE is set properly.
2510          */
2511         if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2512                 if ((ifp->if_flags & IFF_OACTIVE) == 0) {
2513                         device_printf(sc->re_dev,
2514                                       "Debug: IFF_OACTIVE was not set when"
2515                                       " re_tx_free was below minimum!\n");
2516                         ifp->if_flags |= IFF_OACTIVE;
2517                 }
2518         }
2519         if (!need_trans)
2520                 return;
2521
2522         sc->re_ldata.re_tx_prodidx = idx;
2523
2524         /*
2525          * RealTek put the TX poll request register in a different
2526          * location on the 8169 gigE chip. I don't know why.
2527          */
2528         CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2529
2530         /*
2531          * Set a timeout in case the chip goes out to lunch.
2532          */
2533         ifp->if_timer = 5;
2534 }
2535
2536 static void
2537 re_init(void *xsc)
2538 {
2539         struct re_softc *sc = xsc;
2540         struct ifnet *ifp = &sc->arpcom.ac_if;
2541         struct mii_data *mii;
2542         int error, framelen;
2543
2544         ASSERT_SERIALIZED(ifp->if_serializer);
2545
2546         mii = device_get_softc(sc->re_miibus);
2547
2548         /*
2549          * Cancel pending I/O and free all RX/TX buffers.
2550          */
2551         re_stop(sc);
2552
2553         if (sc->re_caps & RE_C_CONTIGRX) {
2554                 if (ifp->if_mtu > ETHERMTU) {
2555                         KKASSERT(sc->re_ldata.re_jbuf != NULL);
2556                         sc->re_flags |= RE_F_USE_JPOOL;
2557                         sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2558                         sc->re_newbuf = re_newbuf_jumbo;
2559                 } else {
2560                         sc->re_flags &= ~RE_F_USE_JPOOL;
2561                         sc->re_rxbuf_size = MCLBYTES;
2562                         sc->re_newbuf = re_newbuf_std;
2563                 }
2564         }
2565
2566         /*
2567          * Adjust max read request size according to MTU; mainly to
2568          * improve TX performance for common case (ETHERMTU) on GigE
2569          * NICs.  However, this could _not_ be done on 10/100 only
2570          * NICs; their DMA engines will malfunction using non-default
2571          * max read request size.
2572          */
2573         if ((sc->re_caps & (RE_C_PCIE | RE_C_FASTE)) == RE_C_PCIE) {
2574                 if (ifp->if_mtu > ETHERMTU) {
2575                         /*
2576                          * 512 seems to be the only value that works
2577                          * reliably with jumbo frame
2578                          */
2579                         pcie_set_max_readrq(sc->re_dev,
2580                                 PCIEM_DEVCTL_MAX_READRQ_512);
2581                 } else {
2582                         pcie_set_max_readrq(sc->re_dev,
2583                                 PCIEM_DEVCTL_MAX_READRQ_4096);
2584                 }
2585         }
2586
2587         /*
2588          * Enable C+ RX and TX mode, as well as VLAN stripping and
2589          * RX checksum offload. We must configure the C+ register
2590          * before all others.
2591          */
2592         CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2593                     RE_CPLUSCMD_PCI_MRW |
2594                     (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2595                      RE_CPLUSCMD_VLANSTRIP : 0) |
2596                     (ifp->if_capenable & IFCAP_RXCSUM ?
2597                      RE_CPLUSCMD_RXCSUM_ENB : 0));
2598
2599         /*
2600          * Init our MAC address.  Even though the chipset
2601          * documentation doesn't mention it, we need to enter "Config
2602          * register write enable" mode to modify the ID registers.
2603          */
2604         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2605         CSR_WRITE_4(sc, RE_IDR0,
2606             htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2607         CSR_WRITE_2(sc, RE_IDR4,
2608             htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2609         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2610
2611         /*
2612          * For C+ mode, initialize the RX descriptors and mbufs.
2613          */
2614         error = re_rx_list_init(sc);
2615         if (error) {
2616                 re_stop(sc);
2617                 return;
2618         }
2619         error = re_tx_list_init(sc);
2620         if (error) {
2621                 re_stop(sc);
2622                 return;
2623         }
2624
2625         /*
2626          * Load the addresses of the RX and TX lists into the chip.
2627          */
2628         CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2629             RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2630         CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2631             RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2632
2633         CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2634             RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2635         CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2636             RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2637
2638         /*
2639          * Enable transmit and receive.
2640          */
2641         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2642
2643         /*
2644          * Set the initial TX and RX configuration.
2645          */
2646         if (sc->re_flags & RE_F_TESTMODE) {
2647                 if (!RE_IS_8139CP(sc))
2648                         CSR_WRITE_4(sc, RE_TXCFG,
2649                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2650                 else
2651                         CSR_WRITE_4(sc, RE_TXCFG,
2652                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2653         } else
2654                 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2655
2656         framelen = RE_FRAMELEN(ifp->if_mtu);
2657         if (framelen < MCLBYTES)
2658                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2659         else
2660                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2661
2662         CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2663
2664         /*
2665          * Program the multicast filter, if necessary.
2666          */
2667         re_setmulti(sc);
2668
2669 #ifdef IFPOLL_ENABLE
2670         /*
2671          * Disable interrupts if we are polling.
2672          */
2673         if (ifp->if_flags & IFF_NPOLLING)
2674                 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2675         else    /* otherwise ... */
2676 #endif /* IFPOLL_ENABLE */
2677         /*
2678          * Enable interrupts.
2679          */
2680         if (sc->re_flags & RE_F_TESTMODE)
2681                 CSR_WRITE_2(sc, RE_IMR, 0);
2682         else
2683                 re_setup_intr(sc, 1, sc->re_imtype);
2684         CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2685
2686         /* Start RX/TX process. */
2687         CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2688
2689 #ifdef notdef
2690         /* Enable receiver and transmitter. */
2691         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2692 #endif
2693
2694         /*
2695          * For 8169 gigE NICs, set the max allowed RX packet
2696          * size so we can receive jumbo frames.
2697          */
2698         if (!RE_IS_8139CP(sc)) {
2699                 if (sc->re_caps & RE_C_CONTIGRX)
2700                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2701                 else
2702                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2703         }
2704
2705         if (sc->re_flags & RE_F_TESTMODE)
2706                 return;
2707
2708         mii_mediachg(mii);
2709
2710         CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2711
2712         ifp->if_flags |= IFF_RUNNING;
2713         ifp->if_flags &= ~IFF_OACTIVE;
2714
2715         callout_reset(&sc->re_timer, hz, re_tick, sc);
2716 }
2717
2718 /*
2719  * Set media options.
2720  */
2721 static int
2722 re_ifmedia_upd(struct ifnet *ifp)
2723 {
2724         struct re_softc *sc = ifp->if_softc;
2725         struct mii_data *mii;
2726
2727         ASSERT_SERIALIZED(ifp->if_serializer);
2728
2729         mii = device_get_softc(sc->re_miibus);
2730         mii_mediachg(mii);
2731
2732         return(0);
2733 }
2734
2735 /*
2736  * Report current media status.
2737  */
2738 static void
2739 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2740 {
2741         struct re_softc *sc = ifp->if_softc;
2742         struct mii_data *mii;
2743
2744         ASSERT_SERIALIZED(ifp->if_serializer);
2745
2746         mii = device_get_softc(sc->re_miibus);
2747
2748         mii_pollstat(mii);
2749         ifmr->ifm_active = mii->mii_media_active;
2750         ifmr->ifm_status = mii->mii_media_status;
2751 }
2752
2753 static int
2754 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2755 {
2756         struct re_softc *sc = ifp->if_softc;
2757         struct ifreq *ifr = (struct ifreq *) data;
2758         struct mii_data *mii;
2759         int error = 0, mask;
2760
2761         ASSERT_SERIALIZED(ifp->if_serializer);
2762
2763         switch(command) {
2764         case SIOCSIFMTU:
2765                 if (ifr->ifr_mtu > sc->re_maxmtu) {
2766                         error = EINVAL;
2767                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2768                         ifp->if_mtu = ifr->ifr_mtu;
2769                         if (ifp->if_flags & IFF_RUNNING)
2770                                 ifp->if_init(sc);
2771                 }
2772                 break;
2773
2774         case SIOCSIFFLAGS:
2775                 if (ifp->if_flags & IFF_UP) {
2776                         if (ifp->if_flags & IFF_RUNNING) {
2777                                 if ((ifp->if_flags ^ sc->re_if_flags) &
2778                                     (IFF_PROMISC | IFF_ALLMULTI))
2779                                         re_setmulti(sc);
2780                         } else {
2781                                 re_init(sc);
2782                         }
2783                 } else if (ifp->if_flags & IFF_RUNNING) {
2784                         re_stop(sc);
2785                 }
2786                 sc->re_if_flags = ifp->if_flags;
2787                 break;
2788
2789         case SIOCADDMULTI:
2790         case SIOCDELMULTI:
2791                 re_setmulti(sc);
2792                 break;
2793
2794         case SIOCGIFMEDIA:
2795         case SIOCSIFMEDIA:
2796                 mii = device_get_softc(sc->re_miibus);
2797                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2798                 break;
2799
2800         case SIOCSIFCAP:
2801                 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2802                        ifp->if_capabilities;
2803                 ifp->if_capenable ^= mask;
2804
2805                 if (mask & IFCAP_HWCSUM) {
2806                         if (ifp->if_capenable & IFCAP_TXCSUM)
2807                                 ifp->if_hwassist = RE_CSUM_FEATURES;
2808                         else
2809                                 ifp->if_hwassist = 0;
2810                 }
2811                 if (mask && (ifp->if_flags & IFF_RUNNING))
2812                         re_init(sc);
2813                 break;
2814
2815         default:
2816                 error = ether_ioctl(ifp, command, data);
2817                 break;
2818         }
2819         return(error);
2820 }
2821
2822 static void
2823 re_watchdog(struct ifnet *ifp)
2824 {
2825         struct re_softc *sc = ifp->if_softc;
2826
2827         ASSERT_SERIALIZED(ifp->if_serializer);
2828
2829         if_printf(ifp, "watchdog timeout\n");
2830
2831         ifp->if_oerrors++;
2832
2833         re_txeof(sc);
2834         re_rxeof(sc);
2835
2836         re_init(sc);
2837
2838         if (!ifq_is_empty(&ifp->if_snd))
2839                 if_devstart(ifp);
2840 }
2841
2842 /*
2843  * Stop the adapter and free any mbufs allocated to the
2844  * RX and TX lists.
2845  */
2846 static void
2847 re_stop(struct re_softc *sc)
2848 {
2849         struct ifnet *ifp = &sc->arpcom.ac_if;
2850         int i;
2851
2852         ASSERT_SERIALIZED(ifp->if_serializer);
2853
2854         /* Reset the adapter. */
2855         re_reset(sc, ifp->if_flags & IFF_RUNNING);
2856
2857         ifp->if_timer = 0;
2858         callout_stop(&sc->re_timer);
2859
2860         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2861         sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2862
2863         CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2864         CSR_WRITE_2(sc, RE_IMR, 0x0000);
2865         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2866
2867         re_free_rxchain(sc);
2868
2869         /* Free the TX list buffers. */
2870         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2871                 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2872                         bus_dmamap_unload(sc->re_ldata.re_tx_mtag,
2873                                           sc->re_ldata.re_tx_dmamap[i]);
2874                         m_freem(sc->re_ldata.re_tx_mbuf[i]);
2875                         sc->re_ldata.re_tx_mbuf[i] = NULL;
2876                 }
2877         }
2878
2879         /* Free the RX list buffers. */
2880         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2881                 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2882                         if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2883                                 bus_dmamap_unload(sc->re_ldata.re_rx_mtag,
2884                                                   sc->re_ldata.re_rx_dmamap[i]);
2885                         }
2886                         m_freem(sc->re_ldata.re_rx_mbuf[i]);
2887                         sc->re_ldata.re_rx_mbuf[i] = NULL;
2888                 }
2889         }
2890 }
2891
2892 /*
2893  * Device suspend routine.  Stop the interface and save some PCI
2894  * settings in case the BIOS doesn't restore them properly on
2895  * resume.
2896  */
2897 static int
2898 re_suspend(device_t dev)
2899 {
2900 #ifndef BURN_BRIDGES
2901         int i;
2902 #endif
2903         struct re_softc *sc = device_get_softc(dev);
2904         struct ifnet *ifp = &sc->arpcom.ac_if;
2905
2906         lwkt_serialize_enter(ifp->if_serializer);
2907
2908         re_stop(sc);
2909
2910 #ifndef BURN_BRIDGES
2911         for (i = 0; i < 5; i++)
2912                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2913         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2914         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2915         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2916         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2917 #endif
2918
2919         sc->re_flags |= RE_F_SUSPENDED;
2920
2921         lwkt_serialize_exit(ifp->if_serializer);
2922
2923         return (0);
2924 }
2925
2926 /*
2927  * Device resume routine.  Restore some PCI settings in case the BIOS
2928  * doesn't, re-enable busmastering, and restart the interface if
2929  * appropriate.
2930  */
2931 static int
2932 re_resume(device_t dev)
2933 {
2934         struct re_softc *sc = device_get_softc(dev);
2935         struct ifnet *ifp = &sc->arpcom.ac_if;
2936 #ifndef BURN_BRIDGES
2937         int i;
2938 #endif
2939
2940         lwkt_serialize_enter(ifp->if_serializer);
2941
2942 #ifndef BURN_BRIDGES
2943         /* better way to do this? */
2944         for (i = 0; i < 5; i++)
2945                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2946         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2947         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2948         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2949         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
2950
2951         /* reenable busmastering */
2952         pci_enable_busmaster(dev);
2953         pci_enable_io(dev, SYS_RES_IOPORT);
2954 #endif
2955
2956         /* reinitialize interface if necessary */
2957         if (ifp->if_flags & IFF_UP)
2958                 re_init(sc);
2959
2960         sc->re_flags &= ~RE_F_SUSPENDED;
2961
2962         lwkt_serialize_exit(ifp->if_serializer);
2963
2964         return (0);
2965 }
2966
2967 /*
2968  * Stop all chip I/O so that the kernel's probe routines don't
2969  * get confused by errant DMAs when rebooting.
2970  */
2971 static void
2972 re_shutdown(device_t dev)
2973 {
2974         struct re_softc *sc = device_get_softc(dev);
2975         struct ifnet *ifp = &sc->arpcom.ac_if;
2976
2977         lwkt_serialize_enter(ifp->if_serializer);
2978         re_stop(sc);
2979         lwkt_serialize_exit(ifp->if_serializer);
2980 }
2981
2982 static int
2983 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
2984 {
2985         struct re_softc *sc = arg1;
2986
2987         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
2988 }
2989
2990 static int
2991 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
2992 {
2993         struct re_softc *sc = arg1;
2994
2995         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
2996 }
2997
2998 static int
2999 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
3000 {
3001         struct re_softc *sc = arg1;
3002         struct ifnet *ifp = &sc->arpcom.ac_if;
3003         int error, v;
3004
3005         lwkt_serialize_enter(ifp->if_serializer);
3006
3007         v = *hwtime;
3008         error = sysctl_handle_int(oidp, &v, 0, req);
3009         if (error || req->newptr == NULL)
3010                 goto back;
3011
3012         if (v <= 0) {
3013                 error = EINVAL;
3014                 goto back;
3015         }
3016
3017         if (v != *hwtime) {
3018                 *hwtime = v;
3019
3020                 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) ==
3021                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
3022                         re_setup_hw_im(sc);
3023         }
3024 back:
3025         lwkt_serialize_exit(ifp->if_serializer);
3026         return error;
3027 }
3028
3029 static int
3030 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
3031 {
3032         struct re_softc *sc = arg1;
3033         struct ifnet *ifp = &sc->arpcom.ac_if;
3034         int error, v;
3035
3036         lwkt_serialize_enter(ifp->if_serializer);
3037
3038         v = sc->re_sim_time;
3039         error = sysctl_handle_int(oidp, &v, 0, req);
3040         if (error || req->newptr == NULL)
3041                 goto back;
3042
3043         if (v <= 0) {
3044                 error = EINVAL;
3045                 goto back;
3046         }
3047
3048         if (v != sc->re_sim_time) {
3049                 sc->re_sim_time = v;
3050
3051                 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) ==
3052                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3053 #ifdef foo
3054                         int reg;
3055
3056                         /*
3057                          * Following code causes various strange
3058                          * performance problems.  Hmm ...
3059                          */
3060                         CSR_WRITE_2(sc, RE_IMR, 0);
3061                         if (!RE_IS_8139CP(sc))
3062                                 reg = RE_TIMERINT_8169;
3063                         else
3064                                 reg = RE_TIMERINT;
3065                         CSR_WRITE_4(sc, reg, 0);
3066                         CSR_READ_4(sc, reg); /* flush */
3067
3068                         CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3069                         re_setup_sim_im(sc);
3070 #else
3071                         re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3072                         DELAY(10);
3073                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3074 #endif
3075                 }
3076         }
3077 back:
3078         lwkt_serialize_exit(ifp->if_serializer);
3079         return error;
3080 }
3081
3082 static int
3083 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3084 {
3085         struct re_softc *sc = arg1;
3086         struct ifnet *ifp = &sc->arpcom.ac_if;
3087         int error, v;
3088
3089         lwkt_serialize_enter(ifp->if_serializer);
3090
3091         v = sc->re_imtype;
3092         error = sysctl_handle_int(oidp, &v, 0, req);
3093         if (error || req->newptr == NULL)
3094                 goto back;
3095
3096         if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3097                 error = EINVAL;
3098                 goto back;
3099         }
3100         if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3101                 /* Can't do hardware interrupt moderation */
3102                 error = EOPNOTSUPP;
3103                 goto back;
3104         }
3105
3106         if (v != sc->re_imtype) {
3107                 sc->re_imtype = v;
3108                 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) ==
3109                     IFF_RUNNING)
3110                         re_setup_intr(sc, 1, sc->re_imtype);
3111         }
3112 back:
3113         lwkt_serialize_exit(ifp->if_serializer);
3114         return error;
3115 }
3116
3117 static void
3118 re_setup_hw_im(struct re_softc *sc)
3119 {
3120         KKASSERT(sc->re_caps & RE_C_HWIM);
3121
3122         /*
3123          * Interrupt moderation
3124          *
3125          * 0xABCD
3126          * A - unknown (maybe TX related)
3127          * B - TX timer (unit: 25us)
3128          * C - unknown (maybe RX related)
3129          * D - RX timer (unit: 25us)
3130          *
3131          *
3132          * re(4)'s interrupt moderation is actually controlled by
3133          * two variables, like most other NICs (bge, bce etc.)
3134          * o  timer
3135          * o  number of packets [P]
3136          *
3137          * The logic relationship between these two variables is
3138          * similar to other NICs too:
3139          * if (timer expire || packets > [P])
3140          *     Interrupt is delivered
3141          *
3142          * Currently we only know how to set 'timer', but not
3143          * 'number of packets', which should be ~30, as far as I
3144          * tested (sink ~900Kpps, interrupt rate is 30KHz)
3145          */
3146         CSR_WRITE_2(sc, RE_IM,
3147                     RE_IM_RXTIME(sc->re_rx_time) |
3148                     RE_IM_TXTIME(sc->re_tx_time) |
3149                     RE_IM_MAGIC);
3150 }
3151
3152 static void
3153 re_disable_hw_im(struct re_softc *sc)
3154 {
3155         if (sc->re_caps & RE_C_HWIM)
3156                 CSR_WRITE_2(sc, RE_IM, 0);
3157 }
3158
3159 static void
3160 re_setup_sim_im(struct re_softc *sc)
3161 {
3162         if (!RE_IS_8139CP(sc)) {
3163                 uint32_t ticks;
3164
3165                 /*
3166                  * Datasheet says tick decreases at bus speed,
3167                  * but it seems the clock runs a little bit
3168                  * faster, so we do some compensation here.
3169                  */
3170                 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3171                 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3172         } else {
3173                 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3174         }
3175         CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3176         sc->re_flags |= RE_F_TIMER_INTR;
3177 }
3178
3179 static void
3180 re_disable_sim_im(struct re_softc *sc)
3181 {
3182         if (!RE_IS_8139CP(sc))
3183                 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3184         else
3185                 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3186         sc->re_flags &= ~RE_F_TIMER_INTR;
3187 }
3188
3189 static void
3190 re_config_imtype(struct re_softc *sc, int imtype)
3191 {
3192         switch (imtype) {
3193         case RE_IMTYPE_HW:
3194                 KKASSERT(sc->re_caps & RE_C_HWIM);
3195                 /* FALL THROUGH */
3196         case RE_IMTYPE_NONE:
3197                 sc->re_intrs = RE_INTRS;
3198                 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3199                                 RE_ISR_RX_OVERRUN;
3200                 sc->re_tx_ack = RE_ISR_TX_OK;
3201                 break;
3202
3203         case RE_IMTYPE_SIM:
3204                 sc->re_intrs = RE_INTRS_TIMER;
3205                 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3206                 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3207                 break;
3208
3209         default:
3210                 panic("%s: unknown imtype %d",
3211                       sc->arpcom.ac_if.if_xname, imtype);
3212         }
3213 }
3214
3215 static void
3216 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3217 {
3218         re_config_imtype(sc, imtype);
3219
3220         if (enable_intrs)
3221                 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3222         else
3223                 CSR_WRITE_2(sc, RE_IMR, 0);
3224
3225         sc->re_npoll.ifpc_stcount = 0;
3226
3227         switch (imtype) {
3228         case RE_IMTYPE_NONE:
3229                 re_disable_sim_im(sc);
3230                 re_disable_hw_im(sc);
3231                 break;
3232
3233         case RE_IMTYPE_HW:
3234                 KKASSERT(sc->re_caps & RE_C_HWIM);
3235                 re_disable_sim_im(sc);
3236                 re_setup_hw_im(sc);
3237                 break;
3238
3239         case RE_IMTYPE_SIM:
3240                 re_disable_hw_im(sc);
3241                 re_setup_sim_im(sc);
3242                 break;
3243
3244         default:
3245                 panic("%s: unknown imtype %d",
3246                       sc->arpcom.ac_if.if_xname, imtype);
3247         }
3248 }
3249
3250 static void
3251 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3252 {
3253         int i;
3254
3255         if (sc->re_macver == RE_MACVER_11 ||
3256             sc->re_macver == RE_MACVER_12 ||
3257             sc->re_macver == RE_MACVER_30 ||
3258             sc->re_macver == RE_MACVER_31) {
3259                 uint16_t re_did;
3260
3261                 re_get_eewidth(sc);
3262                 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3263                 if (re_did == 0x8128) {
3264                         uint16_t as[ETHER_ADDR_LEN / 2];
3265                         int eaddr_off;
3266
3267                         if (sc->re_macver == RE_MACVER_30 ||
3268                             sc->re_macver == RE_MACVER_31)
3269                                 eaddr_off = RE_EE_EADDR1;
3270                         else
3271                                 eaddr_off = RE_EE_EADDR0;
3272
3273                         /*
3274                          * Get station address from the EEPROM.
3275                          */
3276                         re_read_eeprom(sc, (caddr_t)as, eaddr_off, 3);
3277                         for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3278                                 as[i] = le16toh(as[i]);
3279                         bcopy(as, eaddr, ETHER_ADDR_LEN);
3280                         return;
3281                 }
3282         }
3283
3284         /*
3285          * Get station address from IDRx.
3286          */
3287         for (i = 0; i < ETHER_ADDR_LEN; ++i)
3288                 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3289 }
3290
3291 static int
3292 re_jpool_alloc(struct re_softc *sc)
3293 {
3294         struct re_list_data *ldata = &sc->re_ldata;
3295         struct re_jbuf *jbuf;
3296         bus_addr_t paddr;
3297         bus_size_t jpool_size;
3298         bus_dmamem_t dmem;
3299         caddr_t buf;
3300         int i, error;
3301
3302         lwkt_serialize_init(&ldata->re_jbuf_serializer);
3303
3304         ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3305                                  M_DEVBUF, M_WAITOK | M_ZERO);
3306
3307         jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3308
3309         error = bus_dmamem_coherent(sc->re_parent_tag,
3310                         RE_RXBUF_ALIGN, 0,
3311                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3312                         jpool_size, BUS_DMA_WAITOK, &dmem);
3313         if (error) {
3314                 device_printf(sc->re_dev, "could not allocate jumbo memory\n");
3315                 return error;
3316         }
3317         ldata->re_jpool_tag = dmem.dmem_tag;
3318         ldata->re_jpool_map = dmem.dmem_map;
3319         ldata->re_jpool = dmem.dmem_addr;
3320         paddr = dmem.dmem_busaddr;
3321
3322         /* ..and split it into 9KB chunks */
3323         SLIST_INIT(&ldata->re_jbuf_free);
3324
3325         buf = ldata->re_jpool;
3326         for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3327                 jbuf = &ldata->re_jbuf[i];
3328
3329                 jbuf->re_sc = sc;
3330                 jbuf->re_inuse = 0;
3331                 jbuf->re_slot = i;
3332                 jbuf->re_buf = buf;
3333                 jbuf->re_paddr = paddr;
3334
3335                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3336
3337                 buf += RE_JBUF_SIZE;
3338                 paddr += RE_JBUF_SIZE;
3339         }
3340         return 0;
3341 }
3342
3343 static void
3344 re_jpool_free(struct re_softc *sc)
3345 {
3346         struct re_list_data *ldata = &sc->re_ldata;
3347
3348         if (ldata->re_jpool_tag != NULL) {
3349                 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3350                 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3351                                 ldata->re_jpool_map);
3352                 bus_dma_tag_destroy(ldata->re_jpool_tag);
3353                 ldata->re_jpool_tag = NULL;
3354         }
3355
3356         if (ldata->re_jbuf != NULL) {
3357                 kfree(ldata->re_jbuf, M_DEVBUF);
3358                 ldata->re_jbuf = NULL;
3359         }
3360 }
3361
3362 static struct re_jbuf *
3363 re_jbuf_alloc(struct re_softc *sc)
3364 {
3365         struct re_list_data *ldata = &sc->re_ldata;
3366         struct re_jbuf *jbuf;
3367
3368         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3369
3370         jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3371         if (jbuf != NULL) {
3372                 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3373                 jbuf->re_inuse = 1;
3374         }
3375
3376         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3377
3378         return jbuf;
3379 }
3380
3381 static void
3382 re_jbuf_free(void *arg)
3383 {
3384         struct re_jbuf *jbuf = arg;
3385         struct re_softc *sc = jbuf->re_sc;
3386         struct re_list_data *ldata = &sc->re_ldata;
3387
3388         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3389                 panic("%s: free wrong jumbo buffer",
3390                       sc->arpcom.ac_if.if_xname);
3391         } else if (jbuf->re_inuse == 0) {
3392                 panic("%s: jumbo buffer already freed",
3393                       sc->arpcom.ac_if.if_xname);
3394         }
3395
3396         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3397         atomic_subtract_int(&jbuf->re_inuse, 1);
3398         if (jbuf->re_inuse == 0)
3399                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3400         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3401 }
3402
3403 static void
3404 re_jbuf_ref(void *arg)
3405 {
3406         struct re_jbuf *jbuf = arg;
3407         struct re_softc *sc = jbuf->re_sc;
3408         struct re_list_data *ldata = &sc->re_ldata;
3409
3410         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3411                 panic("%s: ref wrong jumbo buffer",
3412                       sc->arpcom.ac_if.if_xname);
3413         } else if (jbuf->re_inuse == 0) {
3414                 panic("%s: jumbo buffer already freed",
3415                       sc->arpcom.ac_if.if_xname);
3416         }
3417         atomic_add_int(&jbuf->re_inuse, 1);
3418 }