2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
38 * for FreeBSD. Datasheets are available from:
40 * http://www.national.com/ds/DP/DP83820.pdf
41 * http://www.national.com/ds/DP/DP83821.pdf
43 * These chips are used on several low cost gigabit ethernet NICs
44 * sold by D-Link, Addtron, SMC and Asante. Both parts are
45 * virtually the same, except the 83820 is a 64-bit/32-bit part,
46 * while the 83821 is 32-bit only.
48 * Many cards also use National gigE transceivers, such as the
49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
50 * contains a full register description that applies to all of these
53 * http://www.national.com/ds/DP/DP83861.pdf
55 * Written by Bill Paul <wpaul@bsdi.com>
56 * BSDi Open Source Solutions
60 * The NatSemi DP83820 and 83821 controllers are enhanced versions
61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
66 * matching buffers, one perfect address filter buffer and interrupt
67 * moderation. The 83820 supports both 64-bit and 32-bit addressing
68 * and data transfers: the 64-bit support can be toggled on or off
69 * via software. This affects the size of certain fields in the DMA
72 * There are two bugs/misfeatures in the 83820/83821 that I have
75 * - Receive buffers must be aligned on 64-bit boundaries, which means
76 * you must resort to copying data in order to fix up the payload
79 * - In order to transmit jumbo frames larger than 8170 bytes, you have
80 * to turn off transmit checksum offloading, because the chip can't
81 * compute the checksum on an outgoing frame unless it fits entirely
82 * within the TX FIFO, which is only 8192 bytes in size. If you have
83 * TX checksum offload enabled and you transmit attempt to transmit a
84 * frame larger than 8170 bytes, the transmitter will wedge.
86 * To work around the latter problem, TX checksum offload is disabled
87 * if the user selects an MTU larger than 8152 (8170 - 18).
90 #include "opt_polling.h"
92 #include <sys/param.h>
93 #include <sys/systm.h>
94 #include <sys/sockio.h>
96 #include <sys/malloc.h>
97 #include <sys/kernel.h>
98 #include <sys/interrupt.h>
99 #include <sys/socket.h>
100 #include <sys/serialize.h>
102 #include <sys/rman.h>
103 #include <sys/thread2.h>
106 #include <net/ifq_var.h>
107 #include <net/if_arp.h>
108 #include <net/ethernet.h>
109 #include <net/if_dl.h>
110 #include <net/if_media.h>
111 #include <net/if_types.h>
112 #include <net/vlan/if_vlan_var.h>
113 #include <net/vlan/if_vlan_ether.h>
117 #include <vm/vm.h> /* for vtophys */
118 #include <vm/pmap.h> /* for vtophys */
120 #include <dev/netif/mii_layer/mii.h>
121 #include <dev/netif/mii_layer/miivar.h>
123 #include <bus/pci/pcidevs.h>
124 #include <bus/pci/pcireg.h>
125 #include <bus/pci/pcivar.h>
127 #define NGE_USEIOSPACE
129 #include "if_ngereg.h"
132 /* "controller miibus0" required. See GENERIC if you get errors here. */
133 #include "miibus_if.h"
135 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
138 * Various supported device vendors/types and their names.
140 static struct nge_type nge_devs[] = {
141 { PCI_VENDOR_NS, PCI_PRODUCT_NS_DP83820,
142 "National Semiconductor Gigabit Ethernet" },
146 static int nge_probe(device_t);
147 static int nge_attach(device_t);
148 static int nge_detach(device_t);
150 static int nge_alloc_jumbo_mem(struct nge_softc *);
151 static struct nge_jslot
152 *nge_jalloc(struct nge_softc *);
153 static void nge_jfree(void *);
154 static void nge_jref(void *);
156 static int nge_newbuf(struct nge_softc *, struct nge_desc *,
158 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
159 static void nge_rxeof(struct nge_softc *);
160 static void nge_txeof(struct nge_softc *);
161 static void nge_intr(void *);
162 static void nge_tick(void *);
163 static void nge_start(struct ifnet *);
164 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
165 static void nge_init(void *);
166 static void nge_stop(struct nge_softc *);
167 static void nge_watchdog(struct ifnet *);
168 static void nge_shutdown(device_t);
169 static int nge_ifmedia_upd(struct ifnet *);
170 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
172 static void nge_delay(struct nge_softc *);
173 static void nge_eeprom_idle(struct nge_softc *);
174 static void nge_eeprom_putbyte(struct nge_softc *, int);
175 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
176 static void nge_read_eeprom(struct nge_softc *, void *, int, int);
178 static void nge_mii_sync(struct nge_softc *);
179 static void nge_mii_send(struct nge_softc *, uint32_t, int);
180 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
181 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
183 static int nge_miibus_readreg(device_t, int, int);
184 static int nge_miibus_writereg(device_t, int, int, int);
185 static void nge_miibus_statchg(device_t);
187 static void nge_setmulti(struct nge_softc *);
188 static void nge_reset(struct nge_softc *);
189 static int nge_list_rx_init(struct nge_softc *);
190 static int nge_list_tx_init(struct nge_softc *);
191 #ifdef DEVICE_POLLING
192 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
195 #ifdef NGE_USEIOSPACE
196 #define NGE_RES SYS_RES_IOPORT
197 #define NGE_RID NGE_PCI_LOIO
199 #define NGE_RES SYS_RES_MEMORY
200 #define NGE_RID NGE_PCI_LOMEM
203 static device_method_t nge_methods[] = {
204 /* Device interface */
205 DEVMETHOD(device_probe, nge_probe),
206 DEVMETHOD(device_attach, nge_attach),
207 DEVMETHOD(device_detach, nge_detach),
208 DEVMETHOD(device_shutdown, nge_shutdown),
211 DEVMETHOD(bus_print_child, bus_generic_print_child),
212 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
215 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
216 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
217 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
222 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
223 static devclass_t nge_devclass;
225 DECLARE_DUMMY_MODULE(if_nge);
226 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
227 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, NULL, NULL);
228 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, NULL, NULL);
230 #define NGE_SETBIT(sc, reg, x) \
231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
233 #define NGE_CLRBIT(sc, reg, x) \
234 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
237 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
240 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
243 nge_delay(struct nge_softc *sc)
247 for (idx = (300 / 33) + 1; idx > 0; idx--)
248 CSR_READ_4(sc, NGE_CSR);
252 nge_eeprom_idle(struct nge_softc *sc)
256 SIO_SET(NGE_MEAR_EE_CSEL);
258 SIO_SET(NGE_MEAR_EE_CLK);
261 for (i = 0; i < 25; i++) {
262 SIO_CLR(NGE_MEAR_EE_CLK);
264 SIO_SET(NGE_MEAR_EE_CLK);
268 SIO_CLR(NGE_MEAR_EE_CLK);
270 SIO_CLR(NGE_MEAR_EE_CSEL);
272 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
276 * Send a read command and address to the EEPROM, check for ACK.
279 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
283 d = addr | NGE_EECMD_READ;
286 * Feed in each bit and stobe the clock.
288 for (i = 0x400; i; i >>= 1) {
290 SIO_SET(NGE_MEAR_EE_DIN);
292 SIO_CLR(NGE_MEAR_EE_DIN);
294 SIO_SET(NGE_MEAR_EE_CLK);
296 SIO_CLR(NGE_MEAR_EE_CLK);
302 * Read a word of data stored in the EEPROM at address 'addr.'
305 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
310 /* Force EEPROM to idle state. */
313 /* Enter EEPROM access mode. */
315 SIO_CLR(NGE_MEAR_EE_CLK);
317 SIO_SET(NGE_MEAR_EE_CSEL);
321 * Send address of word we want to read.
323 nge_eeprom_putbyte(sc, addr);
326 * Start reading bits from EEPROM.
328 for (i = 0x8000; i; i >>= 1) {
329 SIO_SET(NGE_MEAR_EE_CLK);
331 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
334 SIO_CLR(NGE_MEAR_EE_CLK);
338 /* Turn off EEPROM access mode. */
345 * Read a sequence of words from the EEPROM.
348 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
351 uint16_t word = 0, *ptr;
353 for (i = 0; i < cnt; i++) {
354 nge_eeprom_getword(sc, off + i, &word);
355 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
361 * Sync the PHYs by setting data bit and strobing the clock 32 times.
364 nge_mii_sync(struct nge_softc *sc)
368 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
370 for (i = 0; i < 32; i++) {
371 SIO_SET(NGE_MEAR_MII_CLK);
373 SIO_CLR(NGE_MEAR_MII_CLK);
379 * Clock a series of bits through the MII.
382 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
386 SIO_CLR(NGE_MEAR_MII_CLK);
388 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
390 SIO_SET(NGE_MEAR_MII_DATA);
392 SIO_CLR(NGE_MEAR_MII_DATA);
394 SIO_CLR(NGE_MEAR_MII_CLK);
396 SIO_SET(NGE_MEAR_MII_CLK);
401 * Read an PHY register through the MII.
404 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
409 * Set up frame for RX.
411 frame->mii_stdelim = NGE_MII_STARTDELIM;
412 frame->mii_opcode = NGE_MII_READOP;
413 frame->mii_turnaround = 0;
416 CSR_WRITE_4(sc, NGE_MEAR, 0);
421 SIO_SET(NGE_MEAR_MII_DIR);
426 * Send command/address info.
428 nge_mii_send(sc, frame->mii_stdelim, 2);
429 nge_mii_send(sc, frame->mii_opcode, 2);
430 nge_mii_send(sc, frame->mii_phyaddr, 5);
431 nge_mii_send(sc, frame->mii_regaddr, 5);
434 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
436 SIO_SET(NGE_MEAR_MII_CLK);
440 SIO_CLR(NGE_MEAR_MII_DIR);
442 SIO_CLR(NGE_MEAR_MII_CLK);
444 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
445 SIO_SET(NGE_MEAR_MII_CLK);
449 * Now try reading data bits. If the ack failed, we still
450 * need to clock through 16 cycles to keep the PHY(s) in sync.
453 for(i = 0; i < 16; i++) {
454 SIO_CLR(NGE_MEAR_MII_CLK);
456 SIO_SET(NGE_MEAR_MII_CLK);
462 for (i = 0x8000; i; i >>= 1) {
463 SIO_CLR(NGE_MEAR_MII_CLK);
466 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
467 frame->mii_data |= i;
470 SIO_SET(NGE_MEAR_MII_CLK);
475 SIO_CLR(NGE_MEAR_MII_CLK);
477 SIO_SET(NGE_MEAR_MII_CLK);
486 * Write to a PHY register through the MII.
489 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
492 * Set up frame for TX.
495 frame->mii_stdelim = NGE_MII_STARTDELIM;
496 frame->mii_opcode = NGE_MII_WRITEOP;
497 frame->mii_turnaround = NGE_MII_TURNAROUND;
500 * Turn on data output.
502 SIO_SET(NGE_MEAR_MII_DIR);
506 nge_mii_send(sc, frame->mii_stdelim, 2);
507 nge_mii_send(sc, frame->mii_opcode, 2);
508 nge_mii_send(sc, frame->mii_phyaddr, 5);
509 nge_mii_send(sc, frame->mii_regaddr, 5);
510 nge_mii_send(sc, frame->mii_turnaround, 2);
511 nge_mii_send(sc, frame->mii_data, 16);
514 SIO_SET(NGE_MEAR_MII_CLK);
516 SIO_CLR(NGE_MEAR_MII_CLK);
522 SIO_CLR(NGE_MEAR_MII_DIR);
528 nge_miibus_readreg(device_t dev, int phy, int reg)
530 struct nge_softc *sc = device_get_softc(dev);
531 struct nge_mii_frame frame;
533 bzero((char *)&frame, sizeof(frame));
535 frame.mii_phyaddr = phy;
536 frame.mii_regaddr = reg;
537 nge_mii_readreg(sc, &frame);
539 return(frame.mii_data);
543 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
545 struct nge_softc *sc = device_get_softc(dev);
546 struct nge_mii_frame frame;
548 bzero((char *)&frame, sizeof(frame));
550 frame.mii_phyaddr = phy;
551 frame.mii_regaddr = reg;
552 frame.mii_data = data;
553 nge_mii_writereg(sc, &frame);
559 nge_miibus_statchg(device_t dev)
561 struct nge_softc *sc = device_get_softc(dev);
562 struct mii_data *mii;
566 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
568 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
569 if (status == 0 || status & NGE_TBIANAR_FDX) {
570 NGE_SETBIT(sc, NGE_TX_CFG,
571 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
572 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
574 NGE_CLRBIT(sc, NGE_TX_CFG,
575 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
576 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
578 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
580 NGE_CLRBIT(sc, NGE_TX_CFG,
581 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
582 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
584 NGE_SETBIT(sc, NGE_TX_CFG,
585 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
586 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
589 mii = device_get_softc(sc->nge_miibus);
591 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
592 NGE_SETBIT(sc, NGE_TX_CFG,
593 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
594 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
596 NGE_CLRBIT(sc, NGE_TX_CFG,
597 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
598 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
601 /* If we have a 1000Mbps link, set the mode_1000 bit. */
602 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
603 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
604 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
606 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
612 nge_setmulti(struct nge_softc *sc)
614 struct ifnet *ifp = &sc->arpcom.ac_if;
615 struct ifmultiaddr *ifma;
616 uint32_t filtsave, h = 0, i;
619 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
620 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
621 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
622 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
627 * We have to explicitly enable the multicast hash table
628 * on the NatSemi chip if we want to use it, which we do.
629 * We also have to tell it that we don't want to use the
630 * hash table for matching unicast addresses.
632 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
633 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
634 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
636 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
638 /* first, zot all the existing hash bits */
639 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
640 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
641 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
645 * From the 11 bits returned by the crc routine, the top 7
646 * bits represent the 16-bit word in the mcast hash table
647 * that needs to be updated, and the lower 4 bits represent
648 * which bit within that byte needs to be set.
650 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
651 if (ifma->ifma_addr->sa_family != AF_LINK)
653 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
654 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
655 index = (h >> 4) & 0x7F;
657 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
658 NGE_FILTADDR_MCAST_LO + (index * 2));
659 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
662 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
666 nge_reset(struct nge_softc *sc)
670 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
672 for (i = 0; i < NGE_TIMEOUT; i++) {
673 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
677 if (i == NGE_TIMEOUT)
678 kprintf("nge%d: reset never completed\n", sc->nge_unit);
680 /* Wait a little while for the chip to get its brains in order. */
684 * If this is a NetSemi chip, make sure to clear
687 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
688 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
692 * Probe for an NatSemi chip. Check the PCI vendor and device
693 * IDs against our list and return a device name if we find a match.
696 nge_probe(device_t dev)
699 uint16_t vendor, product;
701 vendor = pci_get_vendor(dev);
702 product = pci_get_device(dev);
704 for (t = nge_devs; t->nge_name != NULL; t++) {
705 if (vendor == t->nge_vid && product == t->nge_did) {
706 device_set_desc(dev, t->nge_name);
715 * Attach the interface. Allocate softc structures, do ifmedia
716 * setup and ethernet/BPF attach.
719 nge_attach(device_t dev)
721 struct nge_softc *sc;
723 uint8_t eaddr[ETHER_ADDR_LEN];
725 int error = 0, rid, unit;
726 const char *sep = "";
728 sc = device_get_softc(dev);
729 unit = device_get_unit(dev);
730 callout_init(&sc->nge_stat_timer);
731 lwkt_serialize_init(&sc->nge_jslot_serializer);
734 * Handle power management nonsense.
736 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
737 if (command == 0x01) {
738 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
739 if (command & NGE_PSTATE_MASK) {
740 uint32_t iobase, membase, irq;
742 /* Save important PCI config data. */
743 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
744 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
745 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
747 /* Reset the power state. */
748 kprintf("nge%d: chip is in D%d power mode "
749 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
750 command &= 0xFFFFFFFC;
751 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
753 /* Restore PCI config data. */
754 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
755 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
756 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
761 * Map control/status registers.
763 command = pci_read_config(dev, PCIR_COMMAND, 4);
764 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
765 pci_write_config(dev, PCIR_COMMAND, command, 4);
766 command = pci_read_config(dev, PCIR_COMMAND, 4);
768 #ifdef NGE_USEIOSPACE
769 if (!(command & PCIM_CMD_PORTEN)) {
770 kprintf("nge%d: failed to enable I/O ports!\n", unit);
775 if (!(command & PCIM_CMD_MEMEN)) {
776 kprintf("nge%d: failed to enable memory mapping!\n", unit);
783 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
785 if (sc->nge_res == NULL) {
786 kprintf("nge%d: couldn't map ports/memory\n", unit);
791 sc->nge_btag = rman_get_bustag(sc->nge_res);
792 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
794 /* Allocate interrupt */
796 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
797 RF_SHAREABLE | RF_ACTIVE);
799 if (sc->nge_irq == NULL) {
800 kprintf("nge%d: couldn't map interrupt\n", unit);
805 /* Reset the adapter. */
809 * Get station address from the EEPROM.
811 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
812 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
813 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
817 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
818 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
820 if (sc->nge_ldata == NULL) {
821 kprintf("nge%d: no memory for list buffers!\n", unit);
826 /* Try to allocate memory for jumbo buffers. */
827 if (nge_alloc_jumbo_mem(sc)) {
828 kprintf("nge%d: jumbo buffer allocation failed\n",
834 ifp = &sc->arpcom.ac_if;
836 if_initname(ifp, "nge", unit);
837 ifp->if_mtu = ETHERMTU;
838 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
839 ifp->if_ioctl = nge_ioctl;
840 ifp->if_start = nge_start;
841 #ifdef DEVICE_POLLING
842 ifp->if_poll = nge_poll;
844 ifp->if_watchdog = nge_watchdog;
845 ifp->if_init = nge_init;
846 ifp->if_baudrate = 1000000000;
847 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
848 ifq_set_ready(&ifp->if_snd);
849 ifp->if_hwassist = NGE_CSUM_FEATURES;
850 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
851 ifp->if_capenable = ifp->if_capabilities;
856 if (mii_phy_probe(dev, &sc->nge_miibus,
857 nge_ifmedia_upd, nge_ifmedia_sts)) {
858 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
860 device_printf(dev, "Using TBI\n");
862 sc->nge_miibus = dev;
864 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
866 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
867 #define PRINT(s) kprintf("%s%s", sep, s); sep = ", "
868 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
869 device_printf(dev, " ");
870 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
872 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
873 PRINT("1000baseSX-FDX");
874 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
880 ifmedia_set(&sc->nge_ifmedia,
881 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
883 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
885 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
886 | NGE_GPIO_GP3_OUTENB
887 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
890 kprintf("nge%d: MII without any PHY!\n", sc->nge_unit);
897 * Call MI attach routine.
899 ether_ifattach(ifp, eaddr, NULL);
901 error = bus_setup_intr(dev, sc->nge_irq, INTR_MPSAFE,
902 nge_intr, sc, &sc->nge_intrhand,
906 device_printf(dev, "couldn't set up irq\n");
910 ifp->if_cpuid = rman_get_cpuid(sc->nge_irq);
911 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
920 nge_detach(device_t dev)
922 struct nge_softc *sc = device_get_softc(dev);
923 struct ifnet *ifp = &sc->arpcom.ac_if;
925 if (device_is_attached(dev)) {
926 lwkt_serialize_enter(ifp->if_serializer);
929 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
930 lwkt_serialize_exit(ifp->if_serializer);
936 device_delete_child(dev, sc->nge_miibus);
937 bus_generic_detach(dev);
940 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
942 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
944 contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
947 if (sc->nge_cdata.nge_jumbo_buf)
948 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
954 * Initialize the transmit descriptors.
957 nge_list_tx_init(struct nge_softc *sc)
959 struct nge_list_data *ld;
960 struct nge_ring_data *cd;
966 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
967 if (i == (NGE_TX_LIST_CNT - 1)) {
968 ld->nge_tx_list[i].nge_nextdesc =
970 ld->nge_tx_list[i].nge_next =
971 vtophys(&ld->nge_tx_list[0]);
973 ld->nge_tx_list[i].nge_nextdesc =
974 &ld->nge_tx_list[i + 1];
975 ld->nge_tx_list[i].nge_next =
976 vtophys(&ld->nge_tx_list[i + 1]);
978 ld->nge_tx_list[i].nge_mbuf = NULL;
979 ld->nge_tx_list[i].nge_ptr = 0;
980 ld->nge_tx_list[i].nge_ctl = 0;
983 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
990 * Initialize the RX descriptors and allocate mbufs for them. Note that
991 * we arrange the descriptors in a closed ring, so that the last descriptor
992 * points back to the first.
995 nge_list_rx_init(struct nge_softc *sc)
997 struct nge_list_data *ld;
998 struct nge_ring_data *cd;
1002 cd = &sc->nge_cdata;
1004 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1005 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1007 if (i == (NGE_RX_LIST_CNT - 1)) {
1008 ld->nge_rx_list[i].nge_nextdesc =
1009 &ld->nge_rx_list[0];
1010 ld->nge_rx_list[i].nge_next =
1011 vtophys(&ld->nge_rx_list[0]);
1013 ld->nge_rx_list[i].nge_nextdesc =
1014 &ld->nge_rx_list[i + 1];
1015 ld->nge_rx_list[i].nge_next =
1016 vtophys(&ld->nge_rx_list[i + 1]);
1020 cd->nge_rx_prod = 0;
1026 * Initialize an RX descriptor and attach an MBUF cluster.
1029 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1031 struct mbuf *m_new = NULL;
1032 struct nge_jslot *buf;
1035 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1036 if (m_new == NULL) {
1037 kprintf("nge%d: no memory for rx list "
1038 "-- packet dropped!\n", sc->nge_unit);
1042 /* Allocate the jumbo buffer */
1043 buf = nge_jalloc(sc);
1046 kprintf("nge%d: jumbo allocation failed "
1047 "-- packet dropped!\n", sc->nge_unit);
1052 /* Attach the buffer to the mbuf */
1053 m_new->m_ext.ext_arg = buf;
1054 m_new->m_ext.ext_buf = buf->nge_buf;
1055 m_new->m_ext.ext_free = nge_jfree;
1056 m_new->m_ext.ext_ref = nge_jref;
1057 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1059 m_new->m_data = m_new->m_ext.ext_buf;
1060 m_new->m_flags |= M_EXT;
1061 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1064 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
1065 m_new->m_data = m_new->m_ext.ext_buf;
1068 m_adj(m_new, sizeof(uint64_t));
1070 c->nge_mbuf = m_new;
1071 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1072 c->nge_ctl = m_new->m_len;
1079 nge_alloc_jumbo_mem(struct nge_softc *sc)
1083 struct nge_jslot *entry;
1085 /* Grab a big chunk o' storage. */
1086 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1087 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1089 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1090 kprintf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1094 SLIST_INIT(&sc->nge_jfree_listhead);
1097 * Now divide it up into 9K pieces and save the addresses
1100 ptr = sc->nge_cdata.nge_jumbo_buf;
1101 for (i = 0; i < NGE_JSLOTS; i++) {
1102 entry = &sc->nge_cdata.nge_jslots[i];
1104 entry->nge_buf = ptr;
1105 entry->nge_inuse = 0;
1106 entry->nge_slot = i;
1107 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1116 * Allocate a jumbo buffer.
1118 static struct nge_jslot *
1119 nge_jalloc(struct nge_softc *sc)
1121 struct nge_jslot *entry;
1123 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1124 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1126 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1127 entry->nge_inuse = 1;
1130 kprintf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1133 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1138 * Adjust usage count on a jumbo buffer. In general this doesn't
1139 * get used much because our jumbo buffers don't get passed around
1140 * a lot, but it's implemented for correctness.
1145 struct nge_jslot *entry = (struct nge_jslot *)arg;
1146 struct nge_softc *sc = entry->nge_sc;
1149 panic("nge_jref: can't find softc pointer!");
1151 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1152 panic("nge_jref: asked to reference buffer "
1153 "that we don't manage!");
1154 else if (entry->nge_inuse == 0)
1155 panic("nge_jref: buffer already free!");
1157 atomic_add_int(&entry->nge_inuse, 1);
1161 * Release a jumbo buffer.
1164 nge_jfree(void *arg)
1166 struct nge_jslot *entry = (struct nge_jslot *)arg;
1167 struct nge_softc *sc = entry->nge_sc;
1170 panic("nge_jref: can't find softc pointer!");
1172 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry) {
1173 panic("nge_jref: asked to reference buffer "
1174 "that we don't manage!");
1175 } else if (entry->nge_inuse == 0) {
1176 panic("nge_jref: buffer already free!");
1178 lwkt_serialize_enter(&sc->nge_jslot_serializer);
1179 atomic_subtract_int(&entry->nge_inuse, 1);
1180 if (entry->nge_inuse == 0) {
1181 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead,
1184 lwkt_serialize_exit(&sc->nge_jslot_serializer);
1188 * A frame has been uploaded: pass the resulting mbuf chain up to
1189 * the higher level protocols.
1192 nge_rxeof(struct nge_softc *sc)
1195 struct ifnet *ifp = &sc->arpcom.ac_if;
1196 struct nge_desc *cur_rx;
1197 int i, total_len = 0;
1200 i = sc->nge_cdata.nge_rx_prod;
1202 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1203 struct mbuf *m0 = NULL;
1206 #ifdef DEVICE_POLLING
1207 if (ifp->if_flags & IFF_POLLING) {
1208 if (sc->rxcycles <= 0)
1212 #endif /* DEVICE_POLLING */
1214 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1215 rxstat = cur_rx->nge_rxstat;
1216 extsts = cur_rx->nge_extsts;
1217 m = cur_rx->nge_mbuf;
1218 cur_rx->nge_mbuf = NULL;
1219 total_len = NGE_RXBYTES(cur_rx);
1220 NGE_INC(i, NGE_RX_LIST_CNT);
1222 * If an error occurs, update stats, clear the
1223 * status word and leave the mbuf cluster in place:
1224 * it should simply get re-used next time this descriptor
1225 * comes up in the ring.
1227 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1229 nge_newbuf(sc, cur_rx, m);
1234 * Ok. NatSemi really screwed up here. This is the
1235 * only gigE chip I know of with alignment constraints
1236 * on receive buffers. RX buffers must be 64-bit aligned.
1240 * By popular demand, ignore the alignment problems
1241 * on the Intel x86 platform. The performance hit
1242 * incurred due to unaligned accesses is much smaller
1243 * than the hit produced by forcing buffer copies all
1244 * the time, especially with jumbo frames. We still
1245 * need to fix up the alignment everywhere else though.
1247 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1249 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1250 total_len + ETHER_ALIGN, 0, ifp, NULL);
1251 nge_newbuf(sc, cur_rx, m);
1253 kprintf("nge%d: no receive buffers "
1254 "available -- packet dropped!\n",
1259 m_adj(m0, ETHER_ALIGN);
1263 m->m_pkthdr.rcvif = ifp;
1264 m->m_pkthdr.len = m->m_len = total_len;
1270 /* Do IP checksum checking. */
1271 if (extsts & NGE_RXEXTSTS_IPPKT)
1272 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1273 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1274 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1275 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1276 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1277 (extsts & NGE_RXEXTSTS_UDPPKT &&
1278 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1279 m->m_pkthdr.csum_flags |=
1280 CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
1281 CSUM_FRAG_NOT_CHECKED;
1282 m->m_pkthdr.csum_data = 0xffff;
1286 * If we received a packet with a vlan tag, pass it
1287 * to vlan_input() instead of ether_input().
1289 if (extsts & NGE_RXEXTSTS_VLANPKT) {
1290 m->m_flags |= M_VLANTAG;
1291 m->m_pkthdr.ether_vlantag =
1292 (extsts & NGE_RXEXTSTS_VTCI);
1294 ifp->if_input(ifp, m);
1297 sc->nge_cdata.nge_rx_prod = i;
1301 * A frame was downloaded to the chip. It's safe for us to clean up
1305 nge_txeof(struct nge_softc *sc)
1307 struct ifnet *ifp = &sc->arpcom.ac_if;
1308 struct nge_desc *cur_tx = NULL;
1311 /* Clear the timeout timer. */
1315 * Go through our tx list and free mbufs for those
1316 * frames that have been transmitted.
1318 idx = sc->nge_cdata.nge_tx_cons;
1319 while (idx != sc->nge_cdata.nge_tx_prod) {
1320 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1322 if (NGE_OWNDESC(cur_tx))
1325 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1326 sc->nge_cdata.nge_tx_cnt--;
1327 NGE_INC(idx, NGE_TX_LIST_CNT);
1331 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1333 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1334 ifp->if_collisions++;
1335 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1336 ifp->if_collisions++;
1339 ifp->if_collisions +=
1340 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1343 if (cur_tx->nge_mbuf != NULL) {
1344 m_freem(cur_tx->nge_mbuf);
1345 cur_tx->nge_mbuf = NULL;
1348 sc->nge_cdata.nge_tx_cnt--;
1349 NGE_INC(idx, NGE_TX_LIST_CNT);
1353 sc->nge_cdata.nge_tx_cons = idx;
1356 ifp->if_flags &= ~IFF_OACTIVE;
1362 struct nge_softc *sc = xsc;
1363 struct ifnet *ifp = &sc->arpcom.ac_if;
1364 struct mii_data *mii;
1366 lwkt_serialize_enter(ifp->if_serializer);
1369 if (sc->nge_link == 0) {
1370 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1371 & NGE_TBIBMSR_ANEG_DONE) {
1372 kprintf("nge%d: gigabit link up\n",
1374 nge_miibus_statchg(sc->nge_miibus);
1376 if (!ifq_is_empty(&ifp->if_snd))
1381 mii = device_get_softc(sc->nge_miibus);
1384 if (sc->nge_link == 0) {
1385 if (mii->mii_media_status & IFM_ACTIVE &&
1386 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1388 if (IFM_SUBTYPE(mii->mii_media_active)
1390 kprintf("nge%d: gigabit link up\n",
1392 if (!ifq_is_empty(&ifp->if_snd))
1397 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1399 lwkt_serialize_exit(ifp->if_serializer);
1402 #ifdef DEVICE_POLLING
1405 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1407 struct nge_softc *sc = ifp->if_softc;
1411 /* disable interrupts */
1412 CSR_WRITE_4(sc, NGE_IER, 0);
1414 case POLL_DEREGISTER:
1415 /* enable interrupts */
1416 CSR_WRITE_4(sc, NGE_IER, 1);
1420 * On the nge, reading the status register also clears it.
1421 * So before returning to intr mode we must make sure that all
1422 * possible pending sources of interrupts have been served.
1423 * In practice this means run to completion the *eof routines,
1424 * and then call the interrupt routine
1426 sc->rxcycles = count;
1429 if (!ifq_is_empty(&ifp->if_snd))
1432 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1435 /* Reading the ISR register clears all interrupts. */
1436 status = CSR_READ_4(sc, NGE_ISR);
1438 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1441 if (status & (NGE_ISR_RX_IDLE))
1442 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1444 if (status & NGE_ISR_SYSERR) {
1453 #endif /* DEVICE_POLLING */
1458 struct nge_softc *sc = arg;
1459 struct ifnet *ifp = &sc->arpcom.ac_if;
1462 /* Supress unwanted interrupts */
1463 if (!(ifp->if_flags & IFF_UP)) {
1468 /* Disable interrupts. */
1469 CSR_WRITE_4(sc, NGE_IER, 0);
1471 /* Data LED on for TBI mode */
1473 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1474 | NGE_GPIO_GP3_OUT);
1477 /* Reading the ISR register clears all interrupts. */
1478 status = CSR_READ_4(sc, NGE_ISR);
1480 if ((status & NGE_INTRS) == 0)
1483 if ((status & NGE_ISR_TX_DESC_OK) ||
1484 (status & NGE_ISR_TX_ERR) ||
1485 (status & NGE_ISR_TX_OK) ||
1486 (status & NGE_ISR_TX_IDLE))
1489 if ((status & NGE_ISR_RX_DESC_OK) ||
1490 (status & NGE_ISR_RX_ERR) ||
1491 (status & NGE_ISR_RX_OFLOW) ||
1492 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1493 (status & NGE_ISR_RX_IDLE) ||
1494 (status & NGE_ISR_RX_OK))
1497 if ((status & NGE_ISR_RX_IDLE))
1498 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1500 if (status & NGE_ISR_SYSERR) {
1502 ifp->if_flags &= ~IFF_RUNNING;
1507 /* mii_tick should only be called once per second */
1508 if (status & NGE_ISR_PHY_INTR) {
1510 nge_tick_serialized(sc);
1515 /* Re-enable interrupts. */
1516 CSR_WRITE_4(sc, NGE_IER, 1);
1518 if (!ifq_is_empty(&ifp->if_snd))
1521 /* Data LED off for TBI mode */
1524 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1525 & ~NGE_GPIO_GP3_OUT);
1529 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1530 * pointers to the fragment pointers.
1533 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1535 struct nge_desc *f = NULL;
1537 int frag, cur, cnt = 0;
1540 * Start packing the mbufs in this chain into
1541 * the fragment pointers. Stop when we run out
1542 * of fragments or hit the end of the mbuf chain.
1544 cur = frag = *txidx;
1546 for (m = m_head; m != NULL; m = m->m_next) {
1547 if (m->m_len != 0) {
1548 if ((NGE_TX_LIST_CNT -
1549 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1551 f = &sc->nge_ldata->nge_tx_list[frag];
1552 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1553 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1555 f->nge_ctl |= NGE_CMDSTS_OWN;
1557 NGE_INC(frag, NGE_TX_LIST_CNT);
1561 /* Caller should make sure that 'm_head' is not excessive fragmented */
1562 KASSERT(m == NULL, ("too many fragments\n"));
1564 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1565 if (m_head->m_pkthdr.csum_flags) {
1566 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1567 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1568 NGE_TXEXTSTS_IPCSUM;
1569 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1570 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1571 NGE_TXEXTSTS_TCPCSUM;
1572 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1573 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1574 NGE_TXEXTSTS_UDPCSUM;
1577 if (m_head->m_flags & M_VLANTAG) {
1578 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1579 (NGE_TXEXTSTS_VLANPKT|m_head->m_pkthdr.ether_vlantag);
1582 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1583 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1584 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1585 sc->nge_cdata.nge_tx_cnt += cnt;
1592 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1593 * to the mbuf data regions directly in the transmit lists. We also save a
1594 * copy of the pointers since the transmit list fragment pointers are
1595 * physical addresses.
1599 nge_start(struct ifnet *ifp)
1601 struct nge_softc *sc = ifp->if_softc;
1602 struct mbuf *m_head = NULL, *m_defragged;
1606 if (!sc->nge_link) {
1607 ifq_purge(&ifp->if_snd);
1611 idx = sc->nge_cdata.nge_tx_prod;
1613 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1617 while (sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1622 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1628 for (m = m_head; m != NULL; m = m->m_next)
1630 if ((NGE_TX_LIST_CNT -
1631 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) {
1632 if (m_defragged != NULL) {
1634 * Even after defragmentation, there
1635 * are still too many fragments, so
1639 ifp->if_flags |= IFF_OACTIVE;
1643 m_defragged = m_defrag(m_head, MB_DONTWAIT);
1644 if (m_defragged == NULL) {
1648 m_head = m_defragged;
1650 /* Recount # of fragments */
1654 nge_encap(sc, m_head, &idx);
1657 ETHER_BPF_MTAP(ifp, m_head);
1664 sc->nge_cdata.nge_tx_prod = idx;
1665 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1668 * Set a timeout in case the chip goes out to lunch.
1676 struct nge_softc *sc = xsc;
1677 struct ifnet *ifp = &sc->arpcom.ac_if;
1678 struct mii_data *mii;
1680 if (ifp->if_flags & IFF_RUNNING) {
1685 * Cancel pending I/O and free all RX/TX buffers.
1688 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1693 mii = device_get_softc(sc->nge_miibus);
1695 /* Set MAC address */
1696 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1697 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1698 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1699 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1700 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1701 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1702 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1703 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1704 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1706 /* Init circular RX list. */
1707 if (nge_list_rx_init(sc) == ENOBUFS) {
1708 kprintf("nge%d: initialization failed: no "
1709 "memory for rx buffers\n", sc->nge_unit);
1715 * Init tx descriptors.
1717 nge_list_tx_init(sc);
1720 * For the NatSemi chip, we have to explicitly enable the
1721 * reception of ARP frames, as well as turn on the 'perfect
1722 * match' filter where we store the station address, otherwise
1723 * we won't receive unicasts meant for this host.
1725 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1726 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1728 /* If we want promiscuous mode, set the allframes bit. */
1729 if (ifp->if_flags & IFF_PROMISC)
1730 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1732 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1735 * Set the capture broadcast bit to capture broadcast frames.
1737 if (ifp->if_flags & IFF_BROADCAST)
1738 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1740 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1743 * Load the multicast filter.
1747 /* Turn the receive filter on */
1748 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1751 * Load the address of the RX and TX lists.
1753 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1754 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1755 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1756 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1758 /* Set RX configuration */
1759 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1761 * Enable hardware checksum validation for all IPv4
1762 * packets, do not reject packets with bad checksums.
1764 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1767 * Tell the chip to detect and strip VLAN tag info from
1768 * received frames. The tag will be provided in the extsts
1769 * field in the RX descriptors.
1771 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1772 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1774 /* Set TX configuration */
1775 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1778 * Enable TX IPv4 checksumming on a per-packet basis.
1780 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1783 * Tell the chip to insert VLAN tags on a per-packet basis as
1784 * dictated by the code in the frame encapsulation routine.
1786 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1788 /* Set full/half duplex mode. */
1790 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1792 NGE_SETBIT(sc, NGE_TX_CFG,
1793 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1794 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1796 NGE_CLRBIT(sc, NGE_TX_CFG,
1797 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1798 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1801 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1802 NGE_SETBIT(sc, NGE_TX_CFG,
1803 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1804 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1806 NGE_CLRBIT(sc, NGE_TX_CFG,
1807 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1808 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1813 * Enable the delivery of PHY interrupts based on
1814 * link/speed/duplex status changes. Also enable the
1815 * extsts field in the DMA descriptors (needed for
1816 * TCP/IP checksum offload on transmit).
1818 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1819 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1822 * Configure interrupt holdoff (moderation). We can
1823 * have the chip delay interrupt delivery for a certain
1824 * period. Units are in 100us, and the max setting
1825 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1827 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1830 * Enable interrupts.
1832 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1833 #ifdef DEVICE_POLLING
1835 * ... only enable interrupts if we are not polling, make sure
1836 * they are off otherwise.
1838 if (ifp->if_flags & IFF_POLLING)
1839 CSR_WRITE_4(sc, NGE_IER, 0);
1841 #endif /* DEVICE_POLLING */
1842 CSR_WRITE_4(sc, NGE_IER, 1);
1844 /* Enable receiver and transmitter. */
1845 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1846 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1848 nge_ifmedia_upd(ifp);
1850 ifp->if_flags |= IFF_RUNNING;
1851 ifp->if_flags &= ~IFF_OACTIVE;
1855 * Set media options.
1858 nge_ifmedia_upd(struct ifnet *ifp)
1860 struct nge_softc *sc = ifp->if_softc;
1861 struct mii_data *mii;
1864 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1866 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1867 CSR_READ_4(sc, NGE_TBI_ANAR)
1868 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1869 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1870 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1871 | NGE_TBIBMCR_RESTART_ANEG);
1872 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1873 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1874 & IFM_GMASK) == IFM_FDX) {
1875 NGE_SETBIT(sc, NGE_TX_CFG,
1876 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1877 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1879 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1880 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1882 NGE_CLRBIT(sc, NGE_TX_CFG,
1883 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1884 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1886 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1887 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1890 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1891 & ~NGE_GPIO_GP3_OUT);
1893 mii = device_get_softc(sc->nge_miibus);
1895 if (mii->mii_instance) {
1896 struct mii_softc *miisc;
1897 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1898 miisc = LIST_NEXT(miisc, mii_list))
1899 mii_phy_reset(miisc);
1908 * Report current media status.
1911 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1913 struct nge_softc *sc = ifp->if_softc;
1914 struct mii_data *mii;
1917 ifmr->ifm_status = IFM_AVALID;
1918 ifmr->ifm_active = IFM_ETHER;
1920 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1921 ifmr->ifm_status |= IFM_ACTIVE;
1922 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1923 ifmr->ifm_active |= IFM_LOOP;
1924 if (!(CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)) {
1925 ifmr->ifm_active |= IFM_NONE;
1926 ifmr->ifm_status = 0;
1929 ifmr->ifm_active |= IFM_1000_SX;
1930 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1932 ifmr->ifm_active |= IFM_AUTO;
1933 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1934 & NGE_TBIANAR_FDX) {
1935 ifmr->ifm_active |= IFM_FDX;
1936 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1937 & NGE_TBIANAR_HDX) {
1938 ifmr->ifm_active |= IFM_HDX;
1940 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1942 ifmr->ifm_active |= IFM_FDX;
1944 ifmr->ifm_active |= IFM_HDX;
1947 mii = device_get_softc(sc->nge_miibus);
1949 ifmr->ifm_active = mii->mii_media_active;
1950 ifmr->ifm_status = mii->mii_media_status;
1955 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1957 struct nge_softc *sc = ifp->if_softc;
1958 struct ifreq *ifr = (struct ifreq *) data;
1959 struct mii_data *mii;
1964 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
1967 ifp->if_mtu = ifr->ifr_mtu;
1969 * Workaround: if the MTU is larger than
1970 * 8152 (TX FIFO size minus 64 minus 18), turn off
1971 * TX checksum offloading.
1973 if (ifr->ifr_mtu >= 8152)
1974 ifp->if_hwassist = 0;
1976 ifp->if_hwassist = NGE_CSUM_FEATURES;
1980 if (ifp->if_flags & IFF_UP) {
1981 if (ifp->if_flags & IFF_RUNNING &&
1982 ifp->if_flags & IFF_PROMISC &&
1983 !(sc->nge_if_flags & IFF_PROMISC)) {
1984 NGE_SETBIT(sc, NGE_RXFILT_CTL,
1985 NGE_RXFILTCTL_ALLPHYS|
1986 NGE_RXFILTCTL_ALLMULTI);
1987 } else if (ifp->if_flags & IFF_RUNNING &&
1988 !(ifp->if_flags & IFF_PROMISC) &&
1989 sc->nge_if_flags & IFF_PROMISC) {
1990 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1991 NGE_RXFILTCTL_ALLPHYS);
1992 if (!(ifp->if_flags & IFF_ALLMULTI))
1993 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1994 NGE_RXFILTCTL_ALLMULTI);
1996 ifp->if_flags &= ~IFF_RUNNING;
2000 if (ifp->if_flags & IFF_RUNNING)
2003 sc->nge_if_flags = ifp->if_flags;
2014 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2017 mii = device_get_softc(sc->nge_miibus);
2018 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2023 error = ether_ioctl(ifp, command, data);
2030 nge_watchdog(struct ifnet *ifp)
2032 struct nge_softc *sc = ifp->if_softc;
2035 kprintf("nge%d: watchdog timeout\n", sc->nge_unit);
2039 ifp->if_flags &= ~IFF_RUNNING;
2042 if (!ifq_is_empty(&ifp->if_snd))
2047 * Stop the adapter and free any mbufs allocated to the
2051 nge_stop(struct nge_softc *sc)
2053 struct ifnet *ifp = &sc->arpcom.ac_if;
2054 struct ifmedia_entry *ifm;
2055 struct mii_data *mii;
2056 int i, itmp, mtmp, dtmp;
2062 mii = device_get_softc(sc->nge_miibus);
2064 callout_stop(&sc->nge_stat_timer);
2065 CSR_WRITE_4(sc, NGE_IER, 0);
2066 CSR_WRITE_4(sc, NGE_IMR, 0);
2067 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2069 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2070 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2073 * Isolate/power down the PHY, but leave the media selection
2074 * unchanged so that things will be put back to normal when
2075 * we bring the interface back up.
2077 itmp = ifp->if_flags;
2078 ifp->if_flags |= IFF_UP;
2081 ifm = sc->nge_ifmedia.ifm_cur;
2083 ifm = mii->mii_media.ifm_cur;
2085 mtmp = ifm->ifm_media;
2086 dtmp = ifm->ifm_data;
2087 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2088 ifm->ifm_data = MII_MEDIA_NONE;
2092 ifm->ifm_media = mtmp;
2093 ifm->ifm_data = dtmp;
2094 ifp->if_flags = itmp;
2099 * Free data in the RX lists.
2101 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2102 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2103 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2104 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2107 bzero(&sc->nge_ldata->nge_rx_list,
2108 sizeof(sc->nge_ldata->nge_rx_list));
2111 * Free the TX list buffers.
2113 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2114 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2115 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2116 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2120 bzero(&sc->nge_ldata->nge_tx_list,
2121 sizeof(sc->nge_ldata->nge_tx_list));
2123 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2127 * Stop all chip I/O so that the kernel's probe routines don't
2128 * get confused by errant DMAs when rebooting.
2131 nge_shutdown(device_t dev)
2133 struct nge_softc *sc = device_get_softc(dev);
2134 struct ifnet *ifp = &sc->arpcom.ac_if;
2136 lwkt_serialize_enter(ifp->if_serializer);
2139 lwkt_serialize_exit(ifp->if_serializer);