2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116 if (sc->rss_debug >= lvl) \
117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119 #else /* !EMX_RSS_DEBUG */
120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121 #endif /* EMX_RSS_DEBUG */
123 #define EMX_TX_SERIALIZE 1
124 #define EMX_RX_SERIALIZE 2
126 #define EMX_NAME "Intel(R) PRO/1000 "
128 #define EMX_DEVICE(id) \
129 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
130 #define EMX_DEVICE_NULL { 0, 0, NULL }
132 static const struct emx_device {
137 EMX_DEVICE(82571EB_COPPER),
138 EMX_DEVICE(82571EB_FIBER),
139 EMX_DEVICE(82571EB_SERDES),
140 EMX_DEVICE(82571EB_SERDES_DUAL),
141 EMX_DEVICE(82571EB_SERDES_QUAD),
142 EMX_DEVICE(82571EB_QUAD_COPPER),
143 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
144 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
145 EMX_DEVICE(82571EB_QUAD_FIBER),
146 EMX_DEVICE(82571PT_QUAD_COPPER),
148 EMX_DEVICE(82572EI_COPPER),
149 EMX_DEVICE(82572EI_FIBER),
150 EMX_DEVICE(82572EI_SERDES),
154 EMX_DEVICE(82573E_IAMT),
157 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
158 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
159 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
160 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
165 /* required last entry */
169 static int emx_probe(device_t);
170 static int emx_attach(device_t);
171 static int emx_detach(device_t);
172 static int emx_shutdown(device_t);
173 static int emx_suspend(device_t);
174 static int emx_resume(device_t);
176 static void emx_init(void *);
177 static void emx_stop(struct emx_softc *);
178 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
179 static void emx_start(struct ifnet *);
181 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
183 static void emx_watchdog(struct ifnet *);
184 static void emx_media_status(struct ifnet *, struct ifmediareq *);
185 static int emx_media_change(struct ifnet *);
186 static void emx_timer(void *);
187 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
188 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
189 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
191 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
195 static void emx_intr(void *);
196 static void emx_intr_mask(void *);
197 static void emx_intr_body(struct emx_softc *, boolean_t);
198 static void emx_rxeof(struct emx_softc *, int, int);
199 static void emx_txeof(struct emx_softc *);
200 static void emx_tx_collect(struct emx_softc *);
201 static void emx_tx_purge(struct emx_softc *);
202 static void emx_enable_intr(struct emx_softc *);
203 static void emx_disable_intr(struct emx_softc *);
205 static int emx_dma_alloc(struct emx_softc *);
206 static void emx_dma_free(struct emx_softc *);
207 static void emx_init_tx_ring(struct emx_softc *);
208 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
209 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
210 static int emx_create_tx_ring(struct emx_softc *);
211 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
212 static void emx_destroy_tx_ring(struct emx_softc *, int);
213 static void emx_destroy_rx_ring(struct emx_softc *,
214 struct emx_rxdata *, int);
215 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
216 static int emx_encap(struct emx_softc *, struct mbuf **);
217 static int emx_txcsum(struct emx_softc *, struct mbuf *,
218 uint32_t *, uint32_t *);
219 static int emx_tso_pullup(struct emx_softc *, struct mbuf **);
220 static int emx_tso_setup(struct emx_softc *, struct mbuf *,
221 uint32_t *, uint32_t *);
223 static int emx_is_valid_eaddr(const uint8_t *);
224 static int emx_reset(struct emx_softc *);
225 static void emx_setup_ifp(struct emx_softc *);
226 static void emx_init_tx_unit(struct emx_softc *);
227 static void emx_init_rx_unit(struct emx_softc *);
228 static void emx_update_stats(struct emx_softc *);
229 static void emx_set_promisc(struct emx_softc *);
230 static void emx_disable_promisc(struct emx_softc *);
231 static void emx_set_multi(struct emx_softc *);
232 static void emx_update_link_status(struct emx_softc *);
233 static void emx_smartspeed(struct emx_softc *);
234 static void emx_set_itr(struct emx_softc *, uint32_t);
235 static void emx_disable_aspm(struct emx_softc *);
237 static void emx_print_debug_info(struct emx_softc *);
238 static void emx_print_nvm_info(struct emx_softc *);
239 static void emx_print_hw_stats(struct emx_softc *);
241 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
242 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
243 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
244 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
246 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
247 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
249 static void emx_add_sysctl(struct emx_softc *);
251 static void emx_serialize_skipmain(struct emx_softc *);
252 static void emx_deserialize_skipmain(struct emx_softc *);
254 /* Management and WOL Support */
255 static void emx_get_mgmt(struct emx_softc *);
256 static void emx_rel_mgmt(struct emx_softc *);
257 static void emx_get_hw_control(struct emx_softc *);
258 static void emx_rel_hw_control(struct emx_softc *);
259 static void emx_enable_wol(device_t);
261 static device_method_t emx_methods[] = {
262 /* Device interface */
263 DEVMETHOD(device_probe, emx_probe),
264 DEVMETHOD(device_attach, emx_attach),
265 DEVMETHOD(device_detach, emx_detach),
266 DEVMETHOD(device_shutdown, emx_shutdown),
267 DEVMETHOD(device_suspend, emx_suspend),
268 DEVMETHOD(device_resume, emx_resume),
272 static driver_t emx_driver = {
275 sizeof(struct emx_softc),
278 static devclass_t emx_devclass;
280 DECLARE_DUMMY_MODULE(if_emx);
281 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
282 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
287 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
288 static int emx_rxd = EMX_DEFAULT_RXD;
289 static int emx_txd = EMX_DEFAULT_TXD;
290 static int emx_smart_pwr_down = 0;
291 static int emx_rxr = 0;
293 /* Controls whether promiscuous also shows bad packets */
294 static int emx_debug_sbp = 0;
296 static int emx_82573_workaround = 1;
297 static int emx_msi_enable = 1;
299 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
300 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
301 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
302 TUNABLE_INT("hw.emx.txd", &emx_txd);
303 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
304 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
305 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
306 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
308 /* Global used in WOL setup with multiport cards */
309 static int emx_global_quad_port_a = 0;
311 /* Set this to one to display debug statistics */
312 static int emx_display_debug_stats = 0;
314 #if !defined(KTR_IF_EMX)
315 #define KTR_IF_EMX KTR_ALL
317 KTR_INFO_MASTER(if_emx);
318 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
319 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
320 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
321 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
322 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
323 #define logif(name) KTR_LOG(if_emx_ ## name)
326 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
328 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
329 /* DD bit must be cleared */
330 rxd->rxd_staterr = 0;
334 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
336 /* Ignore Checksum bit is set */
337 if (staterr & E1000_RXD_STAT_IXSM)
340 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
342 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
344 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
345 E1000_RXD_STAT_TCPCS) {
346 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
348 CSUM_FRAG_NOT_CHECKED;
349 mp->m_pkthdr.csum_data = htons(0xffff);
353 static __inline struct pktinfo *
354 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
355 uint32_t mrq, uint32_t hash, uint32_t staterr)
357 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
358 case EMX_RXDMRQ_IPV4_TCP:
359 pi->pi_netisr = NETISR_IP;
361 pi->pi_l3proto = IPPROTO_TCP;
364 case EMX_RXDMRQ_IPV6_TCP:
365 pi->pi_netisr = NETISR_IPV6;
367 pi->pi_l3proto = IPPROTO_TCP;
370 case EMX_RXDMRQ_IPV4:
371 if (staterr & E1000_RXD_STAT_IXSM)
375 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
376 E1000_RXD_STAT_TCPCS) {
377 pi->pi_netisr = NETISR_IP;
379 pi->pi_l3proto = IPPROTO_UDP;
387 m->m_flags |= M_HASH;
388 m->m_pkthdr.hash = toeplitz_hash(hash);
393 emx_probe(device_t dev)
395 const struct emx_device *d;
398 vid = pci_get_vendor(dev);
399 did = pci_get_device(dev);
401 for (d = emx_devices; d->desc != NULL; ++d) {
402 if (vid == d->vid && did == d->did) {
403 device_set_desc(dev, d->desc);
404 device_set_async_attach(dev, TRUE);
412 emx_attach(device_t dev)
414 struct emx_softc *sc = device_get_softc(dev);
415 struct ifnet *ifp = &sc->arpcom.ac_if;
416 int error = 0, i, throttle, msi_enable;
418 uint16_t eeprom_data, device_id, apme_mask;
419 driver_intr_t *intr_func;
421 int offset, offset_def;
424 lwkt_serialize_init(&sc->main_serialize);
425 lwkt_serialize_init(&sc->tx_serialize);
426 for (i = 0; i < EMX_NRX_RING; ++i)
427 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
430 sc->serializes[i++] = &sc->main_serialize;
431 sc->serializes[i++] = &sc->tx_serialize;
432 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
433 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
434 KKASSERT(i == EMX_NSERIALIZE);
436 callout_init_mp(&sc->timer);
438 sc->dev = sc->osdep.dev = dev;
441 * Determine hardware and mac type
443 sc->hw.vendor_id = pci_get_vendor(dev);
444 sc->hw.device_id = pci_get_device(dev);
445 sc->hw.revision_id = pci_get_revid(dev);
446 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
447 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
449 if (e1000_set_mac_type(&sc->hw))
453 * Pullup extra 4bytes into the first data segment, see:
454 * 82571/82572 specification update errata #7
457 * 4bytes instead of 2bytes, which are mentioned in the errata,
458 * are pulled; mainly to keep rest of the data properly aligned.
460 if (sc->hw.mac.type == e1000_82571 || sc->hw.mac.type == e1000_82572)
461 sc->flags |= EMX_FLAG_TSO_PULLEX;
463 /* Enable bus mastering */
464 pci_enable_busmaster(dev);
469 sc->memory_rid = EMX_BAR_MEM;
470 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
471 &sc->memory_rid, RF_ACTIVE);
472 if (sc->memory == NULL) {
473 device_printf(dev, "Unable to allocate bus resource: memory\n");
477 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
478 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
480 /* XXX This is quite goofy, it is not actually used */
481 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
484 * Don't enable MSI-X on 82574, see:
485 * 82574 specification update errata #15
487 * Don't enable MSI on 82571/82572, see:
488 * 82571/82572 specification update errata #63
490 msi_enable = emx_msi_enable;
492 (sc->hw.mac.type == e1000_82571 ||
493 sc->hw.mac.type == e1000_82572))
499 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
500 &sc->intr_rid, &intr_flags);
502 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
505 unshared = device_getenv_int(dev, "irq.unshared", 0);
507 sc->flags |= EMX_FLAG_SHARED_INTR;
509 device_printf(dev, "IRQ shared\n");
511 intr_flags &= ~RF_SHAREABLE;
513 device_printf(dev, "IRQ unshared\n");
517 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
519 if (sc->intr_res == NULL) {
520 device_printf(dev, "Unable to allocate bus resource: "
526 /* Save PCI command register for Shared Code */
527 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
528 sc->hw.back = &sc->osdep;
530 /* Do Shared Code initialization */
531 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
532 device_printf(dev, "Setup of Shared code failed\n");
536 e1000_get_bus_info(&sc->hw);
538 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
539 sc->hw.phy.autoneg_wait_to_complete = FALSE;
540 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
543 * Interrupt throttle rate
545 throttle = device_getenv_int(dev, "int_throttle_ceil",
546 emx_int_throttle_ceil);
548 sc->int_throttle_ceil = 0;
551 throttle = EMX_DEFAULT_ITR;
553 /* Recalculate the tunable value to get the exact frequency. */
554 throttle = 1000000000 / 256 / throttle;
556 /* Upper 16bits of ITR is reserved and should be zero */
557 if (throttle & 0xffff0000)
558 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
560 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
563 e1000_init_script_state_82541(&sc->hw, TRUE);
564 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
567 if (sc->hw.phy.media_type == e1000_media_type_copper) {
568 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
569 sc->hw.phy.disable_polarity_correction = FALSE;
570 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
573 /* Set the frame limits assuming standard ethernet sized frames. */
574 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
575 sc->min_frame_size = ETHER_MIN_LEN;
577 /* This controls when hardware reports transmit completion status. */
578 sc->hw.mac.report_tx_early = 1;
580 /* Calculate # of RX rings */
581 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
582 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
584 /* Allocate RX/TX rings' busdma(9) stuffs */
585 error = emx_dma_alloc(sc);
589 /* Allocate multicast array memory. */
590 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
593 /* Indicate SOL/IDER usage */
594 if (e1000_check_reset_block(&sc->hw)) {
596 "PHY reset is blocked due to SOL/IDER session.\n");
600 * Start from a known state, this is important in reading the
601 * nvm and mac from that.
603 e1000_reset_hw(&sc->hw);
605 /* Make sure we have a good EEPROM before we read from it */
606 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
608 * Some PCI-E parts fail the first check due to
609 * the link being in sleep state, call it again,
610 * if it fails a second time its a real issue.
612 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
614 "The EEPROM Checksum Is Not Valid\n");
620 /* Copy the permanent MAC address out of the EEPROM */
621 if (e1000_read_mac_addr(&sc->hw) < 0) {
622 device_printf(dev, "EEPROM read error while reading MAC"
627 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
628 device_printf(dev, "Invalid MAC address\n");
633 /* Determine if we have to control management hardware */
634 if (e1000_enable_mng_pass_thru(&sc->hw))
635 sc->flags |= EMX_FLAG_HAS_MGMT;
640 apme_mask = EMX_EEPROM_APME;
642 switch (sc->hw.mac.type) {
644 sc->flags |= EMX_FLAG_HAS_AMT;
649 case e1000_80003es2lan:
650 if (sc->hw.bus.func == 1) {
651 e1000_read_nvm(&sc->hw,
652 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
654 e1000_read_nvm(&sc->hw,
655 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
660 e1000_read_nvm(&sc->hw,
661 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
664 if (eeprom_data & apme_mask)
665 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
668 * We have the eeprom settings, now apply the special cases
669 * where the eeprom may be wrong or the board won't support
670 * wake on lan on a particular port
672 device_id = pci_get_device(dev);
674 case E1000_DEV_ID_82571EB_FIBER:
676 * Wake events only supported on port A for dual fiber
677 * regardless of eeprom setting
679 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
684 case E1000_DEV_ID_82571EB_QUAD_COPPER:
685 case E1000_DEV_ID_82571EB_QUAD_FIBER:
686 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
687 /* if quad port sc, disable WoL on all but port A */
688 if (emx_global_quad_port_a != 0)
690 /* Reset for multiple quad port adapters */
691 if (++emx_global_quad_port_a == 4)
692 emx_global_quad_port_a = 0;
696 /* XXX disable wol */
701 * NPOLLING RX CPU offset
703 if (sc->rx_ring_cnt == ncpus2) {
706 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
707 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
708 if (offset >= ncpus2 ||
709 offset % sc->rx_ring_cnt != 0) {
710 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
715 sc->rx_npoll_off = offset;
718 * NPOLLING TX CPU offset
720 offset_def = sc->rx_npoll_off;
721 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
722 if (offset >= ncpus2) {
723 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
727 sc->tx_npoll_off = offset;
730 /* Setup OS specific network interface */
733 /* Add sysctl tree, must after em_setup_ifp() */
736 /* Reset the hardware */
737 error = emx_reset(sc);
739 device_printf(dev, "Unable to reset the hardware\n");
743 /* Initialize statistics */
744 emx_update_stats(sc);
746 sc->hw.mac.get_link_status = 1;
747 emx_update_link_status(sc);
749 sc->spare_tx_desc = EMX_TX_SPARE;
752 * Keep following relationship between spare_tx_desc, oact_tx_desc
754 * (spare_tx_desc + EMX_TX_RESERVED) <=
755 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
757 sc->oact_tx_desc = sc->num_tx_desc / 8;
758 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
759 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
760 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
761 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
763 sc->tx_int_nsegs = sc->num_tx_desc / 16;
764 if (sc->tx_int_nsegs < sc->oact_tx_desc)
765 sc->tx_int_nsegs = sc->oact_tx_desc;
767 /* Non-AMT based hardware can now take control from firmware */
768 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
770 emx_get_hw_control(sc);
773 * Missing Interrupt Following ICR read:
775 * 82571/82572 specification update errata #76
776 * 82573 specification update errata #31
777 * 82574 specification update errata #12
779 intr_func = emx_intr;
780 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
781 (sc->hw.mac.type == e1000_82571 ||
782 sc->hw.mac.type == e1000_82572 ||
783 sc->hw.mac.type == e1000_82573 ||
784 sc->hw.mac.type == e1000_82574))
785 intr_func = emx_intr_mask;
787 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
788 &sc->intr_tag, &sc->main_serialize);
790 device_printf(dev, "Failed to register interrupt handler");
791 ether_ifdetach(&sc->arpcom.ac_if);
795 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
796 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
804 emx_detach(device_t dev)
806 struct emx_softc *sc = device_get_softc(dev);
808 if (device_is_attached(dev)) {
809 struct ifnet *ifp = &sc->arpcom.ac_if;
811 ifnet_serialize_all(ifp);
815 e1000_phy_hw_reset(&sc->hw);
818 emx_rel_hw_control(sc);
821 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
822 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
826 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
828 ifnet_deserialize_all(ifp);
831 } else if (sc->memory != NULL) {
832 emx_rel_hw_control(sc);
834 bus_generic_detach(dev);
836 if (sc->intr_res != NULL) {
837 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
841 if (sc->intr_type == PCI_INTR_TYPE_MSI)
842 pci_release_msi(dev);
844 if (sc->memory != NULL) {
845 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
851 /* Free sysctl tree */
852 if (sc->sysctl_tree != NULL)
853 sysctl_ctx_free(&sc->sysctl_ctx);
856 kfree(sc->mta, M_DEVBUF);
862 emx_shutdown(device_t dev)
864 return emx_suspend(dev);
868 emx_suspend(device_t dev)
870 struct emx_softc *sc = device_get_softc(dev);
871 struct ifnet *ifp = &sc->arpcom.ac_if;
873 ifnet_serialize_all(ifp);
878 emx_rel_hw_control(sc);
881 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
882 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
886 ifnet_deserialize_all(ifp);
888 return bus_generic_suspend(dev);
892 emx_resume(device_t dev)
894 struct emx_softc *sc = device_get_softc(dev);
895 struct ifnet *ifp = &sc->arpcom.ac_if;
897 ifnet_serialize_all(ifp);
903 ifnet_deserialize_all(ifp);
905 return bus_generic_resume(dev);
909 emx_start(struct ifnet *ifp)
911 struct emx_softc *sc = ifp->if_softc;
914 ASSERT_SERIALIZED(&sc->tx_serialize);
916 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
919 if (!sc->link_active) {
920 ifq_purge(&ifp->if_snd);
924 while (!ifq_is_empty(&ifp->if_snd)) {
925 /* Now do we at least have a minimal? */
926 if (EMX_IS_OACTIVE(sc)) {
928 if (EMX_IS_OACTIVE(sc)) {
929 ifp->if_flags |= IFF_OACTIVE;
930 sc->no_tx_desc_avail1++;
936 m_head = ifq_dequeue(&ifp->if_snd, NULL);
940 if (emx_encap(sc, &m_head)) {
946 /* Send a copy of the frame to the BPF listener */
947 ETHER_BPF_MTAP(ifp, m_head);
949 /* Set timeout in case hardware has problems transmitting. */
950 ifp->if_timer = EMX_TX_TIMEOUT;
955 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
957 struct emx_softc *sc = ifp->if_softc;
958 struct ifreq *ifr = (struct ifreq *)data;
959 uint16_t eeprom_data = 0;
960 int max_frame_size, mask, reinit;
963 ASSERT_IFNET_SERIALIZED_ALL(ifp);
967 switch (sc->hw.mac.type) {
970 * 82573 only supports jumbo frames
971 * if ASPM is disabled.
973 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
975 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
976 max_frame_size = ETHER_MAX_LEN;
981 /* Limit Jumbo Frame size */
985 case e1000_80003es2lan:
986 max_frame_size = 9234;
990 max_frame_size = MAX_JUMBO_FRAME_SIZE;
993 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
999 ifp->if_mtu = ifr->ifr_mtu;
1000 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1003 if (ifp->if_flags & IFF_RUNNING)
1008 if (ifp->if_flags & IFF_UP) {
1009 if ((ifp->if_flags & IFF_RUNNING)) {
1010 if ((ifp->if_flags ^ sc->if_flags) &
1011 (IFF_PROMISC | IFF_ALLMULTI)) {
1012 emx_disable_promisc(sc);
1013 emx_set_promisc(sc);
1018 } else if (ifp->if_flags & IFF_RUNNING) {
1021 sc->if_flags = ifp->if_flags;
1026 if (ifp->if_flags & IFF_RUNNING) {
1027 emx_disable_intr(sc);
1029 #ifdef IFPOLL_ENABLE
1030 if (!(ifp->if_flags & IFF_NPOLLING))
1032 emx_enable_intr(sc);
1037 /* Check SOL/IDER usage */
1038 if (e1000_check_reset_block(&sc->hw)) {
1039 device_printf(sc->dev, "Media change is"
1040 " blocked due to SOL/IDER session.\n");
1046 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1051 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1052 if (mask & IFCAP_RXCSUM) {
1053 ifp->if_capenable ^= IFCAP_RXCSUM;
1056 if (mask & IFCAP_VLAN_HWTAGGING) {
1057 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1060 if (mask & IFCAP_TXCSUM) {
1061 ifp->if_capenable ^= IFCAP_TXCSUM;
1062 if (ifp->if_capenable & IFCAP_TXCSUM)
1063 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1065 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1067 if (mask & IFCAP_TSO) {
1068 ifp->if_capenable ^= IFCAP_TSO;
1069 if (ifp->if_capenable & IFCAP_TSO)
1070 ifp->if_hwassist |= CSUM_TSO;
1072 ifp->if_hwassist &= ~CSUM_TSO;
1074 if (mask & IFCAP_RSS)
1075 ifp->if_capenable ^= IFCAP_RSS;
1076 if (reinit && (ifp->if_flags & IFF_RUNNING))
1081 error = ether_ioctl(ifp, command, data);
1088 emx_watchdog(struct ifnet *ifp)
1090 struct emx_softc *sc = ifp->if_softc;
1092 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1095 * The timer is set to 5 every time start queues a packet.
1096 * Then txeof keeps resetting it as long as it cleans at
1097 * least one descriptor.
1098 * Finally, anytime all descriptors are clean the timer is
1102 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
1103 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
1105 * If we reach here, all TX jobs are completed and
1106 * the TX engine should have been idled for some time.
1107 * We don't need to call if_devstart() here.
1109 ifp->if_flags &= ~IFF_OACTIVE;
1115 * If we are in this routine because of pause frames, then
1116 * don't reset the hardware.
1118 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1119 ifp->if_timer = EMX_TX_TIMEOUT;
1123 if (e1000_check_for_link(&sc->hw) == 0)
1124 if_printf(ifp, "watchdog timeout -- resetting\n");
1127 sc->watchdog_events++;
1131 if (!ifq_is_empty(&ifp->if_snd))
1138 struct emx_softc *sc = xsc;
1139 struct ifnet *ifp = &sc->arpcom.ac_if;
1140 device_t dev = sc->dev;
1144 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1149 * Packet Buffer Allocation (PBA)
1150 * Writing PBA sets the receive portion of the buffer
1151 * the remainder is used for the transmit buffer.
1153 switch (sc->hw.mac.type) {
1154 /* Total Packet Buffer on these is 48K */
1157 case e1000_80003es2lan:
1158 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1161 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1162 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1166 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1170 /* Devices before 82547 had a Packet Buffer of 64K. */
1171 if (sc->max_frame_size > 8192)
1172 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1174 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1176 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1178 /* Get the latest mac address, User can use a LAA */
1179 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1181 /* Put the address into the Receive Address Array */
1182 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1185 * With the 82571 sc, RAR[0] may be overwritten
1186 * when the other port is reset, we make a duplicate
1187 * in RAR[14] for that eventuality, this assures
1188 * the interface continues to function.
1190 if (sc->hw.mac.type == e1000_82571) {
1191 e1000_set_laa_state_82571(&sc->hw, TRUE);
1192 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1193 E1000_RAR_ENTRIES - 1);
1196 /* Initialize the hardware */
1197 if (emx_reset(sc)) {
1198 device_printf(dev, "Unable to reset the hardware\n");
1199 /* XXX emx_stop()? */
1202 emx_update_link_status(sc);
1204 /* Setup VLAN support, basic and offload if available */
1205 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1207 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1210 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1211 ctrl |= E1000_CTRL_VME;
1212 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1215 /* Configure for OS presence */
1218 /* Prepare transmit descriptors and buffers */
1219 emx_init_tx_ring(sc);
1220 emx_init_tx_unit(sc);
1222 /* Setup Multicast table */
1225 /* Prepare receive descriptors and buffers */
1226 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1227 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1229 "Could not setup receive structures\n");
1234 emx_init_rx_unit(sc);
1236 /* Don't lose promiscuous settings */
1237 emx_set_promisc(sc);
1239 ifp->if_flags |= IFF_RUNNING;
1240 ifp->if_flags &= ~IFF_OACTIVE;
1242 callout_reset(&sc->timer, hz, emx_timer, sc);
1243 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1245 /* MSI/X configuration for 82574 */
1246 if (sc->hw.mac.type == e1000_82574) {
1249 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1250 tmp |= E1000_CTRL_EXT_PBA_CLR;
1251 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1254 * Set the IVAR - interrupt vector routing.
1255 * Each nibble represents a vector, high bit
1256 * is enable, other 3 bits are the MSIX table
1257 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1258 * Link (other) to 2, hence the magic number.
1260 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1263 #ifdef IFPOLL_ENABLE
1265 * Only enable interrupts if we are not polling, make sure
1266 * they are off otherwise.
1268 if (ifp->if_flags & IFF_NPOLLING)
1269 emx_disable_intr(sc);
1271 #endif /* IFPOLL_ENABLE */
1272 emx_enable_intr(sc);
1274 /* AMT based hardware can now take control from firmware */
1275 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1276 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1277 emx_get_hw_control(sc);
1279 /* Don't reset the phy next time init gets called */
1280 sc->hw.phy.reset_disable = TRUE;
1286 emx_intr_body(xsc, TRUE);
1290 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1292 struct ifnet *ifp = &sc->arpcom.ac_if;
1296 ASSERT_SERIALIZED(&sc->main_serialize);
1298 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1300 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1306 * XXX: some laptops trigger several spurious interrupts
1307 * on emx(4) when in the resume cycle. The ICR register
1308 * reports all-ones value in this case. Processing such
1309 * interrupts would lead to a freeze. I don't know why.
1311 if (reg_icr == 0xffffffff) {
1316 if (ifp->if_flags & IFF_RUNNING) {
1318 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1321 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1322 lwkt_serialize_enter(
1323 &sc->rx_data[i].rx_serialize);
1324 emx_rxeof(sc, i, -1);
1325 lwkt_serialize_exit(
1326 &sc->rx_data[i].rx_serialize);
1329 if (reg_icr & E1000_ICR_TXDW) {
1330 lwkt_serialize_enter(&sc->tx_serialize);
1332 if (!ifq_is_empty(&ifp->if_snd))
1334 lwkt_serialize_exit(&sc->tx_serialize);
1338 /* Link status change */
1339 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1340 emx_serialize_skipmain(sc);
1342 callout_stop(&sc->timer);
1343 sc->hw.mac.get_link_status = 1;
1344 emx_update_link_status(sc);
1346 /* Deal with TX cruft when link lost */
1349 callout_reset(&sc->timer, hz, emx_timer, sc);
1351 emx_deserialize_skipmain(sc);
1354 if (reg_icr & E1000_ICR_RXO)
1361 emx_intr_mask(void *xsc)
1363 struct emx_softc *sc = xsc;
1365 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1368 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1369 * so don't check it.
1371 emx_intr_body(sc, FALSE);
1372 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1376 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1378 struct emx_softc *sc = ifp->if_softc;
1380 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1382 emx_update_link_status(sc);
1384 ifmr->ifm_status = IFM_AVALID;
1385 ifmr->ifm_active = IFM_ETHER;
1387 if (!sc->link_active)
1390 ifmr->ifm_status |= IFM_ACTIVE;
1392 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1393 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1394 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1396 switch (sc->link_speed) {
1398 ifmr->ifm_active |= IFM_10_T;
1401 ifmr->ifm_active |= IFM_100_TX;
1405 ifmr->ifm_active |= IFM_1000_T;
1408 if (sc->link_duplex == FULL_DUPLEX)
1409 ifmr->ifm_active |= IFM_FDX;
1411 ifmr->ifm_active |= IFM_HDX;
1416 emx_media_change(struct ifnet *ifp)
1418 struct emx_softc *sc = ifp->if_softc;
1419 struct ifmedia *ifm = &sc->media;
1421 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1423 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1426 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1428 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1429 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1435 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1436 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1440 sc->hw.mac.autoneg = FALSE;
1441 sc->hw.phy.autoneg_advertised = 0;
1442 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1443 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1445 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1449 sc->hw.mac.autoneg = FALSE;
1450 sc->hw.phy.autoneg_advertised = 0;
1451 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1452 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1454 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1458 if_printf(ifp, "Unsupported media type\n");
1463 * As the speed/duplex settings my have changed we need to
1466 sc->hw.phy.reset_disable = FALSE;
1474 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1476 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1478 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1479 struct e1000_tx_desc *ctxd = NULL;
1480 struct mbuf *m_head = *m_headp;
1481 uint32_t txd_upper, txd_lower, cmd = 0;
1482 int maxsegs, nsegs, i, j, first, last = 0, error;
1484 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1485 error = emx_tso_pullup(sc, m_headp);
1491 txd_upper = txd_lower = 0;
1494 * Capture the first descriptor index, this descriptor
1495 * will have the index of the EOP which is the only one
1496 * that now gets a DONE bit writeback.
1498 first = sc->next_avail_tx_desc;
1499 tx_buffer = &sc->tx_buf[first];
1500 tx_buffer_mapped = tx_buffer;
1501 map = tx_buffer->map;
1503 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1504 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc"));
1505 if (maxsegs > EMX_MAX_SCATTER)
1506 maxsegs = EMX_MAX_SCATTER;
1508 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1509 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1511 if (error == ENOBUFS)
1512 sc->mbuf_alloc_failed++;
1514 sc->no_tx_dma_setup++;
1520 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1523 sc->tx_nsegs += nsegs;
1525 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1526 /* TSO will consume one TX desc */
1527 sc->tx_nsegs += emx_tso_setup(sc, m_head,
1528 &txd_upper, &txd_lower);
1529 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1530 /* TX csum offloading will consume one TX desc */
1531 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1533 i = sc->next_avail_tx_desc;
1535 /* Set up our transmit descriptors */
1536 for (j = 0; j < nsegs; j++) {
1537 tx_buffer = &sc->tx_buf[i];
1538 ctxd = &sc->tx_desc_base[i];
1540 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1541 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1542 txd_lower | segs[j].ds_len);
1543 ctxd->upper.data = htole32(txd_upper);
1546 if (++i == sc->num_tx_desc)
1550 sc->next_avail_tx_desc = i;
1552 KKASSERT(sc->num_tx_desc_avail > nsegs);
1553 sc->num_tx_desc_avail -= nsegs;
1555 /* Handle VLAN tag */
1556 if (m_head->m_flags & M_VLANTAG) {
1557 /* Set the vlan id. */
1558 ctxd->upper.fields.special =
1559 htole16(m_head->m_pkthdr.ether_vlantag);
1561 /* Tell hardware to add tag */
1562 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1565 tx_buffer->m_head = m_head;
1566 tx_buffer_mapped->map = tx_buffer->map;
1567 tx_buffer->map = map;
1569 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1573 * Report Status (RS) is turned on
1574 * every tx_int_nsegs descriptors.
1576 cmd = E1000_TXD_CMD_RS;
1579 * Keep track of the descriptor, which will
1580 * be written back by hardware.
1582 sc->tx_dd[sc->tx_dd_tail] = last;
1583 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1584 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1588 * Last Descriptor of Packet needs End Of Packet (EOP)
1590 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1593 * Advance the Transmit Descriptor Tail (TDT), this tells
1594 * the E1000 that this frame is available to transmit.
1596 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1602 emx_set_promisc(struct emx_softc *sc)
1604 struct ifnet *ifp = &sc->arpcom.ac_if;
1607 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1609 if (ifp->if_flags & IFF_PROMISC) {
1610 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1611 /* Turn this on if you want to see bad packets */
1613 reg_rctl |= E1000_RCTL_SBP;
1614 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1615 } else if (ifp->if_flags & IFF_ALLMULTI) {
1616 reg_rctl |= E1000_RCTL_MPE;
1617 reg_rctl &= ~E1000_RCTL_UPE;
1618 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1623 emx_disable_promisc(struct emx_softc *sc)
1627 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1629 reg_rctl &= ~E1000_RCTL_UPE;
1630 reg_rctl &= ~E1000_RCTL_MPE;
1631 reg_rctl &= ~E1000_RCTL_SBP;
1632 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1636 emx_set_multi(struct emx_softc *sc)
1638 struct ifnet *ifp = &sc->arpcom.ac_if;
1639 struct ifmultiaddr *ifma;
1640 uint32_t reg_rctl = 0;
1645 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1647 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1648 if (ifma->ifma_addr->sa_family != AF_LINK)
1651 if (mcnt == EMX_MCAST_ADDR_MAX)
1654 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1655 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1659 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1660 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1661 reg_rctl |= E1000_RCTL_MPE;
1662 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1664 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1669 * This routine checks for link status and updates statistics.
1672 emx_timer(void *xsc)
1674 struct emx_softc *sc = xsc;
1675 struct ifnet *ifp = &sc->arpcom.ac_if;
1677 lwkt_serialize_enter(&sc->main_serialize);
1679 emx_update_link_status(sc);
1680 emx_update_stats(sc);
1682 /* Reset LAA into RAR[0] on 82571 */
1683 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1684 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1686 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1687 emx_print_hw_stats(sc);
1691 callout_reset(&sc->timer, hz, emx_timer, sc);
1693 lwkt_serialize_exit(&sc->main_serialize);
1697 emx_update_link_status(struct emx_softc *sc)
1699 struct e1000_hw *hw = &sc->hw;
1700 struct ifnet *ifp = &sc->arpcom.ac_if;
1701 device_t dev = sc->dev;
1702 uint32_t link_check = 0;
1704 /* Get the cached link value or read phy for real */
1705 switch (hw->phy.media_type) {
1706 case e1000_media_type_copper:
1707 if (hw->mac.get_link_status) {
1708 /* Do the work to read phy */
1709 e1000_check_for_link(hw);
1710 link_check = !hw->mac.get_link_status;
1711 if (link_check) /* ESB2 fix */
1712 e1000_cfg_on_link_up(hw);
1718 case e1000_media_type_fiber:
1719 e1000_check_for_link(hw);
1720 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1723 case e1000_media_type_internal_serdes:
1724 e1000_check_for_link(hw);
1725 link_check = sc->hw.mac.serdes_has_link;
1728 case e1000_media_type_unknown:
1733 /* Now check for a transition */
1734 if (link_check && sc->link_active == 0) {
1735 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1739 * Check if we should enable/disable SPEED_MODE bit on
1742 if (sc->link_speed != SPEED_1000 &&
1743 (hw->mac.type == e1000_82571 ||
1744 hw->mac.type == e1000_82572)) {
1747 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1748 tarc0 &= ~EMX_TARC_SPEED_MODE;
1749 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1752 device_printf(dev, "Link is up %d Mbps %s\n",
1754 ((sc->link_duplex == FULL_DUPLEX) ?
1755 "Full Duplex" : "Half Duplex"));
1757 sc->link_active = 1;
1759 ifp->if_baudrate = sc->link_speed * 1000000;
1760 ifp->if_link_state = LINK_STATE_UP;
1761 if_link_state_change(ifp);
1762 } else if (!link_check && sc->link_active == 1) {
1763 ifp->if_baudrate = sc->link_speed = 0;
1764 sc->link_duplex = 0;
1766 device_printf(dev, "Link is Down\n");
1767 sc->link_active = 0;
1769 /* Link down, disable watchdog */
1772 ifp->if_link_state = LINK_STATE_DOWN;
1773 if_link_state_change(ifp);
1778 emx_stop(struct emx_softc *sc)
1780 struct ifnet *ifp = &sc->arpcom.ac_if;
1783 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1785 emx_disable_intr(sc);
1787 callout_stop(&sc->timer);
1789 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1793 * Disable multiple receive queues.
1796 * We should disable multiple receive queues before
1797 * resetting the hardware.
1799 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1801 e1000_reset_hw(&sc->hw);
1802 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1804 for (i = 0; i < sc->num_tx_desc; i++) {
1805 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1807 if (tx_buffer->m_head != NULL) {
1808 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1809 m_freem(tx_buffer->m_head);
1810 tx_buffer->m_head = NULL;
1814 for (i = 0; i < sc->rx_ring_cnt; ++i)
1815 emx_free_rx_ring(sc, &sc->rx_data[i]);
1819 sc->csum_iphlen = 0;
1822 sc->csum_pktlen = 0;
1830 emx_reset(struct emx_softc *sc)
1832 device_t dev = sc->dev;
1833 uint16_t rx_buffer_size;
1835 /* Set up smart power down as default off on newer adapters. */
1836 if (!emx_smart_pwr_down &&
1837 (sc->hw.mac.type == e1000_82571 ||
1838 sc->hw.mac.type == e1000_82572)) {
1839 uint16_t phy_tmp = 0;
1841 /* Speed up time to link by disabling smart power down. */
1842 e1000_read_phy_reg(&sc->hw,
1843 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1844 phy_tmp &= ~IGP02E1000_PM_SPD;
1845 e1000_write_phy_reg(&sc->hw,
1846 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1850 * These parameters control the automatic generation (Tx) and
1851 * response (Rx) to Ethernet PAUSE frames.
1852 * - High water mark should allow for at least two frames to be
1853 * received after sending an XOFF.
1854 * - Low water mark works best when it is very near the high water mark.
1855 * This allows the receiver to restart by sending XON when it has
1856 * drained a bit. Here we use an arbitary value of 1500 which will
1857 * restart after one full frame is pulled from the buffer. There
1858 * could be several smaller frames in the buffer and if so they will
1859 * not trigger the XON until their total number reduces the buffer
1861 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1863 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1865 sc->hw.fc.high_water = rx_buffer_size -
1866 roundup2(sc->max_frame_size, 1024);
1867 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1869 if (sc->hw.mac.type == e1000_80003es2lan)
1870 sc->hw.fc.pause_time = 0xFFFF;
1872 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1873 sc->hw.fc.send_xon = TRUE;
1874 sc->hw.fc.requested_mode = e1000_fc_full;
1876 /* Issue a global reset */
1877 e1000_reset_hw(&sc->hw);
1878 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1879 emx_disable_aspm(sc);
1881 if (e1000_init_hw(&sc->hw) < 0) {
1882 device_printf(dev, "Hardware Initialization Failed\n");
1886 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1887 e1000_get_phy_info(&sc->hw);
1888 e1000_check_for_link(&sc->hw);
1894 emx_setup_ifp(struct emx_softc *sc)
1896 struct ifnet *ifp = &sc->arpcom.ac_if;
1898 if_initname(ifp, device_get_name(sc->dev),
1899 device_get_unit(sc->dev));
1901 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1902 ifp->if_init = emx_init;
1903 ifp->if_ioctl = emx_ioctl;
1904 ifp->if_start = emx_start;
1905 #ifdef IFPOLL_ENABLE
1906 ifp->if_npoll = emx_npoll;
1908 ifp->if_watchdog = emx_watchdog;
1909 ifp->if_serialize = emx_serialize;
1910 ifp->if_deserialize = emx_deserialize;
1911 ifp->if_tryserialize = emx_tryserialize;
1913 ifp->if_serialize_assert = emx_serialize_assert;
1915 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1916 ifq_set_ready(&ifp->if_snd);
1918 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1920 ifp->if_capabilities = IFCAP_HWCSUM |
1921 IFCAP_VLAN_HWTAGGING |
1924 if (sc->rx_ring_cnt > 1)
1925 ifp->if_capabilities |= IFCAP_RSS;
1926 ifp->if_capenable = ifp->if_capabilities;
1927 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
1930 * Tell the upper layer(s) we support long frames.
1932 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1935 * Specify the media types supported by this sc and register
1936 * callbacks to update media and link information
1938 ifmedia_init(&sc->media, IFM_IMASK,
1939 emx_media_change, emx_media_status);
1940 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1941 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1942 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1944 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1946 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1947 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1949 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1950 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1952 if (sc->hw.phy.type != e1000_phy_ife) {
1953 ifmedia_add(&sc->media,
1954 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1955 ifmedia_add(&sc->media,
1956 IFM_ETHER | IFM_1000_T, 0, NULL);
1959 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1960 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1964 * Workaround for SmartSpeed on 82541 and 82547 controllers
1967 emx_smartspeed(struct emx_softc *sc)
1971 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1972 sc->hw.mac.autoneg == 0 ||
1973 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1976 if (sc->smartspeed == 0) {
1978 * If Master/Slave config fault is asserted twice,
1979 * we assume back-to-back
1981 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1982 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1984 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1985 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1986 e1000_read_phy_reg(&sc->hw,
1987 PHY_1000T_CTRL, &phy_tmp);
1988 if (phy_tmp & CR_1000T_MS_ENABLE) {
1989 phy_tmp &= ~CR_1000T_MS_ENABLE;
1990 e1000_write_phy_reg(&sc->hw,
1991 PHY_1000T_CTRL, phy_tmp);
1993 if (sc->hw.mac.autoneg &&
1994 !e1000_phy_setup_autoneg(&sc->hw) &&
1995 !e1000_read_phy_reg(&sc->hw,
1996 PHY_CONTROL, &phy_tmp)) {
1997 phy_tmp |= MII_CR_AUTO_NEG_EN |
1998 MII_CR_RESTART_AUTO_NEG;
1999 e1000_write_phy_reg(&sc->hw,
2000 PHY_CONTROL, phy_tmp);
2005 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2006 /* If still no link, perhaps using 2/3 pair cable */
2007 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2008 phy_tmp |= CR_1000T_MS_ENABLE;
2009 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2010 if (sc->hw.mac.autoneg &&
2011 !e1000_phy_setup_autoneg(&sc->hw) &&
2012 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2013 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2014 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2018 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2019 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2024 emx_create_tx_ring(struct emx_softc *sc)
2026 device_t dev = sc->dev;
2027 struct emx_txbuf *tx_buffer;
2028 int error, i, tsize, ntxd;
2031 * Validate number of transmit descriptors. It must not exceed
2032 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2034 ntxd = device_getenv_int(dev, "txd", emx_txd);
2035 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2036 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2037 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2038 EMX_DEFAULT_TXD, ntxd);
2039 sc->num_tx_desc = EMX_DEFAULT_TXD;
2041 sc->num_tx_desc = ntxd;
2045 * Allocate Transmit Descriptor ring
2047 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
2049 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
2050 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2051 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
2052 &sc->tx_desc_paddr);
2053 if (sc->tx_desc_base == NULL) {
2054 device_printf(dev, "Unable to allocate tx_desc memory\n");
2058 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
2059 M_DEVBUF, M_WAITOK | M_ZERO);
2062 * Create DMA tags for tx buffers
2064 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2065 1, 0, /* alignment, bounds */
2066 BUS_SPACE_MAXADDR, /* lowaddr */
2067 BUS_SPACE_MAXADDR, /* highaddr */
2068 NULL, NULL, /* filter, filterarg */
2069 EMX_TSO_SIZE, /* maxsize */
2070 EMX_MAX_SCATTER, /* nsegments */
2071 EMX_MAX_SEGSIZE, /* maxsegsize */
2072 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2073 BUS_DMA_ONEBPAGE, /* flags */
2076 device_printf(dev, "Unable to allocate TX DMA tag\n");
2077 kfree(sc->tx_buf, M_DEVBUF);
2083 * Create DMA maps for tx buffers
2085 for (i = 0; i < sc->num_tx_desc; i++) {
2086 tx_buffer = &sc->tx_buf[i];
2088 error = bus_dmamap_create(sc->txtag,
2089 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2092 device_printf(dev, "Unable to create TX DMA map\n");
2093 emx_destroy_tx_ring(sc, i);
2101 emx_init_tx_ring(struct emx_softc *sc)
2103 /* Clear the old ring contents */
2104 bzero(sc->tx_desc_base,
2105 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2108 sc->next_avail_tx_desc = 0;
2109 sc->next_tx_to_clean = 0;
2110 sc->num_tx_desc_avail = sc->num_tx_desc;
2114 emx_init_tx_unit(struct emx_softc *sc)
2116 uint32_t tctl, tarc, tipg = 0;
2119 /* Setup the Base and Length of the Tx Descriptor Ring */
2120 bus_addr = sc->tx_desc_paddr;
2121 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2122 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2123 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2124 (uint32_t)(bus_addr >> 32));
2125 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2126 (uint32_t)bus_addr);
2127 /* Setup the HW Tx Head and Tail descriptor pointers */
2128 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2129 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2131 /* Set the default values for the Tx Inter Packet Gap timer */
2132 switch (sc->hw.mac.type) {
2133 case e1000_80003es2lan:
2134 tipg = DEFAULT_82543_TIPG_IPGR1;
2135 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2136 E1000_TIPG_IPGR2_SHIFT;
2140 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2141 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2142 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2144 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2145 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2146 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2150 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2152 /* NOTE: 0 is not allowed for TIDV */
2153 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2154 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2156 if (sc->hw.mac.type == e1000_82571 ||
2157 sc->hw.mac.type == e1000_82572) {
2158 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2159 tarc |= EMX_TARC_SPEED_MODE;
2160 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2161 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2162 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2164 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2165 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2167 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2170 /* Program the Transmit Control Register */
2171 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2172 tctl &= ~E1000_TCTL_CT;
2173 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2174 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2175 tctl |= E1000_TCTL_MULR;
2177 /* This write will effectively turn on the transmit unit. */
2178 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2182 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2184 struct emx_txbuf *tx_buffer;
2187 /* Free Transmit Descriptor ring */
2188 if (sc->tx_desc_base) {
2189 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2190 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2192 bus_dma_tag_destroy(sc->tx_desc_dtag);
2194 sc->tx_desc_base = NULL;
2197 if (sc->tx_buf == NULL)
2200 for (i = 0; i < ndesc; i++) {
2201 tx_buffer = &sc->tx_buf[i];
2203 KKASSERT(tx_buffer->m_head == NULL);
2204 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2206 bus_dma_tag_destroy(sc->txtag);
2208 kfree(sc->tx_buf, M_DEVBUF);
2213 * The offload context needs to be set when we transfer the first
2214 * packet of a particular protocol (TCP/UDP). This routine has been
2215 * enhanced to deal with inserted VLAN headers.
2217 * If the new packet's ether header length, ip header length and
2218 * csum offloading type are same as the previous packet, we should
2219 * avoid allocating a new csum context descriptor; mainly to take
2220 * advantage of the pipeline effect of the TX data read request.
2222 * This function returns number of TX descrptors allocated for
2226 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2227 uint32_t *txd_upper, uint32_t *txd_lower)
2229 struct e1000_context_desc *TXD;
2230 int curr_txd, ehdrlen, csum_flags;
2231 uint32_t cmd, hdr_len, ip_hlen;
2233 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2234 ip_hlen = mp->m_pkthdr.csum_iphlen;
2235 ehdrlen = mp->m_pkthdr.csum_lhlen;
2237 if (sc->csum_lhlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2238 sc->csum_flags == csum_flags) {
2240 * Same csum offload context as the previous packets;
2243 *txd_upper = sc->csum_txd_upper;
2244 *txd_lower = sc->csum_txd_lower;
2249 * Setup a new csum offload context.
2252 curr_txd = sc->next_avail_tx_desc;
2253 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2257 /* Setup of IP header checksum. */
2258 if (csum_flags & CSUM_IP) {
2260 * Start offset for header checksum calculation.
2261 * End offset for header checksum calculation.
2262 * Offset of place to put the checksum.
2264 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2265 TXD->lower_setup.ip_fields.ipcse =
2266 htole16(ehdrlen + ip_hlen - 1);
2267 TXD->lower_setup.ip_fields.ipcso =
2268 ehdrlen + offsetof(struct ip, ip_sum);
2269 cmd |= E1000_TXD_CMD_IP;
2270 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2272 hdr_len = ehdrlen + ip_hlen;
2274 if (csum_flags & CSUM_TCP) {
2276 * Start offset for payload checksum calculation.
2277 * End offset for payload checksum calculation.
2278 * Offset of place to put the checksum.
2280 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2281 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2282 TXD->upper_setup.tcp_fields.tucso =
2283 hdr_len + offsetof(struct tcphdr, th_sum);
2284 cmd |= E1000_TXD_CMD_TCP;
2285 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2286 } else if (csum_flags & CSUM_UDP) {
2288 * Start offset for header checksum calculation.
2289 * End offset for header checksum calculation.
2290 * Offset of place to put the checksum.
2292 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2293 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2294 TXD->upper_setup.tcp_fields.tucso =
2295 hdr_len + offsetof(struct udphdr, uh_sum);
2296 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2299 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2300 E1000_TXD_DTYP_D; /* Data descr */
2302 /* Save the information for this csum offloading context */
2303 sc->csum_lhlen = ehdrlen;
2304 sc->csum_iphlen = ip_hlen;
2305 sc->csum_flags = csum_flags;
2306 sc->csum_txd_upper = *txd_upper;
2307 sc->csum_txd_lower = *txd_lower;
2309 TXD->tcp_seg_setup.data = htole32(0);
2310 TXD->cmd_and_length =
2311 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2313 if (++curr_txd == sc->num_tx_desc)
2316 KKASSERT(sc->num_tx_desc_avail > 0);
2317 sc->num_tx_desc_avail--;
2319 sc->next_avail_tx_desc = curr_txd;
2324 emx_txeof(struct emx_softc *sc)
2326 struct ifnet *ifp = &sc->arpcom.ac_if;
2327 struct emx_txbuf *tx_buffer;
2328 int first, num_avail;
2330 if (sc->tx_dd_head == sc->tx_dd_tail)
2333 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2336 num_avail = sc->num_tx_desc_avail;
2337 first = sc->next_tx_to_clean;
2339 while (sc->tx_dd_head != sc->tx_dd_tail) {
2340 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2341 struct e1000_tx_desc *tx_desc;
2343 tx_desc = &sc->tx_desc_base[dd_idx];
2344 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2345 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2347 if (++dd_idx == sc->num_tx_desc)
2350 while (first != dd_idx) {
2355 tx_buffer = &sc->tx_buf[first];
2356 if (tx_buffer->m_head) {
2358 bus_dmamap_unload(sc->txtag,
2360 m_freem(tx_buffer->m_head);
2361 tx_buffer->m_head = NULL;
2364 if (++first == sc->num_tx_desc)
2371 sc->next_tx_to_clean = first;
2372 sc->num_tx_desc_avail = num_avail;
2374 if (sc->tx_dd_head == sc->tx_dd_tail) {
2379 if (!EMX_IS_OACTIVE(sc)) {
2380 ifp->if_flags &= ~IFF_OACTIVE;
2382 /* All clean, turn off the timer */
2383 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2389 emx_tx_collect(struct emx_softc *sc)
2391 struct ifnet *ifp = &sc->arpcom.ac_if;
2392 struct emx_txbuf *tx_buffer;
2393 int tdh, first, num_avail, dd_idx = -1;
2395 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2398 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2399 if (tdh == sc->next_tx_to_clean)
2402 if (sc->tx_dd_head != sc->tx_dd_tail)
2403 dd_idx = sc->tx_dd[sc->tx_dd_head];
2405 num_avail = sc->num_tx_desc_avail;
2406 first = sc->next_tx_to_clean;
2408 while (first != tdh) {
2413 tx_buffer = &sc->tx_buf[first];
2414 if (tx_buffer->m_head) {
2416 bus_dmamap_unload(sc->txtag,
2418 m_freem(tx_buffer->m_head);
2419 tx_buffer->m_head = NULL;
2422 if (first == dd_idx) {
2423 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2424 if (sc->tx_dd_head == sc->tx_dd_tail) {
2429 dd_idx = sc->tx_dd[sc->tx_dd_head];
2433 if (++first == sc->num_tx_desc)
2436 sc->next_tx_to_clean = first;
2437 sc->num_tx_desc_avail = num_avail;
2439 if (!EMX_IS_OACTIVE(sc)) {
2440 ifp->if_flags &= ~IFF_OACTIVE;
2442 /* All clean, turn off the timer */
2443 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2449 * When Link is lost sometimes there is work still in the TX ring
2450 * which will result in a watchdog, rather than allow that do an
2451 * attempted cleanup and then reinit here. Note that this has been
2452 * seens mostly with fiber adapters.
2455 emx_tx_purge(struct emx_softc *sc)
2457 struct ifnet *ifp = &sc->arpcom.ac_if;
2459 if (!sc->link_active && ifp->if_timer) {
2461 if (ifp->if_timer) {
2462 if_printf(ifp, "Link lost, TX pending, reinit\n");
2470 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2473 bus_dma_segment_t seg;
2475 struct emx_rxbuf *rx_buffer;
2478 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2480 rdata->mbuf_cluster_failed++;
2482 if_printf(&sc->arpcom.ac_if,
2483 "Unable to allocate RX mbuf\n");
2487 m->m_len = m->m_pkthdr.len = MCLBYTES;
2489 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2490 m_adj(m, ETHER_ALIGN);
2492 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2493 rdata->rx_sparemap, m,
2494 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2498 if_printf(&sc->arpcom.ac_if,
2499 "Unable to load RX mbuf\n");
2504 rx_buffer = &rdata->rx_buf[i];
2505 if (rx_buffer->m_head != NULL)
2506 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2508 map = rx_buffer->map;
2509 rx_buffer->map = rdata->rx_sparemap;
2510 rdata->rx_sparemap = map;
2512 rx_buffer->m_head = m;
2513 rx_buffer->paddr = seg.ds_addr;
2515 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2520 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2522 device_t dev = sc->dev;
2523 struct emx_rxbuf *rx_buffer;
2524 int i, error, rsize, nrxd;
2527 * Validate number of receive descriptors. It must not exceed
2528 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2530 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2531 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2532 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2533 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2534 EMX_DEFAULT_RXD, nrxd);
2535 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2537 rdata->num_rx_desc = nrxd;
2541 * Allocate Receive Descriptor ring
2543 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2545 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2546 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2547 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2548 &rdata->rx_desc_paddr);
2549 if (rdata->rx_desc == NULL) {
2550 device_printf(dev, "Unable to allocate rx_desc memory\n");
2554 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2555 M_DEVBUF, M_WAITOK | M_ZERO);
2558 * Create DMA tag for rx buffers
2560 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2561 1, 0, /* alignment, bounds */
2562 BUS_SPACE_MAXADDR, /* lowaddr */
2563 BUS_SPACE_MAXADDR, /* highaddr */
2564 NULL, NULL, /* filter, filterarg */
2565 MCLBYTES, /* maxsize */
2567 MCLBYTES, /* maxsegsize */
2568 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2571 device_printf(dev, "Unable to allocate RX DMA tag\n");
2572 kfree(rdata->rx_buf, M_DEVBUF);
2573 rdata->rx_buf = NULL;
2578 * Create spare DMA map for rx buffers
2580 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2581 &rdata->rx_sparemap);
2583 device_printf(dev, "Unable to create spare RX DMA map\n");
2584 bus_dma_tag_destroy(rdata->rxtag);
2585 kfree(rdata->rx_buf, M_DEVBUF);
2586 rdata->rx_buf = NULL;
2591 * Create DMA maps for rx buffers
2593 for (i = 0; i < rdata->num_rx_desc; i++) {
2594 rx_buffer = &rdata->rx_buf[i];
2596 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2599 device_printf(dev, "Unable to create RX DMA map\n");
2600 emx_destroy_rx_ring(sc, rdata, i);
2608 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2612 for (i = 0; i < rdata->num_rx_desc; i++) {
2613 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2615 if (rx_buffer->m_head != NULL) {
2616 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2617 m_freem(rx_buffer->m_head);
2618 rx_buffer->m_head = NULL;
2622 if (rdata->fmp != NULL)
2623 m_freem(rdata->fmp);
2629 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2633 /* Reset descriptor ring */
2634 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2636 /* Allocate new ones. */
2637 for (i = 0; i < rdata->num_rx_desc; i++) {
2638 error = emx_newbuf(sc, rdata, i, 1);
2643 /* Setup our descriptor pointers */
2644 rdata->next_rx_desc_to_check = 0;
2650 emx_init_rx_unit(struct emx_softc *sc)
2652 struct ifnet *ifp = &sc->arpcom.ac_if;
2654 uint32_t rctl, itr, rfctl;
2658 * Make sure receives are disabled while setting
2659 * up the descriptor ring
2661 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2662 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2665 * Set the interrupt throttling rate. Value is calculated
2666 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2668 if (sc->int_throttle_ceil)
2669 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2672 emx_set_itr(sc, itr);
2674 /* Use extended RX descriptor */
2675 rfctl = E1000_RFCTL_EXTEN;
2677 /* Disable accelerated ackknowledge */
2678 if (sc->hw.mac.type == e1000_82574)
2679 rfctl |= E1000_RFCTL_ACK_DIS;
2681 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2684 * Receive Checksum Offload for TCP and UDP
2686 * Checksum offloading is also enabled if multiple receive
2687 * queue is to be supported, since we need it to figure out
2690 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2691 sc->rx_ring_cnt > 1) {
2694 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2698 * PCSD must be enabled to enable multiple
2701 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2703 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2707 * Configure multiple receive queue (RSS)
2709 if (sc->rx_ring_cnt > 1) {
2710 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2713 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2714 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2718 * When we reach here, RSS has already been disabled
2719 * in emx_stop(), so we could safely configure RSS key
2720 * and redirect table.
2726 toeplitz_get_key(key, sizeof(key));
2727 for (i = 0; i < EMX_NRSSRK; ++i) {
2730 rssrk = EMX_RSSRK_VAL(key, i);
2731 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2733 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2737 * Configure RSS redirect table in following fashion:
2738 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2741 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2744 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2745 reta |= q << (8 * i);
2747 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2749 for (i = 0; i < EMX_NRETA; ++i)
2750 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2753 * Enable multiple receive queues.
2754 * Enable IPv4 RSS standard hash functions.
2755 * Disable RSS interrupt.
2757 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2758 E1000_MRQC_ENABLE_RSS_2Q |
2759 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2760 E1000_MRQC_RSS_FIELD_IPV4);
2764 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2765 * long latencies are observed, like Lenovo X60. This
2766 * change eliminates the problem, but since having positive
2767 * values in RDTR is a known source of problems on other
2768 * platforms another solution is being sought.
2770 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2771 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2772 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2775 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2776 struct emx_rxdata *rdata = &sc->rx_data[i];
2779 * Setup the Base and Length of the Rx Descriptor Ring
2781 bus_addr = rdata->rx_desc_paddr;
2782 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2783 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2784 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2785 (uint32_t)(bus_addr >> 32));
2786 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2787 (uint32_t)bus_addr);
2790 * Setup the HW Rx Head and Tail Descriptor Pointers
2792 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2793 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2794 sc->rx_data[i].num_rx_desc - 1);
2797 /* Setup the Receive Control Register */
2798 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2799 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2800 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2801 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2803 /* Make sure VLAN Filters are off */
2804 rctl &= ~E1000_RCTL_VFE;
2806 /* Don't store bad paket */
2807 rctl &= ~E1000_RCTL_SBP;
2810 rctl |= E1000_RCTL_SZ_2048;
2812 if (ifp->if_mtu > ETHERMTU)
2813 rctl |= E1000_RCTL_LPE;
2815 rctl &= ~E1000_RCTL_LPE;
2817 /* Enable Receives */
2818 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2822 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2824 struct emx_rxbuf *rx_buffer;
2827 /* Free Receive Descriptor ring */
2828 if (rdata->rx_desc) {
2829 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2830 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2831 rdata->rx_desc_dmap);
2832 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2834 rdata->rx_desc = NULL;
2837 if (rdata->rx_buf == NULL)
2840 for (i = 0; i < ndesc; i++) {
2841 rx_buffer = &rdata->rx_buf[i];
2843 KKASSERT(rx_buffer->m_head == NULL);
2844 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2846 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2847 bus_dma_tag_destroy(rdata->rxtag);
2849 kfree(rdata->rx_buf, M_DEVBUF);
2850 rdata->rx_buf = NULL;
2854 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2856 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2857 struct ifnet *ifp = &sc->arpcom.ac_if;
2859 emx_rxdesc_t *current_desc;
2863 i = rdata->next_rx_desc_to_check;
2864 current_desc = &rdata->rx_desc[i];
2865 staterr = le32toh(current_desc->rxd_staterr);
2867 if (!(staterr & E1000_RXD_STAT_DD))
2870 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2871 struct pktinfo *pi = NULL, pi0;
2872 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2873 struct mbuf *m = NULL;
2878 mp = rx_buf->m_head;
2881 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2882 * needs to access the last received byte in the mbuf.
2884 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2885 BUS_DMASYNC_POSTREAD);
2887 len = le16toh(current_desc->rxd_length);
2888 if (staterr & E1000_RXD_STAT_EOP) {
2895 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2897 uint32_t mrq, rss_hash;
2900 * Save several necessary information,
2901 * before emx_newbuf() destroy it.
2903 if ((staterr & E1000_RXD_STAT_VP) && eop)
2904 vlan = le16toh(current_desc->rxd_vlan);
2906 mrq = le32toh(current_desc->rxd_mrq);
2907 rss_hash = le32toh(current_desc->rxd_rss);
2909 EMX_RSS_DPRINTF(sc, 10,
2910 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2911 ring_idx, mrq, rss_hash);
2913 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2918 /* Assign correct length to the current fragment */
2921 if (rdata->fmp == NULL) {
2922 mp->m_pkthdr.len = len;
2923 rdata->fmp = mp; /* Store the first mbuf */
2927 * Chain mbuf's together
2929 rdata->lmp->m_next = mp;
2930 rdata->lmp = rdata->lmp->m_next;
2931 rdata->fmp->m_pkthdr.len += len;
2935 rdata->fmp->m_pkthdr.rcvif = ifp;
2938 if (ifp->if_capenable & IFCAP_RXCSUM)
2939 emx_rxcsum(staterr, rdata->fmp);
2941 if (staterr & E1000_RXD_STAT_VP) {
2942 rdata->fmp->m_pkthdr.ether_vlantag =
2944 rdata->fmp->m_flags |= M_VLANTAG;
2950 if (ifp->if_capenable & IFCAP_RSS) {
2951 pi = emx_rssinfo(m, &pi0, mrq,
2954 #ifdef EMX_RSS_DEBUG
2961 emx_setup_rxdesc(current_desc, rx_buf);
2962 if (rdata->fmp != NULL) {
2963 m_freem(rdata->fmp);
2971 ether_input_pkt(ifp, m, pi);
2973 /* Advance our pointers to the next descriptor. */
2974 if (++i == rdata->num_rx_desc)
2977 current_desc = &rdata->rx_desc[i];
2978 staterr = le32toh(current_desc->rxd_staterr);
2980 rdata->next_rx_desc_to_check = i;
2982 /* Advance the E1000's Receive Queue "Tail Pointer". */
2984 i = rdata->num_rx_desc - 1;
2985 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2989 emx_enable_intr(struct emx_softc *sc)
2991 uint32_t ims_mask = IMS_ENABLE_MASK;
2993 lwkt_serialize_handler_enable(&sc->main_serialize);
2996 if (sc->hw.mac.type == e1000_82574) {
2997 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
2998 ims_mask |= EM_MSIX_MASK;
3001 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3005 emx_disable_intr(struct emx_softc *sc)
3007 if (sc->hw.mac.type == e1000_82574)
3008 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3009 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3011 lwkt_serialize_handler_disable(&sc->main_serialize);
3015 * Bit of a misnomer, what this really means is
3016 * to enable OS management of the system... aka
3017 * to disable special hardware management features
3020 emx_get_mgmt(struct emx_softc *sc)
3022 /* A shared code workaround */
3023 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3024 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3025 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3027 /* disable hardware interception of ARP */
3028 manc &= ~(E1000_MANC_ARP_EN);
3030 /* enable receiving management packets to the host */
3031 manc |= E1000_MANC_EN_MNG2HOST;
3032 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3033 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3034 manc2h |= E1000_MNG2HOST_PORT_623;
3035 manc2h |= E1000_MNG2HOST_PORT_664;
3036 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3038 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3043 * Give control back to hardware management
3044 * controller if there is one.
3047 emx_rel_mgmt(struct emx_softc *sc)
3049 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3050 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3052 /* re-enable hardware interception of ARP */
3053 manc |= E1000_MANC_ARP_EN;
3054 manc &= ~E1000_MANC_EN_MNG2HOST;
3056 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3061 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3062 * For ASF and Pass Through versions of f/w this means that
3063 * the driver is loaded. For AMT version (only with 82573)
3064 * of the f/w this means that the network i/f is open.
3067 emx_get_hw_control(struct emx_softc *sc)
3069 /* Let firmware know the driver has taken over */
3070 if (sc->hw.mac.type == e1000_82573) {
3073 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3074 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3075 swsm | E1000_SWSM_DRV_LOAD);
3079 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3080 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3081 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3083 sc->flags |= EMX_FLAG_HW_CTRL;
3087 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3088 * For ASF and Pass Through versions of f/w this means that the
3089 * driver is no longer loaded. For AMT version (only with 82573)
3090 * of the f/w this means that the network i/f is closed.
3093 emx_rel_hw_control(struct emx_softc *sc)
3095 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3097 sc->flags &= ~EMX_FLAG_HW_CTRL;
3099 /* Let firmware taken over control of h/w */
3100 if (sc->hw.mac.type == e1000_82573) {
3103 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3104 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3105 swsm & ~E1000_SWSM_DRV_LOAD);
3109 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3110 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3111 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3116 emx_is_valid_eaddr(const uint8_t *addr)
3118 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3120 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3127 * Enable PCI Wake On Lan capability
3130 emx_enable_wol(device_t dev)
3132 uint16_t cap, status;
3135 /* First find the capabilities pointer*/
3136 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3138 /* Read the PM Capabilities */
3139 id = pci_read_config(dev, cap, 1);
3140 if (id != PCIY_PMG) /* Something wrong */
3144 * OK, we have the power capabilities,
3145 * so now get the status register
3147 cap += PCIR_POWER_STATUS;
3148 status = pci_read_config(dev, cap, 2);
3149 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3150 pci_write_config(dev, cap, status, 2);
3154 emx_update_stats(struct emx_softc *sc)
3156 struct ifnet *ifp = &sc->arpcom.ac_if;
3158 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3159 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3160 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3161 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3163 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3164 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3165 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3166 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3168 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3169 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3170 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3171 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3172 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3173 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3174 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3175 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3176 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3177 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3178 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3179 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3180 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3181 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3182 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3183 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3184 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3185 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3186 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3187 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3189 /* For the 64-bit byte counters the low dword must be read first. */
3190 /* Both registers clear on the read of the high dword */
3192 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3193 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3195 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3196 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3197 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3198 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3199 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3201 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3202 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3204 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3205 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3206 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3207 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3208 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3209 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3210 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3211 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3212 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3213 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3215 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3216 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3217 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3218 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3219 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3220 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3222 ifp->if_collisions = sc->stats.colc;
3225 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3226 sc->stats.crcerrs + sc->stats.algnerrc +
3227 sc->stats.ruc + sc->stats.roc +
3228 sc->stats.mpc + sc->stats.cexterr;
3231 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3232 sc->watchdog_events;
3236 emx_print_debug_info(struct emx_softc *sc)
3238 device_t dev = sc->dev;
3239 uint8_t *hw_addr = sc->hw.hw_addr;
3241 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3242 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3243 E1000_READ_REG(&sc->hw, E1000_CTRL),
3244 E1000_READ_REG(&sc->hw, E1000_RCTL));
3245 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3246 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3247 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3248 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3249 sc->hw.fc.high_water, sc->hw.fc.low_water);
3250 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3251 E1000_READ_REG(&sc->hw, E1000_TIDV),
3252 E1000_READ_REG(&sc->hw, E1000_TADV));
3253 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3254 E1000_READ_REG(&sc->hw, E1000_RDTR),
3255 E1000_READ_REG(&sc->hw, E1000_RADV));
3256 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3257 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3258 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3259 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3260 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3261 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3262 device_printf(dev, "Num Tx descriptors avail = %d\n",
3263 sc->num_tx_desc_avail);
3264 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3265 sc->no_tx_desc_avail1);
3266 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3267 sc->no_tx_desc_avail2);
3268 device_printf(dev, "Std mbuf failed = %ld\n",
3269 sc->mbuf_alloc_failed);
3270 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3271 sc->rx_data[0].mbuf_cluster_failed);
3272 device_printf(dev, "Driver dropped packets = %ld\n",
3274 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3275 sc->no_tx_dma_setup);
3277 device_printf(dev, "TSO segments %lu\n", sc->tso_segments);
3278 device_printf(dev, "TSO ctx reused %lu\n", sc->tso_ctx_reused);
3282 emx_print_hw_stats(struct emx_softc *sc)
3284 device_t dev = sc->dev;
3286 device_printf(dev, "Excessive collisions = %lld\n",
3287 (long long)sc->stats.ecol);
3288 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3289 device_printf(dev, "Symbol errors = %lld\n",
3290 (long long)sc->stats.symerrs);
3292 device_printf(dev, "Sequence errors = %lld\n",
3293 (long long)sc->stats.sec);
3294 device_printf(dev, "Defer count = %lld\n",
3295 (long long)sc->stats.dc);
3296 device_printf(dev, "Missed Packets = %lld\n",
3297 (long long)sc->stats.mpc);
3298 device_printf(dev, "Receive No Buffers = %lld\n",
3299 (long long)sc->stats.rnbc);
3300 /* RLEC is inaccurate on some hardware, calculate our own. */
3301 device_printf(dev, "Receive Length Errors = %lld\n",
3302 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3303 device_printf(dev, "Receive errors = %lld\n",
3304 (long long)sc->stats.rxerrc);
3305 device_printf(dev, "Crc errors = %lld\n",
3306 (long long)sc->stats.crcerrs);
3307 device_printf(dev, "Alignment errors = %lld\n",
3308 (long long)sc->stats.algnerrc);
3309 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3310 (long long)sc->stats.cexterr);
3311 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3312 device_printf(dev, "watchdog timeouts = %ld\n",
3313 sc->watchdog_events);
3314 device_printf(dev, "XON Rcvd = %lld\n",
3315 (long long)sc->stats.xonrxc);
3316 device_printf(dev, "XON Xmtd = %lld\n",
3317 (long long)sc->stats.xontxc);
3318 device_printf(dev, "XOFF Rcvd = %lld\n",
3319 (long long)sc->stats.xoffrxc);
3320 device_printf(dev, "XOFF Xmtd = %lld\n",
3321 (long long)sc->stats.xofftxc);
3322 device_printf(dev, "Good Packets Rcvd = %lld\n",
3323 (long long)sc->stats.gprc);
3324 device_printf(dev, "Good Packets Xmtd = %lld\n",
3325 (long long)sc->stats.gptc);
3329 emx_print_nvm_info(struct emx_softc *sc)
3331 uint16_t eeprom_data;
3334 /* Its a bit crude, but it gets the job done */
3335 kprintf("\nInterface EEPROM Dump:\n");
3336 kprintf("Offset\n0x0000 ");
3337 for (i = 0, j = 0; i < 32; i++, j++) {
3338 if (j == 8) { /* Make the offset block */
3340 kprintf("\n0x00%x0 ",row);
3342 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3343 kprintf("%04x ", eeprom_data);
3349 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3351 struct emx_softc *sc;
3356 error = sysctl_handle_int(oidp, &result, 0, req);
3357 if (error || !req->newptr)
3360 sc = (struct emx_softc *)arg1;
3361 ifp = &sc->arpcom.ac_if;
3363 ifnet_serialize_all(ifp);
3366 emx_print_debug_info(sc);
3369 * This value will cause a hex dump of the
3370 * first 32 16-bit words of the EEPROM to
3374 emx_print_nvm_info(sc);
3376 ifnet_deserialize_all(ifp);
3382 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3387 error = sysctl_handle_int(oidp, &result, 0, req);
3388 if (error || !req->newptr)
3392 struct emx_softc *sc = (struct emx_softc *)arg1;
3393 struct ifnet *ifp = &sc->arpcom.ac_if;
3395 ifnet_serialize_all(ifp);
3396 emx_print_hw_stats(sc);
3397 ifnet_deserialize_all(ifp);
3403 emx_add_sysctl(struct emx_softc *sc)
3405 #ifdef EMX_RSS_DEBUG
3410 sysctl_ctx_init(&sc->sysctl_ctx);
3411 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3412 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3413 device_get_nameunit(sc->dev),
3415 if (sc->sysctl_tree == NULL) {
3416 device_printf(sc->dev, "can't add sysctl node\n");
3420 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3421 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3422 emx_sysctl_debug_info, "I", "Debug Information");
3424 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3425 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3426 emx_sysctl_stats, "I", "Statistics");
3428 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3429 OID_AUTO, "rxd", CTLFLAG_RD,
3430 &sc->rx_data[0].num_rx_desc, 0, NULL);
3431 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3432 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3434 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3435 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3436 sc, 0, emx_sysctl_int_throttle, "I",
3437 "interrupt throttling rate");
3438 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3439 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3440 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3441 "# segments per TX interrupt");
3443 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3444 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD,
3445 &sc->rx_ring_cnt, 0, "RX ring count");
3447 #ifdef IFPOLL_ENABLE
3448 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3449 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3450 sc, 0, emx_sysctl_npoll_rxoff, "I",
3451 "NPOLLING RX cpu offset");
3452 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3453 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3454 sc, 0, emx_sysctl_npoll_txoff, "I",
3455 "NPOLLING TX cpu offset");
3458 #ifdef EMX_RSS_DEBUG
3459 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3460 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3461 0, "RSS debug level");
3462 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3463 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3464 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3465 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3467 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3473 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3475 struct emx_softc *sc = (void *)arg1;
3476 struct ifnet *ifp = &sc->arpcom.ac_if;
3477 int error, throttle;
3479 throttle = sc->int_throttle_ceil;
3480 error = sysctl_handle_int(oidp, &throttle, 0, req);
3481 if (error || req->newptr == NULL)
3483 if (throttle < 0 || throttle > 1000000000 / 256)
3488 * Set the interrupt throttling rate in 256ns increments,
3489 * recalculate sysctl value assignment to get exact frequency.
3491 throttle = 1000000000 / 256 / throttle;
3493 /* Upper 16bits of ITR is reserved and should be zero */
3494 if (throttle & 0xffff0000)
3498 ifnet_serialize_all(ifp);
3501 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3503 sc->int_throttle_ceil = 0;
3505 if (ifp->if_flags & IFF_RUNNING)
3506 emx_set_itr(sc, throttle);
3508 ifnet_deserialize_all(ifp);
3511 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3512 sc->int_throttle_ceil);
3518 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3520 struct emx_softc *sc = (void *)arg1;
3521 struct ifnet *ifp = &sc->arpcom.ac_if;
3524 segs = sc->tx_int_nsegs;
3525 error = sysctl_handle_int(oidp, &segs, 0, req);
3526 if (error || req->newptr == NULL)
3531 ifnet_serialize_all(ifp);
3534 * Don't allow int_tx_nsegs to become:
3535 * o Less the oact_tx_desc
3536 * o Too large that no TX desc will cause TX interrupt to
3537 * be generated (OACTIVE will never recover)
3538 * o Too small that will cause tx_dd[] overflow
3540 if (segs < sc->oact_tx_desc ||
3541 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3542 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3546 sc->tx_int_nsegs = segs;
3549 ifnet_deserialize_all(ifp);
3554 #ifdef IFPOLL_ENABLE
3557 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3559 struct emx_softc *sc = (void *)arg1;
3560 struct ifnet *ifp = &sc->arpcom.ac_if;
3563 off = sc->rx_npoll_off;
3564 error = sysctl_handle_int(oidp, &off, 0, req);
3565 if (error || req->newptr == NULL)
3570 ifnet_serialize_all(ifp);
3571 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3575 sc->rx_npoll_off = off;
3577 ifnet_deserialize_all(ifp);
3583 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3585 struct emx_softc *sc = (void *)arg1;
3586 struct ifnet *ifp = &sc->arpcom.ac_if;
3589 off = sc->tx_npoll_off;
3590 error = sysctl_handle_int(oidp, &off, 0, req);
3591 if (error || req->newptr == NULL)
3596 ifnet_serialize_all(ifp);
3597 if (off >= ncpus2) {
3601 sc->tx_npoll_off = off;
3603 ifnet_deserialize_all(ifp);
3608 #endif /* IFPOLL_ENABLE */
3611 emx_dma_alloc(struct emx_softc *sc)
3616 * Create top level busdma tag
3618 error = bus_dma_tag_create(NULL, 1, 0,
3619 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3621 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3622 0, &sc->parent_dtag);
3624 device_printf(sc->dev, "could not create top level DMA tag\n");
3629 * Allocate transmit descriptors ring and buffers
3631 error = emx_create_tx_ring(sc);
3633 device_printf(sc->dev, "Could not setup transmit structures\n");
3638 * Allocate receive descriptors ring and buffers
3640 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3641 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3643 device_printf(sc->dev,
3644 "Could not setup receive structures\n");
3652 emx_dma_free(struct emx_softc *sc)
3656 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3658 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3659 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3660 sc->rx_data[i].num_rx_desc);
3663 /* Free top level busdma tag */
3664 if (sc->parent_dtag != NULL)
3665 bus_dma_tag_destroy(sc->parent_dtag);
3669 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3671 struct emx_softc *sc = ifp->if_softc;
3673 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE,
3674 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3678 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3680 struct emx_softc *sc = ifp->if_softc;
3682 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE,
3683 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3687 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3689 struct emx_softc *sc = ifp->if_softc;
3691 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE,
3692 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz);
3696 emx_serialize_skipmain(struct emx_softc *sc)
3698 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3702 emx_deserialize_skipmain(struct emx_softc *sc)
3704 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3710 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3711 boolean_t serialized)
3713 struct emx_softc *sc = ifp->if_softc;
3715 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3716 EMX_TX_SERIALIZE, EMX_RX_SERIALIZE, slz, serialized);
3719 #endif /* INVARIANTS */
3721 #ifdef IFPOLL_ENABLE
3724 emx_npoll_status(struct ifnet *ifp, int pollhz __unused)
3726 struct emx_softc *sc = ifp->if_softc;
3729 ASSERT_SERIALIZED(&sc->main_serialize);
3731 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3732 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3733 callout_stop(&sc->timer);
3734 sc->hw.mac.get_link_status = 1;
3735 emx_update_link_status(sc);
3736 callout_reset(&sc->timer, hz, emx_timer, sc);
3741 emx_npoll_tx(struct ifnet *ifp, void *arg __unused, int cycle __unused)
3743 struct emx_softc *sc = ifp->if_softc;
3745 ASSERT_SERIALIZED(&sc->tx_serialize);
3748 if (!ifq_is_empty(&ifp->if_snd))
3753 emx_npoll_rx(struct ifnet *ifp, void *arg, int cycle)
3755 struct emx_softc *sc = ifp->if_softc;
3756 struct emx_rxdata *rdata = arg;
3758 ASSERT_SERIALIZED(&rdata->rx_serialize);
3760 emx_rxeof(sc, rdata - sc->rx_data, cycle);
3764 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3766 struct emx_softc *sc = ifp->if_softc;
3768 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3773 info->ifpi_status.status_func = emx_npoll_status;
3774 info->ifpi_status.serializer = &sc->main_serialize;
3776 off = sc->tx_npoll_off;
3777 KKASSERT(off < ncpus2);
3778 info->ifpi_tx[off].poll_func = emx_npoll_tx;
3779 info->ifpi_tx[off].arg = NULL;
3780 info->ifpi_tx[off].serializer = &sc->tx_serialize;
3782 off = sc->rx_npoll_off;
3783 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3784 struct emx_rxdata *rdata = &sc->rx_data[i];
3787 KKASSERT(idx < ncpus2);
3788 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
3789 info->ifpi_rx[idx].arg = rdata;
3790 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
3793 if (ifp->if_flags & IFF_RUNNING)
3794 emx_disable_intr(sc);
3795 ifp->if_npoll_cpuid = sc->tx_npoll_off;
3797 if (ifp->if_flags & IFF_RUNNING)
3798 emx_enable_intr(sc);
3799 ifp->if_npoll_cpuid = -1;
3803 #endif /* IFPOLL_ENABLE */
3806 emx_set_itr(struct emx_softc *sc, uint32_t itr)
3808 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
3809 if (sc->hw.mac.type == e1000_82574) {
3813 * When using MSIX interrupts we need to
3814 * throttle using the EITR register
3816 for (i = 0; i < 4; ++i)
3817 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
3822 * Disable the L0s, 82574L Errata #20
3825 emx_disable_aspm(struct emx_softc *sc)
3827 uint16_t link_cap, link_ctrl, disable;
3828 uint8_t pcie_ptr, reg;
3829 device_t dev = sc->dev;
3831 switch (sc->hw.mac.type) {
3836 * 82573 specification update
3837 * errata #8 disable L0s
3838 * errata #41 disable L1
3840 * 82571/82572 specification update
3841 # errata #13 disable L1
3842 * errata #68 disable L0s
3844 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
3849 * 82574 specification update errata #20
3851 * There is no need to disable L1
3853 disable = PCIEM_LNKCTL_ASPM_L0S;
3860 pcie_ptr = pci_get_pciecap_ptr(dev);
3864 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
3865 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
3869 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
3871 reg = pcie_ptr + PCIER_LINKCTRL;
3872 link_ctrl = pci_read_config(dev, reg, 2);
3873 link_ctrl &= ~disable;
3874 pci_write_config(dev, reg, link_ctrl, 2);
3878 emx_tso_pullup(struct emx_softc *sc, struct mbuf **mp)
3880 int iphlen, hoff, thoff, ex = 0;
3885 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
3887 iphlen = m->m_pkthdr.csum_iphlen;
3888 thoff = m->m_pkthdr.csum_thlen;
3889 hoff = m->m_pkthdr.csum_lhlen;
3891 KASSERT(iphlen > 0, ("invalid ip hlen"));
3892 KASSERT(thoff > 0, ("invalid tcp hlen"));
3893 KASSERT(hoff > 0, ("invalid ether hlen"));
3895 if (sc->flags & EMX_FLAG_TSO_PULLEX)
3898 if (m->m_len < hoff + iphlen + thoff + ex) {
3899 m = m_pullup(m, hoff + iphlen + thoff + ex);
3906 ip = mtodoff(m, struct ip *, hoff);
3913 emx_tso_setup(struct emx_softc *sc, struct mbuf *mp,
3914 uint32_t *txd_upper, uint32_t *txd_lower)
3916 struct e1000_context_desc *TXD;
3917 int hoff, iphlen, thoff, hlen;
3918 int mss, pktlen, curr_txd;
3920 #ifdef EMX_TSO_DEBUG
3924 iphlen = mp->m_pkthdr.csum_iphlen;
3925 thoff = mp->m_pkthdr.csum_thlen;
3926 hoff = mp->m_pkthdr.csum_lhlen;
3927 mss = mp->m_pkthdr.tso_segsz;
3928 pktlen = mp->m_pkthdr.len;
3930 if (sc->csum_flags == CSUM_TSO &&
3931 sc->csum_iphlen == iphlen &&
3932 sc->csum_lhlen == hoff &&
3933 sc->csum_thlen == thoff &&
3934 sc->csum_mss == mss &&
3935 sc->csum_pktlen == pktlen) {
3936 *txd_upper = sc->csum_txd_upper;
3937 *txd_lower = sc->csum_txd_lower;
3938 #ifdef EMX_TSO_DEBUG
3939 sc->tso_ctx_reused++;
3943 hlen = hoff + iphlen + thoff;
3946 * Setup a new TSO context.
3949 curr_txd = sc->next_avail_tx_desc;
3950 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
3952 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
3953 E1000_TXD_DTYP_D | /* Data descr type */
3954 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
3956 /* IP and/or TCP header checksum calculation and insertion. */
3957 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
3960 * Start offset for header checksum calculation.
3961 * End offset for header checksum calculation.
3962 * Offset of place put the checksum.
3964 TXD->lower_setup.ip_fields.ipcss = hoff;
3965 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
3966 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
3969 * Start offset for payload checksum calculation.
3970 * End offset for payload checksum calculation.
3971 * Offset of place to put the checksum.
3973 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
3974 TXD->upper_setup.tcp_fields.tucse = 0;
3975 TXD->upper_setup.tcp_fields.tucso =
3976 hoff + iphlen + offsetof(struct tcphdr, th_sum);
3979 * Payload size per packet w/o any headers.
3980 * Length of all headers up to payload.
3982 TXD->tcp_seg_setup.fields.mss = htole16(mss);
3983 TXD->tcp_seg_setup.fields.hdr_len = hlen;
3984 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
3985 E1000_TXD_CMD_DEXT | /* Extended descr */
3986 E1000_TXD_CMD_TSE | /* TSE context */
3987 E1000_TXD_CMD_IP | /* Do IP csum */
3988 E1000_TXD_CMD_TCP | /* Do TCP checksum */
3989 (pktlen - hlen)); /* Total len */
3991 /* Save the information for this TSO context */
3992 sc->csum_flags = CSUM_TSO;
3993 sc->csum_lhlen = hoff;
3994 sc->csum_iphlen = iphlen;
3995 sc->csum_thlen = thoff;
3997 sc->csum_pktlen = pktlen;
3998 sc->csum_txd_upper = *txd_upper;
3999 sc->csum_txd_lower = *txd_lower;
4001 if (++curr_txd == sc->num_tx_desc)
4004 KKASSERT(sc->num_tx_desc_avail > 0);
4005 sc->num_tx_desc_avail--;
4007 sc->next_avail_tx_desc = curr_txd;