3 .\" Copyright (c) 1996 A.R.Gordon, andrew.gordon@net-tel.co.uk
4 .\" All rights reserved.
6 .\" Redistribution and use in source and binary forms, with or without
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16 .\" This product includes software developed by the University of
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34 .\" Id: man4.i386/lp.4,v 1.9 1999/02/14 12:06:16 nsouch Exp
35 .\" $FreeBSD: src/share/man/man4/lp.4,v 1.5.2.3 2000/12/29 10:18:00 ru Exp $
42 .Nd printer port Internet Protocol driver
46 .Ar myaddress hisaddress
51 .Cd "device ppc0 at isa? port? irq 7"
55 driver allows a PC parallel printer port to be used as a
56 point-to-point network interface between two similarly configured systems.
57 Data is transferred 4 bits at a time, using the printer status lines for
58 input: hence there is no requirement for special bidirectional hardware
59 and any standard AT-compatible printer port with working interrupts may be used.
61 During the boot process, for each
63 device which is probed and has an interrupt assigned, a corresponding
71 causes the corresponding
73 to be reserved for PLIP until the network interface is configured 'down'.
75 The communication protocol is selected by the
82 mode (LPIP). This is the simpler of the two modes
83 and therefore slightly more efficient.
85 Use Crynwr/Linux compatible mode (CLPIP). This mode has a simulated ethernet
86 packet header, and is easier to interface to other types of equipment.
89 The interface MTU defaults to 1500, but may be set to any value. Both ends
90 of the link must be configured with the same MTU.
92 The cable connecting the two parallel ports should be wired as follows:
108 Cables with this wiring are widely available as 'Laplink' cables, and
109 are often coloured yellow.
111 The connections are symmetric, and provide 5 lines in each direction (four
112 data plus one handshake). The two modes use the same wiring, but make a
113 different choice of which line to use as handshake.
115 The signal lines are used as follows:
116 .Bl -tag -width dataxxxx(Pinxx)
127 .It Em ERROR* (pin 15)
139 When idle, all data lines are at zero. Each byte is signalled in four steps:
140 sender writes the 4 most significant bits and raises the handshake line;
141 receiver reads the 4 bits and raises its handshake to acknowledge;
142 sender places the 4 least significant bits on the data lines and lowers
143 the handshake; receiver reads the data and lowers its handshake.
145 The packet format has a two-byte header, comprising the fixed values 0x08,
146 0x00, immediately followed by the IP header and data.
148 The start of a packet is indicated by simply signalling the first byte
149 of the header. The end of the packet is indicated by inverting
150 the data lines (ie. writing the ones-complement of the previous nibble
151 to be transmitted) without changing the state of the handshake.
153 Note that the end-of-packet marker assumes that the handshake signal and
154 the data-out bits can be written in a single instruction - otherwise
155 certain byte values in the packet data would falsely be interpreted
156 as end-of-packet. This is not a problem for the PC printer port,
157 but requires care when implementing this protocol on other equipment.
158 .Ss Crynwr/Linux CLPIP mode
159 The signal lines are used as follows:
160 .Bl -tag -width dataxxxx(Pinxx)
171 .It Em ERROR* (pin 15)
183 When idle, all data lines are at zero. Each byte is signalled in four steps:
184 sender writes the 4 least significant bits and raises the handshake line;
185 receiver reads the 4 bits and raises its handshake to acknowledge;
186 sender places the 4 most significant bits on the data lines and lowers
187 the handshake; receiver reads the data and lowers its handshake.
188 [Note that this is the opposite nibble order to LPIP mode].
192 Length (least significant byte)
193 Length (most significant byte)
194 12 bytes of supposed MAC addresses (ignored by
202 The length includes the 14 header bytes, but not the length bytes themselves
203 nor the checksum byte.
205 The checksum is a simple arithmetic sum of all the bytes (again, including
206 the header but not checksum or length bytes).
209 outgoing checksums, but does not validate incoming ones.
211 The start of packet has to be signalled specially, since the line chosen
212 for handshake-in cannot be used to generate an interrupt. The sender
213 writes the value 0x08 to the data lines, and waits for the receiver
214 to respond by writing 0x01 to its data lines. The sender then starts
215 signalling the first byte of the packet (the length byte).
217 End of packet is deduced from the packet length and is not signalled
218 specially (although the data lines are restored to the zero, idle
219 state to avoid spuriously indicating the start of the next packet).
225 Busy-waiting loops are used while handshaking bytes, (and worse still when
226 waiting for the receiving system to respond to an interrupt for the start
227 of a packet). Hence a fast system talking to a slow one will consume
228 excessive amounts of CPU. This is unavoidable in the case of CLPIP mode
229 due to the choice of handshake lines; it could theoretically be improved
230 in the case of LPIP mode.
232 Polling timeouts are controlled by counting loop iterations rather than
233 timers, and so are dependent on CPU speed. This is somewhat stabilised
234 by the need to perform (slow) ISA bus cycles to actually read the port.