drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_vgpu.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include "intel_mocs.h"
  36 #include <linux/shmem_fs.h>
  37 #include <linux/slab.h>
  38 #include <linux/swap.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-buf.h>
  41
  42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  44 static void
  45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
  46 static void
  47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
  48
  49 static bool cpu_cache_is_coherent(struct drm_device *dev,
  50                                   enum i915_cache_level level)
  51 {
  52         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  53 }
  54
  55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  56 {
  57         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  58                 return true;
  59
  60         return obj->pin_display;
  61 }
  62
  63 /* some bookkeeping */
  64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  65                                   size_t size)
  66 {
  67         spin_lock(&dev_priv->mm.object_stat_lock);
  68         dev_priv->mm.object_count++;
  69         dev_priv->mm.object_memory += size;
  70         spin_unlock(&dev_priv->mm.object_stat_lock);
  71 }
  72
  73 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  74                                      size_t size)
  75 {
  76         spin_lock(&dev_priv->mm.object_stat_lock);
  77         dev_priv->mm.object_count--;
  78         dev_priv->mm.object_memory -= size;
  79         spin_unlock(&dev_priv->mm.object_stat_lock);
  80 }
  81
  82 static int
  83 i915_gem_wait_for_error(struct i915_gpu_error *error)
  84 {
  85         int ret;
  86
  87         if (!i915_reset_in_progress(error))
  88                 return 0;
  89
  90         /*
  91          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
  92          * userspace. If it takes that long something really bad is going on and
  93          * we should simply try to bail out and fail as gracefully as possible.
  94          */
  95         ret = wait_event_interruptible_timeout(error->reset_queue,
  96                                                !i915_reset_in_progress(error),
  97                                                10*HZ);
  98         if (ret == 0) {
  99                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 100                 return -EIO;
 101         } else if (ret < 0) {
 102                 return ret;
 103         } else {
 104                 return 0;
 105         }
 106 }
 107
 108 int i915_mutex_lock_interruptible(struct drm_device *dev)
 109 {
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         int ret;
 112
 113         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 114         if (ret)
 115                 return ret;
 116
 117         ret = mutex_lock_interruptible(&dev->struct_mutex);
 118         if (ret)
 119                 return ret;
 120
 121         WARN_ON(i915_verify_lists(dev));
 122         return 0;
 123 }
 124
 125 int
 126 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 127                             struct drm_file *file)
 128 {
 129         struct drm_i915_private *dev_priv = to_i915(dev);
 130         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 131         struct drm_i915_gem_get_aperture *args = data;
 132         struct i915_vma *vma;
 133         size_t pinned;
 134
 135         pinned = 0;
 136         mutex_lock(&dev->struct_mutex);
 137         list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
 138                 if (vma->pin_count)
 139                         pinned += vma->node.size;
 140         list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
 141                 if (vma->pin_count)
 142                         pinned += vma->node.size;
 143         mutex_unlock(&dev->struct_mutex);
 144
 145         args->aper_size = ggtt->base.total;
 146         args->aper_available_size = args->aper_size - pinned;
 147
 148         return 0;
 149 }
 150
 151 static int
 152 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 153 {
 154         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 155         char *vaddr = obj->phys_handle->vaddr;
 156         struct sg_table *st;
 157         struct scatterlist *sg;
 158         int i;
 159
 160         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 161                 return -EINVAL;
 162
 163         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 164                 struct page *page;
 165                 char *src;
 166
 167                 page = shmem_read_mapping_page(mapping, i);
 168                 if (IS_ERR(page))
 169                         return PTR_ERR(page);
 170
 171                 src = kmap_atomic(page);
 172                 memcpy(vaddr, src, PAGE_SIZE);
 173                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 174                 kunmap_atomic(src);
 175
 176                 put_page(page);
 177                 vaddr += PAGE_SIZE;
 178         }
 179
 180         i915_gem_chipset_flush(obj->base.dev);
 181
 182         st = kmalloc(sizeof(*st), GFP_KERNEL);
 183         if (st == NULL)
 184                 return -ENOMEM;
 185
 186         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 187                 kfree(st);
 188                 return -ENOMEM;
 189         }
 190
 191         sg = st->sgl;
 192         sg->offset = 0;
 193         sg->length = obj->base.size;
 194
 195         sg_dma_address(sg) = obj->phys_handle->busaddr;
 196         sg_dma_len(sg) = obj->base.size;
 197
 198         obj->pages = st;
 199         return 0;
 200 }
 201
 202 static void
 203 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 204 {
 205         int ret;
 206
 207         BUG_ON(obj->madv == __I915_MADV_PURGED);
 208
 209         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 210         if (WARN_ON(ret)) {
 211                 /* In the event of a disaster, abandon all caches and
 212                  * hope for the best.
 213                  */
 214                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 215         }
 216
 217         if (obj->madv == I915_MADV_DONTNEED)
 218                 obj->dirty = 0;
 219
 220         if (obj->dirty) {
 221                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 222                 char *vaddr = obj->phys_handle->vaddr;
 223                 int i;
 224
 225                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 226                         struct page *page;
 227                         char *dst;
 228
 229                         page = shmem_read_mapping_page(mapping, i);
 230                         if (IS_ERR(page))
 231                                 continue;
 232
 233                         dst = kmap_atomic(page);
 234                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 235                         memcpy(dst, vaddr, PAGE_SIZE);
 236                         kunmap_atomic(dst);
 237
 238                         set_page_dirty(page);
 239                         if (obj->madv == I915_MADV_WILLNEED)
 240                                 mark_page_accessed(page);
 241                         put_page(page);
 242                         vaddr += PAGE_SIZE;
 243                 }
 244                 obj->dirty = 0;
 245         }
 246
 247         sg_free_table(obj->pages);
 248         kfree(obj->pages);
 249 }
 250
 251 static void
 252 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 253 {
 254         drm_pci_free(obj->base.dev, obj->phys_handle);
 255 }
 256
 257 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 258         .get_pages = i915_gem_object_get_pages_phys,
 259         .put_pages = i915_gem_object_put_pages_phys,
 260         .release = i915_gem_object_release_phys,
 261 };
 262
 263 static int
 264 drop_pages(struct drm_i915_gem_object *obj)
 265 {
 266         struct i915_vma *vma, *next;
 267         int ret;
 268
 269         drm_gem_object_reference(&obj->base);
 270         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
 271                 if (i915_vma_unbind(vma))
 272                         break;
 273
 274         ret = i915_gem_object_put_pages(obj);
 275         drm_gem_object_unreference(&obj->base);
 276
 277         return ret;
 278 }
 279
 280 int
 281 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 282                             int align)
 283 {
 284         drm_dma_handle_t *phys;
 285         int ret;
 286
 287         if (obj->phys_handle) {
 288                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 289                         return -EBUSY;
 290
 291                 return 0;
 292         }
 293
 294         if (obj->madv != I915_MADV_WILLNEED)
 295                 return -EFAULT;
 296
 297         if (obj->base.filp == NULL)
 298                 return -EINVAL;
 299
 300         ret = drop_pages(obj);
 301         if (ret)
 302                 return ret;
 303
 304         /* create a new object */
 305         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 306         if (!phys)
 307                 return -ENOMEM;
 308
 309         obj->phys_handle = phys;
 310         obj->ops = &i915_gem_phys_ops;
 311
 312         return i915_gem_object_get_pages(obj);
 313 }
 314
 315 static int
 316 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 317                      struct drm_i915_gem_pwrite *args,
 318                      struct drm_file *file_priv)
 319 {
 320         struct drm_device *dev = obj->base.dev;
 321         void *vaddr = obj->phys_handle->vaddr + args->offset;
 322         char __user *user_data = u64_to_user_ptr(args->data_ptr);
 323         int ret = 0;
 324
 325         /* We manually control the domain here and pretend that it
 326          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 327          */
 328         ret = i915_gem_object_wait_rendering(obj, false);
 329         if (ret)
 330                 return ret;
 331
 332         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
 333         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 334                 unsigned long unwritten;
 335
 336                 /* The physical object once assigned is fixed for the lifetime
 337                  * of the obj, so we can safely drop the lock and continue
 338                  * to access vaddr.
 339                  */
 340                 mutex_unlock(&dev->struct_mutex);
 341                 unwritten = copy_from_user(vaddr, user_data, args->size);
 342                 mutex_lock(&dev->struct_mutex);
 343                 if (unwritten) {
 344                         ret = -EFAULT;
 345                         goto out;
 346                 }
 347         }
 348
 349         drm_clflush_virt_range(vaddr, args->size);
 350         i915_gem_chipset_flush(dev);
 351
 352 out:
 353         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
 354         return ret;
 355 }
 356
 357 void *i915_gem_object_alloc(struct drm_device *dev)
 358 {
 359         struct drm_i915_private *dev_priv = dev->dev_private;
 360         return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
 361 }
 362
 363 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 364 {
 365         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 366         kmem_cache_free(dev_priv->objects, obj);
 367 }
 368
 369 static int
 370 i915_gem_create(struct drm_file *file,
 371                 struct drm_device *dev,
 372                 uint64_t size,
 373                 uint32_t *handle_p)
 374 {
 375         struct drm_i915_gem_object *obj;
 376         int ret;
 377         u32 handle;
 378
 379         size = roundup(size, PAGE_SIZE);
 380         if (size == 0)
 381                 return -EINVAL;
 382
 383         /* Allocate the new object */
 384         obj = i915_gem_alloc_object(dev, size);
 385         if (obj == NULL)
 386                 return -ENOMEM;
 387
 388         ret = drm_gem_handle_create(file, &obj->base, &handle);
 389         /* drop reference from allocate - handle holds it now */
 390         drm_gem_object_unreference_unlocked(&obj->base);
 391         if (ret)
 392                 return ret;
 393
 394         *handle_p = handle;
 395         return 0;
 396 }
 397
 398 int
 399 i915_gem_dumb_create(struct drm_file *file,
 400                      struct drm_device *dev,
 401                      struct drm_mode_create_dumb *args)
 402 {
 403         /* have to work out size/pitch and return them */
 404         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 405         args->size = args->pitch * args->height;
 406         return i915_gem_create(file, dev,
 407                                args->size, &args->handle);
 408 }
 409
 410 /**
 411  * Creates a new mm object and returns a handle to it.
 412  */
 413 int
 414 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 415                       struct drm_file *file)
 416 {
 417         struct drm_i915_gem_create *args = data;
 418
 419         return i915_gem_create(file, dev,
 420                                args->size, &args->handle);
 421 }
 422
 423 static inline int
 424 __copy_to_user_swizzled(char __user *cpu_vaddr,
 425                         const char *gpu_vaddr, int gpu_offset,
 426                         int length)
 427 {
 428         int ret, cpu_offset = 0;
 429
 430         while (length > 0) {
 431                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 432                 int this_length = min(cacheline_end - gpu_offset, length);
 433                 int swizzled_gpu_offset = gpu_offset ^ 64;
 434
 435                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 436                                      gpu_vaddr + swizzled_gpu_offset,
 437                                      this_length);
 438                 if (ret)
 439                         return ret + length;
 440
 441                 cpu_offset += this_length;
 442                 gpu_offset += this_length;
 443                 length -= this_length;
 444         }
 445
 446         return 0;
 447 }
 448
 449 static inline int
 450 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 451                           const char __user *cpu_vaddr,
 452                           int length)
 453 {
 454         int ret, cpu_offset = 0;
 455
 456         while (length > 0) {
 457                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 458                 int this_length = min(cacheline_end - gpu_offset, length);
 459                 int swizzled_gpu_offset = gpu_offset ^ 64;
 460
 461                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 462                                        cpu_vaddr + cpu_offset,
 463                                        this_length);
 464                 if (ret)
 465                         return ret + length;
 466
 467                 cpu_offset += this_length;
 468                 gpu_offset += this_length;
 469                 length -= this_length;
 470         }
 471
 472         return 0;
 473 }
 474
 475 /*
 476  * Pins the specified object's pages and synchronizes the object with
 477  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 478  * flush the object from the CPU cache.
 479  */
 480 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 481                                     int *needs_clflush)
 482 {
 483         int ret;
 484
 485         *needs_clflush = 0;
 486
 487         if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
 488                 return -EINVAL;
 489
 490         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 491                 /* If we're not in the cpu read domain, set ourself into the gtt
 492                  * read domain and manually flush cachelines (if required). This
 493                  * optimizes for the case when the gpu will dirty the data
 494                  * anyway again before the next pread happens. */
 495                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 496                                                         obj->cache_level);
 497                 ret = i915_gem_object_wait_rendering(obj, true);
 498                 if (ret)
 499                         return ret;
 500         }
 501
 502         ret = i915_gem_object_get_pages(obj);
 503         if (ret)
 504                 return ret;
 505
 506         i915_gem_object_pin_pages(obj);
 507
 508         return ret;
 509 }
 510
 511 /* Per-page copy function for the shmem pread fastpath.
 512  * Flushes invalid cachelines before reading the target if
 513  * needs_clflush is set. */
 514 static int
 515 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 516                  char __user *user_data,
 517                  bool page_do_bit17_swizzling, bool needs_clflush)
 518 {
 519         char *vaddr;
 520         int ret;
 521
 522         if (unlikely(page_do_bit17_swizzling))
 523                 return -EINVAL;
 524
 525         vaddr = kmap_atomic(page);
 526         if (needs_clflush)
 527                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 528                                        page_length);
 529         ret = __copy_to_user_inatomic(user_data,
 530                                       vaddr + shmem_page_offset,
 531                                       page_length);
 532         kunmap_atomic(vaddr);
 533
 534         return ret ? -EFAULT : 0;
 535 }
 536
 537 static void
 538 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 539                              bool swizzled)
 540 {
 541         if (unlikely(swizzled)) {
 542                 unsigned long start = (unsigned long) addr;
 543                 unsigned long end = (unsigned long) addr + length;
 544
 545                 /* For swizzling simply ensure that we always flush both
 546                  * channels. Lame, but simple and it works. Swizzled
 547                  * pwrite/pread is far from a hotpath - current userspace
 548                  * doesn't use it at all. */
 549                 start = round_down(start, 128);
 550                 end = round_up(end, 128);
 551
 552                 drm_clflush_virt_range((void *)start, end - start);
 553         } else {
 554                 drm_clflush_virt_range(addr, length);
 555         }
 556
 557 }
 558
 559 /* Only difference to the fast-path function is that this can handle bit17
 560  * and uses non-atomic copy and kmap functions. */
 561 static int
 562 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 563                  char __user *user_data,
 564                  bool page_do_bit17_swizzling, bool needs_clflush)
 565 {
 566         char *vaddr;
 567         int ret;
 568
 569         vaddr = kmap(page);
 570         if (needs_clflush)
 571                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 572                                              page_length,
 573                                              page_do_bit17_swizzling);
 574
 575         if (page_do_bit17_swizzling)
 576                 ret = __copy_to_user_swizzled(user_data,
 577                                               vaddr, shmem_page_offset,
 578                                               page_length);
 579         else
 580                 ret = __copy_to_user(user_data,
 581                                      vaddr + shmem_page_offset,
 582                                      page_length);
 583         kunmap(page);
 584
 585         return ret ? - EFAULT : 0;
 586 }
 587
 588 static int
 589 i915_gem_shmem_pread(struct drm_device *dev,
 590                      struct drm_i915_gem_object *obj,
 591                      struct drm_i915_gem_pread *args,
 592                      struct drm_file *file)
 593 {
 594         char __user *user_data;
 595         ssize_t remain;
 596         loff_t offset;
 597         int shmem_page_offset, page_length, ret = 0;
 598         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 599         int prefaulted = 0;
 600         int needs_clflush = 0;
 601         struct sg_page_iter sg_iter;
 602
 603         user_data = u64_to_user_ptr(args->data_ptr);
 604         remain = args->size;
 605
 606         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 607
 608         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 609         if (ret)
 610                 return ret;
 611
 612         offset = args->offset;
 613
 614         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 615                          offset >> PAGE_SHIFT) {
 616                 struct page *page = sg_page_iter_page(&sg_iter);
 617
 618                 if (remain <= 0)
 619                         break;
 620
 621                 /* Operation in this page
 622                  *
 623                  * shmem_page_offset = offset within page in shmem file
 624                  * page_length = bytes to copy for this page
 625                  */
 626                 shmem_page_offset = offset_in_page(offset);
 627                 page_length = remain;
 628                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 629                         page_length = PAGE_SIZE - shmem_page_offset;
 630
 631                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 632                         (page_to_phys(page) & (1 << 17)) != 0;
 633
 634                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 635                                        user_data, page_do_bit17_swizzling,
 636                                        needs_clflush);
 637                 if (ret == 0)
 638                         goto next_page;
 639
 640                 mutex_unlock(&dev->struct_mutex);
 641
 642                 if (likely(!i915.prefault_disable) && !prefaulted) {
 643                         ret = fault_in_multipages_writeable(user_data, remain);
 644                         /* Userspace is tricking us, but we've already clobbered
 645                          * its pages with the prefault and promised to write the
 646                          * data up to the first fault. Hence ignore any errors
 647                          * and just continue. */
 648                         (void)ret;
 649                         prefaulted = 1;
 650                 }
 651
 652                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 653                                        user_data, page_do_bit17_swizzling,
 654                                        needs_clflush);
 655
 656                 mutex_lock(&dev->struct_mutex);
 657
 658                 if (ret)
 659                         goto out;
 660
 661 next_page:
 662                 remain -= page_length;
 663                 user_data += page_length;
 664                 offset += page_length;
 665         }
 666
 667 out:
 668         i915_gem_object_unpin_pages(obj);
 669
 670         return ret;
 671 }
 672
 673 /**
 674  * Reads data from the object referenced by handle.
 675  *
 676  * On error, the contents of *data are undefined.
 677  */
 678 int
 679 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 680                      struct drm_file *file)
 681 {
 682         struct drm_i915_gem_pread *args = data;
 683         struct drm_i915_gem_object *obj;
 684         int ret = 0;
 685
 686         if (args->size == 0)
 687                 return 0;
 688
 689         if (!access_ok(VERIFY_WRITE,
 690                        u64_to_user_ptr(args->data_ptr),
 691                        args->size))
 692                 return -EFAULT;
 693
 694         ret = i915_mutex_lock_interruptible(dev);
 695         if (ret)
 696                 return ret;
 697
 698         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
 699         if (&obj->base == NULL) {
 700                 ret = -ENOENT;
 701                 goto unlock;
 702         }
 703
 704         /* Bounds check source.  */
 705         if (args->offset > obj->base.size ||
 706             args->size > obj->base.size - args->offset) {
 707                 ret = -EINVAL;
 708                 goto out;
 709         }
 710
 711         /* prime objects have no backing filp to GEM pread/pwrite
 712          * pages from.
 713          */
 714         if (!obj->base.filp) {
 715                 ret = -EINVAL;
 716                 goto out;
 717         }
 718
 719         trace_i915_gem_object_pread(obj, args->offset, args->size);
 720
 721         ret = i915_gem_shmem_pread(dev, obj, args, file);
 722
 723 out:
 724         drm_gem_object_unreference(&obj->base);
 725 unlock:
 726         mutex_unlock(&dev->struct_mutex);
 727         return ret;
 728 }
 729
 730 /* This is the fast write path which cannot handle
 731  * page faults in the source data
 732  */
 733
 734 static inline int
 735 fast_user_write(struct io_mapping *mapping,
 736                 loff_t page_base, int page_offset,
 737                 char __user *user_data,
 738                 int length)
 739 {
 740         void __iomem *vaddr_atomic;
 741         void *vaddr;
 742         unsigned long unwritten;
 743
 744         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 745         /* We can use the cpu mem copy function because this is X86. */
 746         vaddr = (void __force*)vaddr_atomic + page_offset;
 747         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 748                                                       user_data, length);
 749         io_mapping_unmap_atomic(vaddr_atomic);
 750         return unwritten;
 751 }
 752
 753 /**
 754  * This is the fast pwrite path, where we copy the data directly from the
 755  * user into the GTT, uncached.
 756  */
 757 static int
 758 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 759                          struct drm_i915_gem_object *obj,
 760                          struct drm_i915_gem_pwrite *args,
 761                          struct drm_file *file)
 762 {
 763         struct drm_i915_private *dev_priv = to_i915(dev);
 764         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 765         ssize_t remain;
 766         loff_t offset, page_base;
 767         char __user *user_data;
 768         int page_offset, page_length, ret;
 769
 770         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 771         if (ret)
 772                 goto out;
 773
 774         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 775         if (ret)
 776                 goto out_unpin;
 777
 778         ret = i915_gem_object_put_fence(obj);
 779         if (ret)
 780                 goto out_unpin;
 781
 782         user_data = u64_to_user_ptr(args->data_ptr);
 783         remain = args->size;
 784
 785         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 786
 787         intel_fb_obj_invalidate(obj, ORIGIN_GTT);
 788
 789         while (remain > 0) {
 790                 /* Operation in this page
 791                  *
 792                  * page_base = page offset within aperture
 793                  * page_offset = offset within page
 794                  * page_length = bytes to copy for this page
 795                  */
 796                 page_base = offset & PAGE_MASK;
 797                 page_offset = offset_in_page(offset);
 798                 page_length = remain;
 799                 if ((page_offset + remain) > PAGE_SIZE)
 800                         page_length = PAGE_SIZE - page_offset;
 801
 802                 /* If we get a fault while copying data, then (presumably) our
 803                  * source page isn't available.  Return the error and we'll
 804                  * retry in the slow path.
 805                  */
 806                 if (fast_user_write(ggtt->mappable, page_base,
 807                                     page_offset, user_data, page_length)) {
 808                         ret = -EFAULT;
 809                         goto out_flush;
 810                 }
 811
 812                 remain -= page_length;
 813                 user_data += page_length;
 814                 offset += page_length;
 815         }
 816
 817 out_flush:
 818         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
 819 out_unpin:
 820         i915_gem_object_ggtt_unpin(obj);
 821 out:
 822         return ret;
 823 }
 824
 825 /* Per-page copy function for the shmem pwrite fastpath.
 826  * Flushes invalid cachelines before writing to the target if
 827  * needs_clflush_before is set and flushes out any written cachelines after
 828  * writing if needs_clflush is set. */
 829 static int
 830 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 831                   char __user *user_data,
 832                   bool page_do_bit17_swizzling,
 833                   bool needs_clflush_before,
 834                   bool needs_clflush_after)
 835 {
 836         char *vaddr;
 837         int ret;
 838
 839         if (unlikely(page_do_bit17_swizzling))
 840                 return -EINVAL;
 841
 842         vaddr = kmap_atomic(page);
 843         if (needs_clflush_before)
 844                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 845                                        page_length);
 846         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 847                                         user_data, page_length);
 848         if (needs_clflush_after)
 849                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 850                                        page_length);
 851         kunmap_atomic(vaddr);
 852
 853         return ret ? -EFAULT : 0;
 854 }
 855
 856 /* Only difference to the fast-path function is that this can handle bit17
 857  * and uses non-atomic copy and kmap functions. */
 858 static int
 859 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 860                   char __user *user_data,
 861                   bool page_do_bit17_swizzling,
 862                   bool needs_clflush_before,
 863                   bool needs_clflush_after)
 864 {
 865         char *vaddr;
 866         int ret;
 867
 868         vaddr = kmap(page);
 869         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 870                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 871                                              page_length,
 872                                              page_do_bit17_swizzling);
 873         if (page_do_bit17_swizzling)
 874                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 875                                                 user_data,
 876                                                 page_length);
 877         else
 878                 ret = __copy_from_user(vaddr + shmem_page_offset,
 879                                        user_data,
 880                                        page_length);
 881         if (needs_clflush_after)
 882                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 883                                              page_length,
 884                                              page_do_bit17_swizzling);
 885         kunmap(page);
 886
 887         return ret ? -EFAULT : 0;
 888 }
 889
 890 static int
 891 i915_gem_shmem_pwrite(struct drm_device *dev,
 892                       struct drm_i915_gem_object *obj,
 893                       struct drm_i915_gem_pwrite *args,
 894                       struct drm_file *file)
 895 {
 896         ssize_t remain;
 897         loff_t offset;
 898         char __user *user_data;
 899         int shmem_page_offset, page_length, ret = 0;
 900         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 901         int hit_slowpath = 0;
 902         int needs_clflush_after = 0;
 903         int needs_clflush_before = 0;
 904         struct sg_page_iter sg_iter;
 905
 906         user_data = u64_to_user_ptr(args->data_ptr);
 907         remain = args->size;
 908
 909         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 910
 911         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 912                 /* If we're not in the cpu write domain, set ourself into the gtt
 913                  * write domain and manually flush cachelines (if required). This
 914                  * optimizes for the case when the gpu will use the data
 915                  * right away and we therefore have to clflush anyway. */
 916                 needs_clflush_after = cpu_write_needs_clflush(obj);
 917                 ret = i915_gem_object_wait_rendering(obj, false);
 918                 if (ret)
 919                         return ret;
 920         }
 921         /* Same trick applies to invalidate partially written cachelines read
 922          * before writing. */
 923         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 924                 needs_clflush_before =
 925                         !cpu_cache_is_coherent(dev, obj->cache_level);
 926
 927         ret = i915_gem_object_get_pages(obj);
 928         if (ret)
 929                 return ret;
 930
 931         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
 932
 933         i915_gem_object_pin_pages(obj);
 934
 935         offset = args->offset;
 936         obj->dirty = 1;
 937
 938         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 939                          offset >> PAGE_SHIFT) {
 940                 struct page *page = sg_page_iter_page(&sg_iter);
 941                 int partial_cacheline_write;
 942
 943                 if (remain <= 0)
 944                         break;
 945
 946                 /* Operation in this page
 947                  *
 948                  * shmem_page_offset = offset within page in shmem file
 949                  * page_length = bytes to copy for this page
 950                  */
 951                 shmem_page_offset = offset_in_page(offset);
 952
 953                 page_length = remain;
 954                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 955                         page_length = PAGE_SIZE - shmem_page_offset;
 956
 957                 /* If we don't overwrite a cacheline completely we need to be
 958                  * careful to have up-to-date data by first clflushing. Don't
 959                  * overcomplicate things and flush the entire patch. */
 960                 partial_cacheline_write = needs_clflush_before &&
 961                         ((shmem_page_offset | page_length)
 962                                 & (boot_cpu_data.x86_clflush_size - 1));
 963
 964                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 965                         (page_to_phys(page) & (1 << 17)) != 0;
 966
 967                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 968                                         user_data, page_do_bit17_swizzling,
 969                                         partial_cacheline_write,
 970                                         needs_clflush_after);
 971                 if (ret == 0)
 972                         goto next_page;
 973
 974                 hit_slowpath = 1;
 975                 mutex_unlock(&dev->struct_mutex);
 976                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 977                                         user_data, page_do_bit17_swizzling,
 978                                         partial_cacheline_write,
 979                                         needs_clflush_after);
 980
 981                 mutex_lock(&dev->struct_mutex);
 982
 983                 if (ret)
 984                         goto out;
 985
 986 next_page:
 987                 remain -= page_length;
 988                 user_data += page_length;
 989                 offset += page_length;
 990         }
 991
 992 out:
 993         i915_gem_object_unpin_pages(obj);
 994
 995         if (hit_slowpath) {
 996                 /*
 997                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 998                  * cachelines in-line while writing and the object moved
 999                  * out of the cpu write domain while we've dropped the lock.
1000                  */
1001                 if (!needs_clflush_after &&
1002                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1003                         if (i915_gem_clflush_object(obj, obj->pin_display))
1004                                 needs_clflush_after = true;
1005                 }
1006         }
1007
1008         if (needs_clflush_after)
1009                 i915_gem_chipset_flush(dev);
1010         else
1011                 obj->cache_dirty = true;
1012
1013         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1014         return ret;
1015 }
1016
1017 /**
1018  * Writes data to the object referenced by handle.
1019  *
1020  * On error, the contents of the buffer that were to be modified are undefined.
1021  */
1022 int
1023 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1024                       struct drm_file *file)
1025 {
1026         struct drm_i915_private *dev_priv = dev->dev_private;
1027         struct drm_i915_gem_pwrite *args = data;
1028         struct drm_i915_gem_object *obj;
1029         int ret;
1030
1031         if (args->size == 0)
1032                 return 0;
1033
1034         if (!access_ok(VERIFY_READ,
1035                        u64_to_user_ptr(args->data_ptr),
1036                        args->size))
1037                 return -EFAULT;
1038
1039         if (likely(!i915.prefault_disable)) {
1040                 ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr),
1041                                                    args->size);
1042                 if (ret)
1043                         return -EFAULT;
1044         }
1045
1046         intel_runtime_pm_get(dev_priv);
1047
1048         ret = i915_mutex_lock_interruptible(dev);
1049         if (ret)
1050                 goto put_rpm;
1051
1052         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1053         if (&obj->base == NULL) {
1054                 ret = -ENOENT;
1055                 goto unlock;
1056         }
1057
1058         /* Bounds check destination. */
1059         if (args->offset > obj->base.size ||
1060             args->size > obj->base.size - args->offset) {
1061                 ret = -EINVAL;
1062                 goto out;
1063         }
1064
1065         /* prime objects have no backing filp to GEM pread/pwrite
1066          * pages from.
1067          */
1068         if (!obj->base.filp) {
1069                 ret = -EINVAL;
1070                 goto out;
1071         }
1072
1073         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1074
1075         ret = -EFAULT;
1076         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1077          * it would end up going through the fenced access, and we'll get
1078          * different detiling behavior between reading and writing.
1079          * pread/pwrite currently are reading and writing from the CPU
1080          * perspective, requiring manual detiling by the client.
1081          */
1082         if (obj->tiling_mode == I915_TILING_NONE &&
1083             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1084             cpu_write_needs_clflush(obj)) {
1085                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1086                 /* Note that the gtt paths might fail with non-page-backed user
1087                  * pointers (e.g. gtt mappings when moving data between
1088                  * textures). Fallback to the shmem path in that case. */
1089         }
1090
1091         if (ret == -EFAULT || ret == -ENOSPC) {
1092                 if (obj->phys_handle)
1093                         ret = i915_gem_phys_pwrite(obj, args, file);
1094                 else
1095                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1096         }
1097
1098 out:
1099         drm_gem_object_unreference(&obj->base);
1100 unlock:
1101         mutex_unlock(&dev->struct_mutex);
1102 put_rpm:
1103         intel_runtime_pm_put(dev_priv);
1104
1105         return ret;
1106 }
1107
1108 static int
1109 i915_gem_check_wedge(unsigned reset_counter, bool interruptible)
1110 {
1111         if (__i915_terminally_wedged(reset_counter))
1112                 return -EIO;
1113
1114         if (__i915_reset_in_progress(reset_counter)) {
1115                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1116                  * -EIO unconditionally for these. */
1117                 if (!interruptible)
1118                         return -EIO;
1119
1120                 return -EAGAIN;
1121         }
1122
1123         return 0;
1124 }
1125
1126 static void fake_irq(unsigned long data)
1127 {
1128         wake_up_process((struct task_struct *)data);
1129 }
1130
1131 static bool missed_irq(struct drm_i915_private *dev_priv,
1132                        struct intel_engine_cs *engine)
1133 {
1134         return test_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings);
1135 }
1136
1137 static unsigned long local_clock_us(unsigned *cpu)
1138 {
1139         unsigned long t;
1140
1141         /* Cheaply and approximately convert from nanoseconds to microseconds.
1142          * The result and subsequent calculations are also defined in the same
1143          * approximate microseconds units. The principal source of timing
1144          * error here is from the simple truncation.
1145          *
1146          * Note that local_clock() is only defined wrt to the current CPU;
1147          * the comparisons are no longer valid if we switch CPUs. Instead of
1148          * blocking preemption for the entire busywait, we can detect the CPU
1149          * switch and use that as indicator of system load and a reason to
1150          * stop busywaiting, see busywait_stop().
1151          */
1152         *cpu = get_cpu();
1153         t = local_clock() >> 10;
1154         put_cpu();
1155
1156         return t;
1157 }
1158
1159 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1160 {
1161         unsigned this_cpu;
1162
1163         if (time_after(local_clock_us(&this_cpu), timeout))
1164                 return true;
1165
1166         return this_cpu != cpu;
1167 }
1168
1169 static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
1170 {
1171         unsigned long timeout;
1172         unsigned cpu;
1173
1174         /* When waiting for high frequency requests, e.g. during synchronous
1175          * rendering split between the CPU and GPU, the finite amount of time
1176          * required to set up the irq and wait upon it limits the response
1177          * rate. By busywaiting on the request completion for a short while we
1178          * can service the high frequency waits as quick as possible. However,
1179          * if it is a slow request, we want to sleep as quickly as possible.
1180          * The tradeoff between waiting and sleeping is roughly the time it
1181          * takes to sleep on a request, on the order of a microsecond.
1182          */
1183
1184         if (req->engine->irq_refcount)
1185                 return -EBUSY;
1186
1187         /* Only spin if we know the GPU is processing this request */
1188         if (!i915_gem_request_started(req, true))
1189                 return -EAGAIN;
1190
1191         timeout = local_clock_us(&cpu) + 5;
1192         while (!need_resched()) {
1193                 if (i915_gem_request_completed(req, true))
1194                         return 0;
1195
1196                 if (signal_pending_state(state, current))
1197                         break;
1198
1199                 if (busywait_stop(timeout, cpu))
1200                         break;
1201
1202                 cpu_relax_lowlatency();
1203         }
1204
1205         if (i915_gem_request_completed(req, false))
1206                 return 0;
1207
1208         return -EAGAIN;
1209 }
1210
1211 /**
1212  * __i915_wait_request - wait until execution of request has finished
1213  * @req: duh!
1214  * @interruptible: do an interruptible wait (normally yes)
1215  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1216  *
1217  * Note: It is of utmost importance that the passed in seqno and reset_counter
1218  * values have been read by the caller in an smp safe manner. Where read-side
1219  * locks are involved, it is sufficient to read the reset_counter before
1220  * unlocking the lock that protects the seqno. For lockless tricks, the
1221  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1222  * inserted.
1223  *
1224  * Returns 0 if the request was found within the alloted time. Else returns the
1225  * errno with remaining time filled in timeout argument.
1226  */
1227 int __i915_wait_request(struct drm_i915_gem_request *req,
1228                         bool interruptible,
1229                         s64 *timeout,
1230                         struct intel_rps_client *rps)
1231 {
1232         struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1233         struct drm_device *dev = engine->dev;
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         const bool irq_test_in_progress =
1236                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
1237         int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1238         DEFINE_WAIT(wait);
1239         unsigned long timeout_expire;
1240         s64 before = 0; /* Only to silence a compiler warning. */
1241         int ret;
1242
1243         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1244
1245         if (list_empty(&req->list))
1246                 return 0;
1247
1248         if (i915_gem_request_completed(req, true))
1249                 return 0;
1250
1251         timeout_expire = 0;
1252         if (timeout) {
1253                 if (WARN_ON(*timeout < 0))
1254                         return -EINVAL;
1255
1256                 if (*timeout == 0)
1257                         return -ETIME;
1258
1259                 timeout_expire = jiffies + nsecs_to_jiffies_timeout(*timeout);
1260
1261                 /*
1262                  * Record current time in case interrupted by signal, or wedged.
1263                  */
1264                 before = ktime_get_raw_ns();
1265         }
1266
1267         if (INTEL_INFO(dev_priv)->gen >= 6)
1268                 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies);
1269
1270         trace_i915_gem_request_wait_begin(req);
1271
1272         /* Optimistic spin for the next jiffie before touching IRQs */
1273         ret = __i915_spin_request(req, state);
1274         if (ret == 0)
1275                 goto out;
1276
1277         if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
1278                 ret = -ENODEV;
1279                 goto out;
1280         }
1281
1282         for (;;) {
1283                 struct timer_list timer;
1284
1285                 prepare_to_wait(&engine->irq_queue, &wait, state);
1286
1287                 /* We need to check whether any gpu reset happened in between
1288                  * the request being submitted and now. If a reset has occurred,
1289                  * the request is effectively complete (we either are in the
1290                  * process of or have discarded the rendering and completely
1291                  * reset the GPU. The results of the request are lost and we
1292                  * are free to continue on with the original operation.
1293                  */
1294                 if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
1295                         ret = 0;
1296                         break;
1297                 }
1298
1299                 if (i915_gem_request_completed(req, false)) {
1300                         ret = 0;
1301                         break;
1302                 }
1303
1304                 if (signal_pending_state(state, current)) {
1305                         ret = -ERESTARTSYS;
1306                         break;
1307                 }
1308
1309                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1310                         ret = -ETIME;
1311                         break;
1312                 }
1313
1314                 timer.function = NULL;
1315                 if (timeout || missed_irq(dev_priv, engine)) {
1316                         unsigned long expire;
1317
1318                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1319                         expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
1320                         mod_timer(&timer, expire);
1321                 }
1322
1323                 io_schedule();
1324
1325                 if (timer.function) {
1326                         del_singleshot_timer_sync(&timer);
1327                         destroy_timer_on_stack(&timer);
1328                 }
1329         }
1330         if (!irq_test_in_progress)
1331                 engine->irq_put(engine);
1332
1333         finish_wait(&engine->irq_queue, &wait);
1334
1335 out:
1336         trace_i915_gem_request_wait_end(req);
1337
1338         if (timeout) {
1339                 s64 tres = *timeout - (ktime_get_raw_ns() - before);
1340
1341                 *timeout = tres < 0 ? 0 : tres;
1342
1343                 /*
1344                  * Apparently ktime isn't accurate enough and occasionally has a
1345                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1346                  * things up to make the test happy. We allow up to 1 jiffy.
1347                  *
1348                  * This is a regrssion from the timespec->ktime conversion.
1349                  */
1350                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1351                         *timeout = 0;
1352         }
1353
1354         return ret;
1355 }
1356
1357 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1358                                    struct drm_file *file)
1359 {
1360         struct drm_i915_file_private *file_priv;
1361
1362         WARN_ON(!req || !file || req->file_priv);
1363
1364         if (!req || !file)
1365                 return -EINVAL;
1366
1367         if (req->file_priv)
1368                 return -EINVAL;
1369
1370         file_priv = file->driver_priv;
1371
1372         spin_lock(&file_priv->mm.lock);
1373         req->file_priv = file_priv;
1374         list_add_tail(&req->client_list, &file_priv->mm.request_list);
1375         spin_unlock(&file_priv->mm.lock);
1376
1377         req->pid = get_pid(task_pid(current));
1378
1379         return 0;
1380 }
1381
1382 static inline void
1383 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1384 {
1385         struct drm_i915_file_private *file_priv = request->file_priv;
1386
1387         if (!file_priv)
1388                 return;
1389
1390         spin_lock(&file_priv->mm.lock);
1391         list_del(&request->client_list);
1392         request->file_priv = NULL;
1393         spin_unlock(&file_priv->mm.lock);
1394
1395         put_pid(request->pid);
1396         request->pid = NULL;
1397 }
1398
1399 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1400 {
1401         trace_i915_gem_request_retire(request);
1402
1403         /* We know the GPU must have read the request to have
1404          * sent us the seqno + interrupt, so use the position
1405          * of tail of the request to update the last known position
1406          * of the GPU head.
1407          *
1408          * Note this requires that we are always called in request
1409          * completion order.
1410          */
1411         request->ringbuf->last_retired_head = request->postfix;
1412
1413         list_del_init(&request->list);
1414         i915_gem_request_remove_from_client(request);
1415
1416         i915_gem_request_unreference(request);
1417 }
1418
1419 static void
1420 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1421 {
1422         struct intel_engine_cs *engine = req->engine;
1423         struct drm_i915_gem_request *tmp;
1424
1425         lockdep_assert_held(&engine->dev->struct_mutex);
1426
1427         if (list_empty(&req->list))
1428                 return;
1429
1430         do {
1431                 tmp = list_first_entry(&engine->request_list,
1432                                        typeof(*tmp), list);
1433
1434                 i915_gem_request_retire(tmp);
1435         } while (tmp != req);
1436
1437         WARN_ON(i915_verify_lists(engine->dev));
1438 }
1439
1440 /**
1441  * Waits for a request to be signaled, and cleans up the
1442  * request and object lists appropriately for that event.
1443  */
1444 int
1445 i915_wait_request(struct drm_i915_gem_request *req)
1446 {
1447         struct drm_i915_private *dev_priv = req->i915;
1448         bool interruptible;
1449         int ret;
1450
1451         interruptible = dev_priv->mm.interruptible;
1452
1453         BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1454
1455         ret = __i915_wait_request(req, interruptible, NULL, NULL);
1456         if (ret)
1457                 return ret;
1458
1459         __i915_gem_request_retire__upto(req);
1460         return 0;
1461 }
1462
1463 /**
1464  * Ensures that all rendering to the object has completed and the object is
1465  * safe to unbind from the GTT or access from the CPU.
1466  */
1467 int
1468 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1469                                bool readonly)
1470 {
1471         int ret, i;
1472
1473         if (!obj->active)
1474                 return 0;
1475
1476         if (readonly) {
1477                 if (obj->last_write_req != NULL) {
1478                         ret = i915_wait_request(obj->last_write_req);
1479                         if (ret)
1480                                 return ret;
1481
1482                         i = obj->last_write_req->engine->id;
1483                         if (obj->last_read_req[i] == obj->last_write_req)
1484                                 i915_gem_object_retire__read(obj, i);
1485                         else
1486                                 i915_gem_object_retire__write(obj);
1487                 }
1488         } else {
1489                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1490                         if (obj->last_read_req[i] == NULL)
1491                                 continue;
1492
1493                         ret = i915_wait_request(obj->last_read_req[i]);
1494                         if (ret)
1495                                 return ret;
1496
1497                         i915_gem_object_retire__read(obj, i);
1498                 }
1499                 GEM_BUG_ON(obj->active);
1500         }
1501
1502         return 0;
1503 }
1504
1505 static void
1506 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1507                                struct drm_i915_gem_request *req)
1508 {
1509         int ring = req->engine->id;
1510
1511         if (obj->last_read_req[ring] == req)
1512                 i915_gem_object_retire__read(obj, ring);
1513         else if (obj->last_write_req == req)
1514                 i915_gem_object_retire__write(obj);
1515
1516         __i915_gem_request_retire__upto(req);
1517 }
1518
1519 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1520  * as the object state may change during this call.
1521  */
1522 static __must_check int
1523 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1524                                             struct intel_rps_client *rps,
1525                                             bool readonly)
1526 {
1527         struct drm_device *dev = obj->base.dev;
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529         struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
1530         int ret, i, n = 0;
1531
1532         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1533         BUG_ON(!dev_priv->mm.interruptible);
1534
1535         if (!obj->active)
1536                 return 0;
1537
1538         if (readonly) {
1539                 struct drm_i915_gem_request *req;
1540
1541                 req = obj->last_write_req;
1542                 if (req == NULL)
1543                         return 0;
1544
1545                 requests[n++] = i915_gem_request_reference(req);
1546         } else {
1547                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1548                         struct drm_i915_gem_request *req;
1549
1550                         req = obj->last_read_req[i];
1551                         if (req == NULL)
1552                                 continue;
1553
1554                         requests[n++] = i915_gem_request_reference(req);
1555                 }
1556         }
1557
1558         mutex_unlock(&dev->struct_mutex);
1559         ret = 0;
1560         for (i = 0; ret == 0 && i < n; i++)
1561                 ret = __i915_wait_request(requests[i], true, NULL, rps);
1562         mutex_lock(&dev->struct_mutex);
1563
1564         for (i = 0; i < n; i++) {
1565                 if (ret == 0)
1566                         i915_gem_object_retire_request(obj, requests[i]);
1567                 i915_gem_request_unreference(requests[i]);
1568         }
1569
1570         return ret;
1571 }
1572
1573 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1574 {
1575         struct drm_i915_file_private *fpriv = file->driver_priv;
1576         return &fpriv->rps;
1577 }
1578
1579 /**
1580  * Called when user space prepares to use an object with the CPU, either
1581  * through the mmap ioctl's mapping or a GTT mapping.
1582  */
1583 int
1584 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1585                           struct drm_file *file)
1586 {
1587         struct drm_i915_gem_set_domain *args = data;
1588         struct drm_i915_gem_object *obj;
1589         uint32_t read_domains = args->read_domains;
1590         uint32_t write_domain = args->write_domain;
1591         int ret;
1592
1593         /* Only handle setting domains to types used by the CPU. */
1594         if (write_domain & I915_GEM_GPU_DOMAINS)
1595                 return -EINVAL;
1596
1597         if (read_domains & I915_GEM_GPU_DOMAINS)
1598                 return -EINVAL;
1599
1600         /* Having something in the write domain implies it's in the read
1601          * domain, and only that read domain.  Enforce that in the request.
1602          */
1603         if (write_domain != 0 && read_domains != write_domain)
1604                 return -EINVAL;
1605
1606         ret = i915_mutex_lock_interruptible(dev);
1607         if (ret)
1608                 return ret;
1609
1610         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1611         if (&obj->base == NULL) {
1612                 ret = -ENOENT;
1613                 goto unlock;
1614         }
1615
1616         /* Try to flush the object off the GPU without holding the lock.
1617          * We will repeat the flush holding the lock in the normal manner
1618          * to catch cases where we are gazumped.
1619          */
1620         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1621                                                           to_rps_client(file),
1622                                                           !write_domain);
1623         if (ret)
1624                 goto unref;
1625
1626         if (read_domains & I915_GEM_DOMAIN_GTT)
1627                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1628         else
1629                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1630
1631         if (write_domain != 0)
1632                 intel_fb_obj_invalidate(obj,
1633                                         write_domain == I915_GEM_DOMAIN_GTT ?
1634                                         ORIGIN_GTT : ORIGIN_CPU);
1635
1636 unref:
1637         drm_gem_object_unreference(&obj->base);
1638 unlock:
1639         mutex_unlock(&dev->struct_mutex);
1640         return ret;
1641 }
1642
1643 /**
1644  * Called when user space has done writes to this buffer
1645  */
1646 int
1647 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1648                          struct drm_file *file)
1649 {
1650         struct drm_i915_gem_sw_finish *args = data;
1651         struct drm_i915_gem_object *obj;
1652         int ret = 0;
1653
1654         ret = i915_mutex_lock_interruptible(dev);
1655         if (ret)
1656                 return ret;
1657
1658         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1659         if (&obj->base == NULL) {
1660                 ret = -ENOENT;
1661                 goto unlock;
1662         }
1663
1664         /* Pinned buffers may be scanout, so flush the cache */
1665         if (obj->pin_display)
1666                 i915_gem_object_flush_cpu_write_domain(obj);
1667
1668         drm_gem_object_unreference(&obj->base);
1669 unlock:
1670         mutex_unlock(&dev->struct_mutex);
1671         return ret;
1672 }
1673
1674 /**
1675  * Maps the contents of an object, returning the address it is mapped
1676  * into.
1677  *
1678  * While the mapping holds a reference on the contents of the object, it doesn't
1679  * imply a ref on the object itself.
1680  *
1681  * IMPORTANT:
1682  *
1683  * DRM driver writers who look a this function as an example for how to do GEM
1684  * mmap support, please don't implement mmap support like here. The modern way
1685  * to implement DRM mmap support is with an mmap offset ioctl (like
1686  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1687  * That way debug tooling like valgrind will understand what's going on, hiding
1688  * the mmap call in a driver private ioctl will break that. The i915 driver only
1689  * does cpu mmaps this way because we didn't know better.
1690  */
1691 int
1692 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1693                     struct drm_file *file)
1694 {
1695         struct drm_i915_gem_mmap *args = data;
1696         struct drm_gem_object *obj;
1697         unsigned long addr;
1698
1699         if (args->flags & ~(I915_MMAP_WC))
1700                 return -EINVAL;
1701
1702         if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1703                 return -ENODEV;
1704
1705         obj = drm_gem_object_lookup(file, args->handle);
1706         if (obj == NULL)
1707                 return -ENOENT;
1708
1709         /* prime objects have no backing filp to GEM mmap
1710          * pages from.
1711          */
1712         if (!obj->filp) {
1713                 drm_gem_object_unreference_unlocked(obj);
1714                 return -EINVAL;
1715         }
1716
1717         addr = vm_mmap(obj->filp, 0, args->size,
1718                        PROT_READ | PROT_WRITE, MAP_SHARED,
1719                        args->offset);
1720         if (args->flags & I915_MMAP_WC) {
1721                 struct mm_struct *mm = current->mm;
1722                 struct vm_area_struct *vma;
1723
1724                 down_write(&mm->mmap_sem);
1725                 vma = find_vma(mm, addr);
1726                 if (vma)
1727                         vma->vm_page_prot =
1728                                 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1729                 else
1730                         addr = -ENOMEM;
1731                 up_write(&mm->mmap_sem);
1732         }
1733         drm_gem_object_unreference_unlocked(obj);
1734         if (IS_ERR((void *)addr))
1735                 return addr;
1736
1737         args->addr_ptr = (uint64_t) addr;
1738
1739         return 0;
1740 }
1741
1742 /**
1743  * i915_gem_fault - fault a page into the GTT
1744  * @vma: VMA in question
1745  * @vmf: fault info
1746  *
1747  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1748  * from userspace.  The fault handler takes care of binding the object to
1749  * the GTT (if needed), allocating and programming a fence register (again,
1750  * only if needed based on whether the old reg is still valid or the object
1751  * is tiled) and inserting a new PTE into the faulting process.
1752  *
1753  * Note that the faulting process may involve evicting existing objects
1754  * from the GTT and/or fence registers to make room.  So performance may
1755  * suffer if the GTT working set is large or there are few fence registers
1756  * left.
1757  */
1758 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1759 {
1760         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1761         struct drm_device *dev = obj->base.dev;
1762         struct drm_i915_private *dev_priv = to_i915(dev);
1763         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1764         struct i915_ggtt_view view = i915_ggtt_view_normal;
1765         pgoff_t page_offset;
1766         unsigned long pfn;
1767         int ret = 0;
1768         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1769
1770         intel_runtime_pm_get(dev_priv);
1771
1772         /* We don't use vmf->pgoff since that has the fake offset */
1773         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1774                 PAGE_SHIFT;
1775
1776         ret = i915_mutex_lock_interruptible(dev);
1777         if (ret)
1778                 goto out;
1779
1780         trace_i915_gem_object_fault(obj, page_offset, true, write);
1781
1782         /* Try to flush the object off the GPU first without holding the lock.
1783          * Upon reacquiring the lock, we will perform our sanity checks and then
1784          * repeat the flush holding the lock in the normal manner to catch cases
1785          * where we are gazumped.
1786          */
1787         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1788         if (ret)
1789                 goto unlock;
1790
1791         /* Access to snoopable pages through the GTT is incoherent. */
1792         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1793                 ret = -EFAULT;
1794                 goto unlock;
1795         }
1796
1797         /* Use a partial view if the object is bigger than the aperture. */
1798         if (obj->base.size >= ggtt->mappable_end &&
1799             obj->tiling_mode == I915_TILING_NONE) {
1800                 static const unsigned int chunk_size = 256; // 1 MiB
1801
1802                 memset(&view, 0, sizeof(view));
1803                 view.type = I915_GGTT_VIEW_PARTIAL;
1804                 view.params.partial.offset = rounddown(page_offset, chunk_size);
1805                 view.params.partial.size =
1806                         min_t(unsigned int,
1807                               chunk_size,
1808                               (vma->vm_end - vma->vm_start)/PAGE_SIZE -
1809                               view.params.partial.offset);
1810         }
1811
1812         /* Now pin it into the GTT if needed */
1813         ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
1814         if (ret)
1815                 goto unlock;
1816
1817         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1818         if (ret)
1819                 goto unpin;
1820
1821         ret = i915_gem_object_get_fence(obj);
1822         if (ret)
1823                 goto unpin;
1824
1825         /* Finally, remap it using the new GTT offset */
1826         pfn = ggtt->mappable_base +
1827                 i915_gem_obj_ggtt_offset_view(obj, &view);
1828         pfn >>= PAGE_SHIFT;
1829
1830         if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
1831                 /* Overriding existing pages in partial view does not cause
1832                  * us any trouble as TLBs are still valid because the fault
1833                  * is due to userspace losing part of the mapping or never
1834                  * having accessed it before (at this partials' range).
1835                  */
1836                 unsigned long base = vma->vm_start +
1837                                      (view.params.partial.offset << PAGE_SHIFT);
1838                 unsigned int i;
1839
1840                 for (i = 0; i < view.params.partial.size; i++) {
1841                         ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
1842                         if (ret)
1843                                 break;
1844                 }
1845
1846                 obj->fault_mappable = true;
1847         } else {
1848                 if (!obj->fault_mappable) {
1849                         unsigned long size = min_t(unsigned long,
1850                                                    vma->vm_end - vma->vm_start,
1851                                                    obj->base.size);
1852                         int i;
1853
1854                         for (i = 0; i < size >> PAGE_SHIFT; i++) {
1855                                 ret = vm_insert_pfn(vma,
1856                                                     (unsigned long)vma->vm_start + i * PAGE_SIZE,
1857                                                     pfn + i);
1858                                 if (ret)
1859                                         break;
1860                         }
1861
1862                         obj->fault_mappable = true;
1863                 } else
1864                         ret = vm_insert_pfn(vma,
1865                                             (unsigned long)vmf->virtual_address,
1866                                             pfn + page_offset);
1867         }
1868 unpin:
1869         i915_gem_object_ggtt_unpin_view(obj, &view);
1870 unlock:
1871         mutex_unlock(&dev->struct_mutex);
1872 out:
1873         switch (ret) {
1874         case -EIO:
1875                 /*
1876                  * We eat errors when the gpu is terminally wedged to avoid
1877                  * userspace unduly crashing (gl has no provisions for mmaps to
1878                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
1879                  * and so needs to be reported.
1880                  */
1881                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
1882                         ret = VM_FAULT_SIGBUS;
1883                         break;
1884                 }
1885         case -EAGAIN:
1886                 /*
1887                  * EAGAIN means the gpu is hung and we'll wait for the error
1888                  * handler to reset everything when re-faulting in
1889                  * i915_mutex_lock_interruptible.
1890                  */
1891         case 0:
1892         case -ERESTARTSYS:
1893         case -EINTR:
1894         case -EBUSY:
1895                 /*
1896                  * EBUSY is ok: this just means that another thread
1897                  * already did the job.
1898                  */
1899                 ret = VM_FAULT_NOPAGE;
1900                 break;
1901         case -ENOMEM:
1902                 ret = VM_FAULT_OOM;
1903                 break;
1904         case -ENOSPC:
1905         case -EFAULT:
1906                 ret = VM_FAULT_SIGBUS;
1907                 break;
1908         default:
1909                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1910                 ret = VM_FAULT_SIGBUS;
1911                 break;
1912         }
1913
1914         intel_runtime_pm_put(dev_priv);
1915         return ret;
1916 }
1917
1918 /**
1919  * i915_gem_release_mmap - remove physical page mappings
1920  * @obj: obj in question
1921  *
1922  * Preserve the reservation of the mmapping with the DRM core code, but
1923  * relinquish ownership of the pages back to the system.
1924  *
1925  * It is vital that we remove the page mapping if we have mapped a tiled
1926  * object through the GTT and then lose the fence register due to
1927  * resource pressure. Similarly if the object has been moved out of the
1928  * aperture, than pages mapped into userspace must be revoked. Removing the
1929  * mapping will then trigger a page fault on the next user access, allowing
1930  * fixup by i915_gem_fault().
1931  */
1932 void
1933 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1934 {
1935         /* Serialisation between user GTT access and our code depends upon
1936          * revoking the CPU's PTE whilst the mutex is held. The next user
1937          * pagefault then has to wait until we release the mutex.
1938          */
1939         lockdep_assert_held(&obj->base.dev->struct_mutex);
1940
1941         if (!obj->fault_mappable)
1942                 return;
1943
1944         drm_vma_node_unmap(&obj->base.vma_node,
1945                            obj->base.dev->anon_inode->i_mapping);
1946
1947         /* Ensure that the CPU's PTE are revoked and there are not outstanding
1948          * memory transactions from userspace before we return. The TLB
1949          * flushing implied above by changing the PTE above *should* be
1950          * sufficient, an extra barrier here just provides us with a bit
1951          * of paranoid documentation about our requirement to serialise
1952          * memory writes before touching registers / GSM.
1953          */
1954         wmb();
1955
1956         obj->fault_mappable = false;
1957 }
1958
1959 void
1960 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1961 {
1962         struct drm_i915_gem_object *obj;
1963
1964         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1965                 i915_gem_release_mmap(obj);
1966 }
1967
1968 uint32_t
1969 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1970 {
1971         uint32_t gtt_size;
1972
1973         if (INTEL_INFO(dev)->gen >= 4 ||
1974             tiling_mode == I915_TILING_NONE)
1975                 return size;
1976
1977         /* Previous chips need a power-of-two fence region when tiling */
1978         if (INTEL_INFO(dev)->gen == 3)
1979                 gtt_size = 1024*1024;
1980         else
1981                 gtt_size = 512*1024;
1982
1983         while (gtt_size < size)
1984                 gtt_size <<= 1;
1985
1986         return gtt_size;
1987 }
1988
1989 /**
1990  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1991  * @obj: object to check
1992  *
1993  * Return the required GTT alignment for an object, taking into account
1994  * potential fence register mapping.
1995  */
1996 uint32_t
1997 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1998                            int tiling_mode, bool fenced)
1999 {
2000         /*
2001          * Minimum alignment is 4k (GTT page size), but might be greater
2002          * if a fence register is needed for the object.
2003          */
2004         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2005             tiling_mode == I915_TILING_NONE)
2006                 return 4096;
2007
2008         /*
2009          * Previous chips need to be aligned to the size of the smallest
2010          * fence register that can contain the object.
2011          */
2012         return i915_gem_get_gtt_size(dev, size, tiling_mode);
2013 }
2014
2015 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2016 {
2017         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2018         int ret;
2019
2020         dev_priv->mm.shrinker_no_lock_stealing = true;
2021
2022         ret = drm_gem_create_mmap_offset(&obj->base);
2023         if (ret != -ENOSPC)
2024                 goto out;
2025
2026         /* Badly fragmented mmap space? The only way we can recover
2027          * space is by destroying unwanted objects. We can't randomly release
2028          * mmap_offsets as userspace expects them to be persistent for the
2029          * lifetime of the objects. The closest we can is to release the
2030          * offsets on purgeable objects by truncating it and marking it purged,
2031          * which prevents userspace from ever using that object again.
2032          */
2033         i915_gem_shrink(dev_priv,
2034                         obj->base.size >> PAGE_SHIFT,
2035                         I915_SHRINK_BOUND |
2036                         I915_SHRINK_UNBOUND |
2037                         I915_SHRINK_PURGEABLE);
2038         ret = drm_gem_create_mmap_offset(&obj->base);
2039         if (ret != -ENOSPC)
2040                 goto out;
2041
2042         i915_gem_shrink_all(dev_priv);
2043         ret = drm_gem_create_mmap_offset(&obj->base);
2044 out:
2045         dev_priv->mm.shrinker_no_lock_stealing = false;
2046
2047         return ret;
2048 }
2049
2050 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2051 {
2052         drm_gem_free_mmap_offset(&obj->base);
2053 }
2054
2055 int
2056 i915_gem_mmap_gtt(struct drm_file *file,
2057                   struct drm_device *dev,
2058                   uint32_t handle,
2059                   uint64_t *offset)
2060 {
2061         struct drm_i915_gem_object *obj;
2062         int ret;
2063
2064         ret = i915_mutex_lock_interruptible(dev);
2065         if (ret)
2066                 return ret;
2067
2068         obj = to_intel_bo(drm_gem_object_lookup(file, handle));
2069         if (&obj->base == NULL) {
2070                 ret = -ENOENT;
2071                 goto unlock;
2072         }
2073
2074         if (obj->madv != I915_MADV_WILLNEED) {
2075                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2076                 ret = -EFAULT;
2077                 goto out;
2078         }
2079
2080         ret = i915_gem_object_create_mmap_offset(obj);
2081         if (ret)
2082                 goto out;
2083
2084         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2085
2086 out:
2087         drm_gem_object_unreference(&obj->base);
2088 unlock:
2089         mutex_unlock(&dev->struct_mutex);
2090         return ret;
2091 }
2092
2093 /**
2094  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2095  * @dev: DRM device
2096  * @data: GTT mapping ioctl data
2097  * @file: GEM object info
2098  *
2099  * Simply returns the fake offset to userspace so it can mmap it.
2100  * The mmap call will end up in drm_gem_mmap(), which will set things
2101  * up so we can get faults in the handler above.
2102  *
2103  * The fault handler will take care of binding the object into the GTT
2104  * (since it may have been evicted to make room for something), allocating
2105  * a fence register, and mapping the appropriate aperture address into
2106  * userspace.
2107  */
2108 int
2109 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2110                         struct drm_file *file)
2111 {
2112         struct drm_i915_gem_mmap_gtt *args = data;
2113
2114         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2115 }
2116
2117 /* Immediately discard the backing storage */
2118 static void
2119 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2120 {
2121         i915_gem_object_free_mmap_offset(obj);
2122
2123         if (obj->base.filp == NULL)
2124                 return;
2125
2126         /* Our goal here is to return as much of the memory as
2127          * is possible back to the system as we are called from OOM.
2128          * To do this we must instruct the shmfs to drop all of its
2129          * backing pages, *now*.
2130          */
2131         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2132         obj->madv = __I915_MADV_PURGED;
2133 }
2134
2135 /* Try to discard unwanted pages */
2136 static void
2137 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2138 {
2139         struct address_space *mapping;
2140
2141         switch (obj->madv) {
2142         case I915_MADV_DONTNEED:
2143                 i915_gem_object_truncate(obj);
2144         case __I915_MADV_PURGED:
2145                 return;
2146         }
2147
2148         if (obj->base.filp == NULL)
2149                 return;
2150
2151         mapping = file_inode(obj->base.filp)->i_mapping,
2152         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2153 }
2154
2155 static void
2156 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2157 {
2158         struct sg_page_iter sg_iter;
2159         int ret;
2160
2161         BUG_ON(obj->madv == __I915_MADV_PURGED);
2162
2163         ret = i915_gem_object_set_to_cpu_domain(obj, true);
2164         if (WARN_ON(ret)) {
2165                 /* In the event of a disaster, abandon all caches and
2166                  * hope for the best.
2167                  */
2168                 i915_gem_clflush_object(obj, true);
2169                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2170         }
2171
2172         i915_gem_gtt_finish_object(obj);
2173
2174         if (i915_gem_object_needs_bit17_swizzle(obj))
2175                 i915_gem_object_save_bit_17_swizzle(obj);
2176
2177         if (obj->madv == I915_MADV_DONTNEED)
2178                 obj->dirty = 0;
2179
2180         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2181                 struct page *page = sg_page_iter_page(&sg_iter);
2182
2183                 if (obj->dirty)
2184                         set_page_dirty(page);
2185
2186                 if (obj->madv == I915_MADV_WILLNEED)
2187                         mark_page_accessed(page);
2188
2189                 put_page(page);
2190         }
2191         obj->dirty = 0;
2192
2193         sg_free_table(obj->pages);
2194         kfree(obj->pages);
2195 }
2196
2197 int
2198 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2199 {
2200         const struct drm_i915_gem_object_ops *ops = obj->ops;
2201
2202         if (obj->pages == NULL)
2203                 return 0;
2204
2205         if (obj->pages_pin_count)
2206                 return -EBUSY;
2207
2208         BUG_ON(i915_gem_obj_bound_any(obj));
2209
2210         /* ->put_pages might need to allocate memory for the bit17 swizzle
2211          * array, hence protect them from being reaped by removing them from gtt
2212          * lists early. */
2213         list_del(&obj->global_list);
2214
2215         if (obj->mapping) {
2216                 if (is_vmalloc_addr(obj->mapping))
2217                         vunmap(obj->mapping);
2218                 else
2219                         kunmap(kmap_to_page(obj->mapping));
2220                 obj->mapping = NULL;
2221         }
2222
2223         ops->put_pages(obj);
2224         obj->pages = NULL;
2225
2226         i915_gem_object_invalidate(obj);
2227
2228         return 0;
2229 }
2230
2231 static int
2232 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2233 {
2234         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2235         int page_count, i;
2236         struct address_space *mapping;
2237         struct sg_table *st;
2238         struct scatterlist *sg;
2239         struct sg_page_iter sg_iter;
2240         struct page *page;
2241         unsigned long last_pfn = 0;     /* suppress gcc warning */
2242         int ret;
2243         gfp_t gfp;
2244
2245         /* Assert that the object is not currently in any GPU domain. As it
2246          * wasn't in the GTT, there shouldn't be any way it could have been in
2247          * a GPU cache
2248          */
2249         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2250         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2251
2252         st = kmalloc(sizeof(*st), GFP_KERNEL);
2253         if (st == NULL)
2254                 return -ENOMEM;
2255
2256         page_count = obj->base.size / PAGE_SIZE;
2257         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2258                 kfree(st);
2259                 return -ENOMEM;
2260         }
2261
2262         /* Get the list of pages out of our struct file.  They'll be pinned
2263          * at this point until we release them.
2264          *
2265          * Fail silently without starting the shrinker
2266          */
2267         mapping = file_inode(obj->base.filp)->i_mapping;
2268         gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2269         gfp |= __GFP_NORETRY | __GFP_NOWARN;
2270         sg = st->sgl;
2271         st->nents = 0;
2272         for (i = 0; i < page_count; i++) {
2273                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2274                 if (IS_ERR(page)) {
2275                         i915_gem_shrink(dev_priv,
2276                                         page_count,
2277                                         I915_SHRINK_BOUND |
2278                                         I915_SHRINK_UNBOUND |
2279                                         I915_SHRINK_PURGEABLE);
2280                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2281                 }
2282                 if (IS_ERR(page)) {
2283                         /* We've tried hard to allocate the memory by reaping
2284                          * our own buffer, now let the real VM do its job and
2285                          * go down in flames if truly OOM.
2286                          */
2287                         i915_gem_shrink_all(dev_priv);
2288                         page = shmem_read_mapping_page(mapping, i);
2289                         if (IS_ERR(page)) {
2290                                 ret = PTR_ERR(page);
2291                                 goto err_pages;
2292                         }
2293                 }
2294 #ifdef CONFIG_SWIOTLB
2295                 if (swiotlb_nr_tbl()) {
2296                         st->nents++;
2297                         sg_set_page(sg, page, PAGE_SIZE, 0);
2298                         sg = sg_next(sg);
2299                         continue;
2300                 }
2301 #endif
2302                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2303                         if (i)
2304                                 sg = sg_next(sg);
2305                         st->nents++;
2306                         sg_set_page(sg, page, PAGE_SIZE, 0);
2307                 } else {
2308                         sg->length += PAGE_SIZE;
2309                 }
2310                 last_pfn = page_to_pfn(page);
2311
2312                 /* Check that the i965g/gm workaround works. */
2313                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2314         }
2315 #ifdef CONFIG_SWIOTLB
2316         if (!swiotlb_nr_tbl())
2317 #endif
2318                 sg_mark_end(sg);
2319         obj->pages = st;
2320
2321         ret = i915_gem_gtt_prepare_object(obj);
2322         if (ret)
2323                 goto err_pages;
2324
2325         if (i915_gem_object_needs_bit17_swizzle(obj))
2326                 i915_gem_object_do_bit_17_swizzle(obj);
2327
2328         if (obj->tiling_mode != I915_TILING_NONE &&
2329             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2330                 i915_gem_object_pin_pages(obj);
2331
2332         return 0;
2333
2334 err_pages:
2335         sg_mark_end(sg);
2336         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2337                 put_page(sg_page_iter_page(&sg_iter));
2338         sg_free_table(st);
2339         kfree(st);
2340
2341         /* shmemfs first checks if there is enough memory to allocate the page
2342          * and reports ENOSPC should there be insufficient, along with the usual
2343          * ENOMEM for a genuine allocation failure.
2344          *
2345          * We use ENOSPC in our driver to mean that we have run out of aperture
2346          * space and so want to translate the error from shmemfs back to our
2347          * usual understanding of ENOMEM.
2348          */
2349         if (ret == -ENOSPC)
2350                 ret = -ENOMEM;
2351
2352         return ret;
2353 }
2354
2355 /* Ensure that the associated pages are gathered from the backing storage
2356  * and pinned into our object. i915_gem_object_get_pages() may be called
2357  * multiple times before they are released by a single call to
2358  * i915_gem_object_put_pages() - once the pages are no longer referenced
2359  * either as a result of memory pressure (reaping pages under the shrinker)
2360  * or as the object is itself released.
2361  */
2362 int
2363 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2364 {
2365         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2366         const struct drm_i915_gem_object_ops *ops = obj->ops;
2367         int ret;
2368
2369         if (obj->pages)
2370                 return 0;
2371
2372         if (obj->madv != I915_MADV_WILLNEED) {
2373                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2374                 return -EFAULT;
2375         }
2376
2377         BUG_ON(obj->pages_pin_count);
2378
2379         ret = ops->get_pages(obj);
2380         if (ret)
2381                 return ret;
2382
2383         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2384
2385         obj->get_page.sg = obj->pages->sgl;
2386         obj->get_page.last = 0;
2387
2388         return 0;
2389 }
2390
2391 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
2392 {
2393         int ret;
2394
2395         lockdep_assert_held(&obj->base.dev->struct_mutex);
2396
2397         ret = i915_gem_object_get_pages(obj);
2398         if (ret)
2399                 return ERR_PTR(ret);
2400
2401         i915_gem_object_pin_pages(obj);
2402
2403         if (obj->mapping == NULL) {
2404                 struct page **pages;
2405
2406                 pages = NULL;
2407                 if (obj->base.size == PAGE_SIZE)
2408                         obj->mapping = kmap(sg_page(obj->pages->sgl));
2409                 else
2410                         pages = drm_malloc_gfp(obj->base.size >> PAGE_SHIFT,
2411                                                sizeof(*pages),
2412                                                GFP_TEMPORARY);
2413                 if (pages != NULL) {
2414                         struct sg_page_iter sg_iter;
2415                         int n;
2416
2417                         n = 0;
2418                         for_each_sg_page(obj->pages->sgl, &sg_iter,
2419                                          obj->pages->nents, 0)
2420                                 pages[n++] = sg_page_iter_page(&sg_iter);
2421
2422                         obj->mapping = vmap(pages, n, 0, PAGE_KERNEL);
2423                         drm_free_large(pages);
2424                 }
2425                 if (obj->mapping == NULL) {
2426                         i915_gem_object_unpin_pages(obj);
2427                         return ERR_PTR(-ENOMEM);
2428                 }
2429         }
2430
2431         return obj->mapping;
2432 }
2433
2434 void i915_vma_move_to_active(struct i915_vma *vma,
2435                              struct drm_i915_gem_request *req)
2436 {
2437         struct drm_i915_gem_object *obj = vma->obj;
2438         struct intel_engine_cs *engine;
2439
2440         engine = i915_gem_request_get_engine(req);
2441
2442         /* Add a reference if we're newly entering the active list. */
2443         if (obj->active == 0)
2444                 drm_gem_object_reference(&obj->base);
2445         obj->active |= intel_engine_flag(engine);
2446
2447         list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
2448         i915_gem_request_assign(&obj->last_read_req[engine->id], req);
2449
2450         list_move_tail(&vma->vm_link, &vma->vm->active_list);
2451 }
2452
2453 static void
2454 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2455 {
2456         GEM_BUG_ON(obj->last_write_req == NULL);
2457         GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
2458
2459         i915_gem_request_assign(&obj->last_write_req, NULL);
2460         intel_fb_obj_flush(obj, true, ORIGIN_CS);
2461 }
2462
2463 static void
2464 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2465 {
2466         struct i915_vma *vma;
2467
2468         GEM_BUG_ON(obj->last_read_req[ring] == NULL);
2469         GEM_BUG_ON(!(obj->active & (1 << ring)));
2470
2471         list_del_init(&obj->engine_list[ring]);
2472         i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2473
2474         if (obj->last_write_req && obj->last_write_req->engine->id == ring)
2475                 i915_gem_object_retire__write(obj);
2476
2477         obj->active &= ~(1 << ring);
2478         if (obj->active)
2479                 return;
2480
2481         /* Bump our place on the bound list to keep it roughly in LRU order
2482          * so that we don't steal from recently used but inactive objects
2483          * (unless we are forced to ofc!)
2484          */
2485         list_move_tail(&obj->global_list,
2486                        &to_i915(obj->base.dev)->mm.bound_list);
2487
2488         list_for_each_entry(vma, &obj->vma_list, obj_link) {
2489                 if (!list_empty(&vma->vm_link))
2490                         list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
2491         }
2492
2493         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2494         drm_gem_object_unreference(&obj->base);
2495 }
2496
2497 static int
2498 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2499 {
2500         struct drm_i915_private *dev_priv = dev->dev_private;
2501         struct intel_engine_cs *engine;
2502         int ret;
2503
2504         /* Carefully retire all requests without writing to the rings */
2505         for_each_engine(engine, dev_priv) {
2506                 ret = intel_engine_idle(engine);
2507                 if (ret)
2508                         return ret;
2509         }
2510         i915_gem_retire_requests(dev);
2511
2512         /* Finally reset hw state */
2513         for_each_engine(engine, dev_priv)
2514                 intel_ring_init_seqno(engine, seqno);
2515
2516         return 0;
2517 }
2518
2519 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2520 {
2521         struct drm_i915_private *dev_priv = dev->dev_private;
2522         int ret;
2523
2524         if (seqno == 0)
2525                 return -EINVAL;
2526
2527         /* HWS page needs to be set less than what we
2528          * will inject to ring
2529          */
2530         ret = i915_gem_init_seqno(dev, seqno - 1);
2531         if (ret)
2532                 return ret;
2533
2534         /* Carefully set the last_seqno value so that wrap
2535          * detection still works
2536          */
2537         dev_priv->next_seqno = seqno;
2538         dev_priv->last_seqno = seqno - 1;
2539         if (dev_priv->last_seqno == 0)
2540                 dev_priv->last_seqno--;
2541
2542         return 0;
2543 }
2544
2545 int
2546 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2547 {
2548         struct drm_i915_private *dev_priv = dev->dev_private;
2549
2550         /* reserve 0 for non-seqno */
2551         if (dev_priv->next_seqno == 0) {
2552                 int ret = i915_gem_init_seqno(dev, 0);
2553                 if (ret)
2554                         return ret;
2555
2556                 dev_priv->next_seqno = 1;
2557         }
2558
2559         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2560         return 0;
2561 }
2562
2563 /*
2564  * NB: This function is not allowed to fail. Doing so would mean the the
2565  * request is not being tracked for completion but the work itself is
2566  * going to happen on the hardware. This would be a Bad Thing(tm).
2567  */
2568 void __i915_add_request(struct drm_i915_gem_request *request,
2569                         struct drm_i915_gem_object *obj,
2570                         bool flush_caches)
2571 {
2572         struct intel_engine_cs *engine;
2573         struct drm_i915_private *dev_priv;
2574         struct intel_ringbuffer *ringbuf;
2575         u32 request_start;
2576         int ret;
2577
2578         if (WARN_ON(request == NULL))
2579                 return;
2580
2581         engine = request->engine;
2582         dev_priv = request->i915;
2583         ringbuf = request->ringbuf;
2584
2585         /*
2586          * To ensure that this call will not fail, space for its emissions
2587          * should already have been reserved in the ring buffer. Let the ring
2588          * know that it is time to use that space up.
2589          */
2590         intel_ring_reserved_space_use(ringbuf);
2591
2592         request_start = intel_ring_get_tail(ringbuf);
2593         /*
2594          * Emit any outstanding flushes - execbuf can fail to emit the flush
2595          * after having emitted the batchbuffer command. Hence we need to fix
2596          * things up similar to emitting the lazy request. The difference here
2597          * is that the flush _must_ happen before the next request, no matter
2598          * what.
2599          */
2600         if (flush_caches) {
2601                 if (i915.enable_execlists)
2602                         ret = logical_ring_flush_all_caches(request);
2603                 else
2604                         ret = intel_ring_flush_all_caches(request);
2605                 /* Not allowed to fail! */
2606                 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2607         }
2608
2609         trace_i915_gem_request_add(request);
2610
2611         request->head = request_start;
2612
2613         /* Whilst this request exists, batch_obj will be on the
2614          * active_list, and so will hold the active reference. Only when this
2615          * request is retired will the the batch_obj be moved onto the
2616          * inactive_list and lose its active reference. Hence we do not need
2617          * to explicitly hold another reference here.
2618          */
2619         request->batch_obj = obj;
2620
2621         /* Seal the request and mark it as pending execution. Note that
2622          * we may inspect this state, without holding any locks, during
2623          * hangcheck. Hence we apply the barrier to ensure that we do not
2624          * see a more recent value in the hws than we are tracking.
2625          */
2626         request->emitted_jiffies = jiffies;
2627         request->previous_seqno = engine->last_submitted_seqno;
2628         smp_store_mb(engine->last_submitted_seqno, request->seqno);
2629         list_add_tail(&request->list, &engine->request_list);
2630
2631         /* Record the position of the start of the request so that
2632          * should we detect the updated seqno part-way through the
2633          * GPU processing the request, we never over-estimate the
2634          * position of the head.
2635          */
2636         request->postfix = intel_ring_get_tail(ringbuf);
2637
2638         if (i915.enable_execlists)
2639                 ret = engine->emit_request(request);
2640         else {
2641                 ret = engine->add_request(request);
2642
2643                 request->tail = intel_ring_get_tail(ringbuf);
2644         }
2645         /* Not allowed to fail! */
2646         WARN(ret, "emit|add_request failed: %d!\n", ret);
2647
2648         i915_queue_hangcheck(engine->dev);
2649
2650         queue_delayed_work(dev_priv->wq,
2651                            &dev_priv->mm.retire_work,
2652                            round_jiffies_up_relative(HZ));
2653         intel_mark_busy(dev_priv->dev);
2654
2655         /* Sanity check that the reserved size was large enough. */
2656         intel_ring_reserved_space_end(ringbuf);
2657 }
2658
2659 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2660                                    const struct intel_context *ctx)
2661 {
2662         unsigned long elapsed;
2663
2664         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2665
2666         if (ctx->hang_stats.banned)
2667                 return true;
2668
2669         if (ctx->hang_stats.ban_period_seconds &&
2670             elapsed <= ctx->hang_stats.ban_period_seconds) {
2671                 if (!i915_gem_context_is_default(ctx)) {
2672                         DRM_DEBUG("context hanging too fast, banning!\n");
2673                         return true;
2674                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2675                         if (i915_stop_ring_allow_warn(dev_priv))
2676                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2677                         return true;
2678                 }
2679         }
2680
2681         return false;
2682 }
2683
2684 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2685                                   struct intel_context *ctx,
2686                                   const bool guilty)
2687 {
2688         struct i915_ctx_hang_stats *hs;
2689
2690         if (WARN_ON(!ctx))
2691                 return;
2692
2693         hs = &ctx->hang_stats;
2694
2695         if (guilty) {
2696                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2697                 hs->batch_active++;
2698                 hs->guilty_ts = get_seconds();
2699         } else {
2700                 hs->batch_pending++;
2701         }
2702 }
2703
2704 void i915_gem_request_free(struct kref *req_ref)
2705 {
2706         struct drm_i915_gem_request *req = container_of(req_ref,
2707                                                  typeof(*req), ref);
2708         struct intel_context *ctx = req->ctx;
2709
2710         if (req->file_priv)
2711                 i915_gem_request_remove_from_client(req);
2712
2713         if (ctx) {
2714                 if (i915.enable_execlists && ctx != req->i915->kernel_context)
2715                         intel_lr_context_unpin(ctx, req->engine);
2716
2717                 i915_gem_context_unreference(ctx);
2718         }
2719
2720         kmem_cache_free(req->i915->requests, req);
2721 }
2722
2723 static inline int
2724 __i915_gem_request_alloc(struct intel_engine_cs *engine,
2725                          struct intel_context *ctx,
2726                          struct drm_i915_gem_request **req_out)
2727 {
2728         struct drm_i915_private *dev_priv = to_i915(engine->dev);
2729         unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
2730         struct drm_i915_gem_request *req;
2731         int ret;
2732
2733         if (!req_out)
2734                 return -EINVAL;
2735
2736         *req_out = NULL;
2737
2738         /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2739          * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2740          * and restart.
2741          */
2742         ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
2743         if (ret)
2744                 return ret;
2745
2746         req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2747         if (req == NULL)
2748                 return -ENOMEM;
2749
2750         ret = i915_gem_get_seqno(engine->dev, &req->seqno);
2751         if (ret)
2752                 goto err;
2753
2754         kref_init(&req->ref);
2755         req->i915 = dev_priv;
2756         req->engine = engine;
2757         req->reset_counter = reset_counter;
2758         req->ctx  = ctx;
2759         i915_gem_context_reference(req->ctx);
2760
2761         if (i915.enable_execlists)
2762                 ret = intel_logical_ring_alloc_request_extras(req);
2763         else
2764                 ret = intel_ring_alloc_request_extras(req);
2765         if (ret) {
2766                 i915_gem_context_unreference(req->ctx);
2767                 goto err;
2768         }
2769
2770         /*
2771          * Reserve space in the ring buffer for all the commands required to
2772          * eventually emit this request. This is to guarantee that the
2773          * i915_add_request() call can't fail. Note that the reserve may need
2774          * to be redone if the request is not actually submitted straight
2775          * away, e.g. because a GPU scheduler has deferred it.
2776          */
2777         if (i915.enable_execlists)
2778                 ret = intel_logical_ring_reserve_space(req);
2779         else
2780                 ret = intel_ring_reserve_space(req);
2781         if (ret) {
2782                 /*
2783                  * At this point, the request is fully allocated even if not
2784                  * fully prepared. Thus it can be cleaned up using the proper
2785                  * free code.
2786                  */
2787                 intel_ring_reserved_space_cancel(req->ringbuf);
2788                 i915_gem_request_unreference(req);
2789                 return ret;
2790         }
2791
2792         *req_out = req;
2793         return 0;
2794
2795 err:
2796         kmem_cache_free(dev_priv->requests, req);
2797         return ret;
2798 }
2799
2800 /**
2801  * i915_gem_request_alloc - allocate a request structure
2802  *
2803  * @engine: engine that we wish to issue the request on.
2804  * @ctx: context that the request will be associated with.
2805  *       This can be NULL if the request is not directly related to
2806  *       any specific user context, in which case this function will
2807  *       choose an appropriate context to use.
2808  *
2809  * Returns a pointer to the allocated request if successful,
2810  * or an error code if not.
2811  */
2812 struct drm_i915_gem_request *
2813 i915_gem_request_alloc(struct intel_engine_cs *engine,
2814                        struct intel_context *ctx)
2815 {
2816         struct drm_i915_gem_request *req;
2817         int err;
2818
2819         if (ctx == NULL)
2820                 ctx = to_i915(engine->dev)->kernel_context;
2821         err = __i915_gem_request_alloc(engine, ctx, &req);
2822         return err ? ERR_PTR(err) : req;
2823 }
2824
2825 struct drm_i915_gem_request *
2826 i915_gem_find_active_request(struct intel_engine_cs *engine)
2827 {
2828         struct drm_i915_gem_request *request;
2829
2830         list_for_each_entry(request, &engine->request_list, list) {
2831                 if (i915_gem_request_completed(request, false))
2832                         continue;
2833
2834                 return request;
2835         }
2836
2837         return NULL;
2838 }
2839
2840 static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv,
2841                                        struct intel_engine_cs *engine)
2842 {
2843         struct drm_i915_gem_request *request;
2844         bool ring_hung;
2845
2846         request = i915_gem_find_active_request(engine);
2847
2848         if (request == NULL)
2849                 return;
2850
2851         ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2852
2853         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2854
2855         list_for_each_entry_continue(request, &engine->request_list, list)
2856                 i915_set_reset_status(dev_priv, request->ctx, false);
2857 }
2858
2859 static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv,
2860                                         struct intel_engine_cs *engine)
2861 {
2862         struct intel_ringbuffer *buffer;
2863
2864         while (!list_empty(&engine->active_list)) {
2865                 struct drm_i915_gem_object *obj;
2866
2867                 obj = list_first_entry(&engine->active_list,
2868                                        struct drm_i915_gem_object,
2869                                        engine_list[engine->id]);
2870
2871                 i915_gem_object_retire__read(obj, engine->id);
2872         }
2873
2874         /*
2875          * Clear the execlists queue up before freeing the requests, as those
2876          * are the ones that keep the context and ringbuffer backing objects
2877          * pinned in place.
2878          */
2879
2880         if (i915.enable_execlists) {
2881                 /* Ensure irq handler finishes or is cancelled. */
2882                 tasklet_kill(&engine->irq_tasklet);
2883
2884                 spin_lock_bh(&engine->execlist_lock);
2885                 /* list_splice_tail_init checks for empty lists */
2886                 list_splice_tail_init(&engine->execlist_queue,
2887                                       &engine->execlist_retired_req_list);
2888                 spin_unlock_bh(&engine->execlist_lock);
2889
2890                 intel_execlists_retire_requests(engine);
2891         }
2892
2893         /*
2894          * We must free the requests after all the corresponding objects have
2895          * been moved off active lists. Which is the same order as the normal
2896          * retire_requests function does. This is important if object hold
2897          * implicit references on things like e.g. ppgtt address spaces through
2898          * the request.
2899          */
2900         while (!list_empty(&engine->request_list)) {
2901                 struct drm_i915_gem_request *request;
2902
2903                 request = list_first_entry(&engine->request_list,
2904                                            struct drm_i915_gem_request,
2905                                            list);
2906
2907                 i915_gem_request_retire(request);
2908         }
2909
2910         /* Having flushed all requests from all queues, we know that all
2911          * ringbuffers must now be empty. However, since we do not reclaim
2912          * all space when retiring the request (to prevent HEADs colliding
2913          * with rapid ringbuffer wraparound) the amount of available space
2914          * upon reset is less than when we start. Do one more pass over
2915          * all the ringbuffers to reset last_retired_head.
2916          */
2917         list_for_each_entry(buffer, &engine->buffers, link) {
2918                 buffer->last_retired_head = buffer->tail;
2919                 intel_ring_update_space(buffer);
2920         }
2921
2922         intel_ring_init_seqno(engine, engine->last_submitted_seqno);
2923 }
2924
2925 void i915_gem_reset(struct drm_device *dev)
2926 {
2927         struct drm_i915_private *dev_priv = dev->dev_private;
2928         struct intel_engine_cs *engine;
2929
2930         /*
2931          * Before we free the objects from the requests, we need to inspect
2932          * them for finding the guilty party. As the requests only borrow
2933          * their reference to the objects, the inspection must be done first.
2934          */
2935         for_each_engine(engine, dev_priv)
2936                 i915_gem_reset_engine_status(dev_priv, engine);
2937
2938         for_each_engine(engine, dev_priv)
2939                 i915_gem_reset_engine_cleanup(dev_priv, engine);
2940
2941         i915_gem_context_reset(dev);
2942
2943         i915_gem_restore_fences(dev);
2944
2945         WARN_ON(i915_verify_lists(dev));
2946 }
2947
2948 /**
2949  * This function clears the request list as sequence numbers are passed.
2950  */
2951 void
2952 i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
2953 {
2954         WARN_ON(i915_verify_lists(engine->dev));
2955
2956         /* Retire requests first as we use it above for the early return.
2957          * If we retire requests last, we may use a later seqno and so clear
2958          * the requests lists without clearing the active list, leading to
2959          * confusion.
2960          */
2961         while (!list_empty(&engine->request_list)) {
2962                 struct drm_i915_gem_request *request;
2963
2964                 request = list_first_entry(&engine->request_list,
2965                                            struct drm_i915_gem_request,
2966                                            list);
2967
2968                 if (!i915_gem_request_completed(request, true))
2969                         break;
2970
2971                 i915_gem_request_retire(request);
2972         }
2973
2974         /* Move any buffers on the active list that are no longer referenced
2975          * by the ringbuffer to the flushing/inactive lists as appropriate,
2976          * before we free the context associated with the requests.
2977          */
2978         while (!list_empty(&engine->active_list)) {
2979                 struct drm_i915_gem_object *obj;
2980
2981                 obj = list_first_entry(&engine->active_list,
2982                                        struct drm_i915_gem_object,
2983                                        engine_list[engine->id]);
2984
2985                 if (!list_empty(&obj->last_read_req[engine->id]->list))
2986                         break;
2987
2988                 i915_gem_object_retire__read(obj, engine->id);
2989         }
2990
2991         if (unlikely(engine->trace_irq_req &&
2992                      i915_gem_request_completed(engine->trace_irq_req, true))) {
2993                 engine->irq_put(engine);
2994                 i915_gem_request_assign(&engine->trace_irq_req, NULL);
2995         }
2996
2997         WARN_ON(i915_verify_lists(engine->dev));
2998 }
2999
3000 bool
3001 i915_gem_retire_requests(struct drm_device *dev)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         struct intel_engine_cs *engine;
3005         bool idle = true;
3006
3007         for_each_engine(engine, dev_priv) {
3008                 i915_gem_retire_requests_ring(engine);
3009                 idle &= list_empty(&engine->request_list);
3010                 if (i915.enable_execlists) {
3011                         spin_lock_bh(&engine->execlist_lock);
3012                         idle &= list_empty(&engine->execlist_queue);
3013                         spin_unlock_bh(&engine->execlist_lock);
3014
3015                         intel_execlists_retire_requests(engine);
3016                 }
3017         }
3018
3019         if (idle)
3020                 mod_delayed_work(dev_priv->wq,
3021                                    &dev_priv->mm.idle_work,
3022                                    msecs_to_jiffies(100));
3023
3024         return idle;
3025 }
3026
3027 static void
3028 i915_gem_retire_work_handler(struct work_struct *work)
3029 {
3030         struct drm_i915_private *dev_priv =
3031                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
3032         struct drm_device *dev = dev_priv->dev;
3033         bool idle;
3034
3035         /* Come back later if the device is busy... */
3036         idle = false;
3037         if (mutex_trylock(&dev->struct_mutex)) {
3038                 idle = i915_gem_retire_requests(dev);
3039                 mutex_unlock(&dev->struct_mutex);
3040         }
3041         if (!idle)
3042                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3043                                    round_jiffies_up_relative(HZ));
3044 }
3045
3046 static void
3047 i915_gem_idle_work_handler(struct work_struct *work)
3048 {
3049         struct drm_i915_private *dev_priv =
3050                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3051         struct drm_device *dev = dev_priv->dev;
3052         struct intel_engine_cs *engine;
3053
3054         for_each_engine(engine, dev_priv)
3055                 if (!list_empty(&engine->request_list))
3056                         return;
3057
3058         /* we probably should sync with hangcheck here, using cancel_work_sync.
3059          * Also locking seems to be fubar here, engine->request_list is protected
3060          * by dev->struct_mutex. */
3061
3062         intel_mark_idle(dev);
3063
3064         if (mutex_trylock(&dev->struct_mutex)) {
3065                 for_each_engine(engine, dev_priv)
3066                         i915_gem_batch_pool_fini(&engine->batch_pool);
3067
3068                 mutex_unlock(&dev->struct_mutex);
3069         }
3070 }
3071
3072 /**
3073  * Ensures that an object will eventually get non-busy by flushing any required
3074  * write domains, emitting any outstanding lazy request and retiring and
3075  * completed requests.
3076  */
3077 static int
3078 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3079 {
3080         int i;
3081
3082         if (!obj->active)
3083                 return 0;
3084
3085         for (i = 0; i < I915_NUM_ENGINES; i++) {
3086                 struct drm_i915_gem_request *req;
3087
3088                 req = obj->last_read_req[i];
3089                 if (req == NULL)
3090                         continue;
3091
3092                 if (list_empty(&req->list))
3093                         goto retire;
3094
3095                 if (i915_gem_request_completed(req, true)) {
3096                         __i915_gem_request_retire__upto(req);
3097 retire:
3098                         i915_gem_object_retire__read(obj, i);
3099                 }
3100         }
3101
3102         return 0;
3103 }
3104
3105 /**
3106  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3107  * @DRM_IOCTL_ARGS: standard ioctl arguments
3108  *
3109  * Returns 0 if successful, else an error is returned with the remaining time in
3110  * the timeout parameter.
3111  *  -ETIME: object is still busy after timeout
3112  *  -ERESTARTSYS: signal interrupted the wait
3113  *  -ENONENT: object doesn't exist
3114  * Also possible, but rare:
3115  *  -EAGAIN: GPU wedged
3116  *  -ENOMEM: damn
3117  *  -ENODEV: Internal IRQ fail
3118  *  -E?: The add request failed
3119  *
3120  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3121  * non-zero timeout parameter the wait ioctl will wait for the given number of
3122  * nanoseconds on an object becoming unbusy. Since the wait itself does so
3123  * without holding struct_mutex the object may become re-busied before this
3124  * function completes. A similar but shorter * race condition exists in the busy
3125  * ioctl
3126  */
3127 int
3128 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3129 {
3130         struct drm_i915_gem_wait *args = data;
3131         struct drm_i915_gem_object *obj;
3132         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3133         int i, n = 0;
3134         int ret;
3135
3136         if (args->flags != 0)
3137                 return -EINVAL;
3138
3139         ret = i915_mutex_lock_interruptible(dev);
3140         if (ret)
3141                 return ret;
3142
3143         obj = to_intel_bo(drm_gem_object_lookup(file, args->bo_handle));
3144         if (&obj->base == NULL) {
3145                 mutex_unlock(&dev->struct_mutex);
3146                 return -ENOENT;
3147         }
3148
3149         /* Need to make sure the object gets inactive eventually. */
3150         ret = i915_gem_object_flush_active(obj);
3151         if (ret)
3152                 goto out;
3153
3154         if (!obj->active)
3155                 goto out;
3156
3157         /* Do this after OLR check to make sure we make forward progress polling
3158          * on this IOCTL with a timeout == 0 (like busy ioctl)
3159          */
3160         if (args->timeout_ns == 0) {
3161                 ret = -ETIME;
3162                 goto out;
3163         }
3164
3165         drm_gem_object_unreference(&obj->base);
3166
3167         for (i = 0; i < I915_NUM_ENGINES; i++) {
3168                 if (obj->last_read_req[i] == NULL)
3169                         continue;
3170
3171                 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3172         }
3173
3174         mutex_unlock(&dev->struct_mutex);
3175
3176         for (i = 0; i < n; i++) {
3177                 if (ret == 0)
3178                         ret = __i915_wait_request(req[i], true,
3179                                                   args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3180                                                   to_rps_client(file));
3181                 i915_gem_request_unreference__unlocked(req[i]);
3182         }
3183         return ret;
3184
3185 out:
3186         drm_gem_object_unreference(&obj->base);
3187         mutex_unlock(&dev->struct_mutex);
3188         return ret;
3189 }
3190
3191 static int
3192 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3193                        struct intel_engine_cs *to,
3194                        struct drm_i915_gem_request *from_req,
3195                        struct drm_i915_gem_request **to_req)
3196 {
3197         struct intel_engine_cs *from;
3198         int ret;
3199
3200         from = i915_gem_request_get_engine(from_req);
3201         if (to == from)
3202                 return 0;
3203
3204         if (i915_gem_request_completed(from_req, true))
3205                 return 0;
3206
3207         if (!i915_semaphore_is_enabled(obj->base.dev)) {
3208                 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3209                 ret = __i915_wait_request(from_req,
3210                                           i915->mm.interruptible,
3211                                           NULL,
3212                                           &i915->rps.semaphores);
3213                 if (ret)
3214                         return ret;
3215
3216                 i915_gem_object_retire_request(obj, from_req);
3217         } else {
3218                 int idx = intel_ring_sync_index(from, to);
3219                 u32 seqno = i915_gem_request_get_seqno(from_req);
3220
3221                 WARN_ON(!to_req);
3222
3223                 if (seqno <= from->semaphore.sync_seqno[idx])
3224                         return 0;
3225
3226                 if (*to_req == NULL) {
3227                         struct drm_i915_gem_request *req;
3228
3229                         req = i915_gem_request_alloc(to, NULL);
3230                         if (IS_ERR(req))
3231                                 return PTR_ERR(req);
3232
3233                         *to_req = req;
3234                 }
3235
3236                 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3237                 ret = to->semaphore.sync_to(*to_req, from, seqno);
3238                 if (ret)
3239                         return ret;
3240
3241                 /* We use last_read_req because sync_to()
3242                  * might have just caused seqno wrap under
3243                  * the radar.
3244                  */
3245                 from->semaphore.sync_seqno[idx] =
3246                         i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3247         }
3248
3249         return 0;
3250 }
3251
3252 /**
3253  * i915_gem_object_sync - sync an object to a ring.
3254  *
3255  * @obj: object which may be in use on another ring.
3256  * @to: ring we wish to use the object on. May be NULL.
3257  * @to_req: request we wish to use the object for. See below.
3258  *          This will be allocated and returned if a request is
3259  *          required but not passed in.
3260  *
3261  * This code is meant to abstract object synchronization with the GPU.
3262  * Calling with NULL implies synchronizing the object with the CPU
3263  * rather than a particular GPU ring. Conceptually we serialise writes
3264  * between engines inside the GPU. We only allow one engine to write
3265  * into a buffer at any time, but multiple readers. To ensure each has
3266  * a coherent view of memory, we must:
3267  *
3268  * - If there is an outstanding write request to the object, the new
3269  *   request must wait for it to complete (either CPU or in hw, requests
3270  *   on the same ring will be naturally ordered).
3271  *
3272  * - If we are a write request (pending_write_domain is set), the new
3273  *   request must wait for outstanding read requests to complete.
3274  *
3275  * For CPU synchronisation (NULL to) no request is required. For syncing with
3276  * rings to_req must be non-NULL. However, a request does not have to be
3277  * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3278  * request will be allocated automatically and returned through *to_req. Note
3279  * that it is not guaranteed that commands will be emitted (because the system
3280  * might already be idle). Hence there is no need to create a request that
3281  * might never have any work submitted. Note further that if a request is
3282  * returned in *to_req, it is the responsibility of the caller to submit
3283  * that request (after potentially adding more work to it).
3284  *
3285  * Returns 0 if successful, else propagates up the lower layer error.
3286  */
3287 int
3288 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3289                      struct intel_engine_cs *to,
3290                      struct drm_i915_gem_request **to_req)
3291 {
3292         const bool readonly = obj->base.pending_write_domain == 0;
3293         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3294         int ret, i, n;
3295
3296         if (!obj->active)
3297                 return 0;
3298
3299         if (to == NULL)
3300                 return i915_gem_object_wait_rendering(obj, readonly);
3301
3302         n = 0;
3303         if (readonly) {
3304                 if (obj->last_write_req)
3305                         req[n++] = obj->last_write_req;
3306         } else {
3307                 for (i = 0; i < I915_NUM_ENGINES; i++)
3308                         if (obj->last_read_req[i])
3309                                 req[n++] = obj->last_read_req[i];
3310         }
3311         for (i = 0; i < n; i++) {
3312                 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3313                 if (ret)
3314                         return ret;
3315         }
3316
3317         return 0;
3318 }
3319
3320 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3321 {
3322         u32 old_write_domain, old_read_domains;
3323
3324         /* Force a pagefault for domain tracking on next user access */
3325         i915_gem_release_mmap(obj);
3326
3327         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3328                 return;
3329
3330         old_read_domains = obj->base.read_domains;
3331         old_write_domain = obj->base.write_domain;
3332
3333         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3334         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3335
3336         trace_i915_gem_object_change_domain(obj,
3337                                             old_read_domains,
3338                                             old_write_domain);
3339 }
3340
3341 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3342 {
3343         struct drm_i915_gem_object *obj = vma->obj;
3344         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3345         int ret;
3346
3347         if (list_empty(&vma->obj_link))
3348                 return 0;
3349
3350         if (!drm_mm_node_allocated(&vma->node)) {
3351                 i915_gem_vma_destroy(vma);
3352                 return 0;
3353         }
3354
3355         if (vma->pin_count)
3356                 return -EBUSY;
3357
3358         BUG_ON(obj->pages == NULL);
3359
3360         if (wait) {
3361                 ret = i915_gem_object_wait_rendering(obj, false);
3362                 if (ret)
3363                         return ret;
3364         }
3365
3366         if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3367                 i915_gem_object_finish_gtt(obj);
3368
3369                 /* release the fence reg _after_ flushing */
3370                 ret = i915_gem_object_put_fence(obj);
3371                 if (ret)
3372                         return ret;
3373         }
3374
3375         trace_i915_vma_unbind(vma);
3376
3377         vma->vm->unbind_vma(vma);
3378         vma->bound = 0;
3379
3380         list_del_init(&vma->vm_link);
3381         if (vma->is_ggtt) {
3382                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3383                         obj->map_and_fenceable = false;
3384                 } else if (vma->ggtt_view.pages) {
3385                         sg_free_table(vma->ggtt_view.pages);
3386                         kfree(vma->ggtt_view.pages);
3387                 }
3388                 vma->ggtt_view.pages = NULL;
3389         }
3390
3391         drm_mm_remove_node(&vma->node);
3392         i915_gem_vma_destroy(vma);
3393
3394         /* Since the unbound list is global, only move to that list if
3395          * no more VMAs exist. */
3396         if (list_empty(&obj->vma_list))
3397                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3398
3399         /* And finally now the object is completely decoupled from this vma,
3400          * we can drop its hold on the backing storage and allow it to be
3401          * reaped by the shrinker.
3402          */
3403         i915_gem_object_unpin_pages(obj);
3404
3405         return 0;
3406 }
3407
3408 int i915_vma_unbind(struct i915_vma *vma)
3409 {
3410         return __i915_vma_unbind(vma, true);
3411 }
3412
3413 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3414 {
3415         return __i915_vma_unbind(vma, false);
3416 }
3417
3418 int i915_gpu_idle(struct drm_device *dev)
3419 {
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         struct intel_engine_cs *engine;
3422         int ret;
3423
3424         /* Flush everything onto the inactive list. */
3425         for_each_engine(engine, dev_priv) {
3426                 if (!i915.enable_execlists) {
3427                         struct drm_i915_gem_request *req;
3428
3429                         req = i915_gem_request_alloc(engine, NULL);
3430                         if (IS_ERR(req))
3431                                 return PTR_ERR(req);
3432
3433                         ret = i915_switch_context(req);
3434                         i915_add_request_no_flush(req);
3435                         if (ret)
3436                                 return ret;
3437                 }
3438
3439                 ret = intel_engine_idle(engine);
3440                 if (ret)
3441                         return ret;
3442         }
3443
3444         WARN_ON(i915_verify_lists(dev));
3445         return 0;
3446 }
3447
3448 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3449                                      unsigned long cache_level)
3450 {
3451         struct drm_mm_node *gtt_space = &vma->node;
3452         struct drm_mm_node *other;
3453
3454         /*
3455          * On some machines we have to be careful when putting differing types
3456          * of snoopable memory together to avoid the prefetcher crossing memory
3457          * domains and dying. During vm initialisation, we decide whether or not
3458          * these constraints apply and set the drm_mm.color_adjust
3459          * appropriately.
3460          */
3461         if (vma->vm->mm.color_adjust == NULL)
3462                 return true;
3463
3464         if (!drm_mm_node_allocated(gtt_space))
3465                 return true;
3466
3467         if (list_empty(&gtt_space->node_list))
3468                 return true;
3469
3470         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3471         if (other->allocated && !other->hole_follows && other->color != cache_level)
3472                 return false;
3473
3474         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3475         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3476                 return false;
3477
3478         return true;
3479 }
3480
3481 /**
3482  * Finds free space in the GTT aperture and binds the object or a view of it
3483  * there.
3484  */
3485 static struct i915_vma *
3486 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3487                            struct i915_address_space *vm,
3488                            const struct i915_ggtt_view *ggtt_view,
3489                            unsigned alignment,
3490                            uint64_t flags)
3491 {
3492         struct drm_device *dev = obj->base.dev;
3493         struct drm_i915_private *dev_priv = to_i915(dev);
3494         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3495         u32 fence_alignment, unfenced_alignment;
3496         u32 search_flag, alloc_flag;
3497         u64 start, end;
3498         u64 size, fence_size;
3499         struct i915_vma *vma;
3500         int ret;
3501
3502         if (i915_is_ggtt(vm)) {
3503                 u32 view_size;
3504
3505                 if (WARN_ON(!ggtt_view))
3506                         return ERR_PTR(-EINVAL);
3507
3508                 view_size = i915_ggtt_view_size(obj, ggtt_view);
3509
3510                 fence_size = i915_gem_get_gtt_size(dev,
3511                                                    view_size,
3512                                                    obj->tiling_mode);
3513                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3514                                                              view_size,
3515                                                              obj->tiling_mode,
3516                                                              true);
3517                 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3518                                                                 view_size,
3519                                                                 obj->tiling_mode,
3520                                                                 false);
3521                 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3522         } else {
3523                 fence_size = i915_gem_get_gtt_size(dev,
3524                                                    obj->base.size,
3525                                                    obj->tiling_mode);
3526                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3527                                                              obj->base.size,
3528                                                              obj->tiling_mode,
3529                                                              true);
3530                 unfenced_alignment =
3531                         i915_gem_get_gtt_alignment(dev,
3532                                                    obj->base.size,
3533                                                    obj->tiling_mode,
3534                                                    false);
3535                 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3536         }
3537
3538         start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3539         end = vm->total;
3540         if (flags & PIN_MAPPABLE)
3541                 end = min_t(u64, end, ggtt->mappable_end);
3542         if (flags & PIN_ZONE_4G)
3543                 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3544
3545         if (alignment == 0)
3546                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3547                                                 unfenced_alignment;
3548         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3549                 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3550                           ggtt_view ? ggtt_view->type : 0,
3551                           alignment);
3552                 return ERR_PTR(-EINVAL);
3553         }
3554
3555         /* If binding the object/GGTT view requires more space than the entire
3556          * aperture has, reject it early before evicting everything in a vain
3557          * attempt to find space.
3558          */
3559         if (size > end) {
3560                 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3561                           ggtt_view ? ggtt_view->type : 0,
3562                           size,
3563                           flags & PIN_MAPPABLE ? "mappable" : "total",
3564                           end);
3565                 return ERR_PTR(-E2BIG);
3566         }
3567
3568         ret = i915_gem_object_get_pages(obj);
3569         if (ret)
3570                 return ERR_PTR(ret);
3571
3572         i915_gem_object_pin_pages(obj);
3573
3574         vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3575                           i915_gem_obj_lookup_or_create_vma(obj, vm);
3576
3577         if (IS_ERR(vma))
3578                 goto err_unpin;
3579
3580         if (flags & PIN_OFFSET_FIXED) {
3581                 uint64_t offset = flags & PIN_OFFSET_MASK;
3582
3583                 if (offset & (alignment - 1) || offset + size > end) {
3584                         ret = -EINVAL;
3585                         goto err_free_vma;
3586                 }
3587                 vma->node.start = offset;
3588                 vma->node.size = size;
3589                 vma->node.color = obj->cache_level;
3590                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3591                 if (ret) {
3592                         ret = i915_gem_evict_for_vma(vma);
3593                         if (ret == 0)
3594                                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3595                 }
3596                 if (ret)
3597                         goto err_free_vma;
3598         } else {
3599                 if (flags & PIN_HIGH) {
3600                         search_flag = DRM_MM_SEARCH_BELOW;
3601                         alloc_flag = DRM_MM_CREATE_TOP;
3602                 } else {
3603                         search_flag = DRM_MM_SEARCH_DEFAULT;
3604                         alloc_flag = DRM_MM_CREATE_DEFAULT;
3605                 }
3606
3607 search_free:
3608                 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3609                                                           size, alignment,
3610                                                           obj->cache_level,
3611                                                           start, end,
3612                                                           search_flag,
3613                                                           alloc_flag);
3614                 if (ret) {
3615                         ret = i915_gem_evict_something(dev, vm, size, alignment,
3616                                                        obj->cache_level,
3617                                                        start, end,
3618                                                        flags);
3619                         if (ret == 0)
3620                                 goto search_free;
3621
3622                         goto err_free_vma;
3623                 }
3624         }
3625         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3626                 ret = -EINVAL;
3627                 goto err_remove_node;
3628         }
3629
3630         trace_i915_vma_bind(vma, flags);
3631         ret = i915_vma_bind(vma, obj->cache_level, flags);
3632         if (ret)
3633                 goto err_remove_node;
3634
3635         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3636         list_add_tail(&vma->vm_link, &vm->inactive_list);
3637
3638         return vma;
3639
3640 err_remove_node:
3641         drm_mm_remove_node(&vma->node);
3642 err_free_vma:
3643         i915_gem_vma_destroy(vma);
3644         vma = ERR_PTR(ret);
3645 err_unpin:
3646         i915_gem_object_unpin_pages(obj);
3647         return vma;
3648 }
3649
3650 bool
3651 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3652                         bool force)
3653 {
3654         /* If we don't have a page list set up, then we're not pinned
3655          * to GPU, and we can ignore the cache flush because it'll happen
3656          * again at bind time.
3657          */
3658         if (obj->pages == NULL)
3659                 return false;
3660
3661         /*
3662          * Stolen memory is always coherent with the GPU as it is explicitly
3663          * marked as wc by the system, or the system is cache-coherent.
3664          */
3665         if (obj->stolen || obj->phys_handle)
3666                 return false;
3667
3668         /* If the GPU is snooping the contents of the CPU cache,
3669          * we do not need to manually clear the CPU cache lines.  However,
3670          * the caches are only snooped when the render cache is
3671          * flushed/invalidated.  As we always have to emit invalidations
3672          * and flushes when moving into and out of the RENDER domain, correct
3673          * snooping behaviour occurs naturally as the result of our domain
3674          * tracking.
3675          */
3676         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3677                 obj->cache_dirty = true;
3678                 return false;
3679         }
3680
3681         trace_i915_gem_object_clflush(obj);
3682         drm_clflush_sg(obj->pages);
3683         obj->cache_dirty = false;
3684
3685         return true;
3686 }
3687
3688 /** Flushes the GTT write domain for the object if it's dirty. */
3689 static void
3690 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3691 {
3692         uint32_t old_write_domain;
3693
3694         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3695                 return;
3696
3697         /* No actual flushing is required for the GTT write domain.  Writes
3698          * to it immediately go to main memory as far as we know, so there's
3699          * no chipset flush.  It also doesn't land in render cache.
3700          *
3701          * However, we do have to enforce the order so that all writes through
3702          * the GTT land before any writes to the device, such as updates to
3703          * the GATT itself.
3704          */
3705         wmb();
3706
3707         old_write_domain = obj->base.write_domain;
3708         obj->base.write_domain = 0;
3709
3710         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3711
3712         trace_i915_gem_object_change_domain(obj,
3713                                             obj->base.read_domains,
3714                                             old_write_domain);
3715 }
3716
3717 /** Flushes the CPU write domain for the object if it's dirty. */
3718 static void
3719 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3720 {
3721         uint32_t old_write_domain;
3722
3723         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3724                 return;
3725
3726         if (i915_gem_clflush_object(obj, obj->pin_display))
3727                 i915_gem_chipset_flush(obj->base.dev);
3728
3729         old_write_domain = obj->base.write_domain;
3730         obj->base.write_domain = 0;
3731
3732         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3733
3734         trace_i915_gem_object_change_domain(obj,
3735                                             obj->base.read_domains,
3736                                             old_write_domain);
3737 }
3738
3739 /**
3740  * Moves a single object to the GTT read, and possibly write domain.
3741  *
3742  * This function returns when the move is complete, including waiting on
3743  * flushes to occur.
3744  */
3745 int
3746 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3747 {
3748         struct drm_device *dev = obj->base.dev;
3749         struct drm_i915_private *dev_priv = to_i915(dev);
3750         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3751         uint32_t old_write_domain, old_read_domains;
3752         struct i915_vma *vma;
3753         int ret;
3754
3755         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3756                 return 0;
3757
3758         ret = i915_gem_object_wait_rendering(obj, !write);
3759         if (ret)
3760                 return ret;
3761
3762         /* Flush and acquire obj->pages so that we are coherent through
3763          * direct access in memory with previous cached writes through
3764          * shmemfs and that our cache domain tracking remains valid.
3765          * For example, if the obj->filp was moved to swap without us
3766          * being notified and releasing the pages, we would mistakenly
3767          * continue to assume that the obj remained out of the CPU cached
3768          * domain.
3769          */
3770         ret = i915_gem_object_get_pages(obj);
3771         if (ret)
3772                 return ret;
3773
3774         i915_gem_object_flush_cpu_write_domain(obj);
3775
3776         /* Serialise direct access to this object with the barriers for
3777          * coherent writes from the GPU, by effectively invalidating the
3778          * GTT domain upon first access.
3779          */
3780         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3781                 mb();
3782
3783         old_write_domain = obj->base.write_domain;
3784         old_read_domains = obj->base.read_domains;
3785
3786         /* It should now be out of any other write domains, and we can update
3787          * the domain values for our changes.
3788          */
3789         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3790         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3791         if (write) {
3792                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3793                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3794                 obj->dirty = 1;
3795         }
3796
3797         trace_i915_gem_object_change_domain(obj,
3798                                             old_read_domains,
3799                                             old_write_domain);
3800
3801         /* And bump the LRU for this access */
3802         vma = i915_gem_obj_to_ggtt(obj);
3803         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
3804                 list_move_tail(&vma->vm_link,
3805                                &ggtt->base.inactive_list);
3806
3807         return 0;
3808 }
3809
3810 /**
3811  * Changes the cache-level of an object across all VMA.
3812  *
3813  * After this function returns, the object will be in the new cache-level
3814  * across all GTT and the contents of the backing storage will be coherent,
3815  * with respect to the new cache-level. In order to keep the backing storage
3816  * coherent for all users, we only allow a single cache level to be set
3817  * globally on the object and prevent it from being changed whilst the
3818  * hardware is reading from the object. That is if the object is currently
3819  * on the scanout it will be set to uncached (or equivalent display
3820  * cache coherency) and all non-MOCS GPU access will also be uncached so
3821  * that all direct access to the scanout remains coherent.
3822  */
3823 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3824                                     enum i915_cache_level cache_level)
3825 {
3826         struct drm_device *dev = obj->base.dev;
3827         struct i915_vma *vma, *next;
3828         bool bound = false;
3829         int ret = 0;
3830
3831         if (obj->cache_level == cache_level)
3832                 goto out;
3833
3834         /* Inspect the list of currently bound VMA and unbind any that would
3835          * be invalid given the new cache-level. This is principally to
3836          * catch the issue of the CS prefetch crossing page boundaries and
3837          * reading an invalid PTE on older architectures.
3838          */
3839         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
3840                 if (!drm_mm_node_allocated(&vma->node))
3841                         continue;
3842
3843                 if (vma->pin_count) {
3844                         DRM_DEBUG("can not change the cache level of pinned objects\n");
3845                         return -EBUSY;
3846                 }
3847
3848                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
3849                         ret = i915_vma_unbind(vma);
3850                         if (ret)
3851                                 return ret;
3852                 } else
3853                         bound = true;
3854         }
3855
3856         /* We can reuse the existing drm_mm nodes but need to change the
3857          * cache-level on the PTE. We could simply unbind them all and
3858          * rebind with the correct cache-level on next use. However since
3859          * we already have a valid slot, dma mapping, pages etc, we may as
3860          * rewrite the PTE in the belief that doing so tramples upon less
3861          * state and so involves less work.
3862          */
3863         if (bound) {
3864                 /* Before we change the PTE, the GPU must not be accessing it.
3865                  * If we wait upon the object, we know that all the bound
3866                  * VMA are no longer active.
3867                  */
3868                 ret = i915_gem_object_wait_rendering(obj, false);
3869                 if (ret)
3870                         return ret;
3871
3872                 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
3873                         /* Access to snoopable pages through the GTT is
3874                          * incoherent and on some machines causes a hard
3875                          * lockup. Relinquish the CPU mmaping to force
3876                          * userspace to refault in the pages and we can
3877                          * then double check if the GTT mapping is still
3878                          * valid for that pointer access.
3879                          */
3880                         i915_gem_release_mmap(obj);
3881
3882                         /* As we no longer need a fence for GTT access,
3883                          * we can relinquish it now (and so prevent having
3884                          * to steal a fence from someone else on the next
3885                          * fence request). Note GPU activity would have
3886                          * dropped the fence as all snoopable access is
3887                          * supposed to be linear.
3888                          */
3889                         ret = i915_gem_object_put_fence(obj);
3890                         if (ret)
3891                                 return ret;
3892                 } else {
3893                         /* We either have incoherent backing store and
3894                          * so no GTT access or the architecture is fully
3895                          * coherent. In such cases, existing GTT mmaps
3896                          * ignore the cache bit in the PTE and we can
3897                          * rewrite it without confusing the GPU or having
3898                          * to force userspace to fault back in its mmaps.
3899                          */
3900                 }
3901
3902                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3903                         if (!drm_mm_node_allocated(&vma->node))
3904                                 continue;
3905
3906                         ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
3907                         if (ret)
3908                                 return ret;
3909                 }
3910         }
3911
3912         list_for_each_entry(vma, &obj->vma_list, obj_link)
3913                 vma->node.color = cache_level;
3914         obj->cache_level = cache_level;
3915
3916 out:
3917         /* Flush the dirty CPU caches to the backing storage so that the
3918          * object is now coherent at its new cache level (with respect
3919          * to the access domain).
3920          */
3921         if (obj->cache_dirty &&
3922             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
3923             cpu_write_needs_clflush(obj)) {
3924                 if (i915_gem_clflush_object(obj, true))
3925                         i915_gem_chipset_flush(obj->base.dev);
3926         }
3927
3928         return 0;
3929 }
3930
3931 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3932                                struct drm_file *file)
3933 {
3934         struct drm_i915_gem_caching *args = data;
3935         struct drm_i915_gem_object *obj;
3936
3937         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
3938         if (&obj->base == NULL)
3939                 return -ENOENT;
3940
3941         switch (obj->cache_level) {
3942         case I915_CACHE_LLC:
3943         case I915_CACHE_L3_LLC:
3944                 args->caching = I915_CACHING_CACHED;
3945                 break;
3946
3947         case I915_CACHE_WT:
3948                 args->caching = I915_CACHING_DISPLAY;
3949                 break;
3950
3951         default:
3952                 args->caching = I915_CACHING_NONE;
3953                 break;
3954         }
3955
3956         drm_gem_object_unreference_unlocked(&obj->base);
3957         return 0;
3958 }
3959
3960 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3961                                struct drm_file *file)
3962 {
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964         struct drm_i915_gem_caching *args = data;
3965         struct drm_i915_gem_object *obj;
3966         enum i915_cache_level level;
3967         int ret;
3968
3969         switch (args->caching) {
3970         case I915_CACHING_NONE:
3971                 level = I915_CACHE_NONE;
3972                 break;
3973         case I915_CACHING_CACHED:
3974                 /*
3975                  * Due to a HW issue on BXT A stepping, GPU stores via a
3976                  * snooped mapping may leave stale data in a corresponding CPU
3977                  * cacheline, whereas normally such cachelines would get
3978                  * invalidated.
3979                  */
3980                 if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
3981                         return -ENODEV;
3982
3983                 level = I915_CACHE_LLC;
3984                 break;
3985         case I915_CACHING_DISPLAY:
3986                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3987                 break;
3988         default:
3989                 return -EINVAL;
3990         }
3991
3992         intel_runtime_pm_get(dev_priv);
3993
3994         ret = i915_mutex_lock_interruptible(dev);
3995         if (ret)
3996                 goto rpm_put;
3997
3998         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
3999         if (&obj->base == NULL) {
4000                 ret = -ENOENT;
4001                 goto unlock;
4002         }
4003
4004         ret = i915_gem_object_set_cache_level(obj, level);
4005
4006         drm_gem_object_unreference(&obj->base);
4007 unlock:
4008         mutex_unlock(&dev->struct_mutex);
4009 rpm_put:
4010         intel_runtime_pm_put(dev_priv);
4011
4012         return ret;
4013 }
4014
4015 /*
4016  * Prepare buffer for display plane (scanout, cursors, etc).
4017  * Can be called from an uninterruptible phase (modesetting) and allows
4018  * any flushes to be pipelined (for pageflips).
4019  */
4020 int
4021 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4022                                      u32 alignment,
4023                                      const struct i915_ggtt_view *view)
4024 {
4025         u32 old_read_domains, old_write_domain;
4026         int ret;
4027
4028         /* Mark the pin_display early so that we account for the
4029          * display coherency whilst setting up the cache domains.
4030          */
4031         obj->pin_display++;
4032
4033         /* The display engine is not coherent with the LLC cache on gen6.  As
4034          * a result, we make sure that the pinning that is about to occur is
4035          * done with uncached PTEs. This is lowest common denominator for all
4036          * chipsets.
4037          *
4038          * However for gen6+, we could do better by using the GFDT bit instead
4039          * of uncaching, which would allow us to flush all the LLC-cached data
4040          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4041          */
4042         ret = i915_gem_object_set_cache_level(obj,
4043                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4044         if (ret)
4045                 goto err_unpin_display;
4046
4047         /* As the user may map the buffer once pinned in the display plane
4048          * (e.g. libkms for the bootup splash), we have to ensure that we
4049          * always use map_and_fenceable for all scanout buffers.
4050          */
4051         ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4052                                        view->type == I915_GGTT_VIEW_NORMAL ?
4053                                        PIN_MAPPABLE : 0);
4054         if (ret)
4055                 goto err_unpin_display;
4056
4057         i915_gem_object_flush_cpu_write_domain(obj);
4058
4059         old_write_domain = obj->base.write_domain;
4060         old_read_domains = obj->base.read_domains;
4061
4062         /* It should now be out of any other write domains, and we can update
4063          * the domain values for our changes.
4064          */
4065         obj->base.write_domain = 0;
4066         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4067
4068         trace_i915_gem_object_change_domain(obj,
4069                                             old_read_domains,
4070                                             old_write_domain);
4071
4072         return 0;
4073
4074 err_unpin_display:
4075         obj->pin_display--;
4076         return ret;
4077 }
4078
4079 void
4080 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4081                                          const struct i915_ggtt_view *view)
4082 {
4083         if (WARN_ON(obj->pin_display == 0))
4084                 return;
4085
4086         i915_gem_object_ggtt_unpin_view(obj, view);
4087
4088         obj->pin_display--;
4089 }
4090
4091 /**
4092  * Moves a single object to the CPU read, and possibly write domain.
4093  *
4094  * This function returns when the move is complete, including waiting on
4095  * flushes to occur.
4096  */
4097 int
4098 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4099 {
4100         uint32_t old_write_domain, old_read_domains;
4101         int ret;
4102
4103         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4104                 return 0;
4105
4106         ret = i915_gem_object_wait_rendering(obj, !write);
4107         if (ret)
4108                 return ret;
4109
4110         i915_gem_object_flush_gtt_write_domain(obj);
4111
4112         old_write_domain = obj->base.write_domain;
4113         old_read_domains = obj->base.read_domains;
4114
4115         /* Flush the CPU cache if it's still invalid. */
4116         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4117                 i915_gem_clflush_object(obj, false);
4118
4119                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4120         }
4121
4122         /* It should now be out of any other write domains, and we can update
4123          * the domain values for our changes.
4124          */
4125         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4126
4127         /* If we're writing through the CPU, then the GPU read domains will
4128          * need to be invalidated at next use.
4129          */
4130         if (write) {
4131                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4132                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4133         }
4134
4135         trace_i915_gem_object_change_domain(obj,
4136                                             old_read_domains,
4137                                             old_write_domain);
4138
4139         return 0;
4140 }
4141
4142 /* Throttle our rendering by waiting until the ring has completed our requests
4143  * emitted over 20 msec ago.
4144  *
4145  * Note that if we were to use the current jiffies each time around the loop,
4146  * we wouldn't escape the function with any frames outstanding if the time to
4147  * render a frame was over 20ms.
4148  *
4149  * This should get us reasonable parallelism between CPU and GPU but also
4150  * relatively low latency when blocking on a particular request to finish.
4151  */
4152 static int
4153 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4154 {
4155         struct drm_i915_private *dev_priv = dev->dev_private;
4156         struct drm_i915_file_private *file_priv = file->driver_priv;
4157         unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4158         struct drm_i915_gem_request *request, *target = NULL;
4159         int ret;
4160
4161         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4162         if (ret)
4163                 return ret;
4164
4165         /* ABI: return -EIO if already wedged */
4166         if (i915_terminally_wedged(&dev_priv->gpu_error))
4167                 return -EIO;
4168
4169         spin_lock(&file_priv->mm.lock);
4170         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4171                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4172                         break;
4173
4174                 /*
4175                  * Note that the request might not have been submitted yet.
4176                  * In which case emitted_jiffies will be zero.
4177                  */
4178                 if (!request->emitted_jiffies)
4179                         continue;
4180
4181                 target = request;
4182         }
4183         if (target)
4184                 i915_gem_request_reference(target);
4185         spin_unlock(&file_priv->mm.lock);
4186
4187         if (target == NULL)
4188                 return 0;
4189
4190         ret = __i915_wait_request(target, true, NULL, NULL);
4191         if (ret == 0)
4192                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4193
4194         i915_gem_request_unreference__unlocked(target);
4195
4196         return ret;
4197 }
4198
4199 static bool
4200 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4201 {
4202         struct drm_i915_gem_object *obj = vma->obj;
4203
4204         if (alignment &&
4205             vma->node.start & (alignment - 1))
4206                 return true;
4207
4208         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4209                 return true;
4210
4211         if (flags & PIN_OFFSET_BIAS &&
4212             vma->node.start < (flags & PIN_OFFSET_MASK))
4213                 return true;
4214
4215         if (flags & PIN_OFFSET_FIXED &&
4216             vma->node.start != (flags & PIN_OFFSET_MASK))
4217                 return true;
4218
4219         return false;
4220 }
4221
4222 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4223 {
4224         struct drm_i915_gem_object *obj = vma->obj;
4225         bool mappable, fenceable;
4226         u32 fence_size, fence_alignment;
4227
4228         fence_size = i915_gem_get_gtt_size(obj->base.dev,
4229                                            obj->base.size,
4230                                            obj->tiling_mode);
4231         fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4232                                                      obj->base.size,
4233                                                      obj->tiling_mode,
4234                                                      true);
4235
4236         fenceable = (vma->node.size == fence_size &&
4237                      (vma->node.start & (fence_alignment - 1)) == 0);
4238
4239         mappable = (vma->node.start + fence_size <=
4240                     to_i915(obj->base.dev)->ggtt.mappable_end);
4241
4242         obj->map_and_fenceable = mappable && fenceable;
4243 }
4244
4245 static int
4246 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4247                        struct i915_address_space *vm,
4248                        const struct i915_ggtt_view *ggtt_view,
4249                        uint32_t alignment,
4250                        uint64_t flags)
4251 {
4252         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4253         struct i915_vma *vma;
4254         unsigned bound;
4255         int ret;
4256
4257         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4258                 return -ENODEV;
4259
4260         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4261                 return -EINVAL;
4262
4263         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4264                 return -EINVAL;
4265
4266         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4267                 return -EINVAL;
4268
4269         vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4270                           i915_gem_obj_to_vma(obj, vm);
4271
4272         if (vma) {
4273                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4274                         return -EBUSY;
4275
4276                 if (i915_vma_misplaced(vma, alignment, flags)) {
4277                         WARN(vma->pin_count,
4278                              "bo is already pinned in %s with incorrect alignment:"
4279                              " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4280                              " obj->map_and_fenceable=%d\n",
4281                              ggtt_view ? "ggtt" : "ppgtt",
4282                              upper_32_bits(vma->node.start),
4283                              lower_32_bits(vma->node.start),
4284                              alignment,
4285                              !!(flags & PIN_MAPPABLE),
4286                              obj->map_and_fenceable);
4287                         ret = i915_vma_unbind(vma);
4288                         if (ret)
4289                                 return ret;
4290
4291                         vma = NULL;
4292                 }
4293         }
4294
4295         bound = vma ? vma->bound : 0;
4296         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4297                 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4298                                                  flags);
4299                 if (IS_ERR(vma))
4300                         return PTR_ERR(vma);
4301         } else {
4302                 ret = i915_vma_bind(vma, obj->cache_level, flags);
4303                 if (ret)
4304                         return ret;
4305         }
4306
4307         if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4308             (bound ^ vma->bound) & GLOBAL_BIND) {
4309                 __i915_vma_set_map_and_fenceable(vma);
4310                 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4311         }
4312
4313         vma->pin_count++;
4314         return 0;
4315 }
4316
4317 int
4318 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4319                     struct i915_address_space *vm,
4320                     uint32_t alignment,
4321                     uint64_t flags)
4322 {
4323         return i915_gem_object_do_pin(obj, vm,
4324                                       i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4325                                       alignment, flags);
4326 }
4327
4328 int
4329 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4330                          const struct i915_ggtt_view *view,
4331                          uint32_t alignment,
4332                          uint64_t flags)
4333 {
4334         struct drm_device *dev = obj->base.dev;
4335         struct drm_i915_private *dev_priv = to_i915(dev);
4336         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4337
4338         BUG_ON(!view);
4339
4340         return i915_gem_object_do_pin(obj, &ggtt->base, view,
4341                                       alignment, flags | PIN_GLOBAL);
4342 }
4343
4344 void
4345 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4346                                 const struct i915_ggtt_view *view)
4347 {
4348         struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4349
4350         WARN_ON(vma->pin_count == 0);
4351         WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4352
4353         --vma->pin_count;
4354 }
4355
4356 int
4357 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4358                     struct drm_file *file)
4359 {
4360         struct drm_i915_gem_busy *args = data;
4361         struct drm_i915_gem_object *obj;
4362         int ret;
4363
4364         ret = i915_mutex_lock_interruptible(dev);
4365         if (ret)
4366                 return ret;
4367
4368         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
4369         if (&obj->base == NULL) {
4370                 ret = -ENOENT;
4371                 goto unlock;
4372         }
4373
4374         /* Count all active objects as busy, even if they are currently not used
4375          * by the gpu. Users of this interface expect objects to eventually
4376          * become non-busy without any further actions, therefore emit any
4377          * necessary flushes here.
4378          */
4379         ret = i915_gem_object_flush_active(obj);
4380         if (ret)
4381                 goto unref;
4382
4383         args->busy = 0;
4384         if (obj->active) {
4385                 int i;
4386
4387                 for (i = 0; i < I915_NUM_ENGINES; i++) {
4388                         struct drm_i915_gem_request *req;
4389
4390                         req = obj->last_read_req[i];
4391                         if (req)
4392                                 args->busy |= 1 << (16 + req->engine->exec_id);
4393                 }
4394                 if (obj->last_write_req)
4395                         args->busy |= obj->last_write_req->engine->exec_id;
4396         }
4397
4398 unref:
4399         drm_gem_object_unreference(&obj->base);
4400 unlock:
4401         mutex_unlock(&dev->struct_mutex);
4402         return ret;
4403 }
4404
4405 int
4406 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4407                         struct drm_file *file_priv)
4408 {
4409         return i915_gem_ring_throttle(dev, file_priv);
4410 }
4411
4412 int
4413 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4414                        struct drm_file *file_priv)
4415 {
4416         struct drm_i915_private *dev_priv = dev->dev_private;
4417         struct drm_i915_gem_madvise *args = data;
4418         struct drm_i915_gem_object *obj;
4419         int ret;
4420
4421         switch (args->madv) {
4422         case I915_MADV_DONTNEED:
4423         case I915_MADV_WILLNEED:
4424             break;
4425         default:
4426             return -EINVAL;
4427         }
4428
4429         ret = i915_mutex_lock_interruptible(dev);
4430         if (ret)
4431                 return ret;
4432
4433         obj = to_intel_bo(drm_gem_object_lookup(file_priv, args->handle));
4434         if (&obj->base == NULL) {
4435                 ret = -ENOENT;
4436                 goto unlock;
4437         }
4438
4439         if (i915_gem_obj_is_pinned(obj)) {
4440                 ret = -EINVAL;
4441                 goto out;
4442         }
4443
4444         if (obj->pages &&
4445             obj->tiling_mode != I915_TILING_NONE &&
4446             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4447                 if (obj->madv == I915_MADV_WILLNEED)
4448                         i915_gem_object_unpin_pages(obj);
4449                 if (args->madv == I915_MADV_WILLNEED)
4450                         i915_gem_object_pin_pages(obj);
4451         }
4452
4453         if (obj->madv != __I915_MADV_PURGED)
4454                 obj->madv = args->madv;
4455
4456         /* if the object is no longer attached, discard its backing storage */
4457         if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4458                 i915_gem_object_truncate(obj);
4459
4460         args->retained = obj->madv != __I915_MADV_PURGED;
4461
4462 out:
4463         drm_gem_object_unreference(&obj->base);
4464 unlock:
4465         mutex_unlock(&dev->struct_mutex);
4466         return ret;
4467 }
4468
4469 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4470                           const struct drm_i915_gem_object_ops *ops)
4471 {
4472         int i;
4473
4474         INIT_LIST_HEAD(&obj->global_list);
4475         for (i = 0; i < I915_NUM_ENGINES; i++)
4476                 INIT_LIST_HEAD(&obj->engine_list[i]);
4477         INIT_LIST_HEAD(&obj->obj_exec_link);
4478         INIT_LIST_HEAD(&obj->vma_list);
4479         INIT_LIST_HEAD(&obj->batch_pool_link);
4480
4481         obj->ops = ops;
4482
4483         obj->fence_reg = I915_FENCE_REG_NONE;
4484         obj->madv = I915_MADV_WILLNEED;
4485
4486         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4487 }
4488
4489 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4490         .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4491         .get_pages = i915_gem_object_get_pages_gtt,
4492         .put_pages = i915_gem_object_put_pages_gtt,
4493 };
4494
4495 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4496                                                   size_t size)
4497 {
4498         struct drm_i915_gem_object *obj;
4499         struct address_space *mapping;
4500         gfp_t mask;
4501
4502         obj = i915_gem_object_alloc(dev);
4503         if (obj == NULL)
4504                 return NULL;
4505
4506         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4507                 i915_gem_object_free(obj);
4508                 return NULL;
4509         }
4510
4511         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4512         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4513                 /* 965gm cannot relocate objects above 4GiB. */
4514                 mask &= ~__GFP_HIGHMEM;
4515                 mask |= __GFP_DMA32;
4516         }
4517
4518         mapping = file_inode(obj->base.filp)->i_mapping;
4519         mapping_set_gfp_mask(mapping, mask);
4520
4521         i915_gem_object_init(obj, &i915_gem_object_ops);
4522
4523         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4524         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4525
4526         if (HAS_LLC(dev)) {
4527                 /* On some devices, we can have the GPU use the LLC (the CPU
4528                  * cache) for about a 10% performance improvement
4529                  * compared to uncached.  Graphics requests other than
4530                  * display scanout are coherent with the CPU in
4531                  * accessing this cache.  This means in this mode we
4532                  * don't need to clflush on the CPU side, and on the
4533                  * GPU side we only need to flush internal caches to
4534                  * get data visible to the CPU.
4535                  *
4536                  * However, we maintain the display planes as UC, and so
4537                  * need to rebind when first used as such.
4538                  */
4539                 obj->cache_level = I915_CACHE_LLC;
4540         } else
4541                 obj->cache_level = I915_CACHE_NONE;
4542
4543         trace_i915_gem_object_create(obj);
4544
4545         return obj;
4546 }
4547
4548 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4549 {
4550         /* If we are the last user of the backing storage (be it shmemfs
4551          * pages or stolen etc), we know that the pages are going to be
4552          * immediately released. In this case, we can then skip copying
4553          * back the contents from the GPU.
4554          */
4555
4556         if (obj->madv != I915_MADV_WILLNEED)
4557                 return false;
4558
4559         if (obj->base.filp == NULL)
4560                 return true;
4561
4562         /* At first glance, this looks racy, but then again so would be
4563          * userspace racing mmap against close. However, the first external
4564          * reference to the filp can only be obtained through the
4565          * i915_gem_mmap_ioctl() which safeguards us against the user
4566          * acquiring such a reference whilst we are in the middle of
4567          * freeing the object.
4568          */
4569         return atomic_long_read(&obj->base.filp->f_count) == 1;
4570 }
4571
4572 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4573 {
4574         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4575         struct drm_device *dev = obj->base.dev;
4576         struct drm_i915_private *dev_priv = dev->dev_private;
4577         struct i915_vma *vma, *next;
4578
4579         intel_runtime_pm_get(dev_priv);
4580
4581         trace_i915_gem_object_destroy(obj);
4582
4583         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4584                 int ret;
4585
4586                 vma->pin_count = 0;
4587                 ret = i915_vma_unbind(vma);
4588                 if (WARN_ON(ret == -ERESTARTSYS)) {
4589                         bool was_interruptible;
4590
4591                         was_interruptible = dev_priv->mm.interruptible;
4592                         dev_priv->mm.interruptible = false;
4593
4594                         WARN_ON(i915_vma_unbind(vma));
4595
4596                         dev_priv->mm.interruptible = was_interruptible;
4597                 }
4598         }
4599
4600         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4601          * before progressing. */
4602         if (obj->stolen)
4603                 i915_gem_object_unpin_pages(obj);
4604
4605         WARN_ON(obj->frontbuffer_bits);
4606
4607         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4608             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4609             obj->tiling_mode != I915_TILING_NONE)
4610                 i915_gem_object_unpin_pages(obj);
4611
4612         if (WARN_ON(obj->pages_pin_count))
4613                 obj->pages_pin_count = 0;
4614         if (discard_backing_storage(obj))
4615                 obj->madv = I915_MADV_DONTNEED;
4616         i915_gem_object_put_pages(obj);
4617         i915_gem_object_free_mmap_offset(obj);
4618
4619         BUG_ON(obj->pages);
4620
4621         if (obj->base.import_attach)
4622                 drm_prime_gem_destroy(&obj->base, NULL);
4623
4624         if (obj->ops->release)
4625                 obj->ops->release(obj);
4626
4627         drm_gem_object_release(&obj->base);
4628         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4629
4630         kfree(obj->bit_17);
4631         i915_gem_object_free(obj);
4632
4633         intel_runtime_pm_put(dev_priv);
4634 }
4635
4636 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4637                                      struct i915_address_space *vm)
4638 {
4639         struct i915_vma *vma;
4640         list_for_each_entry(vma, &obj->vma_list, obj_link) {
4641                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4642                     vma->vm == vm)
4643                         return vma;
4644         }
4645         return NULL;
4646 }
4647
4648 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4649                                            const struct i915_ggtt_view *view)
4650 {
4651         struct drm_device *dev = obj->base.dev;
4652         struct drm_i915_private *dev_priv = to_i915(dev);
4653         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4654         struct i915_vma *vma;
4655
4656         BUG_ON(!view);
4657
4658         list_for_each_entry(vma, &obj->vma_list, obj_link)
4659                 if (vma->vm == &ggtt->base &&
4660                     i915_ggtt_view_equal(&vma->ggtt_view, view))
4661                         return vma;
4662         return NULL;
4663 }
4664
4665 void i915_gem_vma_destroy(struct i915_vma *vma)
4666 {
4667         WARN_ON(vma->node.allocated);
4668
4669         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4670         if (!list_empty(&vma->exec_list))
4671                 return;
4672
4673         if (!vma->is_ggtt)
4674                 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
4675
4676         list_del(&vma->obj_link);
4677
4678         kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4679 }
4680
4681 static void
4682 i915_gem_stop_engines(struct drm_device *dev)
4683 {
4684         struct drm_i915_private *dev_priv = dev->dev_private;
4685         struct intel_engine_cs *engine;
4686
4687         for_each_engine(engine, dev_priv)
4688                 dev_priv->gt.stop_engine(engine);
4689 }
4690
4691 int
4692 i915_gem_suspend(struct drm_device *dev)
4693 {
4694         struct drm_i915_private *dev_priv = dev->dev_private;
4695         int ret = 0;
4696
4697         mutex_lock(&dev->struct_mutex);
4698         ret = i915_gpu_idle(dev);
4699         if (ret)
4700                 goto err;
4701
4702         i915_gem_retire_requests(dev);
4703
4704         i915_gem_stop_engines(dev);
4705         mutex_unlock(&dev->struct_mutex);
4706
4707         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4708         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4709         flush_delayed_work(&dev_priv->mm.idle_work);
4710
4711         /* Assert that we sucessfully flushed all the work and
4712          * reset the GPU back to its idle, low power state.
4713          */
4714         WARN_ON(dev_priv->mm.busy);
4715
4716         return 0;
4717
4718 err:
4719         mutex_unlock(&dev->struct_mutex);
4720         return ret;
4721 }
4722
4723 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
4724 {
4725         struct intel_engine_cs *engine = req->engine;
4726         struct drm_device *dev = engine->dev;
4727         struct drm_i915_private *dev_priv = dev->dev_private;
4728         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4729         int i, ret;
4730
4731         if (!HAS_L3_DPF(dev) || !remap_info)
4732                 return 0;
4733
4734         ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
4735         if (ret)
4736                 return ret;
4737
4738         /*
4739          * Note: We do not worry about the concurrent register cacheline hang
4740          * here because no other code should access these registers other than
4741          * at initialization time.
4742          */
4743         for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
4744                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
4745                 intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));
4746                 intel_ring_emit(engine, remap_info[i]);
4747         }
4748
4749         intel_ring_advance(engine);
4750
4751         return ret;
4752 }
4753
4754 void i915_gem_init_swizzling(struct drm_device *dev)
4755 {
4756         struct drm_i915_private *dev_priv = dev->dev_private;
4757
4758         if (INTEL_INFO(dev)->gen < 5 ||
4759             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4760                 return;
4761
4762         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4763                                  DISP_TILE_SURFACE_SWIZZLING);
4764
4765         if (IS_GEN5(dev))
4766                 return;
4767
4768         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4769         if (IS_GEN6(dev))
4770                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4771         else if (IS_GEN7(dev))
4772                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4773         else if (IS_GEN8(dev))
4774                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4775         else
4776                 BUG();
4777 }
4778
4779 static void init_unused_ring(struct drm_device *dev, u32 base)
4780 {
4781         struct drm_i915_private *dev_priv = dev->dev_private;
4782
4783         I915_WRITE(RING_CTL(base), 0);
4784         I915_WRITE(RING_HEAD(base), 0);
4785         I915_WRITE(RING_TAIL(base), 0);
4786         I915_WRITE(RING_START(base), 0);
4787 }
4788
4789 static void init_unused_rings(struct drm_device *dev)
4790 {
4791         if (IS_I830(dev)) {
4792                 init_unused_ring(dev, PRB1_BASE);
4793                 init_unused_ring(dev, SRB0_BASE);
4794                 init_unused_ring(dev, SRB1_BASE);
4795                 init_unused_ring(dev, SRB2_BASE);
4796                 init_unused_ring(dev, SRB3_BASE);
4797         } else if (IS_GEN2(dev)) {
4798                 init_unused_ring(dev, SRB0_BASE);
4799                 init_unused_ring(dev, SRB1_BASE);
4800         } else if (IS_GEN3(dev)) {
4801                 init_unused_ring(dev, PRB1_BASE);
4802                 init_unused_ring(dev, PRB2_BASE);
4803         }
4804 }
4805
4806 int i915_gem_init_engines(struct drm_device *dev)
4807 {
4808         struct drm_i915_private *dev_priv = dev->dev_private;
4809         int ret;
4810
4811         ret = intel_init_render_ring_buffer(dev);
4812         if (ret)
4813                 return ret;
4814
4815         if (HAS_BSD(dev)) {
4816                 ret = intel_init_bsd_ring_buffer(dev);
4817                 if (ret)
4818                         goto cleanup_render_ring;
4819         }
4820
4821         if (HAS_BLT(dev)) {
4822                 ret = intel_init_blt_ring_buffer(dev);
4823                 if (ret)
4824                         goto cleanup_bsd_ring;
4825         }
4826
4827         if (HAS_VEBOX(dev)) {
4828                 ret = intel_init_vebox_ring_buffer(dev);
4829                 if (ret)
4830                         goto cleanup_blt_ring;
4831         }
4832
4833         if (HAS_BSD2(dev)) {
4834                 ret = intel_init_bsd2_ring_buffer(dev);
4835                 if (ret)
4836                         goto cleanup_vebox_ring;
4837         }
4838
4839         return 0;
4840
4841 cleanup_vebox_ring:
4842         intel_cleanup_engine(&dev_priv->engine[VECS]);
4843 cleanup_blt_ring:
4844         intel_cleanup_engine(&dev_priv->engine[BCS]);
4845 cleanup_bsd_ring:
4846         intel_cleanup_engine(&dev_priv->engine[VCS]);
4847 cleanup_render_ring:
4848         intel_cleanup_engine(&dev_priv->engine[RCS]);
4849
4850         return ret;
4851 }
4852
4853 int
4854 i915_gem_init_hw(struct drm_device *dev)
4855 {
4856         struct drm_i915_private *dev_priv = dev->dev_private;
4857         struct intel_engine_cs *engine;
4858         int ret, j;
4859
4860         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4861                 return -EIO;
4862
4863         /* Double layer security blanket, see i915_gem_init() */
4864         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4865
4866         if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
4867                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4868
4869         if (IS_HASWELL(dev))
4870                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4871                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4872
4873         if (HAS_PCH_NOP(dev)) {
4874                 if (IS_IVYBRIDGE(dev)) {
4875                         u32 temp = I915_READ(GEN7_MSG_CTL);
4876                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4877                         I915_WRITE(GEN7_MSG_CTL, temp);
4878                 } else if (INTEL_INFO(dev)->gen >= 7) {
4879                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4880                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4881                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4882                 }
4883         }
4884
4885         i915_gem_init_swizzling(dev);
4886
4887         /*
4888          * At least 830 can leave some of the unused rings
4889          * "active" (ie. head != tail) after resume which
4890          * will prevent c3 entry. Makes sure all unused rings
4891          * are totally idle.
4892          */
4893         init_unused_rings(dev);
4894
4895         BUG_ON(!dev_priv->kernel_context);
4896
4897         ret = i915_ppgtt_init_hw(dev);
4898         if (ret) {
4899                 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
4900                 goto out;
4901         }
4902
4903         /* Need to do basic initialisation of all rings first: */
4904         for_each_engine(engine, dev_priv) {
4905                 ret = engine->init_hw(engine);
4906                 if (ret)
4907                         goto out;
4908         }
4909
4910         intel_mocs_init_l3cc_table(dev);
4911
4912         /* We can't enable contexts until all firmware is loaded */
4913         if (HAS_GUC_UCODE(dev)) {
4914                 ret = intel_guc_ucode_load(dev);
4915                 if (ret) {
4916                         DRM_ERROR("Failed to initialize GuC, error %d\n", ret);
4917                         ret = -EIO;
4918                         goto out;
4919                 }
4920         }
4921
4922         /*
4923          * Increment the next seqno by 0x100 so we have a visible break
4924          * on re-initialisation
4925          */
4926         ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
4927         if (ret)
4928                 goto out;
4929
4930         /* Now it is safe to go back round and do everything else: */
4931         for_each_engine(engine, dev_priv) {
4932                 struct drm_i915_gem_request *req;
4933
4934                 req = i915_gem_request_alloc(engine, NULL);
4935                 if (IS_ERR(req)) {
4936                         ret = PTR_ERR(req);
4937                         break;
4938                 }
4939
4940                 if (engine->id == RCS) {
4941                         for (j = 0; j < NUM_L3_SLICES(dev); j++) {
4942                                 ret = i915_gem_l3_remap(req, j);
4943                                 if (ret)
4944                                         goto err_request;
4945                         }
4946                 }
4947
4948                 ret = i915_ppgtt_init_ring(req);
4949                 if (ret)
4950                         goto err_request;
4951
4952                 ret = i915_gem_context_enable(req);
4953                 if (ret)
4954                         goto err_request;
4955
4956 err_request:
4957                 i915_add_request_no_flush(req);
4958                 if (ret) {
4959                         DRM_ERROR("Failed to enable %s, error=%d\n",
4960                                   engine->name, ret);
4961                         i915_gem_cleanup_engines(dev);
4962                         break;
4963                 }
4964         }
4965
4966 out:
4967         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4968         return ret;
4969 }
4970
4971 int i915_gem_init(struct drm_device *dev)
4972 {
4973         struct drm_i915_private *dev_priv = dev->dev_private;
4974         int ret;
4975
4976         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4977                         i915.enable_execlists);
4978
4979         mutex_lock(&dev->struct_mutex);
4980
4981         if (!i915.enable_execlists) {
4982                 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
4983                 dev_priv->gt.init_engines = i915_gem_init_engines;
4984                 dev_priv->gt.cleanup_engine = intel_cleanup_engine;
4985                 dev_priv->gt.stop_engine = intel_stop_engine;
4986         } else {
4987                 dev_priv->gt.execbuf_submit = intel_execlists_submission;
4988                 dev_priv->gt.init_engines = intel_logical_rings_init;
4989                 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
4990                 dev_priv->gt.stop_engine = intel_logical_ring_stop;
4991         }
4992
4993         /* This is just a security blanket to placate dragons.
4994          * On some systems, we very sporadically observe that the first TLBs
4995          * used by the CS may be stale, despite us poking the TLB reset. If
4996          * we hold the forcewake during initialisation these problems
4997          * just magically go away.
4998          */
4999         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5000
5001         ret = i915_gem_init_userptr(dev);
5002         if (ret)
5003                 goto out_unlock;
5004
5005         i915_gem_init_ggtt(dev);
5006
5007         ret = i915_gem_context_init(dev);
5008         if (ret)
5009                 goto out_unlock;
5010
5011         ret = dev_priv->gt.init_engines(dev);
5012         if (ret)
5013                 goto out_unlock;
5014
5015         ret = i915_gem_init_hw(dev);
5016         if (ret == -EIO) {
5017                 /* Allow ring initialisation to fail by marking the GPU as
5018                  * wedged. But we only want to do this where the GPU is angry,
5019                  * for all other failure, such as an allocation failure, bail.
5020                  */
5021                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5022                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5023                 ret = 0;
5024         }
5025
5026 out_unlock:
5027         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5028         mutex_unlock(&dev->struct_mutex);
5029
5030         return ret;
5031 }
5032
5033 void
5034 i915_gem_cleanup_engines(struct drm_device *dev)
5035 {
5036         struct drm_i915_private *dev_priv = dev->dev_private;
5037         struct intel_engine_cs *engine;
5038
5039         for_each_engine(engine, dev_priv)
5040                 dev_priv->gt.cleanup_engine(engine);
5041
5042         if (i915.enable_execlists)
5043                 /*
5044                  * Neither the BIOS, ourselves or any other kernel
5045                  * expects the system to be in execlists mode on startup,
5046                  * so we need to reset the GPU back to legacy mode.
5047                  */
5048                 intel_gpu_reset(dev, ALL_ENGINES);
5049 }
5050
5051 static void
5052 init_engine_lists(struct intel_engine_cs *engine)
5053 {
5054         INIT_LIST_HEAD(&engine->active_list);
5055         INIT_LIST_HEAD(&engine->request_list);
5056 }
5057
5058 void
5059 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
5060 {
5061         struct drm_device *dev = dev_priv->dev;
5062
5063         if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
5064             !IS_CHERRYVIEW(dev_priv))
5065                 dev_priv->num_fence_regs = 32;
5066         else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
5067                  IS_I945GM(dev_priv) || IS_G33(dev_priv))
5068                 dev_priv->num_fence_regs = 16;
5069         else
5070                 dev_priv->num_fence_regs = 8;
5071
5072         if (intel_vgpu_active(dev))
5073                 dev_priv->num_fence_regs =
5074                                 I915_READ(vgtif_reg(avail_rs.fence_num));
5075
5076         /* Initialize fence registers to zero */
5077         i915_gem_restore_fences(dev);
5078
5079         i915_gem_detect_bit_6_swizzle(dev);
5080 }
5081
5082 void
5083 i915_gem_load_init(struct drm_device *dev)
5084 {
5085         struct drm_i915_private *dev_priv = dev->dev_private;
5086         int i;
5087
5088         dev_priv->objects =
5089                 kmem_cache_create("i915_gem_object",
5090                                   sizeof(struct drm_i915_gem_object), 0,
5091                                   SLAB_HWCACHE_ALIGN,
5092                                   NULL);
5093         dev_priv->vmas =
5094                 kmem_cache_create("i915_gem_vma",
5095                                   sizeof(struct i915_vma), 0,
5096                                   SLAB_HWCACHE_ALIGN,
5097                                   NULL);
5098         dev_priv->requests =
5099                 kmem_cache_create("i915_gem_request",
5100                                   sizeof(struct drm_i915_gem_request), 0,
5101                                   SLAB_HWCACHE_ALIGN,
5102                                   NULL);
5103
5104         INIT_LIST_HEAD(&dev_priv->vm_list);
5105         INIT_LIST_HEAD(&dev_priv->context_list);
5106         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5107         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5108         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5109         for (i = 0; i < I915_NUM_ENGINES; i++)
5110                 init_engine_lists(&dev_priv->engine[i]);
5111         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5112                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5113         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5114                           i915_gem_retire_work_handler);
5115         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5116                           i915_gem_idle_work_handler);
5117         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5118
5119         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5120
5121         /*
5122          * Set initial sequence number for requests.
5123          * Using this number allows the wraparound to happen early,
5124          * catching any obvious problems.
5125          */
5126         dev_priv->next_seqno = ((u32)~0 - 0x1100);
5127         dev_priv->last_seqno = ((u32)~0 - 0x1101);
5128
5129         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5130
5131         init_waitqueue_head(&dev_priv->pending_flip_queue);
5132
5133         dev_priv->mm.interruptible = true;
5134
5135         mutex_init(&dev_priv->fb_tracking.lock);
5136 }
5137
5138 void i915_gem_load_cleanup(struct drm_device *dev)
5139 {
5140         struct drm_i915_private *dev_priv = to_i915(dev);
5141
5142         kmem_cache_destroy(dev_priv->requests);
5143         kmem_cache_destroy(dev_priv->vmas);
5144         kmem_cache_destroy(dev_priv->objects);
5145 }
5146
5147 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5148 {
5149         struct drm_i915_file_private *file_priv = file->driver_priv;
5150
5151         /* Clean up our request list when the client is going away, so that
5152          * later retire_requests won't dereference our soon-to-be-gone
5153          * file_priv.
5154          */
5155         spin_lock(&file_priv->mm.lock);
5156         while (!list_empty(&file_priv->mm.request_list)) {
5157                 struct drm_i915_gem_request *request;
5158
5159                 request = list_first_entry(&file_priv->mm.request_list,
5160                                            struct drm_i915_gem_request,
5161                                            client_list);
5162                 list_del(&request->client_list);
5163                 request->file_priv = NULL;
5164         }
5165         spin_unlock(&file_priv->mm.lock);
5166
5167         if (!list_empty(&file_priv->rps.link)) {
5168                 spin_lock(&to_i915(dev)->rps.client_lock);
5169                 list_del(&file_priv->rps.link);
5170                 spin_unlock(&to_i915(dev)->rps.client_lock);
5171         }
5172 }
5173
5174 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5175 {
5176         struct drm_i915_file_private *file_priv;
5177         int ret;
5178
5179         DRM_DEBUG_DRIVER("\n");
5180
5181         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5182         if (!file_priv)
5183                 return -ENOMEM;
5184
5185         file->driver_priv = file_priv;
5186         file_priv->dev_priv = dev->dev_private;
5187         file_priv->file = file;
5188         INIT_LIST_HEAD(&file_priv->rps.link);
5189
5190         spin_lock_init(&file_priv->mm.lock);
5191         INIT_LIST_HEAD(&file_priv->mm.request_list);
5192
5193         file_priv->bsd_ring = -1;
5194
5195         ret = i915_gem_context_open(dev, file);
5196         if (ret)
5197                 kfree(file_priv);
5198
5199         return ret;
5200 }
5201
5202 /**
5203  * i915_gem_track_fb - update frontbuffer tracking
5204  * @old: current GEM buffer for the frontbuffer slots
5205  * @new: new GEM buffer for the frontbuffer slots
5206  * @frontbuffer_bits: bitmask of frontbuffer slots
5207  *
5208  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5209  * from @old and setting them in @new. Both @old and @new can be NULL.
5210  */
5211 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5212                        struct drm_i915_gem_object *new,
5213                        unsigned frontbuffer_bits)
5214 {
5215         if (old) {
5216                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5217                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5218                 old->frontbuffer_bits &= ~frontbuffer_bits;
5219         }
5220
5221         if (new) {
5222                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5223                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5224                 new->frontbuffer_bits |= frontbuffer_bits;
5225         }
5226 }
5227
5228 /* All the new VM stuff */
5229 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5230                         struct i915_address_space *vm)
5231 {
5232         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5233         struct i915_vma *vma;
5234
5235         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5236
5237         list_for_each_entry(vma, &o->vma_list, obj_link) {
5238                 if (vma->is_ggtt &&
5239                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5240                         continue;
5241                 if (vma->vm == vm)
5242                         return vma->node.start;
5243         }
5244
5245         WARN(1, "%s vma for this object not found.\n",
5246              i915_is_ggtt(vm) ? "global" : "ppgtt");
5247         return -1;
5248 }
5249
5250 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5251                                   const struct i915_ggtt_view *view)
5252 {
5253         struct drm_i915_private *dev_priv = to_i915(o->base.dev);
5254         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5255         struct i915_vma *vma;
5256
5257         list_for_each_entry(vma, &o->vma_list, obj_link)
5258                 if (vma->vm == &ggtt->base &&
5259                     i915_ggtt_view_equal(&vma->ggtt_view, view))
5260                         return vma->node.start;
5261
5262         WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5263         return -1;
5264 }
5265
5266 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5267                         struct i915_address_space *vm)
5268 {
5269         struct i915_vma *vma;
5270
5271         list_for_each_entry(vma, &o->vma_list, obj_link) {
5272                 if (vma->is_ggtt &&
5273                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5274                         continue;
5275                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5276                         return true;
5277         }
5278
5279         return false;
5280 }
5281
5282 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5283                                   const struct i915_ggtt_view *view)
5284 {
5285         struct drm_i915_private *dev_priv = to_i915(o->base.dev);
5286         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5287         struct i915_vma *vma;
5288
5289         list_for_each_entry(vma, &o->vma_list, obj_link)
5290                 if (vma->vm == &ggtt->base &&
5291                     i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5292                     drm_mm_node_allocated(&vma->node))
5293                         return true;
5294
5295         return false;
5296 }
5297
5298 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5299 {
5300         struct i915_vma *vma;
5301
5302         list_for_each_entry(vma, &o->vma_list, obj_link)
5303                 if (drm_mm_node_allocated(&vma->node))
5304                         return true;
5305
5306         return false;
5307 }
5308
5309 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5310                                 struct i915_address_space *vm)
5311 {
5312         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5313         struct i915_vma *vma;
5314
5315         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5316
5317         BUG_ON(list_empty(&o->vma_list));
5318
5319         list_for_each_entry(vma, &o->vma_list, obj_link) {
5320                 if (vma->is_ggtt &&
5321                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5322                         continue;
5323                 if (vma->vm == vm)
5324                         return vma->node.size;
5325         }
5326         return 0;
5327 }
5328
5329 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5330 {
5331         struct i915_vma *vma;
5332         list_for_each_entry(vma, &obj->vma_list, obj_link)
5333                 if (vma->pin_count > 0)
5334                         return true;
5335
5336         return false;
5337 }
5338
5339 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5340 struct page *
5341 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
5342 {
5343         struct page *page;
5344
5345         /* Only default objects have per-page dirty tracking */
5346         if (WARN_ON((obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE) == 0))
5347                 return NULL;
5348
5349         page = i915_gem_object_get_page(obj, n);
5350         set_page_dirty(page);
5351         return page;
5352 }
5353
5354 /* Allocate a new GEM object and fill it with the supplied data */
5355 struct drm_i915_gem_object *
5356 i915_gem_object_create_from_data(struct drm_device *dev,
5357                                  const void *data, size_t size)
5358 {
5359         struct drm_i915_gem_object *obj;
5360         struct sg_table *sg;
5361         size_t bytes;
5362         int ret;
5363
5364         obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE));
5365         if (IS_ERR_OR_NULL(obj))
5366                 return obj;
5367
5368         ret = i915_gem_object_set_to_cpu_domain(obj, true);
5369         if (ret)
5370                 goto fail;
5371
5372         ret = i915_gem_object_get_pages(obj);
5373         if (ret)
5374                 goto fail;
5375
5376         i915_gem_object_pin_pages(obj);
5377         sg = obj->pages;
5378         bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5379         obj->dirty = 1;         /* Backing store is now out of date */
5380         i915_gem_object_unpin_pages(obj);
5381
5382         if (WARN_ON(bytes != size)) {
5383                 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5384                 ret = -EFAULT;
5385                 goto fail;
5386         }
5387
5388         return obj;
5389
5390 fail:
5391         drm_gem_object_unreference(&obj->base);
5392         return ERR_PTR(ret);
5393 }