drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* WaDisableSDEUnitClockGating:bxt */
  62         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  63                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  64
  65         /*
  66          * FIXME:
  67          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  68          */
  69         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  70                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  71
  72         /*
  73          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  74          * to stay fully on.
  75          */
  76         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  77                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  78                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  79 }
  80
  81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 tmp;
  85
  86         tmp = I915_READ(CLKCFG);
  87
  88         switch (tmp & CLKCFG_FSB_MASK) {
  89         case CLKCFG_FSB_533:
  90                 dev_priv->fsb_freq = 533; /* 133*4 */
  91                 break;
  92         case CLKCFG_FSB_800:
  93                 dev_priv->fsb_freq = 800; /* 200*4 */
  94                 break;
  95         case CLKCFG_FSB_667:
  96                 dev_priv->fsb_freq =  667; /* 167*4 */
  97                 break;
  98         case CLKCFG_FSB_400:
  99                 dev_priv->fsb_freq = 400; /* 100*4 */
 100                 break;
 101         }
 102
 103         switch (tmp & CLKCFG_MEM_MASK) {
 104         case CLKCFG_MEM_533:
 105                 dev_priv->mem_freq = 533;
 106                 break;
 107         case CLKCFG_MEM_667:
 108                 dev_priv->mem_freq = 667;
 109                 break;
 110         case CLKCFG_MEM_800:
 111                 dev_priv->mem_freq = 800;
 112                 break;
 113         }
 114
 115         /* detect pineview DDR3 setting */
 116         tmp = I915_READ(CSHRDDR3CTL);
 117         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 118 }
 119
 120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u16 ddrpll, csipll;
 124
 125         ddrpll = I915_READ16(DDRMPLL1);
 126         csipll = I915_READ16(CSIPLL0);
 127
 128         switch (ddrpll & 0xff) {
 129         case 0xc:
 130                 dev_priv->mem_freq = 800;
 131                 break;
 132         case 0x10:
 133                 dev_priv->mem_freq = 1066;
 134                 break;
 135         case 0x14:
 136                 dev_priv->mem_freq = 1333;
 137                 break;
 138         case 0x18:
 139                 dev_priv->mem_freq = 1600;
 140                 break;
 141         default:
 142                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 143                                  ddrpll & 0xff);
 144                 dev_priv->mem_freq = 0;
 145                 break;
 146         }
 147
 148         dev_priv->ips.r_t = dev_priv->mem_freq;
 149
 150         switch (csipll & 0x3ff) {
 151         case 0x00c:
 152                 dev_priv->fsb_freq = 3200;
 153                 break;
 154         case 0x00e:
 155                 dev_priv->fsb_freq = 3733;
 156                 break;
 157         case 0x010:
 158                 dev_priv->fsb_freq = 4266;
 159                 break;
 160         case 0x012:
 161                 dev_priv->fsb_freq = 4800;
 162                 break;
 163         case 0x014:
 164                 dev_priv->fsb_freq = 5333;
 165                 break;
 166         case 0x016:
 167                 dev_priv->fsb_freq = 5866;
 168                 break;
 169         case 0x018:
 170                 dev_priv->fsb_freq = 6400;
 171                 break;
 172         default:
 173                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 174                                  csipll & 0x3ff);
 175                 dev_priv->fsb_freq = 0;
 176                 break;
 177         }
 178
 179         if (dev_priv->fsb_freq == 3200) {
 180                 dev_priv->ips.c_m = 0;
 181         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 182                 dev_priv->ips.c_m = 1;
 183         } else {
 184                 dev_priv->ips.c_m = 2;
 185         }
 186 }
 187
 188 static const struct cxsr_latency cxsr_latency_table[] = {
 189         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 190         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 191         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 192         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 193         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 194
 195         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 196         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 197         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 198         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 199         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 200
 201         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 202         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 203         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 204         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 205         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 206
 207         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 208         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 209         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 210         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 211         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 212
 213         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 214         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 215         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 216         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 217         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 218
 219         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 220         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 221         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 222         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 223         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 224 };
 225
 226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 227                                                          int is_ddr3,
 228                                                          int fsb,
 229                                                          int mem)
 230 {
 231         const struct cxsr_latency *latency;
 232         int i;
 233
 234         if (fsb == 0 || mem == 0)
 235                 return NULL;
 236
 237         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 238                 latency = &cxsr_latency_table[i];
 239                 if (is_desktop == latency->is_desktop &&
 240                     is_ddr3 == latency->is_ddr3 &&
 241                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 242                         return latency;
 243         }
 244
 245         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 246
 247         return NULL;
 248 }
 249
 250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 251 {
 252         u32 val;
 253
 254         mutex_lock(&dev_priv->rps.hw_lock);
 255
 256         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 257         if (enable)
 258                 val &= ~FORCE_DDR_HIGH_FREQ;
 259         else
 260                 val |= FORCE_DDR_HIGH_FREQ;
 261         val &= ~FORCE_DDR_LOW_FREQ;
 262         val |= FORCE_DDR_FREQ_REQ_ACK;
 263         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 264
 265         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 266                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 267                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 268
 269         mutex_unlock(&dev_priv->rps.hw_lock);
 270 }
 271
 272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 273 {
 274         u32 val;
 275
 276         mutex_lock(&dev_priv->rps.hw_lock);
 277
 278         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 279         if (enable)
 280                 val |= DSP_MAXFIFO_PM5_ENABLE;
 281         else
 282                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 283         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 284
 285         mutex_unlock(&dev_priv->rps.hw_lock);
 286 }
 287
 288 #define FW_WM(value, plane) \
 289         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 290
 291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 292 {
 293         struct drm_device *dev = dev_priv->dev;
 294         u32 val;
 295
 296         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 297                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 298                 POSTING_READ(FW_BLC_SELF_VLV);
 299                 dev_priv->wm.vlv.cxsr = enable;
 300         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 301                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_PINEVIEW(dev)) {
 304                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 305                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 306                 I915_WRITE(DSPFW3, val);
 307                 POSTING_READ(DSPFW3);
 308         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 309                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 310                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 311                 I915_WRITE(FW_BLC_SELF, val);
 312                 POSTING_READ(FW_BLC_SELF);
 313         } else if (IS_I915GM(dev)) {
 314                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 315                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 316                 I915_WRITE(INSTPM, val);
 317                 POSTING_READ(INSTPM);
 318         } else {
 319                 return;
 320         }
 321
 322         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 323                       enable ? "enabled" : "disabled");
 324 }
 325
 326
 327 /*
 328  * Latency for FIFO fetches is dependent on several factors:
 329  *   - memory configuration (speed, channels)
 330  *   - chipset
 331  *   - current MCH state
 332  * It can be fairly high in some situations, so here we assume a fairly
 333  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 334  * set this value too high, the FIFO will fetch frequently to stay full)
 335  * and power consumption (set it too low to save power and we might see
 336  * FIFO underruns and display "flicker").
 337  *
 338  * A value of 5us seems to be a good balance; safe for very low end
 339  * platforms but not overly aggressive on lower latency configs.
 340  */
 341 static const int pessimal_latency_ns = 5000;
 342
 343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 344         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 345
 346 static int vlv_get_fifo_size(struct drm_device *dev,
 347                               enum pipe pipe, int plane)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int sprite0_start, sprite1_start, size;
 351
 352         switch (pipe) {
 353                 uint32_t dsparb, dsparb2, dsparb3;
 354         case PIPE_A:
 355                 dsparb = I915_READ(DSPARB);
 356                 dsparb2 = I915_READ(DSPARB2);
 357                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 358                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 359                 break;
 360         case PIPE_B:
 361                 dsparb = I915_READ(DSPARB);
 362                 dsparb2 = I915_READ(DSPARB2);
 363                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 364                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 365                 break;
 366         case PIPE_C:
 367                 dsparb2 = I915_READ(DSPARB2);
 368                 dsparb3 = I915_READ(DSPARB3);
 369                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 370                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 371                 break;
 372         default:
 373                 return 0;
 374         }
 375
 376         switch (plane) {
 377         case 0:
 378                 size = sprite0_start;
 379                 break;
 380         case 1:
 381                 size = sprite1_start - sprite0_start;
 382                 break;
 383         case 2:
 384                 size = 512 - 1 - sprite1_start;
 385                 break;
 386         default:
 387                 return 0;
 388         }
 389
 390         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 391                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 392                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 393                       size);
 394
 395         return size;
 396 }
 397
 398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t dsparb = I915_READ(DSPARB);
 402         int size;
 403
 404         size = dsparb & 0x7f;
 405         if (plane)
 406                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 407
 408         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 409                       plane ? "B" : "A", size);
 410
 411         return size;
 412 }
 413
 414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         uint32_t dsparb = I915_READ(DSPARB);
 418         int size;
 419
 420         size = dsparb & 0x1ff;
 421         if (plane)
 422                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 423         size >>= 1; /* Convert to cachelines */
 424
 425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 426                       plane ? "B" : "A", size);
 427
 428         return size;
 429 }
 430
 431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         uint32_t dsparb = I915_READ(DSPARB);
 435         int size;
 436
 437         size = dsparb & 0x7f;
 438         size >>= 2; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A",
 442                       size);
 443
 444         return size;
 445 }
 446
 447 /* Pineview has different values for various configs */
 448 static const struct intel_watermark_params pineview_display_wm = {
 449         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 450         .max_wm = PINEVIEW_MAX_WM,
 451         .default_wm = PINEVIEW_DFT_WM,
 452         .guard_size = PINEVIEW_GUARD_WM,
 453         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 454 };
 455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 456         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 457         .max_wm = PINEVIEW_MAX_WM,
 458         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 459         .guard_size = PINEVIEW_GUARD_WM,
 460         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 461 };
 462 static const struct intel_watermark_params pineview_cursor_wm = {
 463         .fifo_size = PINEVIEW_CURSOR_FIFO,
 464         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 465         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 466         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 467         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 468 };
 469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 470         .fifo_size = PINEVIEW_CURSOR_FIFO,
 471         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 472         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 473         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 474         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 475 };
 476 static const struct intel_watermark_params g4x_wm_info = {
 477         .fifo_size = G4X_FIFO_SIZE,
 478         .max_wm = G4X_MAX_WM,
 479         .default_wm = G4X_MAX_WM,
 480         .guard_size = 2,
 481         .cacheline_size = G4X_FIFO_LINE_SIZE,
 482 };
 483 static const struct intel_watermark_params g4x_cursor_wm_info = {
 484         .fifo_size = I965_CURSOR_FIFO,
 485         .max_wm = I965_CURSOR_MAX_WM,
 486         .default_wm = I965_CURSOR_DFT_WM,
 487         .guard_size = 2,
 488         .cacheline_size = G4X_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params i965_cursor_wm_info = {
 491         .fifo_size = I965_CURSOR_FIFO,
 492         .max_wm = I965_CURSOR_MAX_WM,
 493         .default_wm = I965_CURSOR_DFT_WM,
 494         .guard_size = 2,
 495         .cacheline_size = I915_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params i945_wm_info = {
 498         .fifo_size = I945_FIFO_SIZE,
 499         .max_wm = I915_MAX_WM,
 500         .default_wm = 1,
 501         .guard_size = 2,
 502         .cacheline_size = I915_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params i915_wm_info = {
 505         .fifo_size = I915_FIFO_SIZE,
 506         .max_wm = I915_MAX_WM,
 507         .default_wm = 1,
 508         .guard_size = 2,
 509         .cacheline_size = I915_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params i830_a_wm_info = {
 512         .fifo_size = I855GM_FIFO_SIZE,
 513         .max_wm = I915_MAX_WM,
 514         .default_wm = 1,
 515         .guard_size = 2,
 516         .cacheline_size = I830_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params i830_bc_wm_info = {
 519         .fifo_size = I855GM_FIFO_SIZE,
 520         .max_wm = I915_MAX_WM/2,
 521         .default_wm = 1,
 522         .guard_size = 2,
 523         .cacheline_size = I830_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i845_wm_info = {
 526         .fifo_size = I830_FIFO_SIZE,
 527         .max_wm = I915_MAX_WM,
 528         .default_wm = 1,
 529         .guard_size = 2,
 530         .cacheline_size = I830_FIFO_LINE_SIZE,
 531 };
 532
 533 /**
 534  * intel_calculate_wm - calculate watermark level
 535  * @clock_in_khz: pixel clock
 536  * @wm: chip FIFO params
 537  * @cpp: bytes per pixel
 538  * @latency_ns: memory latency for the platform
 539  *
 540  * Calculate the watermark level (the level at which the display plane will
 541  * start fetching from memory again).  Each chip has a different display
 542  * FIFO size and allocation, so the caller needs to figure that out and pass
 543  * in the correct intel_watermark_params structure.
 544  *
 545  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 546  * on the pixel size.  When it reaches the watermark level, it'll start
 547  * fetching FIFO line sized based chunks from memory until the FIFO fills
 548  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 549  * will occur, and a display engine hang could result.
 550  */
 551 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 552                                         const struct intel_watermark_params *wm,
 553                                         int fifo_size, int cpp,
 554                                         unsigned long latency_ns)
 555 {
 556         long entries_required, wm_size;
 557
 558         /*
 559          * Note: we need to make sure we don't overflow for various clock &
 560          * latency values.
 561          * clocks go from a few thousand to several hundred thousand.
 562          * latency is usually a few thousand
 563          */
 564         entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
 565                 1000;
 566         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 567
 568         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 569
 570         wm_size = fifo_size - (entries_required + wm->guard_size);
 571
 572         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 573
 574         /* Don't promote wm_size to unsigned... */
 575         if (wm_size > (long)wm->max_wm)
 576                 wm_size = wm->max_wm;
 577         if (wm_size <= 0)
 578                 wm_size = wm->default_wm;
 579
 580         /*
 581          * Bspec seems to indicate that the value shouldn't be lower than
 582          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 583          * Lets go for 8 which is the burst size since certain platforms
 584          * already use a hardcoded 8 (which is what the spec says should be
 585          * done).
 586          */
 587         if (wm_size <= 8)
 588                 wm_size = 8;
 589
 590         return wm_size;
 591 }
 592
 593 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 594 {
 595         struct drm_crtc *crtc, *enabled = NULL;
 596
 597         for_each_crtc(dev, crtc) {
 598                 if (intel_crtc_active(crtc)) {
 599                         if (enabled)
 600                                 return NULL;
 601                         enabled = crtc;
 602                 }
 603         }
 604
 605         return enabled;
 606 }
 607
 608 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 609 {
 610         struct drm_device *dev = unused_crtc->dev;
 611         struct drm_i915_private *dev_priv = dev->dev_private;
 612         struct drm_crtc *crtc;
 613         const struct cxsr_latency *latency;
 614         u32 reg;
 615         unsigned long wm;
 616
 617         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 618                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 619         if (!latency) {
 620                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 621                 intel_set_memory_cxsr(dev_priv, false);
 622                 return;
 623         }
 624
 625         crtc = single_enabled_crtc(dev);
 626         if (crtc) {
 627                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 628                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 629                 int clock = adjusted_mode->crtc_clock;
 630
 631                 /* Display SR */
 632                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 633                                         pineview_display_wm.fifo_size,
 634                                         cpp, latency->display_sr);
 635                 reg = I915_READ(DSPFW1);
 636                 reg &= ~DSPFW_SR_MASK;
 637                 reg |= FW_WM(wm, SR);
 638                 I915_WRITE(DSPFW1, reg);
 639                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 640
 641                 /* cursor SR */
 642                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 643                                         pineview_display_wm.fifo_size,
 644                                         cpp, latency->cursor_sr);
 645                 reg = I915_READ(DSPFW3);
 646                 reg &= ~DSPFW_CURSOR_SR_MASK;
 647                 reg |= FW_WM(wm, CURSOR_SR);
 648                 I915_WRITE(DSPFW3, reg);
 649
 650                 /* Display HPLL off SR */
 651                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 652                                         pineview_display_hplloff_wm.fifo_size,
 653                                         cpp, latency->display_hpll_disable);
 654                 reg = I915_READ(DSPFW3);
 655                 reg &= ~DSPFW_HPLL_SR_MASK;
 656                 reg |= FW_WM(wm, HPLL_SR);
 657                 I915_WRITE(DSPFW3, reg);
 658
 659                 /* cursor HPLL off SR */
 660                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 661                                         pineview_display_hplloff_wm.fifo_size,
 662                                         cpp, latency->cursor_hpll_disable);
 663                 reg = I915_READ(DSPFW3);
 664                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 665                 reg |= FW_WM(wm, HPLL_CURSOR);
 666                 I915_WRITE(DSPFW3, reg);
 667                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 668
 669                 intel_set_memory_cxsr(dev_priv, true);
 670         } else {
 671                 intel_set_memory_cxsr(dev_priv, false);
 672         }
 673 }
 674
 675 static bool g4x_compute_wm0(struct drm_device *dev,
 676                             int plane,
 677                             const struct intel_watermark_params *display,
 678                             int display_latency_ns,
 679                             const struct intel_watermark_params *cursor,
 680                             int cursor_latency_ns,
 681                             int *plane_wm,
 682                             int *cursor_wm)
 683 {
 684         struct drm_crtc *crtc;
 685         const struct drm_display_mode *adjusted_mode;
 686         int htotal, hdisplay, clock, cpp;
 687         int line_time_us, line_count;
 688         int entries, tlb_miss;
 689
 690         crtc = intel_get_crtc_for_plane(dev, plane);
 691         if (!intel_crtc_active(crtc)) {
 692                 *cursor_wm = cursor->guard_size;
 693                 *plane_wm = display->guard_size;
 694                 return false;
 695         }
 696
 697         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 698         clock = adjusted_mode->crtc_clock;
 699         htotal = adjusted_mode->crtc_htotal;
 700         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 701         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 702
 703         /* Use the small buffer method to calculate plane watermark */
 704         entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
 705         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 706         if (tlb_miss > 0)
 707                 entries += tlb_miss;
 708         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 709         *plane_wm = entries + display->guard_size;
 710         if (*plane_wm > (int)display->max_wm)
 711                 *plane_wm = display->max_wm;
 712
 713         /* Use the large buffer method to calculate cursor watermark */
 714         line_time_us = max(htotal * 1000 / clock, 1);
 715         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 716         entries = line_count * crtc->cursor->state->crtc_w * cpp;
 717         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 718         if (tlb_miss > 0)
 719                 entries += tlb_miss;
 720         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 721         *cursor_wm = entries + cursor->guard_size;
 722         if (*cursor_wm > (int)cursor->max_wm)
 723                 *cursor_wm = (int)cursor->max_wm;
 724
 725         return true;
 726 }
 727
 728 /*
 729  * Check the wm result.
 730  *
 731  * If any calculated watermark values is larger than the maximum value that
 732  * can be programmed into the associated watermark register, that watermark
 733  * must be disabled.
 734  */
 735 static bool g4x_check_srwm(struct drm_device *dev,
 736                            int display_wm, int cursor_wm,
 737                            const struct intel_watermark_params *display,
 738                            const struct intel_watermark_params *cursor)
 739 {
 740         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 741                       display_wm, cursor_wm);
 742
 743         if (display_wm > display->max_wm) {
 744                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 745                               display_wm, display->max_wm);
 746                 return false;
 747         }
 748
 749         if (cursor_wm > cursor->max_wm) {
 750                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 751                               cursor_wm, cursor->max_wm);
 752                 return false;
 753         }
 754
 755         if (!(display_wm || cursor_wm)) {
 756                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 757                 return false;
 758         }
 759
 760         return true;
 761 }
 762
 763 static bool g4x_compute_srwm(struct drm_device *dev,
 764                              int plane,
 765                              int latency_ns,
 766                              const struct intel_watermark_params *display,
 767                              const struct intel_watermark_params *cursor,
 768                              int *display_wm, int *cursor_wm)
 769 {
 770         struct drm_crtc *crtc;
 771         const struct drm_display_mode *adjusted_mode;
 772         int hdisplay, htotal, cpp, clock;
 773         unsigned long line_time_us;
 774         int line_count, line_size;
 775         int small, large;
 776         int entries;
 777
 778         if (!latency_ns) {
 779                 *display_wm = *cursor_wm = 0;
 780                 return false;
 781         }
 782
 783         crtc = intel_get_crtc_for_plane(dev, plane);
 784         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 785         clock = adjusted_mode->crtc_clock;
 786         htotal = adjusted_mode->crtc_htotal;
 787         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 788         cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
 789
 790         line_time_us = max(htotal * 1000 / clock, 1);
 791         line_count = (latency_ns / line_time_us + 1000) / 1000;
 792         line_size = hdisplay * cpp;
 793
 794         /* Use the minimum of the small and large buffer method for primary */
 795         small = ((clock * cpp / 1000) * latency_ns) / 1000;
 796         large = line_count * line_size;
 797
 798         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 799         *display_wm = entries + display->guard_size;
 800
 801         /* calculate the self-refresh watermark for display cursor */
 802         entries = line_count * cpp * crtc->cursor->state->crtc_w;
 803         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 804         *cursor_wm = entries + cursor->guard_size;
 805
 806         return g4x_check_srwm(dev,
 807                               *display_wm, *cursor_wm,
 808                               display, cursor);
 809 }
 810
 811 #define FW_WM_VLV(value, plane) \
 812         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 813
 814 static void vlv_write_wm_values(struct intel_crtc *crtc,
 815                                 const struct vlv_wm_values *wm)
 816 {
 817         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 818         enum pipe pipe = crtc->pipe;
 819
 820         I915_WRITE(VLV_DDL(pipe),
 821                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 822                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 823                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 824                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 825
 826         I915_WRITE(DSPFW1,
 827                    FW_WM(wm->sr.plane, SR) |
 828                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 829                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 830                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 831         I915_WRITE(DSPFW2,
 832                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 833                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 834                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 835         I915_WRITE(DSPFW3,
 836                    FW_WM(wm->sr.cursor, CURSOR_SR));
 837
 838         if (IS_CHERRYVIEW(dev_priv)) {
 839                 I915_WRITE(DSPFW7_CHV,
 840                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 841                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 842                 I915_WRITE(DSPFW8_CHV,
 843                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 844                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 845                 I915_WRITE(DSPFW9_CHV,
 846                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 847                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 848                 I915_WRITE(DSPHOWM,
 849                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 850                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 851                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 852                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 853                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 854                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 855                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 856                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 857                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 858                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 859         } else {
 860                 I915_WRITE(DSPFW7,
 861                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 862                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 863                 I915_WRITE(DSPHOWM,
 864                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 865                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 866                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 867                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 868                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 869                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 870                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 871         }
 872
 873         /* zero (unused) WM1 watermarks */
 874         I915_WRITE(DSPFW4, 0);
 875         I915_WRITE(DSPFW5, 0);
 876         I915_WRITE(DSPFW6, 0);
 877         I915_WRITE(DSPHOWM1, 0);
 878
 879         POSTING_READ(DSPFW1);
 880 }
 881
 882 #undef FW_WM_VLV
 883
 884 enum vlv_wm_level {
 885         VLV_WM_LEVEL_PM2,
 886         VLV_WM_LEVEL_PM5,
 887         VLV_WM_LEVEL_DDR_DVFS,
 888 };
 889
 890 /* latency must be in 0.1us units. */
 891 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 892                                    unsigned int pipe_htotal,
 893                                    unsigned int horiz_pixels,
 894                                    unsigned int cpp,
 895                                    unsigned int latency)
 896 {
 897         unsigned int ret;
 898
 899         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 900         ret = (ret + 1) * horiz_pixels * cpp;
 901         ret = DIV_ROUND_UP(ret, 64);
 902
 903         return ret;
 904 }
 905
 906 static void vlv_setup_wm_latency(struct drm_device *dev)
 907 {
 908         struct drm_i915_private *dev_priv = dev->dev_private;
 909
 910         /* all latencies in usec */
 911         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 912
 913         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 914
 915         if (IS_CHERRYVIEW(dev_priv)) {
 916                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 917                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 918
 919                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 920         }
 921 }
 922
 923 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 924                                      struct intel_crtc *crtc,
 925                                      const struct intel_plane_state *state,
 926                                      int level)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 929         int clock, htotal, cpp, width, wm;
 930
 931         if (dev_priv->wm.pri_latency[level] == 0)
 932                 return USHRT_MAX;
 933
 934         if (!state->visible)
 935                 return 0;
 936
 937         cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 938         clock = crtc->config->base.adjusted_mode.crtc_clock;
 939         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 940         width = crtc->config->pipe_src_w;
 941         if (WARN_ON(htotal == 0))
 942                 htotal = 1;
 943
 944         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 945                 /*
 946                  * FIXME the formula gives values that are
 947                  * too big for the cursor FIFO, and hence we
 948                  * would never be able to use cursors. For
 949                  * now just hardcode the watermark.
 950                  */
 951                 wm = 63;
 952         } else {
 953                 wm = vlv_wm_method2(clock, htotal, width, cpp,
 954                                     dev_priv->wm.pri_latency[level] * 10);
 955         }
 956
 957         return min_t(int, wm, USHRT_MAX);
 958 }
 959
 960 static void vlv_compute_fifo(struct intel_crtc *crtc)
 961 {
 962         struct drm_device *dev = crtc->base.dev;
 963         struct vlv_wm_state *wm_state = &crtc->wm_state;
 964         struct intel_plane *plane;
 965         unsigned int total_rate = 0;
 966         const int fifo_size = 512 - 1;
 967         int fifo_extra, fifo_left = fifo_size;
 968
 969         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 970                 struct intel_plane_state *state =
 971                         to_intel_plane_state(plane->base.state);
 972
 973                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 974                         continue;
 975
 976                 if (state->visible) {
 977                         wm_state->num_active_planes++;
 978                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 979                 }
 980         }
 981
 982         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 983                 struct intel_plane_state *state =
 984                         to_intel_plane_state(plane->base.state);
 985                 unsigned int rate;
 986
 987                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 988                         plane->wm.fifo_size = 63;
 989                         continue;
 990                 }
 991
 992                 if (!state->visible) {
 993                         plane->wm.fifo_size = 0;
 994                         continue;
 995                 }
 996
 997                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 998                 plane->wm.fifo_size = fifo_size * rate / total_rate;
 999                 fifo_left -= plane->wm.fifo_size;
1000         }
1001
1002         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1003
1004         /* spread the remainder evenly */
1005         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006                 int plane_extra;
1007
1008                 if (fifo_left == 0)
1009                         break;
1010
1011                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1012                         continue;
1013
1014                 /* give it all to the first plane if none are active */
1015                 if (plane->wm.fifo_size == 0 &&
1016                     wm_state->num_active_planes)
1017                         continue;
1018
1019                 plane_extra = min(fifo_extra, fifo_left);
1020                 plane->wm.fifo_size += plane_extra;
1021                 fifo_left -= plane_extra;
1022         }
1023
1024         WARN_ON(fifo_left != 0);
1025 }
1026
1027 static void vlv_invert_wms(struct intel_crtc *crtc)
1028 {
1029         struct vlv_wm_state *wm_state = &crtc->wm_state;
1030         int level;
1031
1032         for (level = 0; level < wm_state->num_levels; level++) {
1033                 struct drm_device *dev = crtc->base.dev;
1034                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1035                 struct intel_plane *plane;
1036
1037                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1038                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1039
1040                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1041                         switch (plane->base.type) {
1042                                 int sprite;
1043                         case DRM_PLANE_TYPE_CURSOR:
1044                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1045                                         wm_state->wm[level].cursor;
1046                                 break;
1047                         case DRM_PLANE_TYPE_PRIMARY:
1048                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1049                                         wm_state->wm[level].primary;
1050                                 break;
1051                         case DRM_PLANE_TYPE_OVERLAY:
1052                                 sprite = plane->plane;
1053                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1054                                         wm_state->wm[level].sprite[sprite];
1055                                 break;
1056                         }
1057                 }
1058         }
1059 }
1060
1061 static void vlv_compute_wm(struct intel_crtc *crtc)
1062 {
1063         struct drm_device *dev = crtc->base.dev;
1064         struct vlv_wm_state *wm_state = &crtc->wm_state;
1065         struct intel_plane *plane;
1066         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1067         int level;
1068
1069         memset(wm_state, 0, sizeof(*wm_state));
1070
1071         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1072         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1073
1074         wm_state->num_active_planes = 0;
1075
1076         vlv_compute_fifo(crtc);
1077
1078         if (wm_state->num_active_planes != 1)
1079                 wm_state->cxsr = false;
1080
1081         if (wm_state->cxsr) {
1082                 for (level = 0; level < wm_state->num_levels; level++) {
1083                         wm_state->sr[level].plane = sr_fifo_size;
1084                         wm_state->sr[level].cursor = 63;
1085                 }
1086         }
1087
1088         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1089                 struct intel_plane_state *state =
1090                         to_intel_plane_state(plane->base.state);
1091
1092                 if (!state->visible)
1093                         continue;
1094
1095                 /* normal watermarks */
1096                 for (level = 0; level < wm_state->num_levels; level++) {
1097                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1098                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1099
1100                         /* hack */
1101                         if (WARN_ON(level == 0 && wm > max_wm))
1102                                 wm = max_wm;
1103
1104                         if (wm > plane->wm.fifo_size)
1105                                 break;
1106
1107                         switch (plane->base.type) {
1108                                 int sprite;
1109                         case DRM_PLANE_TYPE_CURSOR:
1110                                 wm_state->wm[level].cursor = wm;
1111                                 break;
1112                         case DRM_PLANE_TYPE_PRIMARY:
1113                                 wm_state->wm[level].primary = wm;
1114                                 break;
1115                         case DRM_PLANE_TYPE_OVERLAY:
1116                                 sprite = plane->plane;
1117                                 wm_state->wm[level].sprite[sprite] = wm;
1118                                 break;
1119                         }
1120                 }
1121
1122                 wm_state->num_levels = level;
1123
1124                 if (!wm_state->cxsr)
1125                         continue;
1126
1127                 /* maxfifo watermarks */
1128                 switch (plane->base.type) {
1129                         int sprite, level;
1130                 case DRM_PLANE_TYPE_CURSOR:
1131                         for (level = 0; level < wm_state->num_levels; level++)
1132                                 wm_state->sr[level].cursor =
1133                                         wm_state->wm[level].cursor;
1134                         break;
1135                 case DRM_PLANE_TYPE_PRIMARY:
1136                         for (level = 0; level < wm_state->num_levels; level++)
1137                                 wm_state->sr[level].plane =
1138                                         min(wm_state->sr[level].plane,
1139                                             wm_state->wm[level].primary);
1140                         break;
1141                 case DRM_PLANE_TYPE_OVERLAY:
1142                         sprite = plane->plane;
1143                         for (level = 0; level < wm_state->num_levels; level++)
1144                                 wm_state->sr[level].plane =
1145                                         min(wm_state->sr[level].plane,
1146                                             wm_state->wm[level].sprite[sprite]);
1147                         break;
1148                 }
1149         }
1150
1151         /* clear any (partially) filled invalid levels */
1152         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1153                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1154                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1155         }
1156
1157         vlv_invert_wms(crtc);
1158 }
1159
1160 #define VLV_FIFO(plane, value) \
1161         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1162
1163 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1164 {
1165         struct drm_device *dev = crtc->base.dev;
1166         struct drm_i915_private *dev_priv = to_i915(dev);
1167         struct intel_plane *plane;
1168         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1169
1170         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1171                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1172                         WARN_ON(plane->wm.fifo_size != 63);
1173                         continue;
1174                 }
1175
1176                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1177                         sprite0_start = plane->wm.fifo_size;
1178                 else if (plane->plane == 0)
1179                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1180                 else
1181                         fifo_size = sprite1_start + plane->wm.fifo_size;
1182         }
1183
1184         WARN_ON(fifo_size != 512 - 1);
1185
1186         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1187                       pipe_name(crtc->pipe), sprite0_start,
1188                       sprite1_start, fifo_size);
1189
1190         switch (crtc->pipe) {
1191                 uint32_t dsparb, dsparb2, dsparb3;
1192         case PIPE_A:
1193                 dsparb = I915_READ(DSPARB);
1194                 dsparb2 = I915_READ(DSPARB2);
1195
1196                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1197                             VLV_FIFO(SPRITEB, 0xff));
1198                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1199                            VLV_FIFO(SPRITEB, sprite1_start));
1200
1201                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1202                              VLV_FIFO(SPRITEB_HI, 0x1));
1203                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1204                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1205
1206                 I915_WRITE(DSPARB, dsparb);
1207                 I915_WRITE(DSPARB2, dsparb2);
1208                 break;
1209         case PIPE_B:
1210                 dsparb = I915_READ(DSPARB);
1211                 dsparb2 = I915_READ(DSPARB2);
1212
1213                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1214                             VLV_FIFO(SPRITED, 0xff));
1215                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1216                            VLV_FIFO(SPRITED, sprite1_start));
1217
1218                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1219                              VLV_FIFO(SPRITED_HI, 0xff));
1220                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1221                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1222
1223                 I915_WRITE(DSPARB, dsparb);
1224                 I915_WRITE(DSPARB2, dsparb2);
1225                 break;
1226         case PIPE_C:
1227                 dsparb3 = I915_READ(DSPARB3);
1228                 dsparb2 = I915_READ(DSPARB2);
1229
1230                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1231                              VLV_FIFO(SPRITEF, 0xff));
1232                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1233                             VLV_FIFO(SPRITEF, sprite1_start));
1234
1235                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1236                              VLV_FIFO(SPRITEF_HI, 0xff));
1237                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1238                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1239
1240                 I915_WRITE(DSPARB3, dsparb3);
1241                 I915_WRITE(DSPARB2, dsparb2);
1242                 break;
1243         default:
1244                 break;
1245         }
1246 }
1247
1248 #undef VLV_FIFO
1249
1250 static void vlv_merge_wm(struct drm_device *dev,
1251                          struct vlv_wm_values *wm)
1252 {
1253         struct intel_crtc *crtc;
1254         int num_active_crtcs = 0;
1255
1256         wm->level = to_i915(dev)->wm.max_level;
1257         wm->cxsr = true;
1258
1259         for_each_intel_crtc(dev, crtc) {
1260                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1261
1262                 if (!crtc->active)
1263                         continue;
1264
1265                 if (!wm_state->cxsr)
1266                         wm->cxsr = false;
1267
1268                 num_active_crtcs++;
1269                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1270         }
1271
1272         if (num_active_crtcs != 1)
1273                 wm->cxsr = false;
1274
1275         if (num_active_crtcs > 1)
1276                 wm->level = VLV_WM_LEVEL_PM2;
1277
1278         for_each_intel_crtc(dev, crtc) {
1279                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1280                 enum pipe pipe = crtc->pipe;
1281
1282                 if (!crtc->active)
1283                         continue;
1284
1285                 wm->pipe[pipe] = wm_state->wm[wm->level];
1286                 if (wm->cxsr)
1287                         wm->sr = wm_state->sr[wm->level];
1288
1289                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1290                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1291                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1292                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1293         }
1294 }
1295
1296 static void vlv_update_wm(struct drm_crtc *crtc)
1297 {
1298         struct drm_device *dev = crtc->dev;
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1301         enum pipe pipe = intel_crtc->pipe;
1302         struct vlv_wm_values wm = {};
1303
1304         vlv_compute_wm(intel_crtc);
1305         vlv_merge_wm(dev, &wm);
1306
1307         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1308                 /* FIXME should be part of crtc atomic commit */
1309                 vlv_pipe_set_fifo_size(intel_crtc);
1310                 return;
1311         }
1312
1313         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1314             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1315                 chv_set_memory_dvfs(dev_priv, false);
1316
1317         if (wm.level < VLV_WM_LEVEL_PM5 &&
1318             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1319                 chv_set_memory_pm5(dev_priv, false);
1320
1321         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1322                 intel_set_memory_cxsr(dev_priv, false);
1323
1324         /* FIXME should be part of crtc atomic commit */
1325         vlv_pipe_set_fifo_size(intel_crtc);
1326
1327         vlv_write_wm_values(intel_crtc, &wm);
1328
1329         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1330                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1331                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1332                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1333                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1334
1335         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1336                 intel_set_memory_cxsr(dev_priv, true);
1337
1338         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1339             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1340                 chv_set_memory_pm5(dev_priv, true);
1341
1342         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1343             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1344                 chv_set_memory_dvfs(dev_priv, true);
1345
1346         dev_priv->wm.vlv = wm;
1347 }
1348
1349 #define single_plane_enabled(mask) is_power_of_2(mask)
1350
1351 static void g4x_update_wm(struct drm_crtc *crtc)
1352 {
1353         struct drm_device *dev = crtc->dev;
1354         static const int sr_latency_ns = 12000;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357         int plane_sr, cursor_sr;
1358         unsigned int enabled = 0;
1359         bool cxsr_enabled;
1360
1361         if (g4x_compute_wm0(dev, PIPE_A,
1362                             &g4x_wm_info, pessimal_latency_ns,
1363                             &g4x_cursor_wm_info, pessimal_latency_ns,
1364                             &planea_wm, &cursora_wm))
1365                 enabled |= 1 << PIPE_A;
1366
1367         if (g4x_compute_wm0(dev, PIPE_B,
1368                             &g4x_wm_info, pessimal_latency_ns,
1369                             &g4x_cursor_wm_info, pessimal_latency_ns,
1370                             &planeb_wm, &cursorb_wm))
1371                 enabled |= 1 << PIPE_B;
1372
1373         if (single_plane_enabled(enabled) &&
1374             g4x_compute_srwm(dev, ffs(enabled) - 1,
1375                              sr_latency_ns,
1376                              &g4x_wm_info,
1377                              &g4x_cursor_wm_info,
1378                              &plane_sr, &cursor_sr)) {
1379                 cxsr_enabled = true;
1380         } else {
1381                 cxsr_enabled = false;
1382                 intel_set_memory_cxsr(dev_priv, false);
1383                 plane_sr = cursor_sr = 0;
1384         }
1385
1386         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1387                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1388                       planea_wm, cursora_wm,
1389                       planeb_wm, cursorb_wm,
1390                       plane_sr, cursor_sr);
1391
1392         I915_WRITE(DSPFW1,
1393                    FW_WM(plane_sr, SR) |
1394                    FW_WM(cursorb_wm, CURSORB) |
1395                    FW_WM(planeb_wm, PLANEB) |
1396                    FW_WM(planea_wm, PLANEA));
1397         I915_WRITE(DSPFW2,
1398                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1399                    FW_WM(cursora_wm, CURSORA));
1400         /* HPLL off in SR has some issues on G4x... disable it */
1401         I915_WRITE(DSPFW3,
1402                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1403                    FW_WM(cursor_sr, CURSOR_SR));
1404
1405         if (cxsr_enabled)
1406                 intel_set_memory_cxsr(dev_priv, true);
1407 }
1408
1409 static void i965_update_wm(struct drm_crtc *unused_crtc)
1410 {
1411         struct drm_device *dev = unused_crtc->dev;
1412         struct drm_i915_private *dev_priv = dev->dev_private;
1413         struct drm_crtc *crtc;
1414         int srwm = 1;
1415         int cursor_sr = 16;
1416         bool cxsr_enabled;
1417
1418         /* Calc sr entries for one plane configs */
1419         crtc = single_enabled_crtc(dev);
1420         if (crtc) {
1421                 /* self-refresh has much higher latency */
1422                 static const int sr_latency_ns = 12000;
1423                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1424                 int clock = adjusted_mode->crtc_clock;
1425                 int htotal = adjusted_mode->crtc_htotal;
1426                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1427                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1428                 unsigned long line_time_us;
1429                 int entries;
1430
1431                 line_time_us = max(htotal * 1000 / clock, 1);
1432
1433                 /* Use ns/us then divide to preserve precision */
1434                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1435                         cpp * hdisplay;
1436                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1437                 srwm = I965_FIFO_SIZE - entries;
1438                 if (srwm < 0)
1439                         srwm = 1;
1440                 srwm &= 0x1ff;
1441                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1442                               entries, srwm);
1443
1444                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1445                         cpp * crtc->cursor->state->crtc_w;
1446                 entries = DIV_ROUND_UP(entries,
1447                                           i965_cursor_wm_info.cacheline_size);
1448                 cursor_sr = i965_cursor_wm_info.fifo_size -
1449                         (entries + i965_cursor_wm_info.guard_size);
1450
1451                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1452                         cursor_sr = i965_cursor_wm_info.max_wm;
1453
1454                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1455                               "cursor %d\n", srwm, cursor_sr);
1456
1457                 cxsr_enabled = true;
1458         } else {
1459                 cxsr_enabled = false;
1460                 /* Turn off self refresh if both pipes are enabled */
1461                 intel_set_memory_cxsr(dev_priv, false);
1462         }
1463
1464         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1465                       srwm);
1466
1467         /* 965 has limitations... */
1468         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1469                    FW_WM(8, CURSORB) |
1470                    FW_WM(8, PLANEB) |
1471                    FW_WM(8, PLANEA));
1472         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1473                    FW_WM(8, PLANEC_OLD));
1474         /* update cursor SR watermark */
1475         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1476
1477         if (cxsr_enabled)
1478                 intel_set_memory_cxsr(dev_priv, true);
1479 }
1480
1481 #undef FW_WM
1482
1483 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1484 {
1485         struct drm_device *dev = unused_crtc->dev;
1486         struct drm_i915_private *dev_priv = dev->dev_private;
1487         const struct intel_watermark_params *wm_info;
1488         uint32_t fwater_lo;
1489         uint32_t fwater_hi;
1490         int cwm, srwm = 1;
1491         int fifo_size;
1492         int planea_wm, planeb_wm;
1493         struct drm_crtc *crtc, *enabled = NULL;
1494
1495         if (IS_I945GM(dev))
1496                 wm_info = &i945_wm_info;
1497         else if (!IS_GEN2(dev))
1498                 wm_info = &i915_wm_info;
1499         else
1500                 wm_info = &i830_a_wm_info;
1501
1502         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1503         crtc = intel_get_crtc_for_plane(dev, 0);
1504         if (intel_crtc_active(crtc)) {
1505                 const struct drm_display_mode *adjusted_mode;
1506                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1507                 if (IS_GEN2(dev))
1508                         cpp = 4;
1509
1510                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1511                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1512                                                wm_info, fifo_size, cpp,
1513                                                pessimal_latency_ns);
1514                 enabled = crtc;
1515         } else {
1516                 planea_wm = fifo_size - wm_info->guard_size;
1517                 if (planea_wm > (long)wm_info->max_wm)
1518                         planea_wm = wm_info->max_wm;
1519         }
1520
1521         if (IS_GEN2(dev))
1522                 wm_info = &i830_bc_wm_info;
1523
1524         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1525         crtc = intel_get_crtc_for_plane(dev, 1);
1526         if (intel_crtc_active(crtc)) {
1527                 const struct drm_display_mode *adjusted_mode;
1528                 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
1529                 if (IS_GEN2(dev))
1530                         cpp = 4;
1531
1532                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1533                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1534                                                wm_info, fifo_size, cpp,
1535                                                pessimal_latency_ns);
1536                 if (enabled == NULL)
1537                         enabled = crtc;
1538                 else
1539                         enabled = NULL;
1540         } else {
1541                 planeb_wm = fifo_size - wm_info->guard_size;
1542                 if (planeb_wm > (long)wm_info->max_wm)
1543                         planeb_wm = wm_info->max_wm;
1544         }
1545
1546         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1547
1548         if (IS_I915GM(dev) && enabled) {
1549                 struct drm_i915_gem_object *obj;
1550
1551                 obj = intel_fb_obj(enabled->primary->state->fb);
1552
1553                 /* self-refresh seems busted with untiled */
1554                 if (obj->tiling_mode == I915_TILING_NONE)
1555                         enabled = NULL;
1556         }
1557
1558         /*
1559          * Overlay gets an aggressive default since video jitter is bad.
1560          */
1561         cwm = 2;
1562
1563         /* Play safe and disable self-refresh before adjusting watermarks. */
1564         intel_set_memory_cxsr(dev_priv, false);
1565
1566         /* Calc sr entries for one plane configs */
1567         if (HAS_FW_BLC(dev) && enabled) {
1568                 /* self-refresh has much higher latency */
1569                 static const int sr_latency_ns = 6000;
1570                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1571                 int clock = adjusted_mode->crtc_clock;
1572                 int htotal = adjusted_mode->crtc_htotal;
1573                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1574                 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
1575                 unsigned long line_time_us;
1576                 int entries;
1577
1578                 line_time_us = max(htotal * 1000 / clock, 1);
1579
1580                 /* Use ns/us then divide to preserve precision */
1581                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1582                         cpp * hdisplay;
1583                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1584                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1585                 srwm = wm_info->fifo_size - entries;
1586                 if (srwm < 0)
1587                         srwm = 1;
1588
1589                 if (IS_I945G(dev) || IS_I945GM(dev))
1590                         I915_WRITE(FW_BLC_SELF,
1591                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1592                 else if (IS_I915GM(dev))
1593                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1594         }
1595
1596         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1597                       planea_wm, planeb_wm, cwm, srwm);
1598
1599         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1600         fwater_hi = (cwm & 0x1f);
1601
1602         /* Set request length to 8 cachelines per fetch */
1603         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1604         fwater_hi = fwater_hi | (1 << 8);
1605
1606         I915_WRITE(FW_BLC, fwater_lo);
1607         I915_WRITE(FW_BLC2, fwater_hi);
1608
1609         if (enabled)
1610                 intel_set_memory_cxsr(dev_priv, true);
1611 }
1612
1613 static void i845_update_wm(struct drm_crtc *unused_crtc)
1614 {
1615         struct drm_device *dev = unused_crtc->dev;
1616         struct drm_i915_private *dev_priv = dev->dev_private;
1617         struct drm_crtc *crtc;
1618         const struct drm_display_mode *adjusted_mode;
1619         uint32_t fwater_lo;
1620         int planea_wm;
1621
1622         crtc = single_enabled_crtc(dev);
1623         if (crtc == NULL)
1624                 return;
1625
1626         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1627         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1628                                        &i845_wm_info,
1629                                        dev_priv->display.get_fifo_size(dev, 0),
1630                                        4, pessimal_latency_ns);
1631         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1632         fwater_lo |= (3<<8) | planea_wm;
1633
1634         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1635
1636         I915_WRITE(FW_BLC, fwater_lo);
1637 }
1638
1639 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1640 {
1641         uint32_t pixel_rate;
1642
1643         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1644
1645         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1646          * adjust the pixel_rate here. */
1647
1648         if (pipe_config->pch_pfit.enabled) {
1649                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1650                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1651
1652                 pipe_w = pipe_config->pipe_src_w;
1653                 pipe_h = pipe_config->pipe_src_h;
1654
1655                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1656                 pfit_h = pfit_size & 0xFFFF;
1657                 if (pipe_w < pfit_w)
1658                         pipe_w = pfit_w;
1659                 if (pipe_h < pfit_h)
1660                         pipe_h = pfit_h;
1661
1662                 if (WARN_ON(!pfit_w || !pfit_h))
1663                         return pixel_rate;
1664
1665                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1666                                      pfit_w * pfit_h);
1667         }
1668
1669         return pixel_rate;
1670 }
1671
1672 /* latency must be in 0.1us units. */
1673 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
1674 {
1675         uint64_t ret;
1676
1677         if (WARN(latency == 0, "Latency value missing\n"))
1678                 return UINT_MAX;
1679
1680         ret = (uint64_t) pixel_rate * cpp * latency;
1681         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1682
1683         return ret;
1684 }
1685
1686 /* latency must be in 0.1us units. */
1687 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1688                                uint32_t horiz_pixels, uint8_t cpp,
1689                                uint32_t latency)
1690 {
1691         uint32_t ret;
1692
1693         if (WARN(latency == 0, "Latency value missing\n"))
1694                 return UINT_MAX;
1695         if (WARN_ON(!pipe_htotal))
1696                 return UINT_MAX;
1697
1698         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1699         ret = (ret + 1) * horiz_pixels * cpp;
1700         ret = DIV_ROUND_UP(ret, 64) + 2;
1701         return ret;
1702 }
1703
1704 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1705                            uint8_t cpp)
1706 {
1707         /*
1708          * Neither of these should be possible since this function shouldn't be
1709          * called if the CRTC is off or the plane is invisible.  But let's be
1710          * extra paranoid to avoid a potential divide-by-zero if we screw up
1711          * elsewhere in the driver.
1712          */
1713         if (WARN_ON(!cpp))
1714                 return 0;
1715         if (WARN_ON(!horiz_pixels))
1716                 return 0;
1717
1718         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
1719 }
1720
1721 struct ilk_wm_maximums {
1722         uint16_t pri;
1723         uint16_t spr;
1724         uint16_t cur;
1725         uint16_t fbc;
1726 };
1727
1728 /*
1729  * For both WM_PIPE and WM_LP.
1730  * mem_value must be in 0.1us units.
1731  */
1732 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1733                                    const struct intel_plane_state *pstate,
1734                                    uint32_t mem_value,
1735                                    bool is_lp)
1736 {
1737         int cpp = pstate->base.fb ?
1738                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1739         uint32_t method1, method2;
1740
1741         if (!cstate->base.active || !pstate->visible)
1742                 return 0;
1743
1744         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1745
1746         if (!is_lp)
1747                 return method1;
1748
1749         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1750                                  cstate->base.adjusted_mode.crtc_htotal,
1751                                  drm_rect_width(&pstate->dst),
1752                                  cpp, mem_value);
1753
1754         return min(method1, method2);
1755 }
1756
1757 /*
1758  * For both WM_PIPE and WM_LP.
1759  * mem_value must be in 0.1us units.
1760  */
1761 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1762                                    const struct intel_plane_state *pstate,
1763                                    uint32_t mem_value)
1764 {
1765         int cpp = pstate->base.fb ?
1766                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1767         uint32_t method1, method2;
1768
1769         if (!cstate->base.active || !pstate->visible)
1770                 return 0;
1771
1772         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
1773         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1774                                  cstate->base.adjusted_mode.crtc_htotal,
1775                                  drm_rect_width(&pstate->dst),
1776                                  cpp, mem_value);
1777         return min(method1, method2);
1778 }
1779
1780 /*
1781  * For both WM_PIPE and WM_LP.
1782  * mem_value must be in 0.1us units.
1783  */
1784 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1785                                    const struct intel_plane_state *pstate,
1786                                    uint32_t mem_value)
1787 {
1788         /*
1789          * We treat the cursor plane as always-on for the purposes of watermark
1790          * calculation.  Until we have two-stage watermark programming merged,
1791          * this is necessary to avoid flickering.
1792          */
1793         int cpp = 4;
1794         int width = pstate->visible ? pstate->base.crtc_w : 64;
1795
1796         if (!cstate->base.active)
1797                 return 0;
1798
1799         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1800                               cstate->base.adjusted_mode.crtc_htotal,
1801                               width, cpp, mem_value);
1802 }
1803
1804 /* Only for WM_LP. */
1805 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1806                                    const struct intel_plane_state *pstate,
1807                                    uint32_t pri_val)
1808 {
1809         int cpp = pstate->base.fb ?
1810                 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
1811
1812         if (!cstate->base.active || !pstate->visible)
1813                 return 0;
1814
1815         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
1816 }
1817
1818 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1819 {
1820         if (INTEL_INFO(dev)->gen >= 8)
1821                 return 3072;
1822         else if (INTEL_INFO(dev)->gen >= 7)
1823                 return 768;
1824         else
1825                 return 512;
1826 }
1827
1828 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1829                                          int level, bool is_sprite)
1830 {
1831         if (INTEL_INFO(dev)->gen >= 8)
1832                 /* BDW primary/sprite plane watermarks */
1833                 return level == 0 ? 255 : 2047;
1834         else if (INTEL_INFO(dev)->gen >= 7)
1835                 /* IVB/HSW primary/sprite plane watermarks */
1836                 return level == 0 ? 127 : 1023;
1837         else if (!is_sprite)
1838                 /* ILK/SNB primary plane watermarks */
1839                 return level == 0 ? 127 : 511;
1840         else
1841                 /* ILK/SNB sprite plane watermarks */
1842                 return level == 0 ? 63 : 255;
1843 }
1844
1845 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1846                                           int level)
1847 {
1848         if (INTEL_INFO(dev)->gen >= 7)
1849                 return level == 0 ? 63 : 255;
1850         else
1851                 return level == 0 ? 31 : 63;
1852 }
1853
1854 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1855 {
1856         if (INTEL_INFO(dev)->gen >= 8)
1857                 return 31;
1858         else
1859                 return 15;
1860 }
1861
1862 /* Calculate the maximum primary/sprite plane watermark */
1863 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1864                                      int level,
1865                                      const struct intel_wm_config *config,
1866                                      enum intel_ddb_partitioning ddb_partitioning,
1867                                      bool is_sprite)
1868 {
1869         unsigned int fifo_size = ilk_display_fifo_size(dev);
1870
1871         /* if sprites aren't enabled, sprites get nothing */
1872         if (is_sprite && !config->sprites_enabled)
1873                 return 0;
1874
1875         /* HSW allows LP1+ watermarks even with multiple pipes */
1876         if (level == 0 || config->num_pipes_active > 1) {
1877                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1878
1879                 /*
1880                  * For some reason the non self refresh
1881                  * FIFO size is only half of the self
1882                  * refresh FIFO size on ILK/SNB.
1883                  */
1884                 if (INTEL_INFO(dev)->gen <= 6)
1885                         fifo_size /= 2;
1886         }
1887
1888         if (config->sprites_enabled) {
1889                 /* level 0 is always calculated with 1:1 split */
1890                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1891                         if (is_sprite)
1892                                 fifo_size *= 5;
1893                         fifo_size /= 6;
1894                 } else {
1895                         fifo_size /= 2;
1896                 }
1897         }
1898
1899         /* clamp to max that the registers can hold */
1900         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1901 }
1902
1903 /* Calculate the maximum cursor plane watermark */
1904 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1905                                       int level,
1906                                       const struct intel_wm_config *config)
1907 {
1908         /* HSW LP1+ watermarks w/ multiple pipes */
1909         if (level > 0 && config->num_pipes_active > 1)
1910                 return 64;
1911
1912         /* otherwise just report max that registers can hold */
1913         return ilk_cursor_wm_reg_max(dev, level);
1914 }
1915
1916 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1917                                     int level,
1918                                     const struct intel_wm_config *config,
1919                                     enum intel_ddb_partitioning ddb_partitioning,
1920                                     struct ilk_wm_maximums *max)
1921 {
1922         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1923         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1924         max->cur = ilk_cursor_wm_max(dev, level, config);
1925         max->fbc = ilk_fbc_wm_reg_max(dev);
1926 }
1927
1928 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1929                                         int level,
1930                                         struct ilk_wm_maximums *max)
1931 {
1932         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1933         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1934         max->cur = ilk_cursor_wm_reg_max(dev, level);
1935         max->fbc = ilk_fbc_wm_reg_max(dev);
1936 }
1937
1938 static bool ilk_validate_wm_level(int level,
1939                                   const struct ilk_wm_maximums *max,
1940                                   struct intel_wm_level *result)
1941 {
1942         bool ret;
1943
1944         /* already determined to be invalid? */
1945         if (!result->enable)
1946                 return false;
1947
1948         result->enable = result->pri_val <= max->pri &&
1949                          result->spr_val <= max->spr &&
1950                          result->cur_val <= max->cur;
1951
1952         ret = result->enable;
1953
1954         /*
1955          * HACK until we can pre-compute everything,
1956          * and thus fail gracefully if LP0 watermarks
1957          * are exceeded...
1958          */
1959         if (level == 0 && !result->enable) {
1960                 if (result->pri_val > max->pri)
1961                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1962                                       level, result->pri_val, max->pri);
1963                 if (result->spr_val > max->spr)
1964                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1965                                       level, result->spr_val, max->spr);
1966                 if (result->cur_val > max->cur)
1967                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1968                                       level, result->cur_val, max->cur);
1969
1970                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1971                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1972                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1973                 result->enable = true;
1974         }
1975
1976         return ret;
1977 }
1978
1979 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1980                                  const struct intel_crtc *intel_crtc,
1981                                  int level,
1982                                  struct intel_crtc_state *cstate,
1983                                  struct intel_plane_state *pristate,
1984                                  struct intel_plane_state *sprstate,
1985                                  struct intel_plane_state *curstate,
1986                                  struct intel_wm_level *result)
1987 {
1988         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992         /* WM1+ latency values stored in 0.5us units */
1993         if (level > 0) {
1994                 pri_latency *= 5;
1995                 spr_latency *= 5;
1996                 cur_latency *= 5;
1997         }
1998
1999         if (pristate) {
2000                 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2001                                                      pri_latency, level);
2002                 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2003         }
2004
2005         if (sprstate)
2006                 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2007
2008         if (curstate)
2009                 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2010
2011         result->enable = true;
2012 }
2013
2014 static uint32_t
2015 hsw_compute_linetime_wm(struct drm_device *dev,
2016                         struct intel_crtc_state *cstate)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         const struct drm_display_mode *adjusted_mode =
2020                 &cstate->base.adjusted_mode;
2021         u32 linetime, ips_linetime;
2022
2023         if (!cstate->base.active)
2024                 return 0;
2025         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2026                 return 0;
2027         if (WARN_ON(dev_priv->cdclk_freq == 0))
2028                 return 0;
2029
2030         /* The WM are computed with base on how long it takes to fill a single
2031          * row at the given clock rate, multiplied by 8.
2032          * */
2033         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2034                                      adjusted_mode->crtc_clock);
2035         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2036                                          dev_priv->cdclk_freq);
2037
2038         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2039                PIPE_WM_LINETIME_TIME(linetime);
2040 }
2041
2042 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2043 {
2044         struct drm_i915_private *dev_priv = dev->dev_private;
2045
2046         if (IS_GEN9(dev)) {
2047                 uint32_t val;
2048                 int ret, i;
2049                 int level, max_level = ilk_wm_max_level(dev);
2050
2051                 /* read the first set of memory latencies[0:3] */
2052                 val = 0; /* data0 to be programmed to 0 for first set */
2053                 mutex_lock(&dev_priv->rps.hw_lock);
2054                 ret = sandybridge_pcode_read(dev_priv,
2055                                              GEN9_PCODE_READ_MEM_LATENCY,
2056                                              &val);
2057                 mutex_unlock(&dev_priv->rps.hw_lock);
2058
2059                 if (ret) {
2060                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2061                         return;
2062                 }
2063
2064                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2065                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2066                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2067                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2068                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2069                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2070                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2071
2072                 /* read the second set of memory latencies[4:7] */
2073                 val = 1; /* data0 to be programmed to 1 for second set */
2074                 mutex_lock(&dev_priv->rps.hw_lock);
2075                 ret = sandybridge_pcode_read(dev_priv,
2076                                              GEN9_PCODE_READ_MEM_LATENCY,
2077                                              &val);
2078                 mutex_unlock(&dev_priv->rps.hw_lock);
2079                 if (ret) {
2080                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2081                         return;
2082                 }
2083
2084                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2085                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2086                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2087                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2088                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2089                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2090                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2091
2092                 /*
2093                  * WaWmMemoryReadLatency:skl
2094                  *
2095                  * punit doesn't take into account the read latency so we need
2096                  * to add 2us to the various latency levels we retrieve from
2097                  * the punit.
2098                  *   - W0 is a bit special in that it's the only level that
2099                  *   can't be disabled if we want to have display working, so
2100                  *   we always add 2us there.
2101                  *   - For levels >=1, punit returns 0us latency when they are
2102                  *   disabled, so we respect that and don't add 2us then
2103                  *
2104                  * Additionally, if a level n (n > 1) has a 0us latency, all
2105                  * levels m (m >= n) need to be disabled. We make sure to
2106                  * sanitize the values out of the punit to satisfy this
2107                  * requirement.
2108                  */
2109                 wm[0] += 2;
2110                 for (level = 1; level <= max_level; level++)
2111                         if (wm[level] != 0)
2112                                 wm[level] += 2;
2113                         else {
2114                                 for (i = level + 1; i <= max_level; i++)
2115                                         wm[i] = 0;
2116
2117                                 break;
2118                         }
2119         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2120                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2121
2122                 wm[0] = (sskpd >> 56) & 0xFF;
2123                 if (wm[0] == 0)
2124                         wm[0] = sskpd & 0xF;
2125                 wm[1] = (sskpd >> 4) & 0xFF;
2126                 wm[2] = (sskpd >> 12) & 0xFF;
2127                 wm[3] = (sskpd >> 20) & 0x1FF;
2128                 wm[4] = (sskpd >> 32) & 0x1FF;
2129         } else if (INTEL_INFO(dev)->gen >= 6) {
2130                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2131
2132                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2133                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2134                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2135                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2136         } else if (INTEL_INFO(dev)->gen >= 5) {
2137                 uint32_t mltr = I915_READ(MLTR_ILK);
2138
2139                 /* ILK primary LP0 latency is 700 ns */
2140                 wm[0] = 7;
2141                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2142                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2143         }
2144 }
2145
2146 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2147 {
2148         /* ILK sprite LP0 latency is 1300 ns */
2149         if (INTEL_INFO(dev)->gen == 5)
2150                 wm[0] = 13;
2151 }
2152
2153 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2154 {
2155         /* ILK cursor LP0 latency is 1300 ns */
2156         if (INTEL_INFO(dev)->gen == 5)
2157                 wm[0] = 13;
2158
2159         /* WaDoubleCursorLP3Latency:ivb */
2160         if (IS_IVYBRIDGE(dev))
2161                 wm[3] *= 2;
2162 }
2163
2164 int ilk_wm_max_level(const struct drm_device *dev)
2165 {
2166         /* how many WM levels are we expecting */
2167         if (INTEL_INFO(dev)->gen >= 9)
2168                 return 7;
2169         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2170                 return 4;
2171         else if (INTEL_INFO(dev)->gen >= 6)
2172                 return 3;
2173         else
2174                 return 2;
2175 }
2176
2177 static void intel_print_wm_latency(struct drm_device *dev,
2178                                    const char *name,
2179                                    const uint16_t wm[8])
2180 {
2181         int level, max_level = ilk_wm_max_level(dev);
2182
2183         for (level = 0; level <= max_level; level++) {
2184                 unsigned int latency = wm[level];
2185
2186                 if (latency == 0) {
2187                         DRM_ERROR("%s WM%d latency not provided\n",
2188                                   name, level);
2189                         continue;
2190                 }
2191
2192                 /*
2193                  * - latencies are in us on gen9.
2194                  * - before then, WM1+ latency values are in 0.5us units
2195                  */
2196                 if (IS_GEN9(dev))
2197                         latency *= 10;
2198                 else if (level > 0)
2199                         latency *= 5;
2200
2201                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2202                               name, level, wm[level],
2203                               latency / 10, latency % 10);
2204         }
2205 }
2206
2207 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2208                                     uint16_t wm[5], uint16_t min)
2209 {
2210         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2211
2212         if (wm[0] >= min)
2213                 return false;
2214
2215         wm[0] = max(wm[0], min);
2216         for (level = 1; level <= max_level; level++)
2217                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2218
2219         return true;
2220 }
2221
2222 static void snb_wm_latency_quirk(struct drm_device *dev)
2223 {
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225         bool changed;
2226
2227         /*
2228          * The BIOS provided WM memory latency values are often
2229          * inadequate for high resolution displays. Adjust them.
2230          */
2231         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2232                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2233                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2234
2235         if (!changed)
2236                 return;
2237
2238         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2239         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2242 }
2243
2244 static void ilk_setup_wm_latency(struct drm_device *dev)
2245 {
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247
2248         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2249
2250         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2251                sizeof(dev_priv->wm.pri_latency));
2252         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2253                sizeof(dev_priv->wm.pri_latency));
2254
2255         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2256         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2257
2258         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2259         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2260         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2261
2262         if (IS_GEN6(dev))
2263                 snb_wm_latency_quirk(dev);
2264 }
2265
2266 static void skl_setup_wm_latency(struct drm_device *dev)
2267 {
2268         struct drm_i915_private *dev_priv = dev->dev_private;
2269
2270         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2271         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2272 }
2273
2274 static bool ilk_validate_pipe_wm(struct drm_device *dev,
2275                                  struct intel_pipe_wm *pipe_wm)
2276 {
2277         /* LP0 watermark maximums depend on this pipe alone */
2278         const struct intel_wm_config config = {
2279                 .num_pipes_active = 1,
2280                 .sprites_enabled = pipe_wm->sprites_enabled,
2281                 .sprites_scaled = pipe_wm->sprites_scaled,
2282         };
2283         struct ilk_wm_maximums max;
2284
2285         /* LP0 watermarks always use 1/2 DDB partitioning */
2286         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2287
2288         /* At least LP0 must be valid */
2289         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2290                 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2291                 return false;
2292         }
2293
2294         return true;
2295 }
2296
2297 /* Compute new watermarks for the pipe */
2298 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
2299 {
2300         struct drm_atomic_state *state = cstate->base.state;
2301         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2302         struct intel_pipe_wm *pipe_wm;
2303         struct drm_device *dev = state->dev;
2304         const struct drm_i915_private *dev_priv = dev->dev_private;
2305         struct intel_plane *intel_plane;
2306         struct intel_plane_state *pristate = NULL;
2307         struct intel_plane_state *sprstate = NULL;
2308         struct intel_plane_state *curstate = NULL;
2309         int level, max_level = ilk_wm_max_level(dev), usable_level;
2310         struct ilk_wm_maximums max;
2311
2312         pipe_wm = &cstate->wm.optimal.ilk;
2313
2314         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2315                 struct intel_plane_state *ps;
2316
2317                 ps = intel_atomic_get_existing_plane_state(state,
2318                                                            intel_plane);
2319                 if (!ps)
2320                         continue;
2321
2322                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2323                         pristate = ps;
2324                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2325                         sprstate = ps;
2326                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2327                         curstate = ps;
2328         }
2329
2330         pipe_wm->pipe_enabled = cstate->base.active;
2331         if (sprstate) {
2332                 pipe_wm->sprites_enabled = sprstate->visible;
2333                 pipe_wm->sprites_scaled = sprstate->visible &&
2334                         (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2335                          drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2336         }
2337
2338         usable_level = max_level;
2339
2340         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2341         if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
2342                 usable_level = 1;
2343
2344         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2345         if (pipe_wm->sprites_scaled)
2346                 usable_level = 0;
2347
2348         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2349                              pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2350
2351         memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2352         pipe_wm->wm[0] = pipe_wm->raw_wm[0];
2353
2354         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2355                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2356
2357         if (!ilk_validate_pipe_wm(dev, pipe_wm))
2358                 return -EINVAL;
2359
2360         ilk_compute_wm_reg_maximums(dev, 1, &max);
2361
2362         for (level = 1; level <= max_level; level++) {
2363                 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
2364
2365                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2366                                      pristate, sprstate, curstate, wm);
2367
2368                 /*
2369                  * Disable any watermark level that exceeds the
2370                  * register maximums since such watermarks are
2371                  * always invalid.
2372                  */
2373                 if (level > usable_level)
2374                         continue;
2375
2376                 if (ilk_validate_wm_level(level, &max, wm))
2377                         pipe_wm->wm[level] = *wm;
2378                 else
2379                         usable_level = level;
2380         }
2381
2382         return 0;
2383 }
2384
2385 /*
2386  * Build a set of 'intermediate' watermark values that satisfy both the old
2387  * state and the new state.  These can be programmed to the hardware
2388  * immediately.
2389  */
2390 static int ilk_compute_intermediate_wm(struct drm_device *dev,
2391                                        struct intel_crtc *intel_crtc,
2392                                        struct intel_crtc_state *newstate)
2393 {
2394         struct intel_pipe_wm *a = &newstate->wm.intermediate;
2395         struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2396         int level, max_level = ilk_wm_max_level(dev);
2397
2398         /*
2399          * Start with the final, target watermarks, then combine with the
2400          * currently active watermarks to get values that are safe both before
2401          * and after the vblank.
2402          */
2403         *a = newstate->wm.optimal.ilk;
2404         a->pipe_enabled |= b->pipe_enabled;
2405         a->sprites_enabled |= b->sprites_enabled;
2406         a->sprites_scaled |= b->sprites_scaled;
2407
2408         for (level = 0; level <= max_level; level++) {
2409                 struct intel_wm_level *a_wm = &a->wm[level];
2410                 const struct intel_wm_level *b_wm = &b->wm[level];
2411
2412                 a_wm->enable &= b_wm->enable;
2413                 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2414                 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2415                 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2416                 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2417         }
2418
2419         /*
2420          * We need to make sure that these merged watermark values are
2421          * actually a valid configuration themselves.  If they're not,
2422          * there's no safe way to transition from the old state to
2423          * the new state, so we need to fail the atomic transaction.
2424          */
2425         if (!ilk_validate_pipe_wm(dev, a))
2426                 return -EINVAL;
2427
2428         /*
2429          * If our intermediate WM are identical to the final WM, then we can
2430          * omit the post-vblank programming; only update if it's different.
2431          */
2432         if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2433                 newstate->wm.need_postvbl_update = false;
2434
2435         return 0;
2436 }
2437
2438 /*
2439  * Merge the watermarks from all active pipes for a specific level.
2440  */
2441 static void ilk_merge_wm_level(struct drm_device *dev,
2442                                int level,
2443                                struct intel_wm_level *ret_wm)
2444 {
2445         const struct intel_crtc *intel_crtc;
2446
2447         ret_wm->enable = true;
2448
2449         for_each_intel_crtc(dev, intel_crtc) {
2450                 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
2451                 const struct intel_wm_level *wm = &active->wm[level];
2452
2453                 if (!active->pipe_enabled)
2454                         continue;
2455
2456                 /*
2457                  * The watermark values may have been used in the past,
2458                  * so we must maintain them in the registers for some
2459                  * time even if the level is now disabled.
2460                  */
2461                 if (!wm->enable)
2462                         ret_wm->enable = false;
2463
2464                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2465                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2466                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2467                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2468         }
2469 }
2470
2471 /*
2472  * Merge all low power watermarks for all active pipes.
2473  */
2474 static void ilk_wm_merge(struct drm_device *dev,
2475                          const struct intel_wm_config *config,
2476                          const struct ilk_wm_maximums *max,
2477                          struct intel_pipe_wm *merged)
2478 {
2479         struct drm_i915_private *dev_priv = dev->dev_private;
2480         int level, max_level = ilk_wm_max_level(dev);
2481         int last_enabled_level = max_level;
2482
2483         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2484         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2485             config->num_pipes_active > 1)
2486                 last_enabled_level = 0;
2487
2488         /* ILK: FBC WM must be disabled always */
2489         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2490
2491         /* merge each WM1+ level */
2492         for (level = 1; level <= max_level; level++) {
2493                 struct intel_wm_level *wm = &merged->wm[level];
2494
2495                 ilk_merge_wm_level(dev, level, wm);
2496
2497                 if (level > last_enabled_level)
2498                         wm->enable = false;
2499                 else if (!ilk_validate_wm_level(level, max, wm))
2500                         /* make sure all following levels get disabled */
2501                         last_enabled_level = level - 1;
2502
2503                 /*
2504                  * The spec says it is preferred to disable
2505                  * FBC WMs instead of disabling a WM level.
2506                  */
2507                 if (wm->fbc_val > max->fbc) {
2508                         if (wm->enable)
2509                                 merged->fbc_wm_enabled = false;
2510                         wm->fbc_val = 0;
2511                 }
2512         }
2513
2514         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2515         /*
2516          * FIXME this is racy. FBC might get enabled later.
2517          * What we should check here is whether FBC can be
2518          * enabled sometime later.
2519          */
2520         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2521             intel_fbc_is_active(dev_priv)) {
2522                 for (level = 2; level <= max_level; level++) {
2523                         struct intel_wm_level *wm = &merged->wm[level];
2524
2525                         wm->enable = false;
2526                 }
2527         }
2528 }
2529
2530 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2531 {
2532         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2533         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2534 }
2535
2536 /* The value we need to program into the WM_LPx latency field */
2537 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2538 {
2539         struct drm_i915_private *dev_priv = dev->dev_private;
2540
2541         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2542                 return 2 * level;
2543         else
2544                 return dev_priv->wm.pri_latency[level];
2545 }
2546
2547 static void ilk_compute_wm_results(struct drm_device *dev,
2548                                    const struct intel_pipe_wm *merged,
2549                                    enum intel_ddb_partitioning partitioning,
2550                                    struct ilk_wm_values *results)
2551 {
2552         struct intel_crtc *intel_crtc;
2553         int level, wm_lp;
2554
2555         results->enable_fbc_wm = merged->fbc_wm_enabled;
2556         results->partitioning = partitioning;
2557
2558         /* LP1+ register values */
2559         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2560                 const struct intel_wm_level *r;
2561
2562                 level = ilk_wm_lp_to_level(wm_lp, merged);
2563
2564                 r = &merged->wm[level];
2565
2566                 /*
2567                  * Maintain the watermark values even if the level is
2568                  * disabled. Doing otherwise could cause underruns.
2569                  */
2570                 results->wm_lp[wm_lp - 1] =
2571                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2572                         (r->pri_val << WM1_LP_SR_SHIFT) |
2573                         r->cur_val;
2574
2575                 if (r->enable)
2576                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2577
2578                 if (INTEL_INFO(dev)->gen >= 8)
2579                         results->wm_lp[wm_lp - 1] |=
2580                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2581                 else
2582                         results->wm_lp[wm_lp - 1] |=
2583                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2584
2585                 /*
2586                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2587                  * level is disabled. Doing otherwise could cause underruns.
2588                  */
2589                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2590                         WARN_ON(wm_lp != 1);
2591                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2592                 } else
2593                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2594         }
2595
2596         /* LP0 register values */
2597         for_each_intel_crtc(dev, intel_crtc) {
2598                 enum pipe pipe = intel_crtc->pipe;
2599                 const struct intel_wm_level *r =
2600                         &intel_crtc->wm.active.ilk.wm[0];
2601
2602                 if (WARN_ON(!r->enable))
2603                         continue;
2604
2605                 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
2606
2607                 results->wm_pipe[pipe] =
2608                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2609                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2610                         r->cur_val;
2611         }
2612 }
2613
2614 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2615  * case both are at the same level. Prefer r1 in case they're the same. */
2616 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2617                                                   struct intel_pipe_wm *r1,
2618                                                   struct intel_pipe_wm *r2)
2619 {
2620         int level, max_level = ilk_wm_max_level(dev);
2621         int level1 = 0, level2 = 0;
2622
2623         for (level = 1; level <= max_level; level++) {
2624                 if (r1->wm[level].enable)
2625                         level1 = level;
2626                 if (r2->wm[level].enable)
2627                         level2 = level;
2628         }
2629
2630         if (level1 == level2) {
2631                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2632                         return r2;
2633                 else
2634                         return r1;
2635         } else if (level1 > level2) {
2636                 return r1;
2637         } else {
2638                 return r2;
2639         }
2640 }
2641
2642 /* dirty bits used to track which watermarks need changes */
2643 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2644 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2645 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2646 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2647 #define WM_DIRTY_FBC (1 << 24)
2648 #define WM_DIRTY_DDB (1 << 25)
2649
2650 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2651                                          const struct ilk_wm_values *old,
2652                                          const struct ilk_wm_values *new)
2653 {
2654         unsigned int dirty = 0;
2655         enum pipe pipe;
2656         int wm_lp;
2657
2658         for_each_pipe(dev_priv, pipe) {
2659                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2660                         dirty |= WM_DIRTY_LINETIME(pipe);
2661                         /* Must disable LP1+ watermarks too */
2662                         dirty |= WM_DIRTY_LP_ALL;
2663                 }
2664
2665                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2666                         dirty |= WM_DIRTY_PIPE(pipe);
2667                         /* Must disable LP1+ watermarks too */
2668                         dirty |= WM_DIRTY_LP_ALL;
2669                 }
2670         }
2671
2672         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2673                 dirty |= WM_DIRTY_FBC;
2674                 /* Must disable LP1+ watermarks too */
2675                 dirty |= WM_DIRTY_LP_ALL;
2676         }
2677
2678         if (old->partitioning != new->partitioning) {
2679                 dirty |= WM_DIRTY_DDB;
2680                 /* Must disable LP1+ watermarks too */
2681                 dirty |= WM_DIRTY_LP_ALL;
2682         }
2683
2684         /* LP1+ watermarks already deemed dirty, no need to continue */
2685         if (dirty & WM_DIRTY_LP_ALL)
2686                 return dirty;
2687
2688         /* Find the lowest numbered LP1+ watermark in need of an update... */
2689         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2690                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2691                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2692                         break;
2693         }
2694
2695         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2696         for (; wm_lp <= 3; wm_lp++)
2697                 dirty |= WM_DIRTY_LP(wm_lp);
2698
2699         return dirty;
2700 }
2701
2702 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2703                                unsigned int dirty)
2704 {
2705         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2706         bool changed = false;
2707
2708         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2709                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2710                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2711                 changed = true;
2712         }
2713         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2714                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2715                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2716                 changed = true;
2717         }
2718         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2719                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2720                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2721                 changed = true;
2722         }
2723
2724         /*
2725          * Don't touch WM1S_LP_EN here.
2726          * Doing so could cause underruns.
2727          */
2728
2729         return changed;
2730 }
2731
2732 /*
2733  * The spec says we shouldn't write when we don't need, because every write
2734  * causes WMs to be re-evaluated, expending some power.
2735  */
2736 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2737                                 struct ilk_wm_values *results)
2738 {
2739         struct drm_device *dev = dev_priv->dev;
2740         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2741         unsigned int dirty;
2742         uint32_t val;
2743
2744         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2745         if (!dirty)
2746                 return;
2747
2748         _ilk_disable_lp_wm(dev_priv, dirty);
2749
2750         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2751                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2752         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2753                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2754         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2755                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2756
2757         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2758                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2759         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2760                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2761         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2762                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2763
2764         if (dirty & WM_DIRTY_DDB) {
2765                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2766                         val = I915_READ(WM_MISC);
2767                         if (results->partitioning == INTEL_DDB_PART_1_2)
2768                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2769                         else
2770                                 val |= WM_MISC_DATA_PARTITION_5_6;
2771                         I915_WRITE(WM_MISC, val);
2772                 } else {
2773                         val = I915_READ(DISP_ARB_CTL2);
2774                         if (results->partitioning == INTEL_DDB_PART_1_2)
2775                                 val &= ~DISP_DATA_PARTITION_5_6;
2776                         else
2777                                 val |= DISP_DATA_PARTITION_5_6;
2778                         I915_WRITE(DISP_ARB_CTL2, val);
2779                 }
2780         }
2781
2782         if (dirty & WM_DIRTY_FBC) {
2783                 val = I915_READ(DISP_ARB_CTL);
2784                 if (results->enable_fbc_wm)
2785                         val &= ~DISP_FBC_WM_DIS;
2786                 else
2787                         val |= DISP_FBC_WM_DIS;
2788                 I915_WRITE(DISP_ARB_CTL, val);
2789         }
2790
2791         if (dirty & WM_DIRTY_LP(1) &&
2792             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2793                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2794
2795         if (INTEL_INFO(dev)->gen >= 7) {
2796                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2797                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2798                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2799                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2800         }
2801
2802         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2803                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2804         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2805                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2806         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2807                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2808
2809         dev_priv->wm.hw = *results;
2810 }
2811
2812 bool ilk_disable_lp_wm(struct drm_device *dev)
2813 {
2814         struct drm_i915_private *dev_priv = dev->dev_private;
2815
2816         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2817 }
2818
2819 /*
2820  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2821  * different active planes.
2822  */
2823
2824 #define SKL_DDB_SIZE            896     /* in blocks */
2825 #define BXT_DDB_SIZE            512
2826
2827 /*
2828  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2829  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2830  * other universal planes are in indices 1..n.  Note that this may leave unused
2831  * indices between the top "sprite" plane and the cursor.
2832  */
2833 static int
2834 skl_wm_plane_id(const struct intel_plane *plane)
2835 {
2836         switch (plane->base.type) {
2837         case DRM_PLANE_TYPE_PRIMARY:
2838                 return 0;
2839         case DRM_PLANE_TYPE_CURSOR:
2840                 return PLANE_CURSOR;
2841         case DRM_PLANE_TYPE_OVERLAY:
2842                 return plane->plane + 1;
2843         default:
2844                 MISSING_CASE(plane->base.type);
2845                 return plane->plane;
2846         }
2847 }
2848
2849 static void
2850 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2851                                    const struct intel_crtc_state *cstate,
2852                                    const struct intel_wm_config *config,
2853                                    struct skl_ddb_entry *alloc /* out */)
2854 {
2855         struct drm_crtc *for_crtc = cstate->base.crtc;
2856         struct drm_crtc *crtc;
2857         unsigned int pipe_size, ddb_size;
2858         int nth_active_pipe;
2859
2860         if (!cstate->base.active) {
2861                 alloc->start = 0;
2862                 alloc->end = 0;
2863                 return;
2864         }
2865
2866         if (IS_BROXTON(dev))
2867                 ddb_size = BXT_DDB_SIZE;
2868         else
2869                 ddb_size = SKL_DDB_SIZE;
2870
2871         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2872
2873         nth_active_pipe = 0;
2874         for_each_crtc(dev, crtc) {
2875                 if (!to_intel_crtc(crtc)->active)
2876                         continue;
2877
2878                 if (crtc == for_crtc)
2879                         break;
2880
2881                 nth_active_pipe++;
2882         }
2883
2884         pipe_size = ddb_size / config->num_pipes_active;
2885         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2886         alloc->end = alloc->start + pipe_size;
2887 }
2888
2889 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2890 {
2891         if (config->num_pipes_active == 1)
2892                 return 32;
2893
2894         return 8;
2895 }
2896
2897 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2898 {
2899         entry->start = reg & 0x3ff;
2900         entry->end = (reg >> 16) & 0x3ff;
2901         if (entry->end)
2902                 entry->end += 1;
2903 }
2904
2905 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2906                           struct skl_ddb_allocation *ddb /* out */)
2907 {
2908         enum pipe pipe;
2909         int plane;
2910         u32 val;
2911
2912         memset(ddb, 0, sizeof(*ddb));
2913
2914         for_each_pipe(dev_priv, pipe) {
2915                 enum intel_display_power_domain power_domain;
2916
2917                 power_domain = POWER_DOMAIN_PIPE(pipe);
2918                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2919                         continue;
2920
2921                 for_each_plane(dev_priv, pipe, plane) {
2922                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2923                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2924                                                    val);
2925                 }
2926
2927                 val = I915_READ(CUR_BUF_CFG(pipe));
2928                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2929                                            val);
2930
2931                 intel_display_power_put(dev_priv, power_domain);
2932         }
2933 }
2934
2935 static unsigned int
2936 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2937                              const struct drm_plane_state *pstate,
2938                              int y)
2939 {
2940         struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
2941         struct drm_framebuffer *fb = pstate->fb;
2942         uint32_t width = 0, height = 0;
2943
2944         width = drm_rect_width(&intel_pstate->src) >> 16;
2945         height = drm_rect_height(&intel_pstate->src) >> 16;
2946
2947         if (intel_rotation_90_or_270(pstate->rotation))
2948                 swap(width, height);
2949
2950         /* for planar format */
2951         if (fb->pixel_format == DRM_FORMAT_NV12) {
2952                 if (y)  /* y-plane data rate */
2953                         return width * height *
2954                                 drm_format_plane_cpp(fb->pixel_format, 0);
2955                 else    /* uv-plane data rate */
2956                         return (width / 2) * (height / 2) *
2957                                 drm_format_plane_cpp(fb->pixel_format, 1);
2958         }
2959
2960         /* for packed formats */
2961         return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
2962 }
2963
2964 /*
2965  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2966  * a 8192x4096@32bpp framebuffer:
2967  *   3 * 4096 * 8192  * 4 < 2^32
2968  */
2969 static unsigned int
2970 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2971 {
2972         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2973         struct drm_device *dev = intel_crtc->base.dev;
2974         const struct intel_plane *intel_plane;
2975         unsigned int total_data_rate = 0;
2976
2977         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2978                 const struct drm_plane_state *pstate = intel_plane->base.state;
2979
2980                 if (pstate->fb == NULL)
2981                         continue;
2982
2983                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2984                         continue;
2985
2986                 /* packed/uv */
2987                 total_data_rate += skl_plane_relative_data_rate(cstate,
2988                                                                 pstate,
2989                                                                 0);
2990
2991                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2992                         /* y-plane */
2993                         total_data_rate += skl_plane_relative_data_rate(cstate,
2994                                                                         pstate,
2995                                                                         1);
2996         }
2997
2998         return total_data_rate;
2999 }
3000
3001 static void
3002 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
3003                       struct skl_ddb_allocation *ddb /* out */)
3004 {
3005         struct drm_crtc *crtc = cstate->base.crtc;
3006         struct drm_device *dev = crtc->dev;
3007         struct drm_i915_private *dev_priv = to_i915(dev);
3008         struct intel_wm_config *config = &dev_priv->wm.config;
3009         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3010         struct intel_plane *intel_plane;
3011         enum pipe pipe = intel_crtc->pipe;
3012         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
3013         uint16_t alloc_size, start, cursor_blocks;
3014         uint16_t minimum[I915_MAX_PLANES];
3015         uint16_t y_minimum[I915_MAX_PLANES];
3016         unsigned int total_data_rate;
3017
3018         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
3019         alloc_size = skl_ddb_entry_size(alloc);
3020         if (alloc_size == 0) {
3021                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3022                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3023                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
3024                 return;
3025         }
3026
3027         cursor_blocks = skl_cursor_allocation(config);
3028         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3029         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3030
3031         alloc_size -= cursor_blocks;
3032         alloc->end -= cursor_blocks;
3033
3034         /* 1. Allocate the mininum required blocks for each active plane */
3035         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3036                 struct drm_plane *plane = &intel_plane->base;
3037                 struct drm_framebuffer *fb = plane->state->fb;
3038                 int id = skl_wm_plane_id(intel_plane);
3039
3040                 if (!to_intel_plane_state(plane->state)->visible)
3041                         continue;
3042
3043                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3044                         continue;
3045
3046                 minimum[id] = 8;
3047                 alloc_size -= minimum[id];
3048                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3049                 alloc_size -= y_minimum[id];
3050         }
3051
3052         /*
3053          * 2. Distribute the remaining space in proportion to the amount of
3054          * data each plane needs to fetch from memory.
3055          *
3056          * FIXME: we may not allocate every single block here.
3057          */
3058         total_data_rate = skl_get_total_relative_data_rate(cstate);
3059
3060         start = alloc->start;
3061         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3062                 struct drm_plane *plane = &intel_plane->base;
3063                 struct drm_plane_state *pstate = intel_plane->base.state;
3064                 unsigned int data_rate, y_data_rate;
3065                 uint16_t plane_blocks, y_plane_blocks = 0;
3066                 int id = skl_wm_plane_id(intel_plane);
3067
3068                 if (!to_intel_plane_state(pstate)->visible)
3069                         continue;
3070                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3071                         continue;
3072
3073                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3074
3075                 /*
3076                  * allocation for (packed formats) or (uv-plane part of planar format):
3077                  * promote the expression to 64 bits to avoid overflowing, the
3078                  * result is < available as data_rate / total_data_rate < 1
3079                  */
3080                 plane_blocks = minimum[id];
3081                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3082                                         total_data_rate);
3083
3084                 ddb->plane[pipe][id].start = start;
3085                 ddb->plane[pipe][id].end = start + plane_blocks;
3086
3087                 start += plane_blocks;
3088
3089                 /*
3090                  * allocation for y_plane part of planar format:
3091                  */
3092                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3093                         y_data_rate = skl_plane_relative_data_rate(cstate,
3094                                                                    pstate,
3095                                                                    1);
3096                         y_plane_blocks = y_minimum[id];
3097                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3098                                                 total_data_rate);
3099
3100                         ddb->y_plane[pipe][id].start = start;
3101                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3102
3103                         start += y_plane_blocks;
3104                 }
3105
3106         }
3107
3108 }
3109
3110 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3111 {
3112         /* TODO: Take into account the scalers once we support them */
3113         return config->base.adjusted_mode.crtc_clock;
3114 }
3115
3116 /*
3117  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3118  * for the read latency) and cpp should always be <= 8, so that
3119  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3120  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3121 */
3122 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
3123 {
3124         uint32_t wm_intermediate_val, ret;
3125
3126         if (latency == 0)
3127                 return UINT_MAX;
3128
3129         wm_intermediate_val = latency * pixel_rate * cpp / 512;
3130         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3131
3132         return ret;
3133 }
3134
3135 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3136                                uint32_t horiz_pixels, uint8_t cpp,
3137                                uint64_t tiling, uint32_t latency)
3138 {
3139         uint32_t ret;
3140         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3141         uint32_t wm_intermediate_val;
3142
3143         if (latency == 0)
3144                 return UINT_MAX;
3145
3146         plane_bytes_per_line = horiz_pixels * cpp;
3147
3148         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3149             tiling == I915_FORMAT_MOD_Yf_TILED) {
3150                 plane_bytes_per_line *= 4;
3151                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3152                 plane_blocks_per_line /= 4;
3153         } else {
3154                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3155         }
3156
3157         wm_intermediate_val = latency * pixel_rate;
3158         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3159                                 plane_blocks_per_line;
3160
3161         return ret;
3162 }
3163
3164 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3165                                        const struct intel_crtc *intel_crtc)
3166 {
3167         struct drm_device *dev = intel_crtc->base.dev;
3168         struct drm_i915_private *dev_priv = dev->dev_private;
3169         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3170
3171         /*
3172          * If ddb allocation of pipes changed, it may require recalculation of
3173          * watermarks
3174          */
3175         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3176                 return true;
3177
3178         return false;
3179 }
3180
3181 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3182                                  struct intel_crtc_state *cstate,
3183                                  struct intel_plane *intel_plane,
3184                                  uint16_t ddb_allocation,
3185                                  int level,
3186                                  uint16_t *out_blocks, /* out */
3187                                  uint8_t *out_lines /* out */)
3188 {
3189         struct drm_plane *plane = &intel_plane->base;
3190         struct drm_framebuffer *fb = plane->state->fb;
3191         struct intel_plane_state *intel_pstate =
3192                                         to_intel_plane_state(plane->state);
3193         uint32_t latency = dev_priv->wm.skl_latency[level];
3194         uint32_t method1, method2;
3195         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3196         uint32_t res_blocks, res_lines;
3197         uint32_t selected_result;
3198         uint8_t cpp;
3199         uint32_t width = 0, height = 0;
3200
3201         if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
3202                 return false;
3203
3204         width = drm_rect_width(&intel_pstate->src) >> 16;
3205         height = drm_rect_height(&intel_pstate->src) >> 16;
3206
3207         if (intel_rotation_90_or_270(plane->state->rotation))
3208                 swap(width, height);
3209
3210         cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3211         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3212                                  cpp, latency);
3213         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3214                                  cstate->base.adjusted_mode.crtc_htotal,
3215                                  width,
3216                                  cpp,
3217                                  fb->modifier[0],
3218                                  latency);
3219
3220         plane_bytes_per_line = width * cpp;
3221         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3222
3223         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3224             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3225                 uint32_t min_scanlines = 4;
3226                 uint32_t y_tile_minimum;
3227                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3228                         int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3229                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3230                                 drm_format_plane_cpp(fb->pixel_format, 0);
3231
3232                         switch (cpp) {
3233                         case 1:
3234                                 min_scanlines = 16;
3235                                 break;
3236                         case 2:
3237                                 min_scanlines = 8;
3238                                 break;
3239                         case 8:
3240                                 WARN(1, "Unsupported pixel depth for rotation");
3241                         }
3242                 }
3243                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3244                 selected_result = max(method2, y_tile_minimum);
3245         } else {
3246                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3247                         selected_result = min(method1, method2);
3248                 else
3249                         selected_result = method1;
3250         }
3251
3252         res_blocks = selected_result + 1;
3253         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3254
3255         if (level >= 1 && level <= 7) {
3256                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3257                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3258                         res_lines += 4;
3259                 else
3260                         res_blocks++;
3261         }
3262
3263         if (res_blocks >= ddb_allocation || res_lines > 31)
3264                 return false;
3265
3266         *out_blocks = res_blocks;
3267         *out_lines = res_lines;
3268
3269         return true;
3270 }
3271
3272 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3273                                  struct skl_ddb_allocation *ddb,
3274                                  struct intel_crtc_state *cstate,
3275                                  int level,
3276                                  struct skl_wm_level *result)
3277 {
3278         struct drm_device *dev = dev_priv->dev;
3279         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3280         struct intel_plane *intel_plane;
3281         uint16_t ddb_blocks;
3282         enum pipe pipe = intel_crtc->pipe;
3283
3284         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3285                 int i = skl_wm_plane_id(intel_plane);
3286
3287                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3288
3289                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3290                                                 cstate,
3291                                                 intel_plane,
3292                                                 ddb_blocks,
3293                                                 level,
3294                                                 &result->plane_res_b[i],
3295                                                 &result->plane_res_l[i]);
3296         }
3297 }
3298
3299 static uint32_t
3300 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3301 {
3302         if (!cstate->base.active)
3303                 return 0;
3304
3305         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3306                 return 0;
3307
3308         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3309                             skl_pipe_pixel_rate(cstate));
3310 }
3311
3312 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3313                                       struct skl_wm_level *trans_wm /* out */)
3314 {
3315         struct drm_crtc *crtc = cstate->base.crtc;
3316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3317         struct intel_plane *intel_plane;
3318
3319         if (!cstate->base.active)
3320                 return;
3321
3322         /* Until we know more, just disable transition WMs */
3323         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3324                 int i = skl_wm_plane_id(intel_plane);
3325
3326                 trans_wm->plane_en[i] = false;
3327         }
3328 }
3329
3330 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3331                                 struct skl_ddb_allocation *ddb,
3332                                 struct skl_pipe_wm *pipe_wm)
3333 {
3334         struct drm_device *dev = cstate->base.crtc->dev;
3335         const struct drm_i915_private *dev_priv = dev->dev_private;
3336         int level, max_level = ilk_wm_max_level(dev);
3337
3338         for (level = 0; level <= max_level; level++) {
3339                 skl_compute_wm_level(dev_priv, ddb, cstate,
3340                                      level, &pipe_wm->wm[level]);
3341         }
3342         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3343
3344         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3345 }
3346
3347 static void skl_compute_wm_results(struct drm_device *dev,
3348                                    struct skl_pipe_wm *p_wm,
3349                                    struct skl_wm_values *r,
3350                                    struct intel_crtc *intel_crtc)
3351 {
3352         int level, max_level = ilk_wm_max_level(dev);
3353         enum pipe pipe = intel_crtc->pipe;
3354         uint32_t temp;
3355         int i;
3356
3357         for (level = 0; level <= max_level; level++) {
3358                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3359                         temp = 0;
3360
3361                         temp |= p_wm->wm[level].plane_res_l[i] <<
3362                                         PLANE_WM_LINES_SHIFT;
3363                         temp |= p_wm->wm[level].plane_res_b[i];
3364                         if (p_wm->wm[level].plane_en[i])
3365                                 temp |= PLANE_WM_EN;
3366
3367                         r->plane[pipe][i][level] = temp;
3368                 }
3369
3370                 temp = 0;
3371
3372                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3373                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3374
3375                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3376                         temp |= PLANE_WM_EN;
3377
3378                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3379
3380         }
3381
3382         /* transition WMs */
3383         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3384                 temp = 0;
3385                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3386                 temp |= p_wm->trans_wm.plane_res_b[i];
3387                 if (p_wm->trans_wm.plane_en[i])
3388                         temp |= PLANE_WM_EN;
3389
3390                 r->plane_trans[pipe][i] = temp;
3391         }
3392
3393         temp = 0;
3394         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3395         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3396         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3397                 temp |= PLANE_WM_EN;
3398
3399         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3400
3401         r->wm_linetime[pipe] = p_wm->linetime;
3402 }
3403
3404 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3405                                 i915_reg_t reg,
3406                                 const struct skl_ddb_entry *entry)
3407 {
3408         if (entry->end)
3409                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3410         else
3411                 I915_WRITE(reg, 0);
3412 }
3413
3414 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3415                                 const struct skl_wm_values *new)
3416 {
3417         struct drm_device *dev = dev_priv->dev;
3418         struct intel_crtc *crtc;
3419
3420         for_each_intel_crtc(dev, crtc) {
3421                 int i, level, max_level = ilk_wm_max_level(dev);
3422                 enum pipe pipe = crtc->pipe;
3423
3424                 if (!new->dirty[pipe])
3425                         continue;
3426
3427                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3428
3429                 for (level = 0; level <= max_level; level++) {
3430                         for (i = 0; i < intel_num_planes(crtc); i++)
3431                                 I915_WRITE(PLANE_WM(pipe, i, level),
3432                                            new->plane[pipe][i][level]);
3433                         I915_WRITE(CUR_WM(pipe, level),
3434                                    new->plane[pipe][PLANE_CURSOR][level]);
3435                 }
3436                 for (i = 0; i < intel_num_planes(crtc); i++)
3437                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3438                                    new->plane_trans[pipe][i]);
3439                 I915_WRITE(CUR_WM_TRANS(pipe),
3440                            new->plane_trans[pipe][PLANE_CURSOR]);
3441
3442                 for (i = 0; i < intel_num_planes(crtc); i++) {
3443                         skl_ddb_entry_write(dev_priv,
3444                                             PLANE_BUF_CFG(pipe, i),
3445                                             &new->ddb.plane[pipe][i]);
3446                         skl_ddb_entry_write(dev_priv,
3447                                             PLANE_NV12_BUF_CFG(pipe, i),
3448                                             &new->ddb.y_plane[pipe][i]);
3449                 }
3450
3451                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3452                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3453         }
3454 }
3455
3456 /*
3457  * When setting up a new DDB allocation arrangement, we need to correctly
3458  * sequence the times at which the new allocations for the pipes are taken into
3459  * account or we'll have pipes fetching from space previously allocated to
3460  * another pipe.
3461  *
3462  * Roughly the sequence looks like:
3463  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3464  *     overlapping with a previous light-up pipe (another way to put it is:
3465  *     pipes with their new allocation strickly included into their old ones).
3466  *  2. re-allocate the other pipes that get their allocation reduced
3467  *  3. allocate the pipes having their allocation increased
3468  *
3469  * Steps 1. and 2. are here to take care of the following case:
3470  * - Initially DDB looks like this:
3471  *     |   B    |   C    |
3472  * - enable pipe A.
3473  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3474  *   allocation
3475  *     |  A  |  B  |  C  |
3476  *
3477  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3478  */
3479
3480 static void
3481 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3482 {
3483         int plane;
3484
3485         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3486
3487         for_each_plane(dev_priv, pipe, plane) {
3488                 I915_WRITE(PLANE_SURF(pipe, plane),
3489                            I915_READ(PLANE_SURF(pipe, plane)));
3490         }
3491         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3492 }
3493
3494 static bool
3495 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3496                             const struct skl_ddb_allocation *new,
3497                             enum pipe pipe)
3498 {
3499         uint16_t old_size, new_size;
3500
3501         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3502         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3503
3504         return old_size != new_size &&
3505                new->pipe[pipe].start >= old->pipe[pipe].start &&
3506                new->pipe[pipe].end <= old->pipe[pipe].end;
3507 }
3508
3509 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3510                                 struct skl_wm_values *new_values)
3511 {
3512         struct drm_device *dev = dev_priv->dev;
3513         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3514         bool reallocated[I915_MAX_PIPES] = {};
3515         struct intel_crtc *crtc;
3516         enum pipe pipe;
3517
3518         new_ddb = &new_values->ddb;
3519         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3520
3521         /*
3522          * First pass: flush the pipes with the new allocation contained into
3523          * the old space.
3524          *
3525          * We'll wait for the vblank on those pipes to ensure we can safely
3526          * re-allocate the freed space without this pipe fetching from it.
3527          */
3528         for_each_intel_crtc(dev, crtc) {
3529                 if (!crtc->active)
3530                         continue;
3531
3532                 pipe = crtc->pipe;
3533
3534                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3535                         continue;
3536
3537                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3538                 intel_wait_for_vblank(dev, pipe);
3539
3540                 reallocated[pipe] = true;
3541         }
3542
3543
3544         /*
3545          * Second pass: flush the pipes that are having their allocation
3546          * reduced, but overlapping with a previous allocation.
3547          *
3548          * Here as well we need to wait for the vblank to make sure the freed
3549          * space is not used anymore.
3550          */
3551         for_each_intel_crtc(dev, crtc) {
3552                 if (!crtc->active)
3553                         continue;
3554
3555                 pipe = crtc->pipe;
3556
3557                 if (reallocated[pipe])
3558                         continue;
3559
3560                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3561                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3562                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3563                         intel_wait_for_vblank(dev, pipe);
3564                         reallocated[pipe] = true;
3565                 }
3566         }
3567
3568         /*
3569          * Third pass: flush the pipes that got more space allocated.
3570          *
3571          * We don't need to actively wait for the update here, next vblank
3572          * will just get more DDB space with the correct WM values.
3573          */
3574         for_each_intel_crtc(dev, crtc) {
3575                 if (!crtc->active)
3576                         continue;
3577
3578                 pipe = crtc->pipe;
3579
3580                 /*
3581                  * At this point, only the pipes more space than before are
3582                  * left to re-allocate.
3583                  */
3584                 if (reallocated[pipe])
3585                         continue;
3586
3587                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3588         }
3589 }
3590
3591 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3592                                struct skl_ddb_allocation *ddb, /* out */
3593                                struct skl_pipe_wm *pipe_wm /* out */)
3594 {
3595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3597
3598         skl_allocate_pipe_ddb(cstate, ddb);
3599         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3600
3601         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3602                 return false;
3603
3604         intel_crtc->wm.active.skl = *pipe_wm;
3605
3606         return true;
3607 }
3608
3609 static void skl_update_other_pipe_wm(struct drm_device *dev,
3610                                      struct drm_crtc *crtc,
3611                                      struct skl_wm_values *r)
3612 {
3613         struct intel_crtc *intel_crtc;
3614         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3615
3616         /*
3617          * If the WM update hasn't changed the allocation for this_crtc (the
3618          * crtc we are currently computing the new WM values for), other
3619          * enabled crtcs will keep the same allocation and we don't need to
3620          * recompute anything for them.
3621          */
3622         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3623                 return;
3624
3625         /*
3626          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3627          * other active pipes need new DDB allocation and WM values.
3628          */
3629         for_each_intel_crtc(dev, intel_crtc) {
3630                 struct skl_pipe_wm pipe_wm = {};
3631                 bool wm_changed;
3632
3633                 if (this_crtc->pipe == intel_crtc->pipe)
3634                         continue;
3635
3636                 if (!intel_crtc->active)
3637                         continue;
3638
3639                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3640                                                 &r->ddb, &pipe_wm);
3641
3642                 /*
3643                  * If we end up re-computing the other pipe WM values, it's
3644                  * because it was really needed, so we expect the WM values to
3645                  * be different.
3646                  */
3647                 WARN_ON(!wm_changed);
3648
3649                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3650                 r->dirty[intel_crtc->pipe] = true;
3651         }
3652 }
3653
3654 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3655 {
3656         watermarks->wm_linetime[pipe] = 0;
3657         memset(watermarks->plane[pipe], 0,
3658                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3659         memset(watermarks->plane_trans[pipe],
3660                0, sizeof(uint32_t) * I915_MAX_PLANES);
3661         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3662
3663         /* Clear ddb entries for pipe */
3664         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3665         memset(&watermarks->ddb.plane[pipe], 0,
3666                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3667         memset(&watermarks->ddb.y_plane[pipe], 0,
3668                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3669         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3670                sizeof(struct skl_ddb_entry));
3671
3672 }
3673
3674 static void skl_update_wm(struct drm_crtc *crtc)
3675 {
3676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677         struct drm_device *dev = crtc->dev;
3678         struct drm_i915_private *dev_priv = dev->dev_private;
3679         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3680         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3681         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3682
3683
3684         /* Clear all dirty flags */
3685         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3686
3687         skl_clear_wm(results, intel_crtc->pipe);
3688
3689         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3690                 return;
3691
3692         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3693         results->dirty[intel_crtc->pipe] = true;
3694
3695         skl_update_other_pipe_wm(dev, crtc, results);
3696         skl_write_wm_values(dev_priv, results);
3697         skl_flush_wm_values(dev_priv, results);
3698
3699         /* store the new configuration */
3700         dev_priv->wm.skl_hw = *results;
3701 }
3702
3703 static void ilk_compute_wm_config(struct drm_device *dev,
3704                                   struct intel_wm_config *config)
3705 {
3706         struct intel_crtc *crtc;
3707
3708         /* Compute the currently _active_ config */
3709         for_each_intel_crtc(dev, crtc) {
3710                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3711
3712                 if (!wm->pipe_enabled)
3713                         continue;
3714
3715                 config->sprites_enabled |= wm->sprites_enabled;
3716                 config->sprites_scaled |= wm->sprites_scaled;
3717                 config->num_pipes_active++;
3718         }
3719 }
3720
3721 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3722 {
3723         struct drm_device *dev = dev_priv->dev;
3724         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3725         struct ilk_wm_maximums max;
3726         struct intel_wm_config config = {};
3727         struct ilk_wm_values results = {};
3728         enum intel_ddb_partitioning partitioning;
3729
3730         ilk_compute_wm_config(dev, &config);
3731
3732         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3733         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3734
3735         /* 5/6 split only in single pipe config on IVB+ */
3736         if (INTEL_INFO(dev)->gen >= 7 &&
3737             config.num_pipes_active == 1 && config.sprites_enabled) {
3738                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3739                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3740
3741                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3742         } else {
3743                 best_lp_wm = &lp_wm_1_2;
3744         }
3745
3746         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3747                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3748
3749         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3750
3751         ilk_write_wm_values(dev_priv, &results);
3752 }
3753
3754 static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
3755 {
3756         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3757         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3758
3759         mutex_lock(&dev_priv->wm.wm_mutex);
3760         intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3761         ilk_program_watermarks(dev_priv);
3762         mutex_unlock(&dev_priv->wm.wm_mutex);
3763 }
3764
3765 static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3766 {
3767         struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3768         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3769
3770         mutex_lock(&dev_priv->wm.wm_mutex);
3771         if (cstate->wm.need_postvbl_update) {
3772                 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3773                 ilk_program_watermarks(dev_priv);
3774         }
3775         mutex_unlock(&dev_priv->wm.wm_mutex);
3776 }
3777
3778 static void skl_pipe_wm_active_state(uint32_t val,
3779                                      struct skl_pipe_wm *active,
3780                                      bool is_transwm,
3781                                      bool is_cursor,
3782                                      int i,
3783                                      int level)
3784 {
3785         bool is_enabled = (val & PLANE_WM_EN) != 0;
3786
3787         if (!is_transwm) {
3788                 if (!is_cursor) {
3789                         active->wm[level].plane_en[i] = is_enabled;
3790                         active->wm[level].plane_res_b[i] =
3791                                         val & PLANE_WM_BLOCKS_MASK;
3792                         active->wm[level].plane_res_l[i] =
3793                                         (val >> PLANE_WM_LINES_SHIFT) &
3794                                                 PLANE_WM_LINES_MASK;
3795                 } else {
3796                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3797                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3798                                         val & PLANE_WM_BLOCKS_MASK;
3799                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3800                                         (val >> PLANE_WM_LINES_SHIFT) &
3801                                                 PLANE_WM_LINES_MASK;
3802                 }
3803         } else {
3804                 if (!is_cursor) {
3805                         active->trans_wm.plane_en[i] = is_enabled;
3806                         active->trans_wm.plane_res_b[i] =
3807                                         val & PLANE_WM_BLOCKS_MASK;
3808                         active->trans_wm.plane_res_l[i] =
3809                                         (val >> PLANE_WM_LINES_SHIFT) &
3810                                                 PLANE_WM_LINES_MASK;
3811                 } else {
3812                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3813                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3814                                         val & PLANE_WM_BLOCKS_MASK;
3815                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3816                                         (val >> PLANE_WM_LINES_SHIFT) &
3817                                                 PLANE_WM_LINES_MASK;
3818                 }
3819         }
3820 }
3821
3822 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3823 {
3824         struct drm_device *dev = crtc->dev;
3825         struct drm_i915_private *dev_priv = dev->dev_private;
3826         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3827         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3829         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3830         enum pipe pipe = intel_crtc->pipe;
3831         int level, i, max_level;
3832         uint32_t temp;
3833
3834         max_level = ilk_wm_max_level(dev);
3835
3836         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3837
3838         for (level = 0; level <= max_level; level++) {
3839                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3840                         hw->plane[pipe][i][level] =
3841                                         I915_READ(PLANE_WM(pipe, i, level));
3842                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3843         }
3844
3845         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3846                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3847         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3848
3849         if (!intel_crtc->active)
3850                 return;
3851
3852         hw->dirty[pipe] = true;
3853
3854         active->linetime = hw->wm_linetime[pipe];
3855
3856         for (level = 0; level <= max_level; level++) {
3857                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3858                         temp = hw->plane[pipe][i][level];
3859                         skl_pipe_wm_active_state(temp, active, false,
3860                                                 false, i, level);
3861                 }
3862                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3863                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3864         }
3865
3866         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3867                 temp = hw->plane_trans[pipe][i];
3868                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3869         }
3870
3871         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3872         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3873
3874         intel_crtc->wm.active.skl = *active;
3875 }
3876
3877 void skl_wm_get_hw_state(struct drm_device *dev)
3878 {
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3881         struct drm_crtc *crtc;
3882
3883         skl_ddb_get_hw_state(dev_priv, ddb);
3884         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3885                 skl_pipe_wm_get_hw_state(crtc);
3886 }
3887
3888 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3889 {
3890         struct drm_device *dev = crtc->dev;
3891         struct drm_i915_private *dev_priv = dev->dev_private;
3892         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3893         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3894         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3895         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3896         enum pipe pipe = intel_crtc->pipe;
3897         static const i915_reg_t wm0_pipe_reg[] = {
3898                 [PIPE_A] = WM0_PIPEA_ILK,
3899                 [PIPE_B] = WM0_PIPEB_ILK,
3900                 [PIPE_C] = WM0_PIPEC_IVB,
3901         };
3902
3903         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3904         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3905                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3906
3907         active->pipe_enabled = intel_crtc->active;
3908
3909         if (active->pipe_enabled) {
3910                 u32 tmp = hw->wm_pipe[pipe];
3911
3912                 /*
3913                  * For active pipes LP0 watermark is marked as
3914                  * enabled, and LP1+ watermaks as disabled since
3915                  * we can't really reverse compute them in case
3916                  * multiple pipes are active.
3917                  */
3918                 active->wm[0].enable = true;
3919                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3920                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3921                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3922                 active->linetime = hw->wm_linetime[pipe];
3923         } else {
3924                 int level, max_level = ilk_wm_max_level(dev);
3925
3926                 /*
3927                  * For inactive pipes, all watermark levels
3928                  * should be marked as enabled but zeroed,
3929                  * which is what we'd compute them to.
3930                  */
3931                 for (level = 0; level <= max_level; level++)
3932                         active->wm[level].enable = true;
3933         }
3934
3935         intel_crtc->wm.active.ilk = *active;
3936 }
3937
3938 #define _FW_WM(value, plane) \
3939         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3940 #define _FW_WM_VLV(value, plane) \
3941         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3942
3943 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3944                                struct vlv_wm_values *wm)
3945 {
3946         enum pipe pipe;
3947         uint32_t tmp;
3948
3949         for_each_pipe(dev_priv, pipe) {
3950                 tmp = I915_READ(VLV_DDL(pipe));
3951
3952                 wm->ddl[pipe].primary =
3953                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3954                 wm->ddl[pipe].cursor =
3955                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3956                 wm->ddl[pipe].sprite[0] =
3957                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3958                 wm->ddl[pipe].sprite[1] =
3959                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3960         }
3961
3962         tmp = I915_READ(DSPFW1);
3963         wm->sr.plane = _FW_WM(tmp, SR);
3964         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3965         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3966         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3967
3968         tmp = I915_READ(DSPFW2);
3969         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3970         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3971         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3972
3973         tmp = I915_READ(DSPFW3);
3974         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3975
3976         if (IS_CHERRYVIEW(dev_priv)) {
3977                 tmp = I915_READ(DSPFW7_CHV);
3978                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3979                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3980
3981                 tmp = I915_READ(DSPFW8_CHV);
3982                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3983                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3984
3985                 tmp = I915_READ(DSPFW9_CHV);
3986                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3987                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3988
3989                 tmp = I915_READ(DSPHOWM);
3990                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3991                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3992                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3993                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3994                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3995                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3996                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3997                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3998                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3999                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4000         } else {
4001                 tmp = I915_READ(DSPFW7);
4002                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4003                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4004
4005                 tmp = I915_READ(DSPHOWM);
4006                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4007                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4008                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4009                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4010                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4011                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4012                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4013         }
4014 }
4015
4016 #undef _FW_WM
4017 #undef _FW_WM_VLV
4018
4019 void vlv_wm_get_hw_state(struct drm_device *dev)
4020 {
4021         struct drm_i915_private *dev_priv = to_i915(dev);
4022         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4023         struct intel_plane *plane;
4024         enum pipe pipe;
4025         u32 val;
4026
4027         vlv_read_wm_values(dev_priv, wm);
4028
4029         for_each_intel_plane(dev, plane) {
4030                 switch (plane->base.type) {
4031                         int sprite;
4032                 case DRM_PLANE_TYPE_CURSOR:
4033                         plane->wm.fifo_size = 63;
4034                         break;
4035                 case DRM_PLANE_TYPE_PRIMARY:
4036                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4037                         break;
4038                 case DRM_PLANE_TYPE_OVERLAY:
4039                         sprite = plane->plane;
4040                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4041                         break;
4042                 }
4043         }
4044
4045         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4046         wm->level = VLV_WM_LEVEL_PM2;
4047
4048         if (IS_CHERRYVIEW(dev_priv)) {
4049                 mutex_lock(&dev_priv->rps.hw_lock);
4050
4051                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4052                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4053                         wm->level = VLV_WM_LEVEL_PM5;
4054
4055                 /*
4056                  * If DDR DVFS is disabled in the BIOS, Punit
4057                  * will never ack the request. So if that happens
4058                  * assume we don't have to enable/disable DDR DVFS
4059                  * dynamically. To test that just set the REQ_ACK
4060                  * bit to poke the Punit, but don't change the
4061                  * HIGH/LOW bits so that we don't actually change
4062                  * the current state.
4063                  */
4064                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4065                 val |= FORCE_DDR_FREQ_REQ_ACK;
4066                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4067
4068                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4069                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4070                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4071                                       "assuming DDR DVFS is disabled\n");
4072                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4073                 } else {
4074                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4075                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4076                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4077                 }
4078
4079                 mutex_unlock(&dev_priv->rps.hw_lock);
4080         }
4081
4082         for_each_pipe(dev_priv, pipe)
4083                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4084                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4085                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4086
4087         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4088                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4089 }
4090
4091 void ilk_wm_get_hw_state(struct drm_device *dev)
4092 {
4093         struct drm_i915_private *dev_priv = dev->dev_private;
4094         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4095         struct drm_crtc *crtc;
4096
4097         for_each_crtc(dev, crtc)
4098                 ilk_pipe_wm_get_hw_state(crtc);
4099
4100         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4101         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4102         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4103
4104         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4105         if (INTEL_INFO(dev)->gen >= 7) {
4106                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4107                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4108         }
4109
4110         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4111                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4112                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4113         else if (IS_IVYBRIDGE(dev))
4114                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4115                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4116
4117         hw->enable_fbc_wm =
4118                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4119 }
4120
4121 /**
4122  * intel_update_watermarks - update FIFO watermark values based on current modes
4123  *
4124  * Calculate watermark values for the various WM regs based on current mode
4125  * and plane configuration.
4126  *
4127  * There are several cases to deal with here:
4128  *   - normal (i.e. non-self-refresh)
4129  *   - self-refresh (SR) mode
4130  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4131  *   - lines are small relative to FIFO size (buffer can hold more than 2
4132  *     lines), so need to account for TLB latency
4133  *
4134  *   The normal calculation is:
4135  *     watermark = dotclock * bytes per pixel * latency
4136  *   where latency is platform & configuration dependent (we assume pessimal
4137  *   values here).
4138  *
4139  *   The SR calculation is:
4140  *     watermark = (trunc(latency/line time)+1) * surface width *
4141  *       bytes per pixel
4142  *   where
4143  *     line time = htotal / dotclock
4144  *     surface width = hdisplay for normal plane and 64 for cursor
4145  *   and latency is assumed to be high, as above.
4146  *
4147  * The final value programmed to the register should always be rounded up,
4148  * and include an extra 2 entries to account for clock crossings.
4149  *
4150  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4151  * to set the non-SR watermarks to 8.
4152  */
4153 void intel_update_watermarks(struct drm_crtc *crtc)
4154 {
4155         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4156
4157         if (dev_priv->display.update_wm)
4158                 dev_priv->display.update_wm(crtc);
4159 }
4160
4161 /*
4162  * Lock protecting IPS related data structures
4163  */
4164 DEFINE_SPINLOCK(mchdev_lock);
4165
4166 /* Global for IPS driver to get at the current i915 device. Protected by
4167  * mchdev_lock. */
4168 static struct drm_i915_private *i915_mch_dev;
4169
4170 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4171 {
4172         struct drm_i915_private *dev_priv = dev->dev_private;
4173         u16 rgvswctl;
4174
4175         assert_spin_locked(&mchdev_lock);
4176
4177         rgvswctl = I915_READ16(MEMSWCTL);
4178         if (rgvswctl & MEMCTL_CMD_STS) {
4179                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4180                 return false; /* still busy with another command */
4181         }
4182
4183         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4184                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4185         I915_WRITE16(MEMSWCTL, rgvswctl);
4186         POSTING_READ16(MEMSWCTL);
4187
4188         rgvswctl |= MEMCTL_CMD_STS;
4189         I915_WRITE16(MEMSWCTL, rgvswctl);
4190
4191         return true;
4192 }
4193
4194 static void ironlake_enable_drps(struct drm_device *dev)
4195 {
4196         struct drm_i915_private *dev_priv = dev->dev_private;
4197         u32 rgvmodectl;
4198         u8 fmax, fmin, fstart, vstart;
4199
4200         spin_lock_irq(&mchdev_lock);
4201
4202         rgvmodectl = I915_READ(MEMMODECTL);
4203
4204         /* Enable temp reporting */
4205         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4206         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4207
4208         /* 100ms RC evaluation intervals */
4209         I915_WRITE(RCUPEI, 100000);
4210         I915_WRITE(RCDNEI, 100000);
4211
4212         /* Set max/min thresholds to 90ms and 80ms respectively */
4213         I915_WRITE(RCBMAXAVG, 90000);
4214         I915_WRITE(RCBMINAVG, 80000);
4215
4216         I915_WRITE(MEMIHYST, 1);
4217
4218         /* Set up min, max, and cur for interrupt handling */
4219         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4220         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4221         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4222                 MEMMODE_FSTART_SHIFT;
4223
4224         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4225                 PXVFREQ_PX_SHIFT;
4226
4227         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4228         dev_priv->ips.fstart = fstart;
4229
4230         dev_priv->ips.max_delay = fstart;
4231         dev_priv->ips.min_delay = fmin;
4232         dev_priv->ips.cur_delay = fstart;
4233
4234         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4235                          fmax, fmin, fstart);
4236
4237         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4238
4239         /*
4240          * Interrupts will be enabled in ironlake_irq_postinstall
4241          */
4242
4243         I915_WRITE(VIDSTART, vstart);
4244         POSTING_READ(VIDSTART);
4245
4246         rgvmodectl |= MEMMODE_SWMODE_EN;
4247         I915_WRITE(MEMMODECTL, rgvmodectl);
4248
4249         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4250                 DRM_ERROR("stuck trying to change perf mode\n");
4251         mdelay(1);
4252
4253         ironlake_set_drps(dev, fstart);
4254
4255         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4256                 I915_READ(DDREC) + I915_READ(CSIEC);
4257         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4258         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4259         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4260
4261         spin_unlock_irq(&mchdev_lock);
4262 }
4263
4264 static void ironlake_disable_drps(struct drm_device *dev)
4265 {
4266         struct drm_i915_private *dev_priv = dev->dev_private;
4267         u16 rgvswctl;
4268
4269         spin_lock_irq(&mchdev_lock);
4270
4271         rgvswctl = I915_READ16(MEMSWCTL);
4272
4273         /* Ack interrupts, disable EFC interrupt */
4274         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4275         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4276         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4277         I915_WRITE(DEIIR, DE_PCU_EVENT);
4278         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4279
4280         /* Go back to the starting frequency */
4281         ironlake_set_drps(dev, dev_priv->ips.fstart);
4282         mdelay(1);
4283         rgvswctl |= MEMCTL_CMD_STS;
4284         I915_WRITE(MEMSWCTL, rgvswctl);
4285         mdelay(1);
4286
4287         spin_unlock_irq(&mchdev_lock);
4288 }
4289
4290 /* There's a funny hw issue where the hw returns all 0 when reading from
4291  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4292  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4293  * all limits and the gpu stuck at whatever frequency it is at atm).
4294  */
4295 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4296 {
4297         u32 limits;
4298
4299         /* Only set the down limit when we've reached the lowest level to avoid
4300          * getting more interrupts, otherwise leave this clear. This prevents a
4301          * race in the hw when coming out of rc6: There's a tiny window where
4302          * the hw runs at the minimal clock before selecting the desired
4303          * frequency, if the down threshold expires in that window we will not
4304          * receive a down interrupt. */
4305         if (IS_GEN9(dev_priv)) {
4306                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4307                 if (val <= dev_priv->rps.min_freq_softlimit)
4308                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4309         } else {
4310                 limits = dev_priv->rps.max_freq_softlimit << 24;
4311                 if (val <= dev_priv->rps.min_freq_softlimit)
4312                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4313         }
4314
4315         return limits;
4316 }
4317
4318 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4319 {
4320         int new_power;
4321         u32 threshold_up = 0, threshold_down = 0; /* in % */
4322         u32 ei_up = 0, ei_down = 0;
4323
4324         new_power = dev_priv->rps.power;
4325         switch (dev_priv->rps.power) {
4326         case LOW_POWER:
4327                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4328                         new_power = BETWEEN;
4329                 break;
4330
4331         case BETWEEN:
4332                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4333                         new_power = LOW_POWER;
4334                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4335                         new_power = HIGH_POWER;
4336                 break;
4337
4338         case HIGH_POWER:
4339                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4340                         new_power = BETWEEN;
4341                 break;
4342         }
4343         /* Max/min bins are special */
4344         if (val <= dev_priv->rps.min_freq_softlimit)
4345                 new_power = LOW_POWER;
4346         if (val >= dev_priv->rps.max_freq_softlimit)
4347                 new_power = HIGH_POWER;
4348         if (new_power == dev_priv->rps.power)
4349                 return;
4350
4351         /* Note the units here are not exactly 1us, but 1280ns. */
4352         switch (new_power) {
4353         case LOW_POWER:
4354                 /* Upclock if more than 95% busy over 16ms */
4355                 ei_up = 16000;
4356                 threshold_up = 95;
4357
4358                 /* Downclock if less than 85% busy over 32ms */
4359                 ei_down = 32000;
4360                 threshold_down = 85;
4361                 break;
4362
4363         case BETWEEN:
4364                 /* Upclock if more than 90% busy over 13ms */
4365                 ei_up = 13000;
4366                 threshold_up = 90;
4367
4368                 /* Downclock if less than 75% busy over 32ms */
4369                 ei_down = 32000;
4370                 threshold_down = 75;
4371                 break;
4372
4373         case HIGH_POWER:
4374                 /* Upclock if more than 85% busy over 10ms */
4375                 ei_up = 10000;
4376                 threshold_up = 85;
4377
4378                 /* Downclock if less than 60% busy over 32ms */
4379                 ei_down = 32000;
4380                 threshold_down = 60;
4381                 break;
4382         }
4383
4384         I915_WRITE(GEN6_RP_UP_EI,
4385                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4386         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4387                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4388
4389         I915_WRITE(GEN6_RP_DOWN_EI,
4390                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4391         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4392                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4393
4394          I915_WRITE(GEN6_RP_CONTROL,
4395                     GEN6_RP_MEDIA_TURBO |
4396                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4397                     GEN6_RP_MEDIA_IS_GFX |
4398                     GEN6_RP_ENABLE |
4399                     GEN6_RP_UP_BUSY_AVG |
4400                     GEN6_RP_DOWN_IDLE_AVG);
4401
4402         dev_priv->rps.power = new_power;
4403         dev_priv->rps.up_threshold = threshold_up;
4404         dev_priv->rps.down_threshold = threshold_down;
4405         dev_priv->rps.last_adj = 0;
4406 }
4407
4408 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4409 {
4410         u32 mask = 0;
4411
4412         if (val > dev_priv->rps.min_freq_softlimit)
4413                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4414         if (val < dev_priv->rps.max_freq_softlimit)
4415                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4416
4417         mask &= dev_priv->pm_rps_events;
4418
4419         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4420 }
4421
4422 /* gen6_set_rps is called to update the frequency request, but should also be
4423  * called when the range (min_delay and max_delay) is modified so that we can
4424  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4425 static void gen6_set_rps(struct drm_device *dev, u8 val)
4426 {
4427         struct drm_i915_private *dev_priv = dev->dev_private;
4428
4429         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4430         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4431                 return;
4432
4433         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4434         WARN_ON(val > dev_priv->rps.max_freq);
4435         WARN_ON(val < dev_priv->rps.min_freq);
4436
4437         /* min/max delay may still have been modified so be sure to
4438          * write the limits value.
4439          */
4440         if (val != dev_priv->rps.cur_freq) {
4441                 gen6_set_rps_thresholds(dev_priv, val);
4442
4443                 if (IS_GEN9(dev))
4444                         I915_WRITE(GEN6_RPNSWREQ,
4445                                    GEN9_FREQUENCY(val));
4446                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4447                         I915_WRITE(GEN6_RPNSWREQ,
4448                                    HSW_FREQUENCY(val));
4449                 else
4450                         I915_WRITE(GEN6_RPNSWREQ,
4451                                    GEN6_FREQUENCY(val) |
4452                                    GEN6_OFFSET(0) |
4453                                    GEN6_AGGRESSIVE_TURBO);
4454         }
4455
4456         /* Make sure we continue to get interrupts
4457          * until we hit the minimum or maximum frequencies.
4458          */
4459         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4460         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4461
4462         POSTING_READ(GEN6_RPNSWREQ);
4463
4464         dev_priv->rps.cur_freq = val;
4465         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4466 }
4467
4468 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4469 {
4470         struct drm_i915_private *dev_priv = dev->dev_private;
4471
4472         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4473         WARN_ON(val > dev_priv->rps.max_freq);
4474         WARN_ON(val < dev_priv->rps.min_freq);
4475
4476         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4477                       "Odd GPU freq value\n"))
4478                 val &= ~1;
4479
4480         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4481
4482         if (val != dev_priv->rps.cur_freq) {
4483                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4484                 if (!IS_CHERRYVIEW(dev_priv))
4485                         gen6_set_rps_thresholds(dev_priv, val);
4486         }
4487
4488         dev_priv->rps.cur_freq = val;
4489         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4490 }
4491
4492 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4493  *
4494  * * If Gfx is Idle, then
4495  * 1. Forcewake Media well.
4496  * 2. Request idle freq.
4497  * 3. Release Forcewake of Media well.
4498 */
4499 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4500 {
4501         u32 val = dev_priv->rps.idle_freq;
4502
4503         if (dev_priv->rps.cur_freq <= val)
4504                 return;
4505
4506         /* Wake up the media well, as that takes a lot less
4507          * power than the Render well. */
4508         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4509         valleyview_set_rps(dev_priv->dev, val);
4510         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4511 }
4512
4513 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4514 {
4515         mutex_lock(&dev_priv->rps.hw_lock);
4516         if (dev_priv->rps.enabled) {
4517                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4518                         gen6_rps_reset_ei(dev_priv);
4519                 I915_WRITE(GEN6_PMINTRMSK,
4520                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4521         }
4522         mutex_unlock(&dev_priv->rps.hw_lock);
4523 }
4524
4525 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4526 {
4527         struct drm_device *dev = dev_priv->dev;
4528
4529         mutex_lock(&dev_priv->rps.hw_lock);
4530         if (dev_priv->rps.enabled) {
4531                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4532                         vlv_set_rps_idle(dev_priv);
4533                 else
4534                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4535                 dev_priv->rps.last_adj = 0;
4536                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4537         }
4538         mutex_unlock(&dev_priv->rps.hw_lock);
4539
4540         spin_lock(&dev_priv->rps.client_lock);
4541         while (!list_empty(&dev_priv->rps.clients))
4542                 list_del_init(dev_priv->rps.clients.next);
4543         spin_unlock(&dev_priv->rps.client_lock);
4544 }
4545
4546 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4547                     struct intel_rps_client *rps,
4548                     unsigned long submitted)
4549 {
4550         /* This is intentionally racy! We peek at the state here, then
4551          * validate inside the RPS worker.
4552          */
4553         if (!(dev_priv->mm.busy &&
4554               dev_priv->rps.enabled &&
4555               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4556                 return;
4557
4558         /* Force a RPS boost (and don't count it against the client) if
4559          * the GPU is severely congested.
4560          */
4561         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4562                 rps = NULL;
4563
4564         spin_lock(&dev_priv->rps.client_lock);
4565         if (rps == NULL || list_empty(&rps->link)) {
4566                 spin_lock_irq(&dev_priv->irq_lock);
4567                 if (dev_priv->rps.interrupts_enabled) {
4568                         dev_priv->rps.client_boost = true;
4569                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4570                 }
4571                 spin_unlock_irq(&dev_priv->irq_lock);
4572
4573                 if (rps != NULL) {
4574                         list_add(&rps->link, &dev_priv->rps.clients);
4575                         rps->boosts++;
4576                 } else
4577                         dev_priv->rps.boosts++;
4578         }
4579         spin_unlock(&dev_priv->rps.client_lock);
4580 }
4581
4582 void intel_set_rps(struct drm_device *dev, u8 val)
4583 {
4584         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4585                 valleyview_set_rps(dev, val);
4586         else
4587                 gen6_set_rps(dev, val);
4588 }
4589
4590 static void gen9_disable_rc6(struct drm_device *dev)
4591 {
4592         struct drm_i915_private *dev_priv = dev->dev_private;
4593
4594         I915_WRITE(GEN6_RC_CONTROL, 0);
4595         I915_WRITE(GEN9_PG_ENABLE, 0);
4596 }
4597
4598 static void gen9_disable_rps(struct drm_device *dev)
4599 {
4600         struct drm_i915_private *dev_priv = dev->dev_private;
4601
4602         I915_WRITE(GEN6_RP_CONTROL, 0);
4603 }
4604
4605 static void gen6_disable_rps(struct drm_device *dev)
4606 {
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608
4609         I915_WRITE(GEN6_RC_CONTROL, 0);
4610         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4611         I915_WRITE(GEN6_RP_CONTROL, 0);
4612 }
4613
4614 static void cherryview_disable_rps(struct drm_device *dev)
4615 {
4616         struct drm_i915_private *dev_priv = dev->dev_private;
4617
4618         I915_WRITE(GEN6_RC_CONTROL, 0);
4619 }
4620
4621 static void valleyview_disable_rps(struct drm_device *dev)
4622 {
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624
4625         /* we're doing forcewake before Disabling RC6,
4626          * This what the BIOS expects when going into suspend */
4627         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4628
4629         I915_WRITE(GEN6_RC_CONTROL, 0);
4630
4631         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4632 }
4633
4634 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4635 {
4636         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4637                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4638                         mode = GEN6_RC_CTL_RC6_ENABLE;
4639                 else
4640                         mode = 0;
4641         }
4642         if (HAS_RC6p(dev))
4643                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4644                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4645                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4646                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4647
4648         else
4649                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4650                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4651 }
4652
4653 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4654 {
4655         struct drm_i915_private *dev_priv = to_i915(dev);
4656         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4657         bool enable_rc6 = true;
4658         unsigned long rc6_ctx_base;
4659
4660         if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4661                 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4662                 enable_rc6 = false;
4663         }
4664
4665         /*
4666          * The exact context size is not known for BXT, so assume a page size
4667          * for this check.
4668          */
4669         rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
4670         if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4671               (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4672                                         ggtt->stolen_reserved_size))) {
4673                 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4674                 enable_rc6 = false;
4675         }
4676
4677         if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4678               ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4679               ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4680               ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4681                 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4682                 enable_rc6 = false;
4683         }
4684
4685         if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4686                                             GEN6_RC_CTL_HW_ENABLE)) &&
4687             ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4688              !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4689                 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4690                 enable_rc6 = false;
4691         }
4692
4693         return enable_rc6;
4694 }
4695
4696 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4697 {
4698         /* No RC6 before Ironlake and code is gone for ilk. */
4699         if (INTEL_INFO(dev)->gen < 6)
4700                 return 0;
4701
4702         if (!enable_rc6)
4703                 return 0;
4704
4705         if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4706                 DRM_INFO("RC6 disabled by BIOS\n");
4707                 return 0;
4708         }
4709
4710         /* Respect the kernel parameter if it is set */
4711         if (enable_rc6 >= 0) {
4712                 int mask;
4713
4714                 if (HAS_RC6p(dev))
4715                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4716                                INTEL_RC6pp_ENABLE;
4717                 else
4718                         mask = INTEL_RC6_ENABLE;
4719
4720                 if ((enable_rc6 & mask) != enable_rc6)
4721                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4722                                       enable_rc6 & mask, enable_rc6, mask);
4723
4724                 return enable_rc6 & mask;
4725         }
4726
4727         if (IS_IVYBRIDGE(dev))
4728                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4729
4730         return INTEL_RC6_ENABLE;
4731 }
4732
4733 int intel_enable_rc6(const struct drm_device *dev)
4734 {
4735         return i915.enable_rc6;
4736 }
4737
4738 static void gen6_init_rps_frequencies(struct drm_device *dev)
4739 {
4740         struct drm_i915_private *dev_priv = dev->dev_private;
4741         uint32_t rp_state_cap;
4742         u32 ddcc_status = 0;
4743         int ret;
4744
4745         /* All of these values are in units of 50MHz */
4746         dev_priv->rps.cur_freq          = 0;
4747         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4748         if (IS_BROXTON(dev)) {
4749                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4750                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4751                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4752                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4753         } else {
4754                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4755                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4756                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4757                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4758         }
4759
4760         /* hw_max = RP0 until we check for overclocking */
4761         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4762
4763         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4764         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4765             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4766                 ret = sandybridge_pcode_read(dev_priv,
4767                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4768                                         &ddcc_status);
4769                 if (0 == ret)
4770                         dev_priv->rps.efficient_freq =
4771                                 clamp_t(u8,
4772                                         ((ddcc_status >> 8) & 0xff),
4773                                         dev_priv->rps.min_freq,
4774                                         dev_priv->rps.max_freq);
4775         }
4776
4777         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4778                 /* Store the frequency values in 16.66 MHZ units, which is
4779                    the natural hardware unit for SKL */
4780                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4781                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4782                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4783                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4784                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4785         }
4786
4787         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4788
4789         /* Preserve min/max settings in case of re-init */
4790         if (dev_priv->rps.max_freq_softlimit == 0)
4791                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4792
4793         if (dev_priv->rps.min_freq_softlimit == 0) {
4794                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4795                         dev_priv->rps.min_freq_softlimit =
4796                                 max_t(int, dev_priv->rps.efficient_freq,
4797                                       intel_freq_opcode(dev_priv, 450));
4798                 else
4799                         dev_priv->rps.min_freq_softlimit =
4800                                 dev_priv->rps.min_freq;
4801         }
4802 }
4803
4804 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4805 static void gen9_enable_rps(struct drm_device *dev)
4806 {
4807         struct drm_i915_private *dev_priv = dev->dev_private;
4808
4809         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4810
4811         gen6_init_rps_frequencies(dev);
4812
4813         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4814         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4815                 /*
4816                  * BIOS could leave the Hw Turbo enabled, so need to explicitly
4817                  * clear out the Control register just to avoid inconsitency
4818                  * with debugfs interface, which will show  Turbo as enabled
4819                  * only and that is not expected by the User after adding the
4820                  * WaGsvDisableTurbo. Apart from this there is no problem even
4821                  * if the Turbo is left enabled in the Control register, as the
4822                  * Up/Down interrupts would remain masked.
4823                  */
4824                 gen9_disable_rps(dev);
4825                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4826                 return;
4827         }
4828
4829         /* Program defaults and thresholds for RPS*/
4830         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4831                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4832
4833         /* 1 second timeout*/
4834         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4835                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4836
4837         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4838
4839         /* Leaning on the below call to gen6_set_rps to program/setup the
4840          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4841          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4842         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4843         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4844
4845         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4846 }
4847
4848 static void gen9_enable_rc6(struct drm_device *dev)
4849 {
4850         struct drm_i915_private *dev_priv = dev->dev_private;
4851         struct intel_engine_cs *engine;
4852         uint32_t rc6_mask = 0;
4853
4854         /* 1a: Software RC state - RC0 */
4855         I915_WRITE(GEN6_RC_STATE, 0);
4856
4857         /* 1b: Get forcewake during program sequence. Although the driver
4858          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4859         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4860
4861         /* 2a: Disable RC states. */
4862         I915_WRITE(GEN6_RC_CONTROL, 0);
4863
4864         /* 2b: Program RC6 thresholds.*/
4865
4866         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4867         if (IS_SKYLAKE(dev))
4868                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4869         else
4870                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4871         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4872         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4873         for_each_engine(engine, dev_priv)
4874                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4875
4876         if (HAS_GUC_UCODE(dev))
4877                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4878
4879         I915_WRITE(GEN6_RC_SLEEP, 0);
4880
4881         /* 2c: Program Coarse Power Gating Policies. */
4882         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4883         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4884
4885         /* 3a: Enable RC6 */
4886         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4887                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4888         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4889         /* WaRsUseTimeoutMode */
4890         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4891             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4892                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4893                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4894                            GEN7_RC_CTL_TO_MODE |
4895                            rc6_mask);
4896         } else {
4897                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4898                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4899                            GEN6_RC_CTL_EI_MODE(1) |
4900                            rc6_mask);
4901         }
4902
4903         /*
4904          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4905          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4906          */
4907         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4908                 I915_WRITE(GEN9_PG_ENABLE, 0);
4909         else
4910                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4911                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4912
4913         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4914
4915 }
4916
4917 static void gen8_enable_rps(struct drm_device *dev)
4918 {
4919         struct drm_i915_private *dev_priv = dev->dev_private;
4920         struct intel_engine_cs *engine;
4921         uint32_t rc6_mask = 0;
4922
4923         /* 1a: Software RC state - RC0 */
4924         I915_WRITE(GEN6_RC_STATE, 0);
4925
4926         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4927          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4928         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4929
4930         /* 2a: Disable RC states. */
4931         I915_WRITE(GEN6_RC_CONTROL, 0);
4932
4933         /* Initialize rps frequencies */
4934         gen6_init_rps_frequencies(dev);
4935
4936         /* 2b: Program RC6 thresholds.*/
4937         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4938         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4939         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4940         for_each_engine(engine, dev_priv)
4941                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
4942         I915_WRITE(GEN6_RC_SLEEP, 0);
4943         if (IS_BROADWELL(dev))
4944                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4945         else
4946                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4947
4948         /* 3: Enable RC6 */
4949         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4950                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4951         intel_print_rc6_info(dev, rc6_mask);
4952         if (IS_BROADWELL(dev))
4953                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4954                                 GEN7_RC_CTL_TO_MODE |
4955                                 rc6_mask);
4956         else
4957                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4958                                 GEN6_RC_CTL_EI_MODE(1) |
4959                                 rc6_mask);
4960
4961         /* 4 Program defaults and thresholds for RPS*/
4962         I915_WRITE(GEN6_RPNSWREQ,
4963                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4964         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4965                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4966         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4967         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4968
4969         /* Docs recommend 900MHz, and 300 MHz respectively */
4970         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4971                    dev_priv->rps.max_freq_softlimit << 24 |
4972                    dev_priv->rps.min_freq_softlimit << 16);
4973
4974         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4975         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4976         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4977         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4978
4979         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4980
4981         /* 5: Enable RPS */
4982         I915_WRITE(GEN6_RP_CONTROL,
4983                    GEN6_RP_MEDIA_TURBO |
4984                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4985                    GEN6_RP_MEDIA_IS_GFX |
4986                    GEN6_RP_ENABLE |
4987                    GEN6_RP_UP_BUSY_AVG |
4988                    GEN6_RP_DOWN_IDLE_AVG);
4989
4990         /* 6: Ring frequency + overclocking (our driver does this later */
4991
4992         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4993         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4994
4995         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4996 }
4997
4998 static void gen6_enable_rps(struct drm_device *dev)
4999 {
5000         struct drm_i915_private *dev_priv = dev->dev_private;
5001         struct intel_engine_cs *engine;
5002         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
5003         u32 gtfifodbg;
5004         int rc6_mode;
5005         int ret;
5006
5007         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5008
5009         /* Here begins a magic sequence of register writes to enable
5010          * auto-downclocking.
5011          *
5012          * Perhaps there might be some value in exposing these to
5013          * userspace...
5014          */
5015         I915_WRITE(GEN6_RC_STATE, 0);
5016
5017         /* Clear the DBG now so we don't confuse earlier errors */
5018         gtfifodbg = I915_READ(GTFIFODBG);
5019         if (gtfifodbg) {
5020                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5021                 I915_WRITE(GTFIFODBG, gtfifodbg);
5022         }
5023
5024         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5025
5026         /* Initialize rps frequencies */
5027         gen6_init_rps_frequencies(dev);
5028
5029         /* disable the counters and set deterministic thresholds */
5030         I915_WRITE(GEN6_RC_CONTROL, 0);
5031
5032         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5033         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5034         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5035         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5036         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5037
5038         for_each_engine(engine, dev_priv)
5039                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5040
5041         I915_WRITE(GEN6_RC_SLEEP, 0);
5042         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
5043         if (IS_IVYBRIDGE(dev))
5044                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5045         else
5046                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
5047         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
5048         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5049
5050         /* Check if we are enabling RC6 */
5051         rc6_mode = intel_enable_rc6(dev_priv->dev);
5052         if (rc6_mode & INTEL_RC6_ENABLE)
5053                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5054
5055         /* We don't use those on Haswell */
5056         if (!IS_HASWELL(dev)) {
5057                 if (rc6_mode & INTEL_RC6p_ENABLE)
5058                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5059
5060                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5061                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5062         }
5063
5064         intel_print_rc6_info(dev, rc6_mask);
5065
5066         I915_WRITE(GEN6_RC_CONTROL,
5067                    rc6_mask |
5068                    GEN6_RC_CTL_EI_MODE(1) |
5069                    GEN6_RC_CTL_HW_ENABLE);
5070
5071         /* Power down if completely idle for over 50ms */
5072         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5073         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5074
5075         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5076         if (ret)
5077                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5078
5079         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5080         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5081                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5082                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5083                                  (pcu_mbox & 0xff) * 50);
5084                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5085         }
5086
5087         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5088         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5089
5090         rc6vids = 0;
5091         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5092         if (IS_GEN6(dev) && ret) {
5093                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5094         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5095                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5096                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5097                 rc6vids &= 0xffff00;
5098                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5099                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5100                 if (ret)
5101                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5102         }
5103
5104         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5105 }
5106
5107 static void __gen6_update_ring_freq(struct drm_device *dev)
5108 {
5109         struct drm_i915_private *dev_priv = dev->dev_private;
5110         int min_freq = 15;
5111         unsigned int gpu_freq;
5112         unsigned int max_ia_freq, min_ring_freq;
5113         unsigned int max_gpu_freq, min_gpu_freq;
5114         int scaling_factor = 180;
5115         struct cpufreq_policy *policy;
5116
5117         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5118
5119         policy = cpufreq_cpu_get(0);
5120         if (policy) {
5121                 max_ia_freq = policy->cpuinfo.max_freq;
5122                 cpufreq_cpu_put(policy);
5123         } else {
5124                 /*
5125                  * Default to measured freq if none found, PCU will ensure we
5126                  * don't go over
5127                  */
5128                 max_ia_freq = tsc_khz;
5129         }
5130
5131         /* Convert from kHz to MHz */
5132         max_ia_freq /= 1000;
5133
5134         min_ring_freq = I915_READ(DCLK) & 0xf;
5135         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5136         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5137
5138         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5139                 /* Convert GT frequency to 50 HZ units */
5140                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5141                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5142         } else {
5143                 min_gpu_freq = dev_priv->rps.min_freq;
5144                 max_gpu_freq = dev_priv->rps.max_freq;
5145         }
5146
5147         /*
5148          * For each potential GPU frequency, load a ring frequency we'd like
5149          * to use for memory access.  We do this by specifying the IA frequency
5150          * the PCU should use as a reference to determine the ring frequency.
5151          */
5152         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5153                 int diff = max_gpu_freq - gpu_freq;
5154                 unsigned int ia_freq = 0, ring_freq = 0;
5155
5156                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5157                         /*
5158                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5159                          * No floor required for ring frequency on SKL.
5160                          */
5161                         ring_freq = gpu_freq;
5162                 } else if (INTEL_INFO(dev)->gen >= 8) {
5163                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5164                         ring_freq = max(min_ring_freq, gpu_freq);
5165                 } else if (IS_HASWELL(dev)) {
5166                         ring_freq = mult_frac(gpu_freq, 5, 4);
5167                         ring_freq = max(min_ring_freq, ring_freq);
5168                         /* leave ia_freq as the default, chosen by cpufreq */
5169                 } else {
5170                         /* On older processors, there is no separate ring
5171                          * clock domain, so in order to boost the bandwidth
5172                          * of the ring, we need to upclock the CPU (ia_freq).
5173                          *
5174                          * For GPU frequencies less than 750MHz,
5175                          * just use the lowest ring freq.
5176                          */
5177                         if (gpu_freq < min_freq)
5178                                 ia_freq = 800;
5179                         else
5180                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5181                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5182                 }
5183
5184                 sandybridge_pcode_write(dev_priv,
5185                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5186                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5187                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5188                                         gpu_freq);
5189         }
5190 }
5191
5192 void gen6_update_ring_freq(struct drm_device *dev)
5193 {
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195
5196         if (!HAS_CORE_RING_FREQ(dev))
5197                 return;
5198
5199         mutex_lock(&dev_priv->rps.hw_lock);
5200         __gen6_update_ring_freq(dev);
5201         mutex_unlock(&dev_priv->rps.hw_lock);
5202 }
5203
5204 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5205 {
5206         struct drm_device *dev = dev_priv->dev;
5207         u32 val, rp0;
5208
5209         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5210
5211         switch (INTEL_INFO(dev)->eu_total) {
5212         case 8:
5213                 /* (2 * 4) config */
5214                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5215                 break;
5216         case 12:
5217                 /* (2 * 6) config */
5218                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5219                 break;
5220         case 16:
5221                 /* (2 * 8) config */
5222         default:
5223                 /* Setting (2 * 8) Min RP0 for any other combination */
5224                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5225                 break;
5226         }
5227
5228         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5229
5230         return rp0;
5231 }
5232
5233 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5234 {
5235         u32 val, rpe;
5236
5237         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5238         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5239
5240         return rpe;
5241 }
5242
5243 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5244 {
5245         u32 val, rp1;
5246
5247         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5248         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5249
5250         return rp1;
5251 }
5252
5253 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5254 {
5255         u32 val, rp1;
5256
5257         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5258
5259         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5260
5261         return rp1;
5262 }
5263
5264 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5265 {
5266         u32 val, rp0;
5267
5268         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5269
5270         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5271         /* Clamp to max */
5272         rp0 = min_t(u32, rp0, 0xea);
5273
5274         return rp0;
5275 }
5276
5277 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5278 {
5279         u32 val, rpe;
5280
5281         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5282         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5283         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5284         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5285
5286         return rpe;
5287 }
5288
5289 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5290 {
5291         u32 val;
5292
5293         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5294         /*
5295          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5296          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5297          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5298          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5299          * to make sure it matches what Punit accepts.
5300          */
5301         return max_t(u32, val, 0xc0);
5302 }
5303
5304 /* Check that the pctx buffer wasn't move under us. */
5305 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5306 {
5307         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5308
5309         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5310                              dev_priv->vlv_pctx->stolen->start);
5311 }
5312
5313
5314 /* Check that the pcbr address is not empty. */
5315 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5316 {
5317         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5318
5319         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5320 }
5321
5322 static void cherryview_setup_pctx(struct drm_device *dev)
5323 {
5324         struct drm_i915_private *dev_priv = to_i915(dev);
5325         struct i915_ggtt *ggtt = &dev_priv->ggtt;
5326         unsigned long pctx_paddr, paddr;
5327         u32 pcbr;
5328         int pctx_size = 32*1024;
5329
5330         pcbr = I915_READ(VLV_PCBR);
5331         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5332                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5333                 paddr = (dev_priv->mm.stolen_base +
5334                          (ggtt->stolen_size - pctx_size));
5335
5336                 pctx_paddr = (paddr & (~4095));
5337                 I915_WRITE(VLV_PCBR, pctx_paddr);
5338         }
5339
5340         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5341 }
5342
5343 static void valleyview_setup_pctx(struct drm_device *dev)
5344 {
5345         struct drm_i915_private *dev_priv = dev->dev_private;
5346         struct drm_i915_gem_object *pctx;
5347         unsigned long pctx_paddr;
5348         u32 pcbr;
5349         int pctx_size = 24*1024;
5350
5351         mutex_lock(&dev->struct_mutex);
5352
5353         pcbr = I915_READ(VLV_PCBR);
5354         if (pcbr) {
5355                 /* BIOS set it up already, grab the pre-alloc'd space */
5356                 int pcbr_offset;
5357
5358                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5359                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5360                                                                       pcbr_offset,
5361                                                                       I915_GTT_OFFSET_NONE,
5362                                                                       pctx_size);
5363                 goto out;
5364         }
5365
5366         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5367
5368         /*
5369          * From the Gunit register HAS:
5370          * The Gfx driver is expected to program this register and ensure
5371          * proper allocation within Gfx stolen memory.  For example, this
5372          * register should be programmed such than the PCBR range does not
5373          * overlap with other ranges, such as the frame buffer, protected
5374          * memory, or any other relevant ranges.
5375          */
5376         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5377         if (!pctx) {
5378                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5379                 goto out;
5380         }
5381
5382         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5383         I915_WRITE(VLV_PCBR, pctx_paddr);
5384
5385 out:
5386         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5387         dev_priv->vlv_pctx = pctx;
5388         mutex_unlock(&dev->struct_mutex);
5389 }
5390
5391 static void valleyview_cleanup_pctx(struct drm_device *dev)
5392 {
5393         struct drm_i915_private *dev_priv = dev->dev_private;
5394
5395         if (WARN_ON(!dev_priv->vlv_pctx))
5396                 return;
5397
5398         drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
5399         dev_priv->vlv_pctx = NULL;
5400 }
5401
5402 static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5403 {
5404         dev_priv->rps.gpll_ref_freq =
5405                 vlv_get_cck_clock(dev_priv, "GPLL ref",
5406                                   CCK_GPLL_CLOCK_CONTROL,
5407                                   dev_priv->czclk_freq);
5408
5409         DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5410                          dev_priv->rps.gpll_ref_freq);
5411 }
5412
5413 static void valleyview_init_gt_powersave(struct drm_device *dev)
5414 {
5415         struct drm_i915_private *dev_priv = dev->dev_private;
5416         u32 val;
5417
5418         valleyview_setup_pctx(dev);
5419
5420         vlv_init_gpll_ref_freq(dev_priv);
5421
5422         mutex_lock(&dev_priv->rps.hw_lock);
5423
5424         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5425         switch ((val >> 6) & 3) {
5426         case 0:
5427         case 1:
5428                 dev_priv->mem_freq = 800;
5429                 break;
5430         case 2:
5431                 dev_priv->mem_freq = 1066;
5432                 break;
5433         case 3:
5434                 dev_priv->mem_freq = 1333;
5435                 break;
5436         }
5437         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5438
5439         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5440         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5441         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5442                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5443                          dev_priv->rps.max_freq);
5444
5445         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5446         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5447                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5448                          dev_priv->rps.efficient_freq);
5449
5450         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5451         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5452                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5453                          dev_priv->rps.rp1_freq);
5454
5455         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5456         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5457                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5458                          dev_priv->rps.min_freq);
5459
5460         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5461
5462         /* Preserve min/max settings in case of re-init */
5463         if (dev_priv->rps.max_freq_softlimit == 0)
5464                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5465
5466         if (dev_priv->rps.min_freq_softlimit == 0)
5467                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5468
5469         mutex_unlock(&dev_priv->rps.hw_lock);
5470 }
5471
5472 static void cherryview_init_gt_powersave(struct drm_device *dev)
5473 {
5474         struct drm_i915_private *dev_priv = dev->dev_private;
5475         u32 val;
5476
5477         cherryview_setup_pctx(dev);
5478
5479         vlv_init_gpll_ref_freq(dev_priv);
5480
5481         mutex_lock(&dev_priv->rps.hw_lock);
5482
5483         mutex_lock(&dev_priv->sb_lock);
5484         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5485         mutex_unlock(&dev_priv->sb_lock);
5486
5487         switch ((val >> 2) & 0x7) {
5488         case 3:
5489                 dev_priv->mem_freq = 2000;
5490                 break;
5491         default:
5492                 dev_priv->mem_freq = 1600;
5493                 break;
5494         }
5495         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5496
5497         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5498         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5499         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5500                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5501                          dev_priv->rps.max_freq);
5502
5503         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5504         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5505                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5506                          dev_priv->rps.efficient_freq);
5507
5508         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5509         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5510                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5511                          dev_priv->rps.rp1_freq);
5512
5513         /* PUnit validated range is only [RPe, RP0] */
5514         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5515         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5516                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5517                          dev_priv->rps.min_freq);
5518
5519         WARN_ONCE((dev_priv->rps.max_freq |
5520                    dev_priv->rps.efficient_freq |
5521                    dev_priv->rps.rp1_freq |
5522                    dev_priv->rps.min_freq) & 1,
5523                   "Odd GPU freq values\n");
5524
5525         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5526
5527         /* Preserve min/max settings in case of re-init */
5528         if (dev_priv->rps.max_freq_softlimit == 0)
5529                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5530
5531         if (dev_priv->rps.min_freq_softlimit == 0)
5532                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5533
5534         mutex_unlock(&dev_priv->rps.hw_lock);
5535 }
5536
5537 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5538 {
5539         valleyview_cleanup_pctx(dev);
5540 }
5541
5542 static void cherryview_enable_rps(struct drm_device *dev)
5543 {
5544         struct drm_i915_private *dev_priv = dev->dev_private;
5545         struct intel_engine_cs *engine;
5546         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5547
5548         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5549
5550         gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5551                                              GT_FIFO_FREE_ENTRIES_CHV);
5552         if (gtfifodbg) {
5553                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5554                                  gtfifodbg);
5555                 I915_WRITE(GTFIFODBG, gtfifodbg);
5556         }
5557
5558         cherryview_check_pctx(dev_priv);
5559
5560         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5561          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5562         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5563
5564         /*  Disable RC states. */
5565         I915_WRITE(GEN6_RC_CONTROL, 0);
5566
5567         /* 2a: Program RC6 thresholds.*/
5568         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5569         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5570         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5571
5572         for_each_engine(engine, dev_priv)
5573                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5574         I915_WRITE(GEN6_RC_SLEEP, 0);
5575
5576         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5577         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5578
5579         /* allows RC6 residency counter to work */
5580         I915_WRITE(VLV_COUNTER_CONTROL,
5581                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5582                                       VLV_MEDIA_RC6_COUNT_EN |
5583                                       VLV_RENDER_RC6_COUNT_EN));
5584
5585         /* For now we assume BIOS is allocating and populating the PCBR  */
5586         pcbr = I915_READ(VLV_PCBR);
5587
5588         /* 3: Enable RC6 */
5589         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5590                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5591                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5592
5593         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5594
5595         /* 4 Program defaults and thresholds for RPS*/
5596         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5597         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5598         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5599         I915_WRITE(GEN6_RP_UP_EI, 66000);
5600         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5601
5602         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5603
5604         /* 5: Enable RPS */
5605         I915_WRITE(GEN6_RP_CONTROL,
5606                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5607                    GEN6_RP_MEDIA_IS_GFX |
5608                    GEN6_RP_ENABLE |
5609                    GEN6_RP_UP_BUSY_AVG |
5610                    GEN6_RP_DOWN_IDLE_AVG);
5611
5612         /* Setting Fixed Bias */
5613         val = VLV_OVERRIDE_EN |
5614                   VLV_SOC_TDP_EN |
5615                   CHV_BIAS_CPU_50_SOC_50;
5616         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5617
5618         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5619
5620         /* RPS code assumes GPLL is used */
5621         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5622
5623         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5624         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5625
5626         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5627         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5628                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5629                          dev_priv->rps.cur_freq);
5630
5631         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5632                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5633                          dev_priv->rps.idle_freq);
5634
5635         valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5636
5637         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5638 }
5639
5640 static void valleyview_enable_rps(struct drm_device *dev)
5641 {
5642         struct drm_i915_private *dev_priv = dev->dev_private;
5643         struct intel_engine_cs *engine;
5644         u32 gtfifodbg, val, rc6_mode = 0;
5645
5646         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5647
5648         valleyview_check_pctx(dev_priv);
5649
5650         gtfifodbg = I915_READ(GTFIFODBG);
5651         if (gtfifodbg) {
5652                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5653                                  gtfifodbg);
5654                 I915_WRITE(GTFIFODBG, gtfifodbg);
5655         }
5656
5657         /* If VLV, Forcewake all wells, else re-direct to regular path */
5658         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5659
5660         /*  Disable RC states. */
5661         I915_WRITE(GEN6_RC_CONTROL, 0);
5662
5663         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5664         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5665         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5666         I915_WRITE(GEN6_RP_UP_EI, 66000);
5667         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5668
5669         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5670
5671         I915_WRITE(GEN6_RP_CONTROL,
5672                    GEN6_RP_MEDIA_TURBO |
5673                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5674                    GEN6_RP_MEDIA_IS_GFX |
5675                    GEN6_RP_ENABLE |
5676                    GEN6_RP_UP_BUSY_AVG |
5677                    GEN6_RP_DOWN_IDLE_CONT);
5678
5679         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5680         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5681         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5682
5683         for_each_engine(engine, dev_priv)
5684                 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
5685
5686         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5687
5688         /* allows RC6 residency counter to work */
5689         I915_WRITE(VLV_COUNTER_CONTROL,
5690                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5691                                       VLV_RENDER_RC0_COUNT_EN |
5692                                       VLV_MEDIA_RC6_COUNT_EN |
5693                                       VLV_RENDER_RC6_COUNT_EN));
5694
5695         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5696                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5697
5698         intel_print_rc6_info(dev, rc6_mode);
5699
5700         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5701
5702         /* Setting Fixed Bias */
5703         val = VLV_OVERRIDE_EN |
5704                   VLV_SOC_TDP_EN |
5705                   VLV_BIAS_CPU_125_SOC_875;
5706         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5707
5708         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5709
5710         /* RPS code assumes GPLL is used */
5711         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5712
5713         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5714         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5715
5716         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5717         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5718                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5719                          dev_priv->rps.cur_freq);
5720
5721         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5722                          intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5723                          dev_priv->rps.idle_freq);
5724
5725         valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5726
5727         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5728 }
5729
5730 static unsigned long intel_pxfreq(u32 vidfreq)
5731 {
5732         unsigned long freq;
5733         int div = (vidfreq & 0x3f0000) >> 16;
5734         int post = (vidfreq & 0x3000) >> 12;
5735         int pre = (vidfreq & 0x7);
5736
5737         if (!pre)
5738                 return 0;
5739
5740         freq = ((div * 133333) / ((1<<post) * pre));
5741
5742         return freq;
5743 }
5744
5745 static const struct cparams {
5746         u16 i;
5747         u16 t;
5748         u16 m;
5749         u16 c;
5750 } cparams[] = {
5751         { 1, 1333, 301, 28664 },
5752         { 1, 1066, 294, 24460 },
5753         { 1, 800, 294, 25192 },
5754         { 0, 1333, 276, 27605 },
5755         { 0, 1066, 276, 27605 },
5756         { 0, 800, 231, 23784 },
5757 };
5758
5759 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5760 {
5761         u64 total_count, diff, ret;
5762         u32 count1, count2, count3, m = 0, c = 0;
5763         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5764         int i;
5765
5766         assert_spin_locked(&mchdev_lock);
5767
5768         diff1 = now - dev_priv->ips.last_time1;
5769
5770         /* Prevent division-by-zero if we are asking too fast.
5771          * Also, we don't get interesting results if we are polling
5772          * faster than once in 10ms, so just return the saved value
5773          * in such cases.
5774          */
5775         if (diff1 <= 10)
5776                 return dev_priv->ips.chipset_power;
5777
5778         count1 = I915_READ(DMIEC);
5779         count2 = I915_READ(DDREC);
5780         count3 = I915_READ(CSIEC);
5781
5782         total_count = count1 + count2 + count3;
5783
5784         /* FIXME: handle per-counter overflow */
5785         if (total_count < dev_priv->ips.last_count1) {
5786                 diff = ~0UL - dev_priv->ips.last_count1;
5787                 diff += total_count;
5788         } else {
5789                 diff = total_count - dev_priv->ips.last_count1;
5790         }
5791
5792         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5793                 if (cparams[i].i == dev_priv->ips.c_m &&
5794                     cparams[i].t == dev_priv->ips.r_t) {
5795                         m = cparams[i].m;
5796                         c = cparams[i].c;
5797                         break;
5798                 }
5799         }
5800
5801         diff = div_u64(diff, diff1);
5802         ret = ((m * diff) + c);
5803         ret = div_u64(ret, 10);
5804
5805         dev_priv->ips.last_count1 = total_count;
5806         dev_priv->ips.last_time1 = now;
5807
5808         dev_priv->ips.chipset_power = ret;
5809
5810         return ret;
5811 }
5812
5813 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5814 {
5815         struct drm_device *dev = dev_priv->dev;
5816         unsigned long val;
5817
5818         if (INTEL_INFO(dev)->gen != 5)
5819                 return 0;
5820
5821         spin_lock_irq(&mchdev_lock);
5822
5823         val = __i915_chipset_val(dev_priv);
5824
5825         spin_unlock_irq(&mchdev_lock);
5826
5827         return val;
5828 }
5829
5830 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5831 {
5832         unsigned long m, x, b;
5833         u32 tsfs;
5834
5835         tsfs = I915_READ(TSFS);
5836
5837         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5838         x = I915_READ8(TR1);
5839
5840         b = tsfs & TSFS_INTR_MASK;
5841
5842         return ((m * x) / 127) - b;
5843 }
5844
5845 static int _pxvid_to_vd(u8 pxvid)
5846 {
5847         if (pxvid == 0)
5848                 return 0;
5849
5850         if (pxvid >= 8 && pxvid < 31)
5851                 pxvid = 31;
5852
5853         return (pxvid + 2) * 125;
5854 }
5855
5856 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5857 {
5858         struct drm_device *dev = dev_priv->dev;
5859         const int vd = _pxvid_to_vd(pxvid);
5860         const int vm = vd - 1125;
5861
5862         if (INTEL_INFO(dev)->is_mobile)
5863                 return vm > 0 ? vm : 0;
5864
5865         return vd;
5866 }
5867
5868 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5869 {
5870         u64 now, diff, diffms;
5871         u32 count;
5872
5873         assert_spin_locked(&mchdev_lock);
5874
5875         now = ktime_get_raw_ns();
5876         diffms = now - dev_priv->ips.last_time2;
5877         do_div(diffms, NSEC_PER_MSEC);
5878
5879         /* Don't divide by 0 */
5880         if (!diffms)
5881                 return;
5882
5883         count = I915_READ(GFXEC);
5884
5885         if (count < dev_priv->ips.last_count2) {
5886                 diff = ~0UL - dev_priv->ips.last_count2;
5887                 diff += count;
5888         } else {
5889                 diff = count - dev_priv->ips.last_count2;
5890         }
5891
5892         dev_priv->ips.last_count2 = count;
5893         dev_priv->ips.last_time2 = now;
5894
5895         /* More magic constants... */
5896         diff = diff * 1181;
5897         diff = div_u64(diff, diffms * 10);
5898         dev_priv->ips.gfx_power = diff;
5899 }
5900
5901 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5902 {
5903         struct drm_device *dev = dev_priv->dev;
5904
5905         if (INTEL_INFO(dev)->gen != 5)
5906                 return;
5907
5908         spin_lock_irq(&mchdev_lock);
5909
5910         __i915_update_gfx_val(dev_priv);
5911
5912         spin_unlock_irq(&mchdev_lock);
5913 }
5914
5915 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5916 {
5917         unsigned long t, corr, state1, corr2, state2;
5918         u32 pxvid, ext_v;
5919
5920         assert_spin_locked(&mchdev_lock);
5921
5922         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5923         pxvid = (pxvid >> 24) & 0x7f;
5924         ext_v = pvid_to_extvid(dev_priv, pxvid);
5925
5926         state1 = ext_v;
5927
5928         t = i915_mch_val(dev_priv);
5929
5930         /* Revel in the empirically derived constants */
5931
5932         /* Correction factor in 1/100000 units */
5933         if (t > 80)
5934                 corr = ((t * 2349) + 135940);
5935         else if (t >= 50)
5936                 corr = ((t * 964) + 29317);
5937         else /* < 50 */
5938                 corr = ((t * 301) + 1004);
5939
5940         corr = corr * ((150142 * state1) / 10000 - 78642);
5941         corr /= 100000;
5942         corr2 = (corr * dev_priv->ips.corr);
5943
5944         state2 = (corr2 * state1) / 10000;
5945         state2 /= 100; /* convert to mW */
5946
5947         __i915_update_gfx_val(dev_priv);
5948
5949         return dev_priv->ips.gfx_power + state2;
5950 }
5951
5952 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5953 {
5954         struct drm_device *dev = dev_priv->dev;
5955         unsigned long val;
5956
5957         if (INTEL_INFO(dev)->gen != 5)
5958                 return 0;
5959
5960         spin_lock_irq(&mchdev_lock);
5961
5962         val = __i915_gfx_val(dev_priv);
5963
5964         spin_unlock_irq(&mchdev_lock);
5965
5966         return val;
5967 }
5968
5969 /**
5970  * i915_read_mch_val - return value for IPS use
5971  *
5972  * Calculate and return a value for the IPS driver to use when deciding whether
5973  * we have thermal and power headroom to increase CPU or GPU power budget.
5974  */
5975 unsigned long i915_read_mch_val(void)
5976 {
5977         struct drm_i915_private *dev_priv;
5978         unsigned long chipset_val, graphics_val, ret = 0;
5979
5980         spin_lock_irq(&mchdev_lock);
5981         if (!i915_mch_dev)
5982                 goto out_unlock;
5983         dev_priv = i915_mch_dev;
5984
5985         chipset_val = __i915_chipset_val(dev_priv);
5986         graphics_val = __i915_gfx_val(dev_priv);
5987
5988         ret = chipset_val + graphics_val;
5989
5990 out_unlock:
5991         spin_unlock_irq(&mchdev_lock);
5992
5993         return ret;
5994 }
5995 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5996
5997 /**
5998  * i915_gpu_raise - raise GPU frequency limit
5999  *
6000  * Raise the limit; IPS indicates we have thermal headroom.
6001  */
6002 bool i915_gpu_raise(void)
6003 {
6004         struct drm_i915_private *dev_priv;
6005         bool ret = true;
6006
6007         spin_lock_irq(&mchdev_lock);
6008         if (!i915_mch_dev) {
6009                 ret = false;
6010                 goto out_unlock;
6011         }
6012         dev_priv = i915_mch_dev;
6013
6014         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6015                 dev_priv->ips.max_delay--;
6016
6017 out_unlock:
6018         spin_unlock_irq(&mchdev_lock);
6019
6020         return ret;
6021 }
6022 EXPORT_SYMBOL_GPL(i915_gpu_raise);
6023
6024 /**
6025  * i915_gpu_lower - lower GPU frequency limit
6026  *
6027  * IPS indicates we're close to a thermal limit, so throttle back the GPU
6028  * frequency maximum.
6029  */
6030 bool i915_gpu_lower(void)
6031 {
6032         struct drm_i915_private *dev_priv;
6033         bool ret = true;
6034
6035         spin_lock_irq(&mchdev_lock);
6036         if (!i915_mch_dev) {
6037                 ret = false;
6038                 goto out_unlock;
6039         }
6040         dev_priv = i915_mch_dev;
6041
6042         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6043                 dev_priv->ips.max_delay++;
6044
6045 out_unlock:
6046         spin_unlock_irq(&mchdev_lock);
6047
6048         return ret;
6049 }
6050 EXPORT_SYMBOL_GPL(i915_gpu_lower);
6051
6052 /**
6053  * i915_gpu_busy - indicate GPU business to IPS
6054  *
6055  * Tell the IPS driver whether or not the GPU is busy.
6056  */
6057 bool i915_gpu_busy(void)
6058 {
6059         struct drm_i915_private *dev_priv;
6060         struct intel_engine_cs *engine;
6061         bool ret = false;
6062
6063         spin_lock_irq(&mchdev_lock);
6064         if (!i915_mch_dev)
6065                 goto out_unlock;
6066         dev_priv = i915_mch_dev;
6067
6068         for_each_engine(engine, dev_priv)
6069                 ret |= !list_empty(&engine->request_list);
6070
6071 out_unlock:
6072         spin_unlock_irq(&mchdev_lock);
6073
6074         return ret;
6075 }
6076 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6077
6078 /**
6079  * i915_gpu_turbo_disable - disable graphics turbo
6080  *
6081  * Disable graphics turbo by resetting the max frequency and setting the
6082  * current frequency to the default.
6083  */
6084 bool i915_gpu_turbo_disable(void)
6085 {
6086         struct drm_i915_private *dev_priv;
6087         bool ret = true;
6088
6089         spin_lock_irq(&mchdev_lock);
6090         if (!i915_mch_dev) {
6091                 ret = false;
6092                 goto out_unlock;
6093         }
6094         dev_priv = i915_mch_dev;
6095
6096         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6097
6098         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6099                 ret = false;
6100
6101 out_unlock:
6102         spin_unlock_irq(&mchdev_lock);
6103
6104         return ret;
6105 }
6106 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6107
6108 /**
6109  * Tells the intel_ips driver that the i915 driver is now loaded, if
6110  * IPS got loaded first.
6111  *
6112  * This awkward dance is so that neither module has to depend on the
6113  * other in order for IPS to do the appropriate communication of
6114  * GPU turbo limits to i915.
6115  */
6116 static void
6117 ips_ping_for_i915_load(void)
6118 {
6119         void (*link)(void);
6120
6121         link = symbol_get(ips_link_to_i915_driver);
6122         if (link) {
6123                 link();
6124                 symbol_put(ips_link_to_i915_driver);
6125         }
6126 }
6127
6128 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6129 {
6130         /* We only register the i915 ips part with intel-ips once everything is
6131          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6132         spin_lock_irq(&mchdev_lock);
6133         i915_mch_dev = dev_priv;
6134         spin_unlock_irq(&mchdev_lock);
6135
6136         ips_ping_for_i915_load();
6137 }
6138
6139 void intel_gpu_ips_teardown(void)
6140 {
6141         spin_lock_irq(&mchdev_lock);
6142         i915_mch_dev = NULL;
6143         spin_unlock_irq(&mchdev_lock);
6144 }
6145
6146 static void intel_init_emon(struct drm_device *dev)
6147 {
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149         u32 lcfuse;
6150         u8 pxw[16];
6151         int i;
6152
6153         /* Disable to program */
6154         I915_WRITE(ECR, 0);
6155         POSTING_READ(ECR);
6156
6157         /* Program energy weights for various events */
6158         I915_WRITE(SDEW, 0x15040d00);
6159         I915_WRITE(CSIEW0, 0x007f0000);
6160         I915_WRITE(CSIEW1, 0x1e220004);
6161         I915_WRITE(CSIEW2, 0x04000004);
6162
6163         for (i = 0; i < 5; i++)
6164                 I915_WRITE(PEW(i), 0);
6165         for (i = 0; i < 3; i++)
6166                 I915_WRITE(DEW(i), 0);
6167
6168         /* Program P-state weights to account for frequency power adjustment */
6169         for (i = 0; i < 16; i++) {
6170                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6171                 unsigned long freq = intel_pxfreq(pxvidfreq);
6172                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6173                         PXVFREQ_PX_SHIFT;
6174                 unsigned long val;
6175
6176                 val = vid * vid;
6177                 val *= (freq / 1000);
6178                 val *= 255;
6179                 val /= (127*127*900);
6180                 if (val > 0xff)
6181                         DRM_ERROR("bad pxval: %ld\n", val);
6182                 pxw[i] = val;
6183         }
6184         /* Render standby states get 0 weight */
6185         pxw[14] = 0;
6186         pxw[15] = 0;
6187
6188         for (i = 0; i < 4; i++) {
6189                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6190                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6191                 I915_WRITE(PXW(i), val);
6192         }
6193
6194         /* Adjust magic regs to magic values (more experimental results) */
6195         I915_WRITE(OGW0, 0);
6196         I915_WRITE(OGW1, 0);
6197         I915_WRITE(EG0, 0x00007f00);
6198         I915_WRITE(EG1, 0x0000000e);
6199         I915_WRITE(EG2, 0x000e0000);
6200         I915_WRITE(EG3, 0x68000300);
6201         I915_WRITE(EG4, 0x42000000);
6202         I915_WRITE(EG5, 0x00140031);
6203         I915_WRITE(EG6, 0);
6204         I915_WRITE(EG7, 0);
6205
6206         for (i = 0; i < 8; i++)
6207                 I915_WRITE(PXWL(i), 0);
6208
6209         /* Enable PMON + select events */
6210         I915_WRITE(ECR, 0x80000019);
6211
6212         lcfuse = I915_READ(LCFUSE02);
6213
6214         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6215 }
6216
6217 void intel_init_gt_powersave(struct drm_device *dev)
6218 {
6219         struct drm_i915_private *dev_priv = dev->dev_private;
6220
6221         /*
6222          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6223          * requirement.
6224          */
6225         if (!i915.enable_rc6) {
6226                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6227                 intel_runtime_pm_get(dev_priv);
6228         }
6229
6230         if (IS_CHERRYVIEW(dev))
6231                 cherryview_init_gt_powersave(dev);
6232         else if (IS_VALLEYVIEW(dev))
6233                 valleyview_init_gt_powersave(dev);
6234 }
6235
6236 void intel_cleanup_gt_powersave(struct drm_device *dev)
6237 {
6238         struct drm_i915_private *dev_priv = dev->dev_private;
6239
6240         if (IS_CHERRYVIEW(dev))
6241                 return;
6242         else if (IS_VALLEYVIEW(dev))
6243                 valleyview_cleanup_gt_powersave(dev);
6244
6245         if (!i915.enable_rc6)
6246                 intel_runtime_pm_put(dev_priv);
6247 }
6248
6249 static void gen6_suspend_rps(struct drm_device *dev)
6250 {
6251         struct drm_i915_private *dev_priv = dev->dev_private;
6252
6253         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6254
6255         gen6_disable_rps_interrupts(dev);
6256 }
6257
6258 /**
6259  * intel_suspend_gt_powersave - suspend PM work and helper threads
6260  * @dev: drm device
6261  *
6262  * We don't want to disable RC6 or other features here, we just want
6263  * to make sure any work we've queued has finished and won't bother
6264  * us while we're suspended.
6265  */
6266 void intel_suspend_gt_powersave(struct drm_device *dev)
6267 {
6268         struct drm_i915_private *dev_priv = dev->dev_private;
6269
6270         if (INTEL_INFO(dev)->gen < 6)
6271                 return;
6272
6273         gen6_suspend_rps(dev);
6274
6275         /* Force GPU to min freq during suspend */
6276         gen6_rps_idle(dev_priv);
6277 }
6278
6279 void intel_disable_gt_powersave(struct drm_device *dev)
6280 {
6281         struct drm_i915_private *dev_priv = dev->dev_private;
6282
6283         if (IS_IRONLAKE_M(dev)) {
6284                 ironlake_disable_drps(dev);
6285         } else if (INTEL_INFO(dev)->gen >= 6) {
6286                 intel_suspend_gt_powersave(dev);
6287
6288                 mutex_lock(&dev_priv->rps.hw_lock);
6289                 if (INTEL_INFO(dev)->gen >= 9) {
6290                         gen9_disable_rc6(dev);
6291                         gen9_disable_rps(dev);
6292                 } else if (IS_CHERRYVIEW(dev))
6293                         cherryview_disable_rps(dev);
6294                 else if (IS_VALLEYVIEW(dev))
6295                         valleyview_disable_rps(dev);
6296                 else
6297                         gen6_disable_rps(dev);
6298
6299                 dev_priv->rps.enabled = false;
6300                 mutex_unlock(&dev_priv->rps.hw_lock);
6301         }
6302 }
6303
6304 static void intel_gen6_powersave_work(struct work_struct *work)
6305 {
6306         struct drm_i915_private *dev_priv =
6307                 container_of(work, struct drm_i915_private,
6308                              rps.delayed_resume_work.work);
6309         struct drm_device *dev = dev_priv->dev;
6310
6311         mutex_lock(&dev_priv->rps.hw_lock);
6312
6313         gen6_reset_rps_interrupts(dev);
6314
6315         if (IS_CHERRYVIEW(dev)) {
6316                 cherryview_enable_rps(dev);
6317         } else if (IS_VALLEYVIEW(dev)) {
6318                 valleyview_enable_rps(dev);
6319         } else if (INTEL_INFO(dev)->gen >= 9) {
6320                 gen9_enable_rc6(dev);
6321                 gen9_enable_rps(dev);
6322                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6323                         __gen6_update_ring_freq(dev);
6324         } else if (IS_BROADWELL(dev)) {
6325                 gen8_enable_rps(dev);
6326                 __gen6_update_ring_freq(dev);
6327         } else {
6328                 gen6_enable_rps(dev);
6329                 __gen6_update_ring_freq(dev);
6330         }
6331
6332         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6333         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6334
6335         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6336         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6337
6338         dev_priv->rps.enabled = true;
6339
6340         gen6_enable_rps_interrupts(dev);
6341
6342         mutex_unlock(&dev_priv->rps.hw_lock);
6343
6344         intel_runtime_pm_put(dev_priv);
6345 }
6346
6347 void intel_enable_gt_powersave(struct drm_device *dev)
6348 {
6349         struct drm_i915_private *dev_priv = dev->dev_private;
6350
6351         /* Powersaving is controlled by the host when inside a VM */
6352         if (intel_vgpu_active(dev))
6353                 return;
6354
6355         if (IS_IRONLAKE_M(dev)) {
6356                 ironlake_enable_drps(dev);
6357                 mutex_lock(&dev->struct_mutex);
6358                 intel_init_emon(dev);
6359                 mutex_unlock(&dev->struct_mutex);
6360         } else if (INTEL_INFO(dev)->gen >= 6) {
6361                 /*
6362                  * PCU communication is slow and this doesn't need to be
6363                  * done at any specific time, so do this out of our fast path
6364                  * to make resume and init faster.
6365                  *
6366                  * We depend on the HW RC6 power context save/restore
6367                  * mechanism when entering D3 through runtime PM suspend. So
6368                  * disable RPM until RPS/RC6 is properly setup. We can only
6369                  * get here via the driver load/system resume/runtime resume
6370                  * paths, so the _noresume version is enough (and in case of
6371                  * runtime resume it's necessary).
6372                  */
6373                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6374                                            round_jiffies_up_relative(HZ)))
6375                         intel_runtime_pm_get_noresume(dev_priv);
6376         }
6377 }
6378
6379 void intel_reset_gt_powersave(struct drm_device *dev)
6380 {
6381         struct drm_i915_private *dev_priv = dev->dev_private;
6382
6383         if (INTEL_INFO(dev)->gen < 6)
6384                 return;
6385
6386         gen6_suspend_rps(dev);
6387         dev_priv->rps.enabled = false;
6388 }
6389
6390 static void ibx_init_clock_gating(struct drm_device *dev)
6391 {
6392         struct drm_i915_private *dev_priv = dev->dev_private;
6393
6394         /*
6395          * On Ibex Peak and Cougar Point, we need to disable clock
6396          * gating for the panel power sequencer or it will fail to
6397          * start up when no ports are active.
6398          */
6399         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6400 }
6401
6402 static void g4x_disable_trickle_feed(struct drm_device *dev)
6403 {
6404         struct drm_i915_private *dev_priv = dev->dev_private;
6405         enum pipe pipe;
6406
6407         for_each_pipe(dev_priv, pipe) {
6408                 I915_WRITE(DSPCNTR(pipe),
6409                            I915_READ(DSPCNTR(pipe)) |
6410                            DISPPLANE_TRICKLE_FEED_DISABLE);
6411
6412                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6413                 POSTING_READ(DSPSURF(pipe));
6414         }
6415 }
6416
6417 static void ilk_init_lp_watermarks(struct drm_device *dev)
6418 {
6419         struct drm_i915_private *dev_priv = dev->dev_private;
6420
6421         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6422         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6423         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6424
6425         /*
6426          * Don't touch WM1S_LP_EN here.
6427          * Doing so could cause underruns.
6428          */
6429 }
6430
6431 static void ironlake_init_clock_gating(struct drm_device *dev)
6432 {
6433         struct drm_i915_private *dev_priv = dev->dev_private;
6434         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6435
6436         /*
6437          * Required for FBC
6438          * WaFbcDisableDpfcClockGating:ilk
6439          */
6440         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6441                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6442                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6443
6444         I915_WRITE(PCH_3DCGDIS0,
6445                    MARIUNIT_CLOCK_GATE_DISABLE |
6446                    SVSMUNIT_CLOCK_GATE_DISABLE);
6447         I915_WRITE(PCH_3DCGDIS1,
6448                    VFMUNIT_CLOCK_GATE_DISABLE);
6449
6450         /*
6451          * According to the spec the following bits should be set in
6452          * order to enable memory self-refresh
6453          * The bit 22/21 of 0x42004
6454          * The bit 5 of 0x42020
6455          * The bit 15 of 0x45000
6456          */
6457         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6458                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6459                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6460         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6461         I915_WRITE(DISP_ARB_CTL,
6462                    (I915_READ(DISP_ARB_CTL) |
6463                     DISP_FBC_WM_DIS));
6464
6465         ilk_init_lp_watermarks(dev);
6466
6467         /*
6468          * Based on the document from hardware guys the following bits
6469          * should be set unconditionally in order to enable FBC.
6470          * The bit 22 of 0x42000
6471          * The bit 22 of 0x42004
6472          * The bit 7,8,9 of 0x42020.
6473          */
6474         if (IS_IRONLAKE_M(dev)) {
6475                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6476                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6477                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6478                            ILK_FBCQ_DIS);
6479                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6480                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6481                            ILK_DPARB_GATE);
6482         }
6483
6484         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6485
6486         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6487                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6488                    ILK_ELPIN_409_SELECT);
6489         I915_WRITE(_3D_CHICKEN2,
6490                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6491                    _3D_CHICKEN2_WM_READ_PIPELINED);
6492
6493         /* WaDisableRenderCachePipelinedFlush:ilk */
6494         I915_WRITE(CACHE_MODE_0,
6495                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6496
6497         /* WaDisable_RenderCache_OperationalFlush:ilk */
6498         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6499
6500         g4x_disable_trickle_feed(dev);
6501
6502         ibx_init_clock_gating(dev);
6503 }
6504
6505 static void cpt_init_clock_gating(struct drm_device *dev)
6506 {
6507         struct drm_i915_private *dev_priv = dev->dev_private;
6508         int pipe;
6509         uint32_t val;
6510
6511         /*
6512          * On Ibex Peak and Cougar Point, we need to disable clock
6513          * gating for the panel power sequencer or it will fail to
6514          * start up when no ports are active.
6515          */
6516         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6517                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6518                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6519         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6520                    DPLS_EDP_PPS_FIX_DIS);
6521         /* The below fixes the weird display corruption, a few pixels shifted
6522          * downward, on (only) LVDS of some HP laptops with IVY.
6523          */
6524         for_each_pipe(dev_priv, pipe) {
6525                 val = I915_READ(TRANS_CHICKEN2(pipe));
6526                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6527                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6528                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6529                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6530                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6531                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6532                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6533                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6534         }
6535         /* WADP0ClockGatingDisable */
6536         for_each_pipe(dev_priv, pipe) {
6537                 I915_WRITE(TRANS_CHICKEN1(pipe),
6538                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6539         }
6540 }
6541
6542 static void gen6_check_mch_setup(struct drm_device *dev)
6543 {
6544         struct drm_i915_private *dev_priv = dev->dev_private;
6545         uint32_t tmp;
6546
6547         tmp = I915_READ(MCH_SSKPD);
6548         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6549                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6550                               tmp);
6551 }
6552
6553 static void gen6_init_clock_gating(struct drm_device *dev)
6554 {
6555         struct drm_i915_private *dev_priv = dev->dev_private;
6556         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6557
6558         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6559
6560         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6561                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6562                    ILK_ELPIN_409_SELECT);
6563
6564         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6565         I915_WRITE(_3D_CHICKEN,
6566                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6567
6568         /* WaDisable_RenderCache_OperationalFlush:snb */
6569         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6570
6571         /*
6572          * BSpec recoomends 8x4 when MSAA is used,
6573          * however in practice 16x4 seems fastest.
6574          *
6575          * Note that PS/WM thread counts depend on the WIZ hashing
6576          * disable bit, which we don't touch here, but it's good
6577          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6578          */
6579         I915_WRITE(GEN6_GT_MODE,
6580                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6581
6582         ilk_init_lp_watermarks(dev);
6583
6584         I915_WRITE(CACHE_MODE_0,
6585                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6586
6587         I915_WRITE(GEN6_UCGCTL1,
6588                    I915_READ(GEN6_UCGCTL1) |
6589                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6590                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6591
6592         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6593          * gating disable must be set.  Failure to set it results in
6594          * flickering pixels due to Z write ordering failures after
6595          * some amount of runtime in the Mesa "fire" demo, and Unigine
6596          * Sanctuary and Tropics, and apparently anything else with
6597          * alpha test or pixel discard.
6598          *
6599          * According to the spec, bit 11 (RCCUNIT) must also be set,
6600          * but we didn't debug actual testcases to find it out.
6601          *
6602          * WaDisableRCCUnitClockGating:snb
6603          * WaDisableRCPBUnitClockGating:snb
6604          */
6605         I915_WRITE(GEN6_UCGCTL2,
6606                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6607                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6608
6609         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6610         I915_WRITE(_3D_CHICKEN3,
6611                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6612
6613         /*
6614          * Bspec says:
6615          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6616          * 3DSTATE_SF number of SF output attributes is more than 16."
6617          */
6618         I915_WRITE(_3D_CHICKEN3,
6619                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6620
6621         /*
6622          * According to the spec the following bits should be
6623          * set in order to enable memory self-refresh and fbc:
6624          * The bit21 and bit22 of 0x42000
6625          * The bit21 and bit22 of 0x42004
6626          * The bit5 and bit7 of 0x42020
6627          * The bit14 of 0x70180
6628          * The bit14 of 0x71180
6629          *
6630          * WaFbcAsynchFlipDisableFbcQueue:snb
6631          */
6632         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6633                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6634                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6635         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6636                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6637                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6638         I915_WRITE(ILK_DSPCLK_GATE_D,
6639                    I915_READ(ILK_DSPCLK_GATE_D) |
6640                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6641                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6642
6643         g4x_disable_trickle_feed(dev);
6644
6645         cpt_init_clock_gating(dev);
6646
6647         gen6_check_mch_setup(dev);
6648 }
6649
6650 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6651 {
6652         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6653
6654         /*
6655          * WaVSThreadDispatchOverride:ivb,vlv
6656          *
6657          * This actually overrides the dispatch
6658          * mode for all thread types.
6659          */
6660         reg &= ~GEN7_FF_SCHED_MASK;
6661         reg |= GEN7_FF_TS_SCHED_HW;
6662         reg |= GEN7_FF_VS_SCHED_HW;
6663         reg |= GEN7_FF_DS_SCHED_HW;
6664
6665         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6666 }
6667
6668 static void lpt_init_clock_gating(struct drm_device *dev)
6669 {
6670         struct drm_i915_private *dev_priv = dev->dev_private;
6671
6672         /*
6673          * TODO: this bit should only be enabled when really needed, then
6674          * disabled when not needed anymore in order to save power.
6675          */
6676         if (HAS_PCH_LPT_LP(dev))
6677                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6678                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6679                            PCH_LP_PARTITION_LEVEL_DISABLE);
6680
6681         /* WADPOClockGatingDisable:hsw */
6682         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6683                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6684                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6685 }
6686
6687 static void lpt_suspend_hw(struct drm_device *dev)
6688 {
6689         struct drm_i915_private *dev_priv = dev->dev_private;
6690
6691         if (HAS_PCH_LPT_LP(dev)) {
6692                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6693
6694                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6695                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6696         }
6697 }
6698
6699 static void broadwell_init_clock_gating(struct drm_device *dev)
6700 {
6701         struct drm_i915_private *dev_priv = dev->dev_private;
6702         enum pipe pipe;
6703         uint32_t misccpctl;
6704
6705         ilk_init_lp_watermarks(dev);
6706
6707         /* WaSwitchSolVfFArbitrationPriority:bdw */
6708         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6709
6710         /* WaPsrDPAMaskVBlankInSRD:bdw */
6711         I915_WRITE(CHICKEN_PAR1_1,
6712                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6713
6714         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6715         for_each_pipe(dev_priv, pipe) {
6716                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6717                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6718                            BDW_DPRS_MASK_VBLANK_SRD);
6719         }
6720
6721         /* WaVSRefCountFullforceMissDisable:bdw */
6722         /* WaDSRefCountFullforceMissDisable:bdw */
6723         I915_WRITE(GEN7_FF_THREAD_MODE,
6724                    I915_READ(GEN7_FF_THREAD_MODE) &
6725                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6726
6727         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6728                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6729
6730         /* WaDisableSDEUnitClockGating:bdw */
6731         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6732                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6733
6734         /*
6735          * WaProgramL3SqcReg1Default:bdw
6736          * WaTempDisableDOPClkGating:bdw
6737          */
6738         misccpctl = I915_READ(GEN7_MISCCPCTL);
6739         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6740         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6741         /*
6742          * Wait at least 100 clocks before re-enabling clock gating. See
6743          * the definition of L3SQCREG1 in BSpec.
6744          */
6745         POSTING_READ(GEN8_L3SQCREG1);
6746         udelay(1);
6747         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6748
6749         /*
6750          * WaGttCachingOffByDefault:bdw
6751          * GTT cache may not work with big pages, so if those
6752          * are ever enabled GTT cache may need to be disabled.
6753          */
6754         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6755
6756         lpt_init_clock_gating(dev);
6757 }
6758
6759 static void haswell_init_clock_gating(struct drm_device *dev)
6760 {
6761         struct drm_i915_private *dev_priv = dev->dev_private;
6762
6763         ilk_init_lp_watermarks(dev);
6764
6765         /* L3 caching of data atomics doesn't work -- disable it. */
6766         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6767         I915_WRITE(HSW_ROW_CHICKEN3,
6768                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6769
6770         /* This is required by WaCatErrorRejectionIssue:hsw */
6771         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6772                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6773                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6774
6775         /* WaVSRefCountFullforceMissDisable:hsw */
6776         I915_WRITE(GEN7_FF_THREAD_MODE,
6777                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6778
6779         /* WaDisable_RenderCache_OperationalFlush:hsw */
6780         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6781
6782         /* enable HiZ Raw Stall Optimization */
6783         I915_WRITE(CACHE_MODE_0_GEN7,
6784                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6785
6786         /* WaDisable4x2SubspanOptimization:hsw */
6787         I915_WRITE(CACHE_MODE_1,
6788                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6789
6790         /*
6791          * BSpec recommends 8x4 when MSAA is used,
6792          * however in practice 16x4 seems fastest.
6793          *
6794          * Note that PS/WM thread counts depend on the WIZ hashing
6795          * disable bit, which we don't touch here, but it's good
6796          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6797          */
6798         I915_WRITE(GEN7_GT_MODE,
6799                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6800
6801         /* WaSampleCChickenBitEnable:hsw */
6802         I915_WRITE(HALF_SLICE_CHICKEN3,
6803                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6804
6805         /* WaSwitchSolVfFArbitrationPriority:hsw */
6806         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6807
6808         /* WaRsPkgCStateDisplayPMReq:hsw */
6809         I915_WRITE(CHICKEN_PAR1_1,
6810                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6811
6812         lpt_init_clock_gating(dev);
6813 }
6814
6815 static void ivybridge_init_clock_gating(struct drm_device *dev)
6816 {
6817         struct drm_i915_private *dev_priv = dev->dev_private;
6818         uint32_t snpcr;
6819
6820         ilk_init_lp_watermarks(dev);
6821
6822         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6823
6824         /* WaDisableEarlyCull:ivb */
6825         I915_WRITE(_3D_CHICKEN3,
6826                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6827
6828         /* WaDisableBackToBackFlipFix:ivb */
6829         I915_WRITE(IVB_CHICKEN3,
6830                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6831                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6832
6833         /* WaDisablePSDDualDispatchEnable:ivb */
6834         if (IS_IVB_GT1(dev))
6835                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6836                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6837
6838         /* WaDisable_RenderCache_OperationalFlush:ivb */
6839         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6840
6841         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6842         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6843                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6844
6845         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6846         I915_WRITE(GEN7_L3CNTLREG1,
6847                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6848         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6849                    GEN7_WA_L3_CHICKEN_MODE);
6850         if (IS_IVB_GT1(dev))
6851                 I915_WRITE(GEN7_ROW_CHICKEN2,
6852                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6853         else {
6854                 /* must write both registers */
6855                 I915_WRITE(GEN7_ROW_CHICKEN2,
6856                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6857                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6858                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6859         }
6860
6861         /* WaForceL3Serialization:ivb */
6862         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6863                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6864
6865         /*
6866          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6867          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6868          */
6869         I915_WRITE(GEN6_UCGCTL2,
6870                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6871
6872         /* This is required by WaCatErrorRejectionIssue:ivb */
6873         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6874                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6875                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6876
6877         g4x_disable_trickle_feed(dev);
6878
6879         gen7_setup_fixed_func_scheduler(dev_priv);
6880
6881         if (0) { /* causes HiZ corruption on ivb:gt1 */
6882                 /* enable HiZ Raw Stall Optimization */
6883                 I915_WRITE(CACHE_MODE_0_GEN7,
6884                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6885         }
6886
6887         /* WaDisable4x2SubspanOptimization:ivb */
6888         I915_WRITE(CACHE_MODE_1,
6889                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6890
6891         /*
6892          * BSpec recommends 8x4 when MSAA is used,
6893          * however in practice 16x4 seems fastest.
6894          *
6895          * Note that PS/WM thread counts depend on the WIZ hashing
6896          * disable bit, which we don't touch here, but it's good
6897          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6898          */
6899         I915_WRITE(GEN7_GT_MODE,
6900                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6901
6902         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6903         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6904         snpcr |= GEN6_MBC_SNPCR_MED;
6905         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6906
6907         if (!HAS_PCH_NOP(dev))
6908                 cpt_init_clock_gating(dev);
6909
6910         gen6_check_mch_setup(dev);
6911 }
6912
6913 static void valleyview_init_clock_gating(struct drm_device *dev)
6914 {
6915         struct drm_i915_private *dev_priv = dev->dev_private;
6916
6917         /* WaDisableEarlyCull:vlv */
6918         I915_WRITE(_3D_CHICKEN3,
6919                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6920
6921         /* WaDisableBackToBackFlipFix:vlv */
6922         I915_WRITE(IVB_CHICKEN3,
6923                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6924                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6925
6926         /* WaPsdDispatchEnable:vlv */
6927         /* WaDisablePSDDualDispatchEnable:vlv */
6928         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6929                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6930                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6931
6932         /* WaDisable_RenderCache_OperationalFlush:vlv */
6933         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6934
6935         /* WaForceL3Serialization:vlv */
6936         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6937                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6938
6939         /* WaDisableDopClockGating:vlv */
6940         I915_WRITE(GEN7_ROW_CHICKEN2,
6941                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6942
6943         /* This is required by WaCatErrorRejectionIssue:vlv */
6944         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6945                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6946                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6947
6948         gen7_setup_fixed_func_scheduler(dev_priv);
6949
6950         /*
6951          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6952          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6953          */
6954         I915_WRITE(GEN6_UCGCTL2,
6955                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6956
6957         /* WaDisableL3Bank2xClockGate:vlv
6958          * Disabling L3 clock gating- MMIO 940c[25] = 1
6959          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6960         I915_WRITE(GEN7_UCGCTL4,
6961                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6962
6963         /*
6964          * BSpec says this must be set, even though
6965          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6966          */
6967         I915_WRITE(CACHE_MODE_1,
6968                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6969
6970         /*
6971          * BSpec recommends 8x4 when MSAA is used,
6972          * however in practice 16x4 seems fastest.
6973          *
6974          * Note that PS/WM thread counts depend on the WIZ hashing
6975          * disable bit, which we don't touch here, but it's good
6976          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6977          */
6978         I915_WRITE(GEN7_GT_MODE,
6979                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6980
6981         /*
6982          * WaIncreaseL3CreditsForVLVB0:vlv
6983          * This is the hardware default actually.
6984          */
6985         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6986
6987         /*
6988          * WaDisableVLVClockGating_VBIIssue:vlv
6989          * Disable clock gating on th GCFG unit to prevent a delay
6990          * in the reporting of vblank events.
6991          */
6992         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6993 }
6994
6995 static void cherryview_init_clock_gating(struct drm_device *dev)
6996 {
6997         struct drm_i915_private *dev_priv = dev->dev_private;
6998
6999         /* WaVSRefCountFullforceMissDisable:chv */
7000         /* WaDSRefCountFullforceMissDisable:chv */
7001         I915_WRITE(GEN7_FF_THREAD_MODE,
7002                    I915_READ(GEN7_FF_THREAD_MODE) &
7003                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
7004
7005         /* WaDisableSemaphoreAndSyncFlipWait:chv */
7006         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7007                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
7008
7009         /* WaDisableCSUnitClockGating:chv */
7010         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7011                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7012
7013         /* WaDisableSDEUnitClockGating:chv */
7014         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7015                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
7016
7017         /*
7018          * GTT cache may not work with big pages, so if those
7019          * are ever enabled GTT cache may need to be disabled.
7020          */
7021         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7022 }
7023
7024 static void g4x_init_clock_gating(struct drm_device *dev)
7025 {
7026         struct drm_i915_private *dev_priv = dev->dev_private;
7027         uint32_t dspclk_gate;
7028
7029         I915_WRITE(RENCLK_GATE_D1, 0);
7030         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7031                    GS_UNIT_CLOCK_GATE_DISABLE |
7032                    CL_UNIT_CLOCK_GATE_DISABLE);
7033         I915_WRITE(RAMCLK_GATE_D, 0);
7034         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7035                 OVRUNIT_CLOCK_GATE_DISABLE |
7036                 OVCUNIT_CLOCK_GATE_DISABLE;
7037         if (IS_GM45(dev))
7038                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7039         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7040
7041         /* WaDisableRenderCachePipelinedFlush */
7042         I915_WRITE(CACHE_MODE_0,
7043                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
7044
7045         /* WaDisable_RenderCache_OperationalFlush:g4x */
7046         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7047
7048         g4x_disable_trickle_feed(dev);
7049 }
7050
7051 static void crestline_init_clock_gating(struct drm_device *dev)
7052 {
7053         struct drm_i915_private *dev_priv = dev->dev_private;
7054
7055         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7056         I915_WRITE(RENCLK_GATE_D2, 0);
7057         I915_WRITE(DSPCLK_GATE_D, 0);
7058         I915_WRITE(RAMCLK_GATE_D, 0);
7059         I915_WRITE16(DEUC, 0);
7060         I915_WRITE(MI_ARB_STATE,
7061                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7062
7063         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7064         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7065 }
7066
7067 static void broadwater_init_clock_gating(struct drm_device *dev)
7068 {
7069         struct drm_i915_private *dev_priv = dev->dev_private;
7070
7071         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7072                    I965_RCC_CLOCK_GATE_DISABLE |
7073                    I965_RCPB_CLOCK_GATE_DISABLE |
7074                    I965_ISC_CLOCK_GATE_DISABLE |
7075                    I965_FBC_CLOCK_GATE_DISABLE);
7076         I915_WRITE(RENCLK_GATE_D2, 0);
7077         I915_WRITE(MI_ARB_STATE,
7078                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7079
7080         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7081         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7082 }
7083
7084 static void gen3_init_clock_gating(struct drm_device *dev)
7085 {
7086         struct drm_i915_private *dev_priv = dev->dev_private;
7087         u32 dstate = I915_READ(D_STATE);
7088
7089         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7090                 DSTATE_DOT_CLOCK_GATING;
7091         I915_WRITE(D_STATE, dstate);
7092
7093         if (IS_PINEVIEW(dev))
7094                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7095
7096         /* IIR "flip pending" means done if this bit is set */
7097         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7098
7099         /* interrupts should cause a wake up from C3 */
7100         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7101
7102         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7103         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7104
7105         I915_WRITE(MI_ARB_STATE,
7106                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7107 }
7108
7109 static void i85x_init_clock_gating(struct drm_device *dev)
7110 {
7111         struct drm_i915_private *dev_priv = dev->dev_private;
7112
7113         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7114
7115         /* interrupts should cause a wake up from C3 */
7116         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7117                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7118
7119         I915_WRITE(MEM_MODE,
7120                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7121 }
7122
7123 static void i830_init_clock_gating(struct drm_device *dev)
7124 {
7125         struct drm_i915_private *dev_priv = dev->dev_private;
7126
7127         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7128
7129         I915_WRITE(MEM_MODE,
7130                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7131                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7132 }
7133
7134 void intel_init_clock_gating(struct drm_device *dev)
7135 {
7136         struct drm_i915_private *dev_priv = dev->dev_private;
7137
7138         dev_priv->display.init_clock_gating(dev);
7139 }
7140
7141 void intel_suspend_hw(struct drm_device *dev)
7142 {
7143         if (HAS_PCH_LPT(dev))
7144                 lpt_suspend_hw(dev);
7145 }
7146
7147 static void nop_init_clock_gating(struct drm_device *dev)
7148 {
7149         DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7150 }
7151
7152 /**
7153  * intel_init_clock_gating_hooks - setup the clock gating hooks
7154  * @dev_priv: device private
7155  *
7156  * Setup the hooks that configure which clocks of a given platform can be
7157  * gated and also apply various GT and display specific workarounds for these
7158  * platforms. Note that some GT specific workarounds are applied separately
7159  * when GPU contexts or batchbuffers start their execution.
7160  */
7161 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7162 {
7163         if (IS_SKYLAKE(dev_priv))
7164                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7165         else if (IS_KABYLAKE(dev_priv))
7166                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7167         else if (IS_BROXTON(dev_priv))
7168                 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7169         else if (IS_BROADWELL(dev_priv))
7170                 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7171         else if (IS_CHERRYVIEW(dev_priv))
7172                 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7173         else if (IS_HASWELL(dev_priv))
7174                 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7175         else if (IS_IVYBRIDGE(dev_priv))
7176                 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7177         else if (IS_VALLEYVIEW(dev_priv))
7178                 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7179         else if (IS_GEN6(dev_priv))
7180                 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7181         else if (IS_GEN5(dev_priv))
7182                 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7183         else if (IS_G4X(dev_priv))
7184                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7185         else if (IS_CRESTLINE(dev_priv))
7186                 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7187         else if (IS_BROADWATER(dev_priv))
7188                 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7189         else if (IS_GEN3(dev_priv))
7190                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7191         else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7192                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7193         else if (IS_GEN2(dev_priv))
7194                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7195         else {
7196                 MISSING_CASE(INTEL_DEVID(dev_priv));
7197                 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7198         }
7199 }
7200
7201 /* Set up chip specific power management-related functions */
7202 void intel_init_pm(struct drm_device *dev)
7203 {
7204         struct drm_i915_private *dev_priv = dev->dev_private;
7205
7206         intel_fbc_init(dev_priv);
7207
7208         /* For cxsr */
7209         if (IS_PINEVIEW(dev))
7210                 i915_pineview_get_mem_freq(dev);
7211         else if (IS_GEN5(dev))
7212                 i915_ironlake_get_mem_freq(dev);
7213
7214         /* For FIFO watermark updates */
7215         if (INTEL_INFO(dev)->gen >= 9) {
7216                 skl_setup_wm_latency(dev);
7217                 dev_priv->display.update_wm = skl_update_wm;
7218         } else if (HAS_PCH_SPLIT(dev)) {
7219                 ilk_setup_wm_latency(dev);
7220
7221                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7222                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7223                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7224                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7225                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7226                         dev_priv->display.compute_intermediate_wm =
7227                                 ilk_compute_intermediate_wm;
7228                         dev_priv->display.initial_watermarks =
7229                                 ilk_initial_watermarks;
7230                         dev_priv->display.optimize_watermarks =
7231                                 ilk_optimize_watermarks;
7232                 } else {
7233                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7234                                       "Disable CxSR\n");
7235                 }
7236         } else if (IS_CHERRYVIEW(dev)) {
7237                 vlv_setup_wm_latency(dev);
7238                 dev_priv->display.update_wm = vlv_update_wm;
7239         } else if (IS_VALLEYVIEW(dev)) {
7240                 vlv_setup_wm_latency(dev);
7241                 dev_priv->display.update_wm = vlv_update_wm;
7242         } else if (IS_PINEVIEW(dev)) {
7243                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7244                                             dev_priv->is_ddr3,
7245                                             dev_priv->fsb_freq,
7246                                             dev_priv->mem_freq)) {
7247                         DRM_INFO("failed to find known CxSR latency "
7248                                  "(found ddr%s fsb freq %d, mem freq %d), "
7249                                  "disabling CxSR\n",
7250                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7251                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7252                         /* Disable CxSR and never update its watermark again */
7253                         intel_set_memory_cxsr(dev_priv, false);
7254                         dev_priv->display.update_wm = NULL;
7255                 } else
7256                         dev_priv->display.update_wm = pineview_update_wm;
7257         } else if (IS_G4X(dev)) {
7258                 dev_priv->display.update_wm = g4x_update_wm;
7259         } else if (IS_GEN4(dev)) {
7260                 dev_priv->display.update_wm = i965_update_wm;
7261         } else if (IS_GEN3(dev)) {
7262                 dev_priv->display.update_wm = i9xx_update_wm;
7263                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7264         } else if (IS_GEN2(dev)) {
7265                 if (INTEL_INFO(dev)->num_pipes == 1) {
7266                         dev_priv->display.update_wm = i845_update_wm;
7267                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7268                 } else {
7269                         dev_priv->display.update_wm = i9xx_update_wm;
7270                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7271                 }
7272         } else {
7273                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7274         }
7275 }
7276
7277 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7278 {
7279         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7280
7281         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7282                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7283                 return -EAGAIN;
7284         }
7285
7286         I915_WRITE(GEN6_PCODE_DATA, *val);
7287         I915_WRITE(GEN6_PCODE_DATA1, 0);
7288         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7289
7290         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7291                      500)) {
7292                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7293                 return -ETIMEDOUT;
7294         }
7295
7296         *val = I915_READ(GEN6_PCODE_DATA);
7297         I915_WRITE(GEN6_PCODE_DATA, 0);
7298
7299         return 0;
7300 }
7301
7302 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7303 {
7304         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7305
7306         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7307                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7308                 return -EAGAIN;
7309         }
7310
7311         I915_WRITE(GEN6_PCODE_DATA, val);
7312         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7313
7314         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7315                      500)) {
7316                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7317                 return -ETIMEDOUT;
7318         }
7319
7320         I915_WRITE(GEN6_PCODE_DATA, 0);
7321
7322         return 0;
7323 }
7324
7325 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7326 {
7327         /*
7328          * N = val - 0xb7
7329          * Slow = Fast = GPLL ref * N
7330          */
7331         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
7332 }
7333
7334 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7335 {
7336         return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
7337 }
7338
7339 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7340 {
7341         /*
7342          * N = val / 2
7343          * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7344          */
7345         return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
7346 }
7347
7348 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7349 {
7350         /* CHV needs even values */
7351         return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
7352 }
7353
7354 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7355 {
7356         if (IS_GEN9(dev_priv))
7357                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7358                                          GEN9_FREQ_SCALER);
7359         else if (IS_CHERRYVIEW(dev_priv))
7360                 return chv_gpu_freq(dev_priv, val);
7361         else if (IS_VALLEYVIEW(dev_priv))
7362                 return byt_gpu_freq(dev_priv, val);
7363         else
7364                 return val * GT_FREQUENCY_MULTIPLIER;
7365 }
7366
7367 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7368 {
7369         if (IS_GEN9(dev_priv))
7370                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7371                                          GT_FREQUENCY_MULTIPLIER);
7372         else if (IS_CHERRYVIEW(dev_priv))
7373                 return chv_freq_opcode(dev_priv, val);
7374         else if (IS_VALLEYVIEW(dev_priv))
7375                 return byt_freq_opcode(dev_priv, val);
7376         else
7377                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7378 }
7379
7380 struct request_boost {
7381         struct work_struct work;
7382         struct drm_i915_gem_request *req;
7383 };
7384
7385 static void __intel_rps_boost_work(struct work_struct *work)
7386 {
7387         struct request_boost *boost = container_of(work, struct request_boost, work);
7388         struct drm_i915_gem_request *req = boost->req;
7389
7390         if (!i915_gem_request_completed(req, true))
7391                 gen6_rps_boost(to_i915(req->engine->dev), NULL,
7392                                req->emitted_jiffies);
7393
7394         i915_gem_request_unreference__unlocked(req);
7395         kfree(boost);
7396 }
7397
7398 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7399                                        struct drm_i915_gem_request *req)
7400 {
7401         struct request_boost *boost;
7402
7403         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7404                 return;
7405
7406         if (i915_gem_request_completed(req, true))
7407                 return;
7408
7409         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7410         if (boost == NULL)
7411                 return;
7412
7413         i915_gem_request_reference(req);
7414         boost->req = req;
7415
7416         INIT_WORK(&boost->work, __intel_rps_boost_work);
7417         queue_work(to_i915(dev)->wq, &boost->work);
7418 }
7419
7420 void intel_pm_setup(struct drm_device *dev)
7421 {
7422         struct drm_i915_private *dev_priv = dev->dev_private;
7423
7424         mutex_init(&dev_priv->rps.hw_lock);
7425         spin_lock_init(&dev_priv->rps.client_lock);
7426
7427         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7428                           intel_gen6_powersave_work);
7429         INIT_LIST_HEAD(&dev_priv->rps.clients);
7430         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7431         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7432
7433         dev_priv->pm.suspended = false;
7434         atomic_set(&dev_priv->pm.wakeref_count, 0);
7435         atomic_set(&dev_priv->pm.atomic_seq, 0);
7436 }