1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
5 #ifndef _DPU_HW_INTERRUPTS_H
6 #define _DPU_HW_INTERRUPTS_H
8 #include <linux/types.h>
11 #include "dpu_hw_catalog.h"
12 #include "dpu_hw_util.h"
13 #include "dpu_hw_mdss.h"
15 /* When making changes be sure to sync with dpu_intr_set */
16 enum dpu_hw_intr_reg {
19 MDP_SSPP_TOP0_HIST_INTR,
20 /* All MDP_INTFn_INTR should come sequentially */
37 #define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0))
39 #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset)
42 * struct dpu_hw_intr: hw interrupts handling data structure
43 * @hw: virtual address mapping
44 * @ops: function pointer mapping for IRQ handling
45 * @cache_irq_mask: array of IRQ enable masks reg storage created during init
46 * @save_irq_status: array of IRQ status reg storage created during init
47 * @total_irqs: total number of irq_idx mapped in the hw_interrupts
48 * @irq_lock: spinlock for accessing IRQ resources
49 * @irq_cb_tbl: array of IRQ callbacks
52 struct dpu_hw_blk_reg_map hw;
53 u32 cache_irq_mask[MDP_INTR_MAX];
57 unsigned long irq_mask;
58 const struct dpu_intr_reg *intr_set;
61 void (*cb)(void *arg, int irq_idx);
64 } irq_tbl[] __counted_by(total_irqs);
68 * dpu_hw_intr_init(): Initializes the interrupts hw object
69 * @addr: mapped register io address of MDP
70 * @m: pointer to MDSS catalog data
72 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
73 const struct dpu_mdss_cfg *m);
76 * dpu_hw_intr_destroy(): Cleanup interrutps hw object
77 * @intr: pointer to interrupts hw object
79 void dpu_hw_intr_destroy(struct dpu_hw_intr *intr);