drivers/infiniband/hw/hfi1/verbs.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <rdma/ib_mad.h>
  49 #include <rdma/ib_user_verbs.h>
  50 #include <linux/io.h>
  51 #include <linux/module.h>
  52 #include <linux/utsname.h>
  53 #include <linux/rculist.h>
  54 #include <linux/mm.h>
  55 #include <linux/vmalloc.h>
  56
  57 #include "hfi.h"
  58 #include "common.h"
  59 #include "device.h"
  60 #include "trace.h"
  61 #include "qp.h"
  62 #include "verbs_txreq.h"
  63
  64 static unsigned int hfi1_lkey_table_size = 16;
  65 module_param_named(lkey_table_size, hfi1_lkey_table_size, uint,
  66                    S_IRUGO);
  67 MODULE_PARM_DESC(lkey_table_size,
  68                  "LKEY table size in bits (2^n, 1 <= n <= 23)");
  69
  70 static unsigned int hfi1_max_pds = 0xFFFF;
  71 module_param_named(max_pds, hfi1_max_pds, uint, S_IRUGO);
  72 MODULE_PARM_DESC(max_pds,
  73                  "Maximum number of protection domains to support");
  74
  75 static unsigned int hfi1_max_ahs = 0xFFFF;
  76 module_param_named(max_ahs, hfi1_max_ahs, uint, S_IRUGO);
  77 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  78
  79 unsigned int hfi1_max_cqes = 0x2FFFFF;
  80 module_param_named(max_cqes, hfi1_max_cqes, uint, S_IRUGO);
  81 MODULE_PARM_DESC(max_cqes,
  82                  "Maximum number of completion queue entries to support");
  83
  84 unsigned int hfi1_max_cqs = 0x1FFFF;
  85 module_param_named(max_cqs, hfi1_max_cqs, uint, S_IRUGO);
  86 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  87
  88 unsigned int hfi1_max_qp_wrs = 0x3FFF;
  89 module_param_named(max_qp_wrs, hfi1_max_qp_wrs, uint, S_IRUGO);
  90 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  91
  92 unsigned int hfi1_max_qps = 32768;
  93 module_param_named(max_qps, hfi1_max_qps, uint, S_IRUGO);
  94 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  95
  96 unsigned int hfi1_max_sges = 0x60;
  97 module_param_named(max_sges, hfi1_max_sges, uint, S_IRUGO);
  98 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
  99
 100 unsigned int hfi1_max_mcast_grps = 16384;
 101 module_param_named(max_mcast_grps, hfi1_max_mcast_grps, uint, S_IRUGO);
 102 MODULE_PARM_DESC(max_mcast_grps,
 103                  "Maximum number of multicast groups to support");
 104
 105 unsigned int hfi1_max_mcast_qp_attached = 16;
 106 module_param_named(max_mcast_qp_attached, hfi1_max_mcast_qp_attached,
 107                    uint, S_IRUGO);
 108 MODULE_PARM_DESC(max_mcast_qp_attached,
 109                  "Maximum number of attached QPs to support");
 110
 111 unsigned int hfi1_max_srqs = 1024;
 112 module_param_named(max_srqs, hfi1_max_srqs, uint, S_IRUGO);
 113 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
 114
 115 unsigned int hfi1_max_srq_sges = 128;
 116 module_param_named(max_srq_sges, hfi1_max_srq_sges, uint, S_IRUGO);
 117 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
 118
 119 unsigned int hfi1_max_srq_wrs = 0x1FFFF;
 120 module_param_named(max_srq_wrs, hfi1_max_srq_wrs, uint, S_IRUGO);
 121 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
 122
 123 unsigned short piothreshold = 256;
 124 module_param(piothreshold, ushort, S_IRUGO);
 125 MODULE_PARM_DESC(piothreshold, "size used to determine sdma vs. pio");
 126
 127 #define COPY_CACHELESS 1
 128 #define COPY_ADAPTIVE  2
 129 static unsigned int sge_copy_mode;
 130 module_param(sge_copy_mode, uint, S_IRUGO);
 131 MODULE_PARM_DESC(sge_copy_mode,
 132                  "Verbs copy mode: 0 use memcpy, 1 use cacheless copy, 2 adapt based on WSS");
 133
 134 static void verbs_sdma_complete(
 135         struct sdma_txreq *cookie,
 136         int status);
 137
 138 static int pio_wait(struct rvt_qp *qp,
 139                     struct send_context *sc,
 140                     struct hfi1_pkt_state *ps,
 141                     u32 flag);
 142
 143 /* Length of buffer to create verbs txreq cache name */
 144 #define TXREQ_NAME_LEN 24
 145
 146 static uint wss_threshold;
 147 module_param(wss_threshold, uint, S_IRUGO);
 148 MODULE_PARM_DESC(wss_threshold, "Percentage (1-100) of LLC to use as a threshold for a cacheless copy");
 149 static uint wss_clean_period = 256;
 150 module_param(wss_clean_period, uint, S_IRUGO);
 151 MODULE_PARM_DESC(wss_clean_period, "Count of verbs copies before an entry in the page copy table is cleaned");
 152
 153 /* memory working set size */
 154 struct hfi1_wss {
 155         unsigned long *entries;
 156         atomic_t total_count;
 157         atomic_t clean_counter;
 158         atomic_t clean_entry;
 159
 160         int threshold;
 161         int num_entries;
 162         long pages_mask;
 163 };
 164
 165 static struct hfi1_wss wss;
 166
 167 int hfi1_wss_init(void)
 168 {
 169         long llc_size;
 170         long llc_bits;
 171         long table_size;
 172         long table_bits;
 173
 174         /* check for a valid percent range - default to 80 if none or invalid */
 175         if (wss_threshold < 1 || wss_threshold > 100)
 176                 wss_threshold = 80;
 177         /* reject a wildly large period */
 178         if (wss_clean_period > 1000000)
 179                 wss_clean_period = 256;
 180         /* reject a zero period */
 181         if (wss_clean_period == 0)
 182                 wss_clean_period = 1;
 183
 184         /*
 185          * Calculate the table size - the next power of 2 larger than the
 186          * LLC size.  LLC size is in KiB.
 187          */
 188         llc_size = wss_llc_size() * 1024;
 189         table_size = roundup_pow_of_two(llc_size);
 190
 191         /* one bit per page in rounded up table */
 192         llc_bits = llc_size / PAGE_SIZE;
 193         table_bits = table_size / PAGE_SIZE;
 194         wss.pages_mask = table_bits - 1;
 195         wss.num_entries = table_bits / BITS_PER_LONG;
 196
 197         wss.threshold = (llc_bits * wss_threshold) / 100;
 198         if (wss.threshold == 0)
 199                 wss.threshold = 1;
 200
 201         atomic_set(&wss.clean_counter, wss_clean_period);
 202
 203         wss.entries = kcalloc(wss.num_entries, sizeof(*wss.entries),
 204                               GFP_KERNEL);
 205         if (!wss.entries) {
 206                 hfi1_wss_exit();
 207                 return -ENOMEM;
 208         }
 209
 210         return 0;
 211 }
 212
 213 void hfi1_wss_exit(void)
 214 {
 215         /* coded to handle partially initialized and repeat callers */
 216         kfree(wss.entries);
 217         wss.entries = NULL;
 218 }
 219
 220 /*
 221  * Advance the clean counter.  When the clean period has expired,
 222  * clean an entry.
 223  *
 224  * This is implemented in atomics to avoid locking.  Because multiple
 225  * variables are involved, it can be racy which can lead to slightly
 226  * inaccurate information.  Since this is only a heuristic, this is
 227  * OK.  Any innaccuracies will clean themselves out as the counter
 228  * advances.  That said, it is unlikely the entry clean operation will
 229  * race - the next possible racer will not start until the next clean
 230  * period.
 231  *
 232  * The clean counter is implemented as a decrement to zero.  When zero
 233  * is reached an entry is cleaned.
 234  */
 235 static void wss_advance_clean_counter(void)
 236 {
 237         int entry;
 238         int weight;
 239         unsigned long bits;
 240
 241         /* become the cleaner if we decrement the counter to zero */
 242         if (atomic_dec_and_test(&wss.clean_counter)) {
 243                 /*
 244                  * Set, not add, the clean period.  This avoids an issue
 245                  * where the counter could decrement below the clean period.
 246                  * Doing a set can result in lost decrements, slowing the
 247                  * clean advance.  Since this a heuristic, this possible
 248                  * slowdown is OK.
 249                  *
 250                  * An alternative is to loop, advancing the counter by a
 251                  * clean period until the result is > 0. However, this could
 252                  * lead to several threads keeping another in the clean loop.
 253                  * This could be mitigated by limiting the number of times
 254                  * we stay in the loop.
 255                  */
 256                 atomic_set(&wss.clean_counter, wss_clean_period);
 257
 258                 /*
 259                  * Uniquely grab the entry to clean and move to next.
 260                  * The current entry is always the lower bits of
 261                  * wss.clean_entry.  The table size, wss.num_entries,
 262                  * is always a power-of-2.
 263                  */
 264                 entry = (atomic_inc_return(&wss.clean_entry) - 1)
 265                         & (wss.num_entries - 1);
 266
 267                 /* clear the entry and count the bits */
 268                 bits = xchg(&wss.entries[entry], 0);
 269                 weight = hweight64((u64)bits);
 270                 /* only adjust the contended total count if needed */
 271                 if (weight)
 272                         atomic_sub(weight, &wss.total_count);
 273         }
 274 }
 275
 276 /*
 277  * Insert the given address into the working set array.
 278  */
 279 static void wss_insert(void *address)
 280 {
 281         u32 page = ((unsigned long)address >> PAGE_SHIFT) & wss.pages_mask;
 282         u32 entry = page / BITS_PER_LONG; /* assumes this ends up a shift */
 283         u32 nr = page & (BITS_PER_LONG - 1);
 284
 285         if (!test_and_set_bit(nr, &wss.entries[entry]))
 286                 atomic_inc(&wss.total_count);
 287
 288         wss_advance_clean_counter();
 289 }
 290
 291 /*
 292  * Is the working set larger than the threshold?
 293  */
 294 static inline int wss_exceeds_threshold(void)
 295 {
 296         return atomic_read(&wss.total_count) >= wss.threshold;
 297 }
 298
 299 /*
 300  * Length of header by opcode, 0 --> not supported
 301  */
 302 const u8 hdr_len_by_opcode[256] = {
 303         /* RC */
 304         [IB_OPCODE_RC_SEND_FIRST]                     = 12 + 8,
 305         [IB_OPCODE_RC_SEND_MIDDLE]                    = 12 + 8,
 306         [IB_OPCODE_RC_SEND_LAST]                      = 12 + 8,
 307         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 308         [IB_OPCODE_RC_SEND_ONLY]                      = 12 + 8,
 309         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 310         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 311         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 312         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = 12 + 8,
 313         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 314         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 315         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 316         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = 12 + 8 + 16,
 317         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = 12 + 8 + 4,
 318         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = 12 + 8,
 319         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = 12 + 8 + 4,
 320         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = 12 + 8 + 4,
 321         [IB_OPCODE_RC_ACKNOWLEDGE]                    = 12 + 8 + 4,
 322         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = 12 + 8 + 4 + 8,
 323         [IB_OPCODE_RC_COMPARE_SWAP]                   = 12 + 8 + 28,
 324         [IB_OPCODE_RC_FETCH_ADD]                      = 12 + 8 + 28,
 325         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = 12 + 8 + 4,
 326         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = 12 + 8 + 4,
 327         /* UC */
 328         [IB_OPCODE_UC_SEND_FIRST]                     = 12 + 8,
 329         [IB_OPCODE_UC_SEND_MIDDLE]                    = 12 + 8,
 330         [IB_OPCODE_UC_SEND_LAST]                      = 12 + 8,
 331         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = 12 + 8 + 4,
 332         [IB_OPCODE_UC_SEND_ONLY]                      = 12 + 8,
 333         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 4,
 334         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = 12 + 8 + 16,
 335         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = 12 + 8,
 336         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = 12 + 8,
 337         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = 12 + 8 + 4,
 338         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = 12 + 8 + 16,
 339         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = 12 + 8 + 20,
 340         /* UD */
 341         [IB_OPCODE_UD_SEND_ONLY]                      = 12 + 8 + 8,
 342         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = 12 + 8 + 12
 343 };
 344
 345 static const opcode_handler opcode_handler_tbl[256] = {
 346         /* RC */
 347         [IB_OPCODE_RC_SEND_FIRST]                     = &hfi1_rc_rcv,
 348         [IB_OPCODE_RC_SEND_MIDDLE]                    = &hfi1_rc_rcv,
 349         [IB_OPCODE_RC_SEND_LAST]                      = &hfi1_rc_rcv,
 350         [IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 351         [IB_OPCODE_RC_SEND_ONLY]                      = &hfi1_rc_rcv,
 352         [IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_rc_rcv,
 353         [IB_OPCODE_RC_RDMA_WRITE_FIRST]               = &hfi1_rc_rcv,
 354         [IB_OPCODE_RC_RDMA_WRITE_MIDDLE]              = &hfi1_rc_rcv,
 355         [IB_OPCODE_RC_RDMA_WRITE_LAST]                = &hfi1_rc_rcv,
 356         [IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 357         [IB_OPCODE_RC_RDMA_WRITE_ONLY]                = &hfi1_rc_rcv,
 358         [IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_rc_rcv,
 359         [IB_OPCODE_RC_RDMA_READ_REQUEST]              = &hfi1_rc_rcv,
 360         [IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST]       = &hfi1_rc_rcv,
 361         [IB_OPCODE_RC_RDMA_READ_RESPONSE_MIDDLE]      = &hfi1_rc_rcv,
 362         [IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST]        = &hfi1_rc_rcv,
 363         [IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY]        = &hfi1_rc_rcv,
 364         [IB_OPCODE_RC_ACKNOWLEDGE]                    = &hfi1_rc_rcv,
 365         [IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE]             = &hfi1_rc_rcv,
 366         [IB_OPCODE_RC_COMPARE_SWAP]                   = &hfi1_rc_rcv,
 367         [IB_OPCODE_RC_FETCH_ADD]                      = &hfi1_rc_rcv,
 368         [IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 369         [IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE]      = &hfi1_rc_rcv,
 370         /* UC */
 371         [IB_OPCODE_UC_SEND_FIRST]                     = &hfi1_uc_rcv,
 372         [IB_OPCODE_UC_SEND_MIDDLE]                    = &hfi1_uc_rcv,
 373         [IB_OPCODE_UC_SEND_LAST]                      = &hfi1_uc_rcv,
 374         [IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 375         [IB_OPCODE_UC_SEND_ONLY]                      = &hfi1_uc_rcv,
 376         [IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_uc_rcv,
 377         [IB_OPCODE_UC_RDMA_WRITE_FIRST]               = &hfi1_uc_rcv,
 378         [IB_OPCODE_UC_RDMA_WRITE_MIDDLE]              = &hfi1_uc_rcv,
 379         [IB_OPCODE_UC_RDMA_WRITE_LAST]                = &hfi1_uc_rcv,
 380         [IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 381         [IB_OPCODE_UC_RDMA_WRITE_ONLY]                = &hfi1_uc_rcv,
 382         [IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = &hfi1_uc_rcv,
 383         /* UD */
 384         [IB_OPCODE_UD_SEND_ONLY]                      = &hfi1_ud_rcv,
 385         [IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE]       = &hfi1_ud_rcv,
 386         /* CNP */
 387         [IB_OPCODE_CNP]                               = &hfi1_cnp_rcv
 388 };
 389
 390 #define OPMASK 0x1f
 391
 392 static const u32 pio_opmask[BIT(3)] = {
 393         /* RC */
 394         [IB_OPCODE_RC >> 5] =
 395                 BIT(RC_OP(SEND_ONLY) & OPMASK) |
 396                 BIT(RC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 397                 BIT(RC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 398                 BIT(RC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK) |
 399                 BIT(RC_OP(RDMA_READ_REQUEST) & OPMASK) |
 400                 BIT(RC_OP(ACKNOWLEDGE) & OPMASK) |
 401                 BIT(RC_OP(ATOMIC_ACKNOWLEDGE) & OPMASK) |
 402                 BIT(RC_OP(COMPARE_SWAP) & OPMASK) |
 403                 BIT(RC_OP(FETCH_ADD) & OPMASK),
 404         /* UC */
 405         [IB_OPCODE_UC >> 5] =
 406                 BIT(UC_OP(SEND_ONLY) & OPMASK) |
 407                 BIT(UC_OP(SEND_ONLY_WITH_IMMEDIATE) & OPMASK) |
 408                 BIT(UC_OP(RDMA_WRITE_ONLY) & OPMASK) |
 409                 BIT(UC_OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE) & OPMASK),
 410 };
 411
 412 /*
 413  * System image GUID.
 414  */
 415 __be64 ib_hfi1_sys_image_guid;
 416
 417 /**
 418  * hfi1_copy_sge - copy data to SGE memory
 419  * @ss: the SGE state
 420  * @data: the data to copy
 421  * @length: the length of the data
 422  * @copy_last: do a separate copy of the last 8 bytes
 423  */
 424 void hfi1_copy_sge(
 425         struct rvt_sge_state *ss,
 426         void *data, u32 length,
 427         int release,
 428         int copy_last)
 429 {
 430         struct rvt_sge *sge = &ss->sge;
 431         int in_last = 0;
 432         int i;
 433         int cacheless_copy = 0;
 434
 435         if (sge_copy_mode == COPY_CACHELESS) {
 436                 cacheless_copy = length >= PAGE_SIZE;
 437         } else if (sge_copy_mode == COPY_ADAPTIVE) {
 438                 if (length >= PAGE_SIZE) {
 439                         /*
 440                          * NOTE: this *assumes*:
 441                          * o The first vaddr is the dest.
 442                          * o If multiple pages, then vaddr is sequential.
 443                          */
 444                         wss_insert(sge->vaddr);
 445                         if (length >= (2 * PAGE_SIZE))
 446                                 wss_insert(sge->vaddr + PAGE_SIZE);
 447
 448                         cacheless_copy = wss_exceeds_threshold();
 449                 } else {
 450                         wss_advance_clean_counter();
 451                 }
 452         }
 453         if (copy_last) {
 454                 if (length > 8) {
 455                         length -= 8;
 456                 } else {
 457                         copy_last = 0;
 458                         in_last = 1;
 459                 }
 460         }
 461
 462 again:
 463         while (length) {
 464                 u32 len = sge->length;
 465
 466                 if (len > length)
 467                         len = length;
 468                 if (len > sge->sge_length)
 469                         len = sge->sge_length;
 470                 WARN_ON_ONCE(len == 0);
 471                 if (unlikely(in_last)) {
 472                         /* enforce byte transfer ordering */
 473                         for (i = 0; i < len; i++)
 474                                 ((u8 *)sge->vaddr)[i] = ((u8 *)data)[i];
 475                 } else if (cacheless_copy) {
 476                         cacheless_memcpy(sge->vaddr, data, len);
 477                 } else {
 478                         memcpy(sge->vaddr, data, len);
 479                 }
 480                 sge->vaddr += len;
 481                 sge->length -= len;
 482                 sge->sge_length -= len;
 483                 if (sge->sge_length == 0) {
 484                         if (release)
 485                                 rvt_put_mr(sge->mr);
 486                         if (--ss->num_sge)
 487                                 *sge = *ss->sg_list++;
 488                 } else if (sge->length == 0 && sge->mr->lkey) {
 489                         if (++sge->n >= RVT_SEGSZ) {
 490                                 if (++sge->m >= sge->mr->mapsz)
 491                                         break;
 492                                 sge->n = 0;
 493                         }
 494                         sge->vaddr =
 495                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 496                         sge->length =
 497                                 sge->mr->map[sge->m]->segs[sge->n].length;
 498                 }
 499                 data += len;
 500                 length -= len;
 501         }
 502
 503         if (copy_last) {
 504                 copy_last = 0;
 505                 in_last = 1;
 506                 length = 8;
 507                 goto again;
 508         }
 509 }
 510
 511 /**
 512  * hfi1_skip_sge - skip over SGE memory
 513  * @ss: the SGE state
 514  * @length: the number of bytes to skip
 515  */
 516 void hfi1_skip_sge(struct rvt_sge_state *ss, u32 length, int release)
 517 {
 518         struct rvt_sge *sge = &ss->sge;
 519
 520         while (length) {
 521                 u32 len = sge->length;
 522
 523                 if (len > length)
 524                         len = length;
 525                 if (len > sge->sge_length)
 526                         len = sge->sge_length;
 527                 WARN_ON_ONCE(len == 0);
 528                 sge->vaddr += len;
 529                 sge->length -= len;
 530                 sge->sge_length -= len;
 531                 if (sge->sge_length == 0) {
 532                         if (release)
 533                                 rvt_put_mr(sge->mr);
 534                         if (--ss->num_sge)
 535                                 *sge = *ss->sg_list++;
 536                 } else if (sge->length == 0 && sge->mr->lkey) {
 537                         if (++sge->n >= RVT_SEGSZ) {
 538                                 if (++sge->m >= sge->mr->mapsz)
 539                                         break;
 540                                 sge->n = 0;
 541                         }
 542                         sge->vaddr =
 543                                 sge->mr->map[sge->m]->segs[sge->n].vaddr;
 544                         sge->length =
 545                                 sge->mr->map[sge->m]->segs[sge->n].length;
 546                 }
 547                 length -= len;
 548         }
 549 }
 550
 551 /*
 552  * Make sure the QP is ready and able to accept the given opcode.
 553  */
 554 static inline opcode_handler qp_ok(int opcode, struct hfi1_packet *packet)
 555 {
 556         if (!(ib_rvt_state_ops[packet->qp->state] & RVT_PROCESS_RECV_OK))
 557                 return NULL;
 558         if (((opcode & RVT_OPCODE_QP_MASK) == packet->qp->allowed_ops) ||
 559             (opcode == IB_OPCODE_CNP))
 560                 return opcode_handler_tbl[opcode];
 561
 562         return NULL;
 563 }
 564
 565 /**
 566  * hfi1_ib_rcv - process an incoming packet
 567  * @packet: data packet information
 568  *
 569  * This is called to process an incoming packet at interrupt level.
 570  *
 571  * Tlen is the length of the header + data + CRC in bytes.
 572  */
 573 void hfi1_ib_rcv(struct hfi1_packet *packet)
 574 {
 575         struct hfi1_ctxtdata *rcd = packet->rcd;
 576         struct ib_header *hdr = packet->hdr;
 577         u32 tlen = packet->tlen;
 578         struct hfi1_pportdata *ppd = rcd->ppd;
 579         struct hfi1_ibport *ibp = &ppd->ibport_data;
 580         struct rvt_dev_info *rdi = &ppd->dd->verbs_dev.rdi;
 581         opcode_handler packet_handler;
 582         unsigned long flags;
 583         u32 qp_num;
 584         int lnh;
 585         u8 opcode;
 586         u16 lid;
 587
 588         /* Check for GRH */
 589         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
 590         if (lnh == HFI1_LRH_BTH) {
 591                 packet->ohdr = &hdr->u.oth;
 592         } else if (lnh == HFI1_LRH_GRH) {
 593                 u32 vtf;
 594
 595                 packet->ohdr = &hdr->u.l.oth;
 596                 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
 597                         goto drop;
 598                 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
 599                 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
 600                         goto drop;
 601                 packet->rcv_flags |= HFI1_HAS_GRH;
 602         } else {
 603                 goto drop;
 604         }
 605
 606         trace_input_ibhdr(rcd->dd, hdr);
 607
 608         opcode = (be32_to_cpu(packet->ohdr->bth[0]) >> 24);
 609         inc_opstats(tlen, &rcd->opstats->stats[opcode]);
 610
 611         /* Get the destination QP number. */
 612         qp_num = be32_to_cpu(packet->ohdr->bth[1]) & RVT_QPN_MASK;
 613         lid = be16_to_cpu(hdr->lrh[1]);
 614         if (unlikely((lid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
 615                      (lid != be16_to_cpu(IB_LID_PERMISSIVE)))) {
 616                 struct rvt_mcast *mcast;
 617                 struct rvt_mcast_qp *p;
 618
 619                 if (lnh != HFI1_LRH_GRH)
 620                         goto drop;
 621                 mcast = rvt_mcast_find(&ibp->rvp, &hdr->u.l.grh.dgid);
 622                 if (!mcast)
 623                         goto drop;
 624                 list_for_each_entry_rcu(p, &mcast->qp_list, list) {
 625                         packet->qp = p->qp;
 626                         spin_lock_irqsave(&packet->qp->r_lock, flags);
 627                         packet_handler = qp_ok(opcode, packet);
 628                         if (likely(packet_handler))
 629                                 packet_handler(packet);
 630                         else
 631                                 ibp->rvp.n_pkt_drops++;
 632                         spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 633                 }
 634                 /*
 635                  * Notify rvt_multicast_detach() if it is waiting for us
 636                  * to finish.
 637                  */
 638                 if (atomic_dec_return(&mcast->refcount) <= 1)
 639                         wake_up(&mcast->wait);
 640         } else {
 641                 rcu_read_lock();
 642                 packet->qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
 643                 if (!packet->qp) {
 644                         rcu_read_unlock();
 645                         goto drop;
 646                 }
 647                 spin_lock_irqsave(&packet->qp->r_lock, flags);
 648                 packet_handler = qp_ok(opcode, packet);
 649                 if (likely(packet_handler))
 650                         packet_handler(packet);
 651                 else
 652                         ibp->rvp.n_pkt_drops++;
 653                 spin_unlock_irqrestore(&packet->qp->r_lock, flags);
 654                 rcu_read_unlock();
 655         }
 656         return;
 657
 658 drop:
 659         ibp->rvp.n_pkt_drops++;
 660 }
 661
 662 /*
 663  * This is called from a timer to check for QPs
 664  * which need kernel memory in order to send a packet.
 665  */
 666 static void mem_timer(unsigned long data)
 667 {
 668         struct hfi1_ibdev *dev = (struct hfi1_ibdev *)data;
 669         struct list_head *list = &dev->memwait;
 670         struct rvt_qp *qp = NULL;
 671         struct iowait *wait;
 672         unsigned long flags;
 673         struct hfi1_qp_priv *priv;
 674
 675         write_seqlock_irqsave(&dev->iowait_lock, flags);
 676         if (!list_empty(list)) {
 677                 wait = list_first_entry(list, struct iowait, list);
 678                 qp = iowait_to_qp(wait);
 679                 priv = qp->priv;
 680                 list_del_init(&priv->s_iowait.list);
 681                 priv->s_iowait.lock = NULL;
 682                 /* refcount held until actual wake up */
 683                 if (!list_empty(list))
 684                         mod_timer(&dev->mem_timer, jiffies + 1);
 685         }
 686         write_sequnlock_irqrestore(&dev->iowait_lock, flags);
 687
 688         if (qp)
 689                 hfi1_qp_wakeup(qp, RVT_S_WAIT_KMEM);
 690 }
 691
 692 void update_sge(struct rvt_sge_state *ss, u32 length)
 693 {
 694         struct rvt_sge *sge = &ss->sge;
 695
 696         sge->vaddr += length;
 697         sge->length -= length;
 698         sge->sge_length -= length;
 699         if (sge->sge_length == 0) {
 700                 if (--ss->num_sge)
 701                         *sge = *ss->sg_list++;
 702         } else if (sge->length == 0 && sge->mr->lkey) {
 703                 if (++sge->n >= RVT_SEGSZ) {
 704                         if (++sge->m >= sge->mr->mapsz)
 705                                 return;
 706                         sge->n = 0;
 707                 }
 708                 sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
 709                 sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
 710         }
 711 }
 712
 713 /*
 714  * This is called with progress side lock held.
 715  */
 716 /* New API */
 717 static void verbs_sdma_complete(
 718         struct sdma_txreq *cookie,
 719         int status)
 720 {
 721         struct verbs_txreq *tx =
 722                 container_of(cookie, struct verbs_txreq, txreq);
 723         struct rvt_qp *qp = tx->qp;
 724
 725         spin_lock(&qp->s_lock);
 726         if (tx->wqe) {
 727                 hfi1_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
 728         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
 729                 struct ib_header *hdr;
 730
 731                 hdr = &tx->phdr.hdr;
 732                 hfi1_rc_send_complete(qp, hdr);
 733         }
 734         spin_unlock(&qp->s_lock);
 735
 736         hfi1_put_txreq(tx);
 737 }
 738
 739 static int wait_kmem(struct hfi1_ibdev *dev,
 740                      struct rvt_qp *qp,
 741                      struct hfi1_pkt_state *ps)
 742 {
 743         struct hfi1_qp_priv *priv = qp->priv;
 744         unsigned long flags;
 745         int ret = 0;
 746
 747         spin_lock_irqsave(&qp->s_lock, flags);
 748         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 749                 write_seqlock(&dev->iowait_lock);
 750                 list_add_tail(&ps->s_txreq->txreq.list,
 751                               &priv->s_iowait.tx_head);
 752                 if (list_empty(&priv->s_iowait.list)) {
 753                         if (list_empty(&dev->memwait))
 754                                 mod_timer(&dev->mem_timer, jiffies + 1);
 755                         qp->s_flags |= RVT_S_WAIT_KMEM;
 756                         list_add_tail(&priv->s_iowait.list, &dev->memwait);
 757                         priv->s_iowait.lock = &dev->iowait_lock;
 758                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_KMEM);
 759                         rvt_get_qp(qp);
 760                 }
 761                 write_sequnlock(&dev->iowait_lock);
 762                 qp->s_flags &= ~RVT_S_BUSY;
 763                 ret = -EBUSY;
 764         }
 765         spin_unlock_irqrestore(&qp->s_lock, flags);
 766
 767         return ret;
 768 }
 769
 770 /*
 771  * This routine calls txadds for each sg entry.
 772  *
 773  * Add failures will revert the sge cursor
 774  */
 775 static noinline int build_verbs_ulp_payload(
 776         struct sdma_engine *sde,
 777         u32 length,
 778         struct verbs_txreq *tx)
 779 {
 780         struct rvt_sge_state *ss = tx->ss;
 781         struct rvt_sge *sg_list = ss->sg_list;
 782         struct rvt_sge sge = ss->sge;
 783         u8 num_sge = ss->num_sge;
 784         u32 len;
 785         int ret = 0;
 786
 787         while (length) {
 788                 len = ss->sge.length;
 789                 if (len > length)
 790                         len = length;
 791                 if (len > ss->sge.sge_length)
 792                         len = ss->sge.sge_length;
 793                 WARN_ON_ONCE(len == 0);
 794                 ret = sdma_txadd_kvaddr(
 795                         sde->dd,
 796                         &tx->txreq,
 797                         ss->sge.vaddr,
 798                         len);
 799                 if (ret)
 800                         goto bail_txadd;
 801                 update_sge(ss, len);
 802                 length -= len;
 803         }
 804         return ret;
 805 bail_txadd:
 806         /* unwind cursor */
 807         ss->sge = sge;
 808         ss->num_sge = num_sge;
 809         ss->sg_list = sg_list;
 810         return ret;
 811 }
 812
 813 /*
 814  * Build the number of DMA descriptors needed to send length bytes of data.
 815  *
 816  * NOTE: DMA mapping is held in the tx until completed in the ring or
 817  *       the tx desc is freed without having been submitted to the ring
 818  *
 819  * This routine ensures all the helper routine calls succeed.
 820  */
 821 /* New API */
 822 static int build_verbs_tx_desc(
 823         struct sdma_engine *sde,
 824         u32 length,
 825         struct verbs_txreq *tx,
 826         struct hfi1_ahg_info *ahg_info,
 827         u64 pbc)
 828 {
 829         int ret = 0;
 830         struct hfi1_sdma_header *phdr = &tx->phdr;
 831         u16 hdrbytes = tx->hdr_dwords << 2;
 832
 833         if (!ahg_info->ahgcount) {
 834                 ret = sdma_txinit_ahg(
 835                         &tx->txreq,
 836                         ahg_info->tx_flags,
 837                         hdrbytes + length,
 838                         ahg_info->ahgidx,
 839                         0,
 840                         NULL,
 841                         0,
 842                         verbs_sdma_complete);
 843                 if (ret)
 844                         goto bail_txadd;
 845                 phdr->pbc = cpu_to_le64(pbc);
 846                 ret = sdma_txadd_kvaddr(
 847                         sde->dd,
 848                         &tx->txreq,
 849                         phdr,
 850                         hdrbytes);
 851                 if (ret)
 852                         goto bail_txadd;
 853         } else {
 854                 ret = sdma_txinit_ahg(
 855                         &tx->txreq,
 856                         ahg_info->tx_flags,
 857                         length,
 858                         ahg_info->ahgidx,
 859                         ahg_info->ahgcount,
 860                         ahg_info->ahgdesc,
 861                         hdrbytes,
 862                         verbs_sdma_complete);
 863                 if (ret)
 864                         goto bail_txadd;
 865         }
 866
 867         /* add the ulp payload - if any. tx->ss can be NULL for acks */
 868         if (tx->ss)
 869                 ret = build_verbs_ulp_payload(sde, length, tx);
 870 bail_txadd:
 871         return ret;
 872 }
 873
 874 int hfi1_verbs_send_dma(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 875                         u64 pbc)
 876 {
 877         struct hfi1_qp_priv *priv = qp->priv;
 878         struct hfi1_ahg_info *ahg_info = priv->s_ahg;
 879         u32 hdrwords = qp->s_hdrwords;
 880         u32 len = ps->s_txreq->s_cur_size;
 881         u32 plen = hdrwords + ((len + 3) >> 2) + 2; /* includes pbc */
 882         struct hfi1_ibdev *dev = ps->dev;
 883         struct hfi1_pportdata *ppd = ps->ppd;
 884         struct verbs_txreq *tx;
 885         u64 pbc_flags = 0;
 886         u8 sc5 = priv->s_sc;
 887
 888         int ret;
 889
 890         tx = ps->s_txreq;
 891         if (!sdma_txreq_built(&tx->txreq)) {
 892                 if (likely(pbc == 0)) {
 893                         u32 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
 894                         /* No vl15 here */
 895                         /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
 896                         pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
 897
 898                         pbc = create_pbc(ppd,
 899                                          pbc_flags,
 900                                          qp->srate_mbps,
 901                                          vl,
 902                                          plen);
 903                 }
 904                 tx->wqe = qp->s_wqe;
 905                 ret = build_verbs_tx_desc(tx->sde, len, tx, ahg_info, pbc);
 906                 if (unlikely(ret))
 907                         goto bail_build;
 908         }
 909         ret =  sdma_send_txreq(tx->sde, &priv->s_iowait, &tx->txreq);
 910         if (unlikely(ret < 0)) {
 911                 if (ret == -ECOMM)
 912                         goto bail_ecomm;
 913                 return ret;
 914         }
 915         trace_sdma_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
 916                                 &ps->s_txreq->phdr.hdr);
 917         return ret;
 918
 919 bail_ecomm:
 920         /* The current one got "sent" */
 921         return 0;
 922 bail_build:
 923         ret = wait_kmem(dev, qp, ps);
 924         if (!ret) {
 925                 /* free txreq - bad state */
 926                 hfi1_put_txreq(ps->s_txreq);
 927                 ps->s_txreq = NULL;
 928         }
 929         return ret;
 930 }
 931
 932 /*
 933  * If we are now in the error state, return zero to flush the
 934  * send work request.
 935  */
 936 static int pio_wait(struct rvt_qp *qp,
 937                     struct send_context *sc,
 938                     struct hfi1_pkt_state *ps,
 939                     u32 flag)
 940 {
 941         struct hfi1_qp_priv *priv = qp->priv;
 942         struct hfi1_devdata *dd = sc->dd;
 943         struct hfi1_ibdev *dev = &dd->verbs_dev;
 944         unsigned long flags;
 945         int ret = 0;
 946
 947         /*
 948          * Note that as soon as want_buffer() is called and
 949          * possibly before it returns, sc_piobufavail()
 950          * could be called. Therefore, put QP on the I/O wait list before
 951          * enabling the PIO avail interrupt.
 952          */
 953         spin_lock_irqsave(&qp->s_lock, flags);
 954         if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
 955                 write_seqlock(&dev->iowait_lock);
 956                 list_add_tail(&ps->s_txreq->txreq.list,
 957                               &priv->s_iowait.tx_head);
 958                 if (list_empty(&priv->s_iowait.list)) {
 959                         struct hfi1_ibdev *dev = &dd->verbs_dev;
 960                         int was_empty;
 961
 962                         dev->n_piowait += !!(flag & RVT_S_WAIT_PIO);
 963                         dev->n_piodrain += !!(flag & RVT_S_WAIT_PIO_DRAIN);
 964                         qp->s_flags |= flag;
 965                         was_empty = list_empty(&sc->piowait);
 966                         list_add_tail(&priv->s_iowait.list, &sc->piowait);
 967                         priv->s_iowait.lock = &dev->iowait_lock;
 968                         trace_hfi1_qpsleep(qp, RVT_S_WAIT_PIO);
 969                         rvt_get_qp(qp);
 970                         /* counting: only call wantpiobuf_intr if first user */
 971                         if (was_empty)
 972                                 hfi1_sc_wantpiobuf_intr(sc, 1);
 973                 }
 974                 write_sequnlock(&dev->iowait_lock);
 975                 qp->s_flags &= ~RVT_S_BUSY;
 976                 ret = -EBUSY;
 977         }
 978         spin_unlock_irqrestore(&qp->s_lock, flags);
 979         return ret;
 980 }
 981
 982 static void verbs_pio_complete(void *arg, int code)
 983 {
 984         struct rvt_qp *qp = (struct rvt_qp *)arg;
 985         struct hfi1_qp_priv *priv = qp->priv;
 986
 987         if (iowait_pio_dec(&priv->s_iowait))
 988                 iowait_drain_wakeup(&priv->s_iowait);
 989 }
 990
 991 int hfi1_verbs_send_pio(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
 992                         u64 pbc)
 993 {
 994         struct hfi1_qp_priv *priv = qp->priv;
 995         u32 hdrwords = qp->s_hdrwords;
 996         struct rvt_sge_state *ss = ps->s_txreq->ss;
 997         u32 len = ps->s_txreq->s_cur_size;
 998         u32 dwords = (len + 3) >> 2;
 999         u32 plen = hdrwords + dwords + 2; /* includes pbc */
1000         struct hfi1_pportdata *ppd = ps->ppd;
1001         u32 *hdr = (u32 *)&ps->s_txreq->phdr.hdr;
1002         u64 pbc_flags = 0;
1003         u8 sc5;
1004         unsigned long flags = 0;
1005         struct send_context *sc;
1006         struct pio_buf *pbuf;
1007         int wc_status = IB_WC_SUCCESS;
1008         int ret = 0;
1009         pio_release_cb cb = NULL;
1010
1011         /* only RC/UC use complete */
1012         switch (qp->ibqp.qp_type) {
1013         case IB_QPT_RC:
1014         case IB_QPT_UC:
1015                 cb = verbs_pio_complete;
1016                 break;
1017         default:
1018                 break;
1019         }
1020
1021         /* vl15 special case taken care of in ud.c */
1022         sc5 = priv->s_sc;
1023         sc = ps->s_txreq->psc;
1024
1025         if (likely(pbc == 0)) {
1026                 u8 vl = sc_to_vlt(dd_from_ibdev(qp->ibqp.device), sc5);
1027                 /* set PBC_DC_INFO bit (aka SC[4]) in pbc_flags */
1028                 pbc_flags |= (!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT;
1029                 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps, vl, plen);
1030         }
1031         if (cb)
1032                 iowait_pio_inc(&priv->s_iowait);
1033         pbuf = sc_buffer_alloc(sc, plen, cb, qp);
1034         if (unlikely(!pbuf)) {
1035                 if (cb)
1036                         verbs_pio_complete(qp, 0);
1037                 if (ppd->host_link_state != HLS_UP_ACTIVE) {
1038                         /*
1039                          * If we have filled the PIO buffers to capacity and are
1040                          * not in an active state this request is not going to
1041                          * go out to so just complete it with an error or else a
1042                          * ULP or the core may be stuck waiting.
1043                          */
1044                         hfi1_cdbg(
1045                                 PIO,
1046                                 "alloc failed. state not active, completing");
1047                         wc_status = IB_WC_GENERAL_ERR;
1048                         goto pio_bail;
1049                 } else {
1050                         /*
1051                          * This is a normal occurrence. The PIO buffs are full
1052                          * up but we are still happily sending, well we could be
1053                          * so lets continue to queue the request.
1054                          */
1055                         hfi1_cdbg(PIO, "alloc failed. state active, queuing");
1056                         ret = pio_wait(qp, sc, ps, RVT_S_WAIT_PIO);
1057                         if (!ret)
1058                                 /* txreq not queued - free */
1059                                 goto bail;
1060                         /* tx consumed in wait */
1061                         return ret;
1062                 }
1063         }
1064
1065         if (len == 0) {
1066                 pio_copy(ppd->dd, pbuf, pbc, hdr, hdrwords);
1067         } else {
1068                 if (ss) {
1069                         seg_pio_copy_start(pbuf, pbc, hdr, hdrwords * 4);
1070                         while (len) {
1071                                 void *addr = ss->sge.vaddr;
1072                                 u32 slen = ss->sge.length;
1073
1074                                 if (slen > len)
1075                                         slen = len;
1076                                 update_sge(ss, slen);
1077                                 seg_pio_copy_mid(pbuf, addr, slen);
1078                                 len -= slen;
1079                         }
1080                         seg_pio_copy_end(pbuf);
1081                 }
1082         }
1083
1084         trace_pio_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1085                                &ps->s_txreq->phdr.hdr);
1086
1087 pio_bail:
1088         if (qp->s_wqe) {
1089                 spin_lock_irqsave(&qp->s_lock, flags);
1090                 hfi1_send_complete(qp, qp->s_wqe, wc_status);
1091                 spin_unlock_irqrestore(&qp->s_lock, flags);
1092         } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1093                 spin_lock_irqsave(&qp->s_lock, flags);
1094                 hfi1_rc_send_complete(qp, &ps->s_txreq->phdr.hdr);
1095                 spin_unlock_irqrestore(&qp->s_lock, flags);
1096         }
1097
1098         ret = 0;
1099
1100 bail:
1101         hfi1_put_txreq(ps->s_txreq);
1102         return ret;
1103 }
1104
1105 /*
1106  * egress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1107  * being an entry from the partition key table), return 0
1108  * otherwise. Use the matching criteria for egress partition keys
1109  * specified in the OPAv1 spec., section 9.1l.7.
1110  */
1111 static inline int egress_pkey_matches_entry(u16 pkey, u16 ent)
1112 {
1113         u16 mkey = pkey & PKEY_LOW_15_MASK;
1114         u16 mentry = ent & PKEY_LOW_15_MASK;
1115
1116         if (mkey == mentry) {
1117                 /*
1118                  * If pkey[15] is set (full partition member),
1119                  * is bit 15 in the corresponding table element
1120                  * clear (limited member)?
1121                  */
1122                 if (pkey & PKEY_MEMBER_MASK)
1123                         return !!(ent & PKEY_MEMBER_MASK);
1124                 return 1;
1125         }
1126         return 0;
1127 }
1128
1129 /**
1130  * egress_pkey_check - check P_KEY of a packet
1131  * @ppd:    Physical IB port data
1132  * @lrh: Local route header
1133  * @bth: Base transport header
1134  * @sc5:    SC for packet
1135  * @s_pkey_index: It will be used for look up optimization for kernel contexts
1136  * only. If it is negative value, then it means user contexts is calling this
1137  * function.
1138  *
1139  * It checks if hdr's pkey is valid.
1140  *
1141  * Return: 0 on success, otherwise, 1
1142  */
1143 int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth,
1144                       u8 sc5, int8_t s_pkey_index)
1145 {
1146         struct hfi1_devdata *dd;
1147         int i;
1148         u16 pkey;
1149         int is_user_ctxt_mechanism = (s_pkey_index < 0);
1150
1151         if (!(ppd->part_enforce & HFI1_PART_ENFORCE_OUT))
1152                 return 0;
1153
1154         pkey = (u16)be32_to_cpu(bth[0]);
1155
1156         /* If SC15, pkey[0:14] must be 0x7fff */
1157         if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1158                 goto bad;
1159
1160         /* Is the pkey = 0x0, or 0x8000? */
1161         if ((pkey & PKEY_LOW_15_MASK) == 0)
1162                 goto bad;
1163
1164         /*
1165          * For the kernel contexts only, if a qp is passed into the function,
1166          * the most likely matching pkey has index qp->s_pkey_index
1167          */
1168         if (!is_user_ctxt_mechanism &&
1169             egress_pkey_matches_entry(pkey, ppd->pkeys[s_pkey_index])) {
1170                 return 0;
1171         }
1172
1173         for (i = 0; i < MAX_PKEY_VALUES; i++) {
1174                 if (egress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1175                         return 0;
1176         }
1177 bad:
1178         /*
1179          * For the user-context mechanism, the P_KEY check would only happen
1180          * once per SDMA request, not once per packet.  Therefore, there's no
1181          * need to increment the counter for the user-context mechanism.
1182          */
1183         if (!is_user_ctxt_mechanism) {
1184                 incr_cntr64(&ppd->port_xmit_constraint_errors);
1185                 dd = ppd->dd;
1186                 if (!(dd->err_info_xmit_constraint.status &
1187                       OPA_EI_STATUS_SMASK)) {
1188                         u16 slid = be16_to_cpu(lrh[3]);
1189
1190                         dd->err_info_xmit_constraint.status |=
1191                                 OPA_EI_STATUS_SMASK;
1192                         dd->err_info_xmit_constraint.slid = slid;
1193                         dd->err_info_xmit_constraint.pkey = pkey;
1194                 }
1195         }
1196         return 1;
1197 }
1198
1199 /**
1200  * get_send_routine - choose an egress routine
1201  *
1202  * Choose an egress routine based on QP type
1203  * and size
1204  */
1205 static inline send_routine get_send_routine(struct rvt_qp *qp,
1206                                             struct verbs_txreq *tx)
1207 {
1208         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1209         struct hfi1_qp_priv *priv = qp->priv;
1210         struct ib_header *h = &tx->phdr.hdr;
1211
1212         if (unlikely(!(dd->flags & HFI1_HAS_SEND_DMA)))
1213                 return dd->process_pio_send;
1214         switch (qp->ibqp.qp_type) {
1215         case IB_QPT_SMI:
1216                 return dd->process_pio_send;
1217         case IB_QPT_GSI:
1218         case IB_QPT_UD:
1219                 break;
1220         case IB_QPT_UC:
1221         case IB_QPT_RC: {
1222                 u8 op = get_opcode(h);
1223
1224                 if (piothreshold &&
1225                     tx->s_cur_size <= min(piothreshold, qp->pmtu) &&
1226                     (BIT(op & OPMASK) & pio_opmask[op >> 5]) &&
1227                     iowait_sdma_pending(&priv->s_iowait) == 0 &&
1228                     !sdma_txreq_built(&tx->txreq))
1229                         return dd->process_pio_send;
1230                 break;
1231         }
1232         default:
1233                 break;
1234         }
1235         return dd->process_dma_send;
1236 }
1237
1238 /**
1239  * hfi1_verbs_send - send a packet
1240  * @qp: the QP to send on
1241  * @ps: the state of the packet to send
1242  *
1243  * Return zero if packet is sent or queued OK.
1244  * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1245  */
1246 int hfi1_verbs_send(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
1247 {
1248         struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1249         struct hfi1_qp_priv *priv = qp->priv;
1250         struct ib_other_headers *ohdr;
1251         struct ib_header *hdr;
1252         send_routine sr;
1253         int ret;
1254         u8 lnh;
1255
1256         hdr = &ps->s_txreq->phdr.hdr;
1257         /* locate the pkey within the headers */
1258         lnh = be16_to_cpu(hdr->lrh[0]) & 3;
1259         if (lnh == HFI1_LRH_GRH)
1260                 ohdr = &hdr->u.l.oth;
1261         else
1262                 ohdr = &hdr->u.oth;
1263
1264         sr = get_send_routine(qp, ps->s_txreq);
1265         ret = egress_pkey_check(dd->pport,
1266                                 hdr->lrh,
1267                                 ohdr->bth,
1268                                 priv->s_sc,
1269                                 qp->s_pkey_index);
1270         if (unlikely(ret)) {
1271                 /*
1272                  * The value we are returning here does not get propagated to
1273                  * the verbs caller. Thus we need to complete the request with
1274                  * error otherwise the caller could be sitting waiting on the
1275                  * completion event. Only do this for PIO. SDMA has its own
1276                  * mechanism for handling the errors. So for SDMA we can just
1277                  * return.
1278                  */
1279                 if (sr == dd->process_pio_send) {
1280                         unsigned long flags;
1281
1282                         hfi1_cdbg(PIO, "%s() Failed. Completing with err",
1283                                   __func__);
1284                         spin_lock_irqsave(&qp->s_lock, flags);
1285                         hfi1_send_complete(qp, qp->s_wqe, IB_WC_GENERAL_ERR);
1286                         spin_unlock_irqrestore(&qp->s_lock, flags);
1287                 }
1288                 return -EINVAL;
1289         }
1290         if (sr == dd->process_dma_send && iowait_pio_pending(&priv->s_iowait))
1291                 return pio_wait(qp,
1292                                 ps->s_txreq->psc,
1293                                 ps,
1294                                 RVT_S_WAIT_PIO_DRAIN);
1295         return sr(qp, ps, 0);
1296 }
1297
1298 /**
1299  * hfi1_fill_device_attr - Fill in rvt dev info device attributes.
1300  * @dd: the device data structure
1301  */
1302 static void hfi1_fill_device_attr(struct hfi1_devdata *dd)
1303 {
1304         struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1305         u16 ver = dd->dc8051_ver;
1306
1307         memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1308
1309         rdi->dparms.props.fw_ver = ((u64)(dc8051_ver_maj(ver)) << 16) |
1310                                     (u64)dc8051_ver_min(ver);
1311         rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1312                         IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1313                         IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1314                         IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE |
1315                         IB_DEVICE_MEM_MGT_EXTENSIONS;
1316         rdi->dparms.props.page_size_cap = PAGE_SIZE;
1317         rdi->dparms.props.vendor_id = dd->oui1 << 16 | dd->oui2 << 8 | dd->oui3;
1318         rdi->dparms.props.vendor_part_id = dd->pcidev->device;
1319         rdi->dparms.props.hw_ver = dd->minrev;
1320         rdi->dparms.props.sys_image_guid = ib_hfi1_sys_image_guid;
1321         rdi->dparms.props.max_mr_size = U64_MAX;
1322         rdi->dparms.props.max_fast_reg_page_list_len = UINT_MAX;
1323         rdi->dparms.props.max_qp = hfi1_max_qps;
1324         rdi->dparms.props.max_qp_wr = hfi1_max_qp_wrs;
1325         rdi->dparms.props.max_sge = hfi1_max_sges;
1326         rdi->dparms.props.max_sge_rd = hfi1_max_sges;
1327         rdi->dparms.props.max_cq = hfi1_max_cqs;
1328         rdi->dparms.props.max_ah = hfi1_max_ahs;
1329         rdi->dparms.props.max_cqe = hfi1_max_cqes;
1330         rdi->dparms.props.max_mr = rdi->lkey_table.max;
1331         rdi->dparms.props.max_fmr = rdi->lkey_table.max;
1332         rdi->dparms.props.max_map_per_fmr = 32767;
1333         rdi->dparms.props.max_pd = hfi1_max_pds;
1334         rdi->dparms.props.max_qp_rd_atom = HFI1_MAX_RDMA_ATOMIC;
1335         rdi->dparms.props.max_qp_init_rd_atom = 255;
1336         rdi->dparms.props.max_srq = hfi1_max_srqs;
1337         rdi->dparms.props.max_srq_wr = hfi1_max_srq_wrs;
1338         rdi->dparms.props.max_srq_sge = hfi1_max_srq_sges;
1339         rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1340         rdi->dparms.props.max_pkeys = hfi1_get_npkeys(dd);
1341         rdi->dparms.props.max_mcast_grp = hfi1_max_mcast_grps;
1342         rdi->dparms.props.max_mcast_qp_attach = hfi1_max_mcast_qp_attached;
1343         rdi->dparms.props.max_total_mcast_qp_attach =
1344                                         rdi->dparms.props.max_mcast_qp_attach *
1345                                         rdi->dparms.props.max_mcast_grp;
1346 }
1347
1348 static inline u16 opa_speed_to_ib(u16 in)
1349 {
1350         u16 out = 0;
1351
1352         if (in & OPA_LINK_SPEED_25G)
1353                 out |= IB_SPEED_EDR;
1354         if (in & OPA_LINK_SPEED_12_5G)
1355                 out |= IB_SPEED_FDR;
1356
1357         return out;
1358 }
1359
1360 /*
1361  * Convert a single OPA link width (no multiple flags) to an IB value.
1362  * A zero OPA link width means link down, which means the IB width value
1363  * is a don't care.
1364  */
1365 static inline u16 opa_width_to_ib(u16 in)
1366 {
1367         switch (in) {
1368         case OPA_LINK_WIDTH_1X:
1369         /* map 2x and 3x to 1x as they don't exist in IB */
1370         case OPA_LINK_WIDTH_2X:
1371         case OPA_LINK_WIDTH_3X:
1372                 return IB_WIDTH_1X;
1373         default: /* link down or unknown, return our largest width */
1374         case OPA_LINK_WIDTH_4X:
1375                 return IB_WIDTH_4X;
1376         }
1377 }
1378
1379 static int query_port(struct rvt_dev_info *rdi, u8 port_num,
1380                       struct ib_port_attr *props)
1381 {
1382         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1383         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1384         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1385         u16 lid = ppd->lid;
1386
1387         props->lid = lid ? lid : 0;
1388         props->lmc = ppd->lmc;
1389         /* OPA logical states match IB logical states */
1390         props->state = driver_lstate(ppd);
1391         props->phys_state = hfi1_ibphys_portstate(ppd);
1392         props->gid_tbl_len = HFI1_GUIDS_PER_PORT;
1393         props->active_width = (u8)opa_width_to_ib(ppd->link_width_active);
1394         /* see rate_show() in ib core/sysfs.c */
1395         props->active_speed = (u8)opa_speed_to_ib(ppd->link_speed_active);
1396         props->max_vl_num = ppd->vls_supported;
1397
1398         /* Once we are a "first class" citizen and have added the OPA MTUs to
1399          * the core we can advertise the larger MTU enum to the ULPs, for now
1400          * advertise only 4K.
1401          *
1402          * Those applications which are either OPA aware or pass the MTU enum
1403          * from the Path Records to us will get the new 8k MTU.  Those that
1404          * attempt to process the MTU enum may fail in various ways.
1405          */
1406         props->max_mtu = mtu_to_enum((!valid_ib_mtu(hfi1_max_mtu) ?
1407                                       4096 : hfi1_max_mtu), IB_MTU_4096);
1408         props->active_mtu = !valid_ib_mtu(ppd->ibmtu) ? props->max_mtu :
1409                 mtu_to_enum(ppd->ibmtu, IB_MTU_2048);
1410
1411         return 0;
1412 }
1413
1414 static int modify_device(struct ib_device *device,
1415                          int device_modify_mask,
1416                          struct ib_device_modify *device_modify)
1417 {
1418         struct hfi1_devdata *dd = dd_from_ibdev(device);
1419         unsigned i;
1420         int ret;
1421
1422         if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1423                                    IB_DEVICE_MODIFY_NODE_DESC)) {
1424                 ret = -EOPNOTSUPP;
1425                 goto bail;
1426         }
1427
1428         if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1429                 memcpy(device->node_desc, device_modify->node_desc,
1430                        IB_DEVICE_NODE_DESC_MAX);
1431                 for (i = 0; i < dd->num_pports; i++) {
1432                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1433
1434                         hfi1_node_desc_chg(ibp);
1435                 }
1436         }
1437
1438         if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1439                 ib_hfi1_sys_image_guid =
1440                         cpu_to_be64(device_modify->sys_image_guid);
1441                 for (i = 0; i < dd->num_pports; i++) {
1442                         struct hfi1_ibport *ibp = &dd->pport[i].ibport_data;
1443
1444                         hfi1_sys_guid_chg(ibp);
1445                 }
1446         }
1447
1448         ret = 0;
1449
1450 bail:
1451         return ret;
1452 }
1453
1454 static int shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1455 {
1456         struct hfi1_ibdev *verbs_dev = dev_from_rdi(rdi);
1457         struct hfi1_devdata *dd = dd_from_dev(verbs_dev);
1458         struct hfi1_pportdata *ppd = &dd->pport[port_num - 1];
1459         int ret;
1460
1461         set_link_down_reason(ppd, OPA_LINKDOWN_REASON_UNKNOWN, 0,
1462                              OPA_LINKDOWN_REASON_UNKNOWN);
1463         ret = set_link_state(ppd, HLS_DN_DOWNDEF);
1464         return ret;
1465 }
1466
1467 static int hfi1_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1468                             int guid_index, __be64 *guid)
1469 {
1470         struct hfi1_ibport *ibp = container_of(rvp, struct hfi1_ibport, rvp);
1471
1472         if (guid_index >= HFI1_GUIDS_PER_PORT)
1473                 return -EINVAL;
1474
1475         *guid = get_sguid(ibp, guid_index);
1476         return 0;
1477 }
1478
1479 /*
1480  * convert ah port,sl to sc
1481  */
1482 u8 ah_to_sc(struct ib_device *ibdev, struct ib_ah_attr *ah)
1483 {
1484         struct hfi1_ibport *ibp = to_iport(ibdev, ah->port_num);
1485
1486         return ibp->sl_to_sc[ah->sl];
1487 }
1488
1489 static int hfi1_check_ah(struct ib_device *ibdev, struct ib_ah_attr *ah_attr)
1490 {
1491         struct hfi1_ibport *ibp;
1492         struct hfi1_pportdata *ppd;
1493         struct hfi1_devdata *dd;
1494         u8 sc5;
1495
1496         /* test the mapping for validity */
1497         ibp = to_iport(ibdev, ah_attr->port_num);
1498         ppd = ppd_from_ibp(ibp);
1499         sc5 = ibp->sl_to_sc[ah_attr->sl];
1500         dd = dd_from_ppd(ppd);
1501         if (sc_to_vlt(dd, sc5) > num_vls && sc_to_vlt(dd, sc5) != 0xf)
1502                 return -EINVAL;
1503         return 0;
1504 }
1505
1506 static void hfi1_notify_new_ah(struct ib_device *ibdev,
1507                                struct ib_ah_attr *ah_attr,
1508                                struct rvt_ah *ah)
1509 {
1510         struct hfi1_ibport *ibp;
1511         struct hfi1_pportdata *ppd;
1512         struct hfi1_devdata *dd;
1513         u8 sc5;
1514
1515         /*
1516          * Do not trust reading anything from rvt_ah at this point as it is not
1517          * done being setup. We can however modify things which we need to set.
1518          */
1519
1520         ibp = to_iport(ibdev, ah_attr->port_num);
1521         ppd = ppd_from_ibp(ibp);
1522         sc5 = ibp->sl_to_sc[ah->attr.sl];
1523         dd = dd_from_ppd(ppd);
1524         ah->vl = sc_to_vlt(dd, sc5);
1525         if (ah->vl < num_vls || ah->vl == 15)
1526                 ah->log_pmtu = ilog2(dd->vld[ah->vl].mtu);
1527 }
1528
1529 struct ib_ah *hfi1_create_qp0_ah(struct hfi1_ibport *ibp, u16 dlid)
1530 {
1531         struct ib_ah_attr attr;
1532         struct ib_ah *ah = ERR_PTR(-EINVAL);
1533         struct rvt_qp *qp0;
1534
1535         memset(&attr, 0, sizeof(attr));
1536         attr.dlid = dlid;
1537         attr.port_num = ppd_from_ibp(ibp)->port;
1538         rcu_read_lock();
1539         qp0 = rcu_dereference(ibp->rvp.qp[0]);
1540         if (qp0)
1541                 ah = ib_create_ah(qp0->ibqp.pd, &attr);
1542         rcu_read_unlock();
1543         return ah;
1544 }
1545
1546 /**
1547  * hfi1_get_npkeys - return the size of the PKEY table for context 0
1548  * @dd: the hfi1_ib device
1549  */
1550 unsigned hfi1_get_npkeys(struct hfi1_devdata *dd)
1551 {
1552         return ARRAY_SIZE(dd->pport[0].pkeys);
1553 }
1554
1555 static void init_ibport(struct hfi1_pportdata *ppd)
1556 {
1557         struct hfi1_ibport *ibp = &ppd->ibport_data;
1558         size_t sz = ARRAY_SIZE(ibp->sl_to_sc);
1559         int i;
1560
1561         for (i = 0; i < sz; i++) {
1562                 ibp->sl_to_sc[i] = i;
1563                 ibp->sc_to_sl[i] = i;
1564         }
1565
1566         spin_lock_init(&ibp->rvp.lock);
1567         /* Set the prefix to the default value (see ch. 4.1.1) */
1568         ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1569         ibp->rvp.sm_lid = 0;
1570         /* Below should only set bits defined in OPA PortInfo.CapabilityMask */
1571         ibp->rvp.port_cap_flags = IB_PORT_AUTO_MIGR_SUP |
1572                 IB_PORT_CAP_MASK_NOTICE_SUP;
1573         ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1574         ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1575         ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1576         ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1577         ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1578
1579         RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1580         RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1581 }
1582
1583 static void hfi1_get_dev_fw_str(struct ib_device *ibdev, char *str,
1584                                 size_t str_len)
1585 {
1586         struct rvt_dev_info *rdi = ib_to_rvt(ibdev);
1587         struct hfi1_ibdev *dev = dev_from_rdi(rdi);
1588         u16 ver = dd_from_dev(dev)->dc8051_ver;
1589
1590         snprintf(str, str_len, "%u.%u", dc8051_ver_maj(ver),
1591                  dc8051_ver_min(ver));
1592 }
1593
1594 static const char * const driver_cntr_names[] = {
1595         /* must be element 0*/
1596         "DRIVER_KernIntr",
1597         "DRIVER_ErrorIntr",
1598         "DRIVER_Tx_Errs",
1599         "DRIVER_Rcv_Errs",
1600         "DRIVER_HW_Errs",
1601         "DRIVER_NoPIOBufs",
1602         "DRIVER_CtxtsOpen",
1603         "DRIVER_RcvLen_Errs",
1604         "DRIVER_EgrBufFull",
1605         "DRIVER_EgrHdrFull"
1606 };
1607
1608 static const char **dev_cntr_names;
1609 static const char **port_cntr_names;
1610 static int num_driver_cntrs = ARRAY_SIZE(driver_cntr_names);
1611 static int num_dev_cntrs;
1612 static int num_port_cntrs;
1613 static int cntr_names_initialized;
1614
1615 /*
1616  * Convert a list of names separated by '\n' into an array of NULL terminated
1617  * strings. Optionally some entries can be reserved in the array to hold extra
1618  * external strings.
1619  */
1620 static int init_cntr_names(const char *names_in,
1621                            const int names_len,
1622                            int num_extra_names,
1623                            int *num_cntrs,
1624                            const char ***cntr_names)
1625 {
1626         char *names_out, *p, **q;
1627         int i, n;
1628
1629         n = 0;
1630         for (i = 0; i < names_len; i++)
1631                 if (names_in[i] == '\n')
1632                         n++;
1633
1634         names_out = kmalloc((n + num_extra_names) * sizeof(char *) + names_len,
1635                             GFP_KERNEL);
1636         if (!names_out) {
1637                 *num_cntrs = 0;
1638                 *cntr_names = NULL;
1639                 return -ENOMEM;
1640         }
1641
1642         p = names_out + (n + num_extra_names) * sizeof(char *);
1643         memcpy(p, names_in, names_len);
1644
1645         q = (char **)names_out;
1646         for (i = 0; i < n; i++) {
1647                 q[i] = p;
1648                 p = strchr(p, '\n');
1649                 *p++ = '\0';
1650         }
1651
1652         *num_cntrs = n;
1653         *cntr_names = (const char **)names_out;
1654         return 0;
1655 }
1656
1657 static struct rdma_hw_stats *alloc_hw_stats(struct ib_device *ibdev,
1658                                             u8 port_num)
1659 {
1660         int i, err;
1661
1662         if (!cntr_names_initialized) {
1663                 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1664
1665                 err = init_cntr_names(dd->cntrnames,
1666                                       dd->cntrnameslen,
1667                                       num_driver_cntrs,
1668                                       &num_dev_cntrs,
1669                                       &dev_cntr_names);
1670                 if (err)
1671                         return NULL;
1672
1673                 for (i = 0; i < num_driver_cntrs; i++)
1674                         dev_cntr_names[num_dev_cntrs + i] =
1675                                 driver_cntr_names[i];
1676
1677                 err = init_cntr_names(dd->portcntrnames,
1678                                       dd->portcntrnameslen,
1679                                       0,
1680                                       &num_port_cntrs,
1681                                       &port_cntr_names);
1682                 if (err) {
1683                         kfree(dev_cntr_names);
1684                         dev_cntr_names = NULL;
1685                         return NULL;
1686                 }
1687                 cntr_names_initialized = 1;
1688         }
1689
1690         if (!port_num)
1691                 return rdma_alloc_hw_stats_struct(
1692                                 dev_cntr_names,
1693                                 num_dev_cntrs + num_driver_cntrs,
1694                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1695         else
1696                 return rdma_alloc_hw_stats_struct(
1697                                 port_cntr_names,
1698                                 num_port_cntrs,
1699                                 RDMA_HW_STATS_DEFAULT_LIFESPAN);
1700 }
1701
1702 static u64 hfi1_sps_ints(void)
1703 {
1704         unsigned long flags;
1705         struct hfi1_devdata *dd;
1706         u64 sps_ints = 0;
1707
1708         spin_lock_irqsave(&hfi1_devs_lock, flags);
1709         list_for_each_entry(dd, &hfi1_dev_list, list) {
1710                 sps_ints += get_all_cpu_total(dd->int_counter);
1711         }
1712         spin_unlock_irqrestore(&hfi1_devs_lock, flags);
1713         return sps_ints;
1714 }
1715
1716 static int get_hw_stats(struct ib_device *ibdev, struct rdma_hw_stats *stats,
1717                         u8 port, int index)
1718 {
1719         u64 *values;
1720         int count;
1721
1722         if (!port) {
1723                 u64 *stats = (u64 *)&hfi1_stats;
1724                 int i;
1725
1726                 hfi1_read_cntrs(dd_from_ibdev(ibdev), NULL, &values);
1727                 values[num_dev_cntrs] = hfi1_sps_ints();
1728                 for (i = 1; i < num_driver_cntrs; i++)
1729                         values[num_dev_cntrs + i] = stats[i];
1730                 count = num_dev_cntrs + num_driver_cntrs;
1731         } else {
1732                 struct hfi1_ibport *ibp = to_iport(ibdev, port);
1733
1734                 hfi1_read_portcntrs(ppd_from_ibp(ibp), NULL, &values);
1735                 count = num_port_cntrs;
1736         }
1737
1738         memcpy(stats->value, values, count * sizeof(u64));
1739         return count;
1740 }
1741
1742 /**
1743  * hfi1_register_ib_device - register our device with the infiniband core
1744  * @dd: the device data structure
1745  * Return 0 if successful, errno if unsuccessful.
1746  */
1747 int hfi1_register_ib_device(struct hfi1_devdata *dd)
1748 {
1749         struct hfi1_ibdev *dev = &dd->verbs_dev;
1750         struct ib_device *ibdev = &dev->rdi.ibdev;
1751         struct hfi1_pportdata *ppd = dd->pport;
1752         struct hfi1_ibport *ibp = &ppd->ibport_data;
1753         unsigned i;
1754         int ret;
1755         size_t lcpysz = IB_DEVICE_NAME_MAX;
1756
1757         for (i = 0; i < dd->num_pports; i++)
1758                 init_ibport(ppd + i);
1759
1760         /* Only need to initialize non-zero fields. */
1761
1762         setup_timer(&dev->mem_timer, mem_timer, (unsigned long)dev);
1763
1764         seqlock_init(&dev->iowait_lock);
1765         seqlock_init(&dev->txwait_lock);
1766         INIT_LIST_HEAD(&dev->txwait);
1767         INIT_LIST_HEAD(&dev->memwait);
1768
1769         ret = verbs_txreq_init(dev);
1770         if (ret)
1771                 goto err_verbs_txreq;
1772
1773         /* Use first-port GUID as node guid */
1774         ibdev->node_guid = get_sguid(ibp, HFI1_PORT_GUID_INDEX);
1775
1776         /*
1777          * The system image GUID is supposed to be the same for all
1778          * HFIs in a single system but since there can be other
1779          * device types in the system, we can't be sure this is unique.
1780          */
1781         if (!ib_hfi1_sys_image_guid)
1782                 ib_hfi1_sys_image_guid = ibdev->node_guid;
1783         lcpysz = strlcpy(ibdev->name, class_name(), lcpysz);
1784         strlcpy(ibdev->name + lcpysz, "_%d", IB_DEVICE_NAME_MAX - lcpysz);
1785         ibdev->owner = THIS_MODULE;
1786         ibdev->phys_port_cnt = dd->num_pports;
1787         ibdev->dma_device = &dd->pcidev->dev;
1788         ibdev->modify_device = modify_device;
1789         ibdev->alloc_hw_stats = alloc_hw_stats;
1790         ibdev->get_hw_stats = get_hw_stats;
1791
1792         /* keep process mad in the driver */
1793         ibdev->process_mad = hfi1_process_mad;
1794         ibdev->get_dev_fw_str = hfi1_get_dev_fw_str;
1795
1796         strncpy(ibdev->node_desc, init_utsname()->nodename,
1797                 sizeof(ibdev->node_desc));
1798
1799         /*
1800          * Fill in rvt info object.
1801          */
1802         dd->verbs_dev.rdi.driver_f.port_callback = hfi1_create_port_files;
1803         dd->verbs_dev.rdi.driver_f.get_card_name = get_card_name;
1804         dd->verbs_dev.rdi.driver_f.get_pci_dev = get_pci_dev;
1805         dd->verbs_dev.rdi.driver_f.check_ah = hfi1_check_ah;
1806         dd->verbs_dev.rdi.driver_f.notify_new_ah = hfi1_notify_new_ah;
1807         dd->verbs_dev.rdi.driver_f.get_guid_be = hfi1_get_guid_be;
1808         dd->verbs_dev.rdi.driver_f.query_port_state = query_port;
1809         dd->verbs_dev.rdi.driver_f.shut_down_port = shut_down_port;
1810         dd->verbs_dev.rdi.driver_f.cap_mask_chg = hfi1_cap_mask_chg;
1811         /*
1812          * Fill in rvt info device attributes.
1813          */
1814         hfi1_fill_device_attr(dd);
1815
1816         /* queue pair */
1817         dd->verbs_dev.rdi.dparms.qp_table_size = hfi1_qp_table_size;
1818         dd->verbs_dev.rdi.dparms.qpn_start = 0;
1819         dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1820         dd->verbs_dev.rdi.dparms.qos_shift = dd->qos_shift;
1821         dd->verbs_dev.rdi.dparms.qpn_res_start = kdeth_qp << 16;
1822         dd->verbs_dev.rdi.dparms.qpn_res_end =
1823         dd->verbs_dev.rdi.dparms.qpn_res_start + 65535;
1824         dd->verbs_dev.rdi.dparms.max_rdma_atomic = HFI1_MAX_RDMA_ATOMIC;
1825         dd->verbs_dev.rdi.dparms.psn_mask = PSN_MASK;
1826         dd->verbs_dev.rdi.dparms.psn_shift = PSN_SHIFT;
1827         dd->verbs_dev.rdi.dparms.psn_modify_mask = PSN_MODIFY_MASK;
1828         dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_INTEL_OPA;
1829         dd->verbs_dev.rdi.dparms.max_mad_size = OPA_MGMT_MAD_SIZE;
1830
1831         dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qp_priv_alloc;
1832         dd->verbs_dev.rdi.driver_f.qp_priv_free = qp_priv_free;
1833         dd->verbs_dev.rdi.driver_f.free_all_qps = free_all_qps;
1834         dd->verbs_dev.rdi.driver_f.notify_qp_reset = notify_qp_reset;
1835         dd->verbs_dev.rdi.driver_f.do_send = hfi1_do_send;
1836         dd->verbs_dev.rdi.driver_f.schedule_send = hfi1_schedule_send;
1837         dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _hfi1_schedule_send;
1838         dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = get_pmtu_from_attr;
1839         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1840         dd->verbs_dev.rdi.driver_f.flush_qp_waiters = flush_qp_waiters;
1841         dd->verbs_dev.rdi.driver_f.stop_send_queue = stop_send_queue;
1842         dd->verbs_dev.rdi.driver_f.quiesce_qp = quiesce_qp;
1843         dd->verbs_dev.rdi.driver_f.notify_error_qp = notify_error_qp;
1844         dd->verbs_dev.rdi.driver_f.mtu_from_qp = mtu_from_qp;
1845         dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = mtu_to_path_mtu;
1846         dd->verbs_dev.rdi.driver_f.check_modify_qp = hfi1_check_modify_qp;
1847         dd->verbs_dev.rdi.driver_f.modify_qp = hfi1_modify_qp;
1848         dd->verbs_dev.rdi.driver_f.check_send_wqe = hfi1_check_send_wqe;
1849
1850         /* completeion queue */
1851         snprintf(dd->verbs_dev.rdi.dparms.cq_name,
1852                  sizeof(dd->verbs_dev.rdi.dparms.cq_name),
1853                  "hfi1_cq%d", dd->unit);
1854         dd->verbs_dev.rdi.dparms.node = dd->node;
1855
1856         /* misc settings */
1857         dd->verbs_dev.rdi.flags = 0; /* Let rdmavt handle it all */
1858         dd->verbs_dev.rdi.dparms.lkey_table_size = hfi1_lkey_table_size;
1859         dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1860         dd->verbs_dev.rdi.dparms.npkeys = hfi1_get_npkeys(dd);
1861
1862         /* post send table */
1863         dd->verbs_dev.rdi.post_parms = hfi1_post_parms;
1864
1865         ppd = dd->pport;
1866         for (i = 0; i < dd->num_pports; i++, ppd++)
1867                 rvt_init_port(&dd->verbs_dev.rdi,
1868                               &ppd->ibport_data.rvp,
1869                               i,
1870                               ppd->pkeys);
1871
1872         ret = rvt_register_device(&dd->verbs_dev.rdi);
1873         if (ret)
1874                 goto err_verbs_txreq;
1875
1876         ret = hfi1_verbs_register_sysfs(dd);
1877         if (ret)
1878                 goto err_class;
1879
1880         return ret;
1881
1882 err_class:
1883         rvt_unregister_device(&dd->verbs_dev.rdi);
1884 err_verbs_txreq:
1885         verbs_txreq_exit(dev);
1886         dd_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1887         return ret;
1888 }
1889
1890 void hfi1_unregister_ib_device(struct hfi1_devdata *dd)
1891 {
1892         struct hfi1_ibdev *dev = &dd->verbs_dev;
1893
1894         hfi1_verbs_unregister_sysfs(dd);
1895
1896         rvt_unregister_device(&dd->verbs_dev.rdi);
1897
1898         if (!list_empty(&dev->txwait))
1899                 dd_dev_err(dd, "txwait list not empty!\n");
1900         if (!list_empty(&dev->memwait))
1901                 dd_dev_err(dd, "memwait list not empty!\n");
1902
1903         del_timer_sync(&dev->mem_timer);
1904         verbs_txreq_exit(dev);
1905
1906         kfree(dev_cntr_names);
1907         kfree(port_cntr_names);
1908         cntr_names_initialized = 0;
1909 }
1910
1911 void hfi1_cnp_rcv(struct hfi1_packet *packet)
1912 {
1913         struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
1914         struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1915         struct ib_header *hdr = packet->hdr;
1916         struct rvt_qp *qp = packet->qp;
1917         u32 lqpn, rqpn = 0;
1918         u16 rlid = 0;
1919         u8 sl, sc5, svc_type;
1920
1921         switch (packet->qp->ibqp.qp_type) {
1922         case IB_QPT_UC:
1923                 rlid = qp->remote_ah_attr.dlid;
1924                 rqpn = qp->remote_qpn;
1925                 svc_type = IB_CC_SVCTYPE_UC;
1926                 break;
1927         case IB_QPT_RC:
1928                 rlid = qp->remote_ah_attr.dlid;
1929                 rqpn = qp->remote_qpn;
1930                 svc_type = IB_CC_SVCTYPE_RC;
1931                 break;
1932         case IB_QPT_SMI:
1933         case IB_QPT_GSI:
1934         case IB_QPT_UD:
1935                 svc_type = IB_CC_SVCTYPE_UD;
1936                 break;
1937         default:
1938                 ibp->rvp.n_pkt_drops++;
1939                 return;
1940         }
1941
1942         sc5 = hdr2sc(hdr, packet->rhf);
1943         sl = ibp->sc_to_sl[sc5];
1944         lqpn = qp->ibqp.qp_num;
1945
1946         process_becn(ppd, sl, rlid, lqpn, rqpn, svc_type);
1947 }