drivers/infiniband/hw/mlx5/main.c

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/init.h>
  36 #include <linux/errno.h>
  37 #include <linux/pci.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/slab.h>
  40 #if defined(CONFIG_X86)
  41 #include <asm/pat.h>
  42 #endif
  43 #include <linux/sched.h>
  44 #include <linux/delay.h>
  45 #include <rdma/ib_user_verbs.h>
  46 #include <rdma/ib_addr.h>
  47 #include <rdma/ib_cache.h>
  48 #include <linux/mlx5/port.h>
  49 #include <linux/mlx5/vport.h>
  50 #include <linux/list.h>
  51 #include <rdma/ib_smi.h>
  52 #include <rdma/ib_umem.h>
  53 #include <linux/in.h>
  54 #include <linux/etherdevice.h>
  55 #include <linux/mlx5/fs.h>
  56 #include <linux/mlx5/vport.h>
  57 #include "mlx5_ib.h"
  58
  59 #define DRIVER_NAME "mlx5_ib"
  60 #define DRIVER_VERSION "2.2-1"
  61 #define DRIVER_RELDATE  "Feb 2014"
  62
  63 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  64 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  65 MODULE_LICENSE("Dual BSD/GPL");
  66 MODULE_VERSION(DRIVER_VERSION);
  67
  68 static char mlx5_version[] =
  69         DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  70         DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  71
  72 enum {
  73         MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
  74 };
  75
  76 static enum rdma_link_layer
  77 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
  78 {
  79         switch (port_type_cap) {
  80         case MLX5_CAP_PORT_TYPE_IB:
  81                 return IB_LINK_LAYER_INFINIBAND;
  82         case MLX5_CAP_PORT_TYPE_ETH:
  83                 return IB_LINK_LAYER_ETHERNET;
  84         default:
  85                 return IB_LINK_LAYER_UNSPECIFIED;
  86         }
  87 }
  88
  89 static enum rdma_link_layer
  90 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
  91 {
  92         struct mlx5_ib_dev *dev = to_mdev(device);
  93         int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
  94
  95         return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
  96 }
  97
  98 static int mlx5_netdev_event(struct notifier_block *this,
  99                              unsigned long event, void *ptr)
 100 {
 101         struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
 102         struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
 103                                                  roce.nb);
 104
 105         switch (event) {
 106         case NETDEV_REGISTER:
 107         case NETDEV_UNREGISTER:
 108                 write_lock(&ibdev->roce.netdev_lock);
 109                 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
 110                         ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
 111                                              NULL : ndev;
 112                 write_unlock(&ibdev->roce.netdev_lock);
 113                 break;
 114
 115         case NETDEV_UP:
 116         case NETDEV_DOWN: {
 117                 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 118                 struct net_device *upper = NULL;
 119
 120                 if (lag_ndev) {
 121                         upper = netdev_master_upper_dev_get(lag_ndev);
 122                         dev_put(lag_ndev);
 123                 }
 124
 125                 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
 126                     && ibdev->ib_active) {
 127                         struct ib_event ibev = { };
 128
 129                         ibev.device = &ibdev->ib_dev;
 130                         ibev.event = (event == NETDEV_UP) ?
 131                                      IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
 132                         ibev.element.port_num = 1;
 133                         ib_dispatch_event(&ibev);
 134                 }
 135                 break;
 136         }
 137
 138         default:
 139                 break;
 140         }
 141
 142         return NOTIFY_DONE;
 143 }
 144
 145 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
 146                                              u8 port_num)
 147 {
 148         struct mlx5_ib_dev *ibdev = to_mdev(device);
 149         struct net_device *ndev;
 150
 151         ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
 152         if (ndev)
 153                 return ndev;
 154
 155         /* Ensure ndev does not disappear before we invoke dev_hold()
 156          */
 157         read_lock(&ibdev->roce.netdev_lock);
 158         ndev = ibdev->roce.netdev;
 159         if (ndev)
 160                 dev_hold(ndev);
 161         read_unlock(&ibdev->roce.netdev_lock);
 162
 163         return ndev;
 164 }
 165
 166 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
 167                                 struct ib_port_attr *props)
 168 {
 169         struct mlx5_ib_dev *dev = to_mdev(device);
 170         struct net_device *ndev, *upper;
 171         enum ib_mtu ndev_ib_mtu;
 172         u16 qkey_viol_cntr;
 173
 174         /* props being zeroed by the caller, avoid zeroing it here */
 175
 176         props->port_cap_flags  |= IB_PORT_CM_SUP;
 177         props->port_cap_flags  |= IB_PORT_IP_BASED_GIDS;
 178
 179         props->gid_tbl_len      = MLX5_CAP_ROCE(dev->mdev,
 180                                                 roce_address_table_size);
 181         props->max_mtu          = IB_MTU_4096;
 182         props->max_msg_sz       = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
 183         props->pkey_tbl_len     = 1;
 184         props->state            = IB_PORT_DOWN;
 185         props->phys_state       = 3;
 186
 187         mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
 188         props->qkey_viol_cntr = qkey_viol_cntr;
 189
 190         ndev = mlx5_ib_get_netdev(device, port_num);
 191         if (!ndev)
 192                 return 0;
 193
 194         if (mlx5_lag_is_active(dev->mdev)) {
 195                 rcu_read_lock();
 196                 upper = netdev_master_upper_dev_get_rcu(ndev);
 197                 if (upper) {
 198                         dev_put(ndev);
 199                         ndev = upper;
 200                         dev_hold(ndev);
 201                 }
 202                 rcu_read_unlock();
 203         }
 204
 205         if (netif_running(ndev) && netif_carrier_ok(ndev)) {
 206                 props->state      = IB_PORT_ACTIVE;
 207                 props->phys_state = 5;
 208         }
 209
 210         ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
 211
 212         dev_put(ndev);
 213
 214         props->active_mtu       = min(props->max_mtu, ndev_ib_mtu);
 215
 216         props->active_width     = IB_WIDTH_4X;  /* TODO */
 217         props->active_speed     = IB_SPEED_QDR; /* TODO */
 218
 219         return 0;
 220 }
 221
 222 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
 223                                      const struct ib_gid_attr *attr,
 224                                      void *mlx5_addr)
 225 {
 226 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
 227         char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 228                                                source_l3_address);
 229         void *mlx5_addr_mac     = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
 230                                                source_mac_47_32);
 231
 232         if (!gid)
 233                 return;
 234
 235         ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
 236
 237         if (is_vlan_dev(attr->ndev)) {
 238                 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
 239                 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
 240         }
 241
 242         switch (attr->gid_type) {
 243         case IB_GID_TYPE_IB:
 244                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
 245                 break;
 246         case IB_GID_TYPE_ROCE_UDP_ENCAP:
 247                 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
 248                 break;
 249
 250         default:
 251                 WARN_ON(true);
 252         }
 253
 254         if (attr->gid_type != IB_GID_TYPE_IB) {
 255                 if (ipv6_addr_v4mapped((void *)gid))
 256                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 257                                     MLX5_ROCE_L3_TYPE_IPV4);
 258                 else
 259                         MLX5_SET_RA(mlx5_addr, roce_l3_type,
 260                                     MLX5_ROCE_L3_TYPE_IPV6);
 261         }
 262
 263         if ((attr->gid_type == IB_GID_TYPE_IB) ||
 264             !ipv6_addr_v4mapped((void *)gid))
 265                 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
 266         else
 267                 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
 268 }
 269
 270 static int set_roce_addr(struct ib_device *device, u8 port_num,
 271                          unsigned int index,
 272                          const union ib_gid *gid,
 273                          const struct ib_gid_attr *attr)
 274 {
 275         struct mlx5_ib_dev *dev = to_mdev(device);
 276         u32  in[MLX5_ST_SZ_DW(set_roce_address_in)]  = {0};
 277         u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
 278         void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
 279         enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
 280
 281         if (ll != IB_LINK_LAYER_ETHERNET)
 282                 return -EINVAL;
 283
 284         ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
 285
 286         MLX5_SET(set_roce_address_in, in, roce_address_index, index);
 287         MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
 288         return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
 289 }
 290
 291 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
 292                            unsigned int index, const union ib_gid *gid,
 293                            const struct ib_gid_attr *attr,
 294                            __always_unused void **context)
 295 {
 296         return set_roce_addr(device, port_num, index, gid, attr);
 297 }
 298
 299 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
 300                            unsigned int index, __always_unused void **context)
 301 {
 302         return set_roce_addr(device, port_num, index, NULL, NULL);
 303 }
 304
 305 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
 306                                int index)
 307 {
 308         struct ib_gid_attr attr;
 309         union ib_gid gid;
 310
 311         if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
 312                 return 0;
 313
 314         if (!attr.ndev)
 315                 return 0;
 316
 317         dev_put(attr.ndev);
 318
 319         if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
 320                 return 0;
 321
 322         return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
 323 }
 324
 325 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
 326                            int index, enum ib_gid_type *gid_type)
 327 {
 328         struct ib_gid_attr attr;
 329         union ib_gid gid;
 330         int ret;
 331
 332         ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
 333         if (ret)
 334                 return ret;
 335
 336         if (!attr.ndev)
 337                 return -ENODEV;
 338
 339         dev_put(attr.ndev);
 340
 341         *gid_type = attr.gid_type;
 342
 343         return 0;
 344 }
 345
 346 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
 347 {
 348         if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
 349                 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
 350         return 0;
 351 }
 352
 353 enum {
 354         MLX5_VPORT_ACCESS_METHOD_MAD,
 355         MLX5_VPORT_ACCESS_METHOD_HCA,
 356         MLX5_VPORT_ACCESS_METHOD_NIC,
 357 };
 358
 359 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
 360 {
 361         if (mlx5_use_mad_ifc(to_mdev(ibdev)))
 362                 return MLX5_VPORT_ACCESS_METHOD_MAD;
 363
 364         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 365             IB_LINK_LAYER_ETHERNET)
 366                 return MLX5_VPORT_ACCESS_METHOD_NIC;
 367
 368         return MLX5_VPORT_ACCESS_METHOD_HCA;
 369 }
 370
 371 static void get_atomic_caps(struct mlx5_ib_dev *dev,
 372                             struct ib_device_attr *props)
 373 {
 374         u8 tmp;
 375         u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
 376         u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
 377         u8 atomic_req_8B_endianness_mode =
 378                 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
 379
 380         /* Check if HW supports 8 bytes standard atomic operations and capable
 381          * of host endianness respond
 382          */
 383         tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
 384         if (((atomic_operations & tmp) == tmp) &&
 385             (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
 386             (atomic_req_8B_endianness_mode)) {
 387                 props->atomic_cap = IB_ATOMIC_HCA;
 388         } else {
 389                 props->atomic_cap = IB_ATOMIC_NONE;
 390         }
 391 }
 392
 393 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
 394                                         __be64 *sys_image_guid)
 395 {
 396         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 397         struct mlx5_core_dev *mdev = dev->mdev;
 398         u64 tmp;
 399         int err;
 400
 401         switch (mlx5_get_vport_access_method(ibdev)) {
 402         case MLX5_VPORT_ACCESS_METHOD_MAD:
 403                 return mlx5_query_mad_ifc_system_image_guid(ibdev,
 404                                                             sys_image_guid);
 405
 406         case MLX5_VPORT_ACCESS_METHOD_HCA:
 407                 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
 408                 break;
 409
 410         case MLX5_VPORT_ACCESS_METHOD_NIC:
 411                 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
 412                 break;
 413
 414         default:
 415                 return -EINVAL;
 416         }
 417
 418         if (!err)
 419                 *sys_image_guid = cpu_to_be64(tmp);
 420
 421         return err;
 422
 423 }
 424
 425 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
 426                                 u16 *max_pkeys)
 427 {
 428         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 429         struct mlx5_core_dev *mdev = dev->mdev;
 430
 431         switch (mlx5_get_vport_access_method(ibdev)) {
 432         case MLX5_VPORT_ACCESS_METHOD_MAD:
 433                 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
 434
 435         case MLX5_VPORT_ACCESS_METHOD_HCA:
 436         case MLX5_VPORT_ACCESS_METHOD_NIC:
 437                 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
 438                                                 pkey_table_size));
 439                 return 0;
 440
 441         default:
 442                 return -EINVAL;
 443         }
 444 }
 445
 446 static int mlx5_query_vendor_id(struct ib_device *ibdev,
 447                                 u32 *vendor_id)
 448 {
 449         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 450
 451         switch (mlx5_get_vport_access_method(ibdev)) {
 452         case MLX5_VPORT_ACCESS_METHOD_MAD:
 453                 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
 454
 455         case MLX5_VPORT_ACCESS_METHOD_HCA:
 456         case MLX5_VPORT_ACCESS_METHOD_NIC:
 457                 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
 458
 459         default:
 460                 return -EINVAL;
 461         }
 462 }
 463
 464 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
 465                                 __be64 *node_guid)
 466 {
 467         u64 tmp;
 468         int err;
 469
 470         switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
 471         case MLX5_VPORT_ACCESS_METHOD_MAD:
 472                 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
 473
 474         case MLX5_VPORT_ACCESS_METHOD_HCA:
 475                 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
 476                 break;
 477
 478         case MLX5_VPORT_ACCESS_METHOD_NIC:
 479                 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
 480                 break;
 481
 482         default:
 483                 return -EINVAL;
 484         }
 485
 486         if (!err)
 487                 *node_guid = cpu_to_be64(tmp);
 488
 489         return err;
 490 }
 491
 492 struct mlx5_reg_node_desc {
 493         u8      desc[IB_DEVICE_NODE_DESC_MAX];
 494 };
 495
 496 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
 497 {
 498         struct mlx5_reg_node_desc in;
 499
 500         if (mlx5_use_mad_ifc(dev))
 501                 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
 502
 503         memset(&in, 0, sizeof(in));
 504
 505         return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
 506                                     sizeof(struct mlx5_reg_node_desc),
 507                                     MLX5_REG_NODE_DESC, 0, 0);
 508 }
 509
 510 static int mlx5_ib_query_device(struct ib_device *ibdev,
 511                                 struct ib_device_attr *props,
 512                                 struct ib_udata *uhw)
 513 {
 514         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 515         struct mlx5_core_dev *mdev = dev->mdev;
 516         int err = -ENOMEM;
 517         int max_sq_desc;
 518         int max_rq_sg;
 519         int max_sq_sg;
 520         u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
 521         struct mlx5_ib_query_device_resp resp = {};
 522         size_t resp_len;
 523         u64 max_tso;
 524
 525         resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
 526         if (uhw->outlen && uhw->outlen < resp_len)
 527                 return -EINVAL;
 528         else
 529                 resp.response_length = resp_len;
 530
 531         if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
 532                 return -EINVAL;
 533
 534         memset(props, 0, sizeof(*props));
 535         err = mlx5_query_system_image_guid(ibdev,
 536                                            &props->sys_image_guid);
 537         if (err)
 538                 return err;
 539
 540         err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
 541         if (err)
 542                 return err;
 543
 544         err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
 545         if (err)
 546                 return err;
 547
 548         props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
 549                 (fw_rev_min(dev->mdev) << 16) |
 550                 fw_rev_sub(dev->mdev);
 551         props->device_cap_flags    = IB_DEVICE_CHANGE_PHY_PORT |
 552                 IB_DEVICE_PORT_ACTIVE_EVENT             |
 553                 IB_DEVICE_SYS_IMAGE_GUID                |
 554                 IB_DEVICE_RC_RNR_NAK_GEN;
 555
 556         if (MLX5_CAP_GEN(mdev, pkv))
 557                 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
 558         if (MLX5_CAP_GEN(mdev, qkv))
 559                 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
 560         if (MLX5_CAP_GEN(mdev, apm))
 561                 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
 562         if (MLX5_CAP_GEN(mdev, xrc))
 563                 props->device_cap_flags |= IB_DEVICE_XRC;
 564         if (MLX5_CAP_GEN(mdev, imaicl)) {
 565                 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
 566                                            IB_DEVICE_MEM_WINDOW_TYPE_2B;
 567                 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 568                 /* We support 'Gappy' memory registration too */
 569                 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
 570         }
 571         props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 572         if (MLX5_CAP_GEN(mdev, sho)) {
 573                 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
 574                 /* At this stage no support for signature handover */
 575                 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
 576                                       IB_PROT_T10DIF_TYPE_2 |
 577                                       IB_PROT_T10DIF_TYPE_3;
 578                 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
 579                                        IB_GUARD_T10DIF_CSUM;
 580         }
 581         if (MLX5_CAP_GEN(mdev, block_lb_mc))
 582                 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
 583
 584         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
 585                 if (MLX5_CAP_ETH(mdev, csum_cap)) {
 586                         /* Legacy bit to support old userspace libraries */
 587                         props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
 588                         props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
 589                 }
 590
 591                 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
 592                         props->raw_packet_caps |=
 593                                 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
 594
 595                 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
 596                         max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
 597                         if (max_tso) {
 598                                 resp.tso_caps.max_tso = 1 << max_tso;
 599                                 resp.tso_caps.supported_qpts |=
 600                                         1 << IB_QPT_RAW_PACKET;
 601                                 resp.response_length += sizeof(resp.tso_caps);
 602                         }
 603                 }
 604
 605                 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
 606                         resp.rss_caps.rx_hash_function =
 607                                                 MLX5_RX_HASH_FUNC_TOEPLITZ;
 608                         resp.rss_caps.rx_hash_fields_mask =
 609                                                 MLX5_RX_HASH_SRC_IPV4 |
 610                                                 MLX5_RX_HASH_DST_IPV4 |
 611                                                 MLX5_RX_HASH_SRC_IPV6 |
 612                                                 MLX5_RX_HASH_DST_IPV6 |
 613                                                 MLX5_RX_HASH_SRC_PORT_TCP |
 614                                                 MLX5_RX_HASH_DST_PORT_TCP |
 615                                                 MLX5_RX_HASH_SRC_PORT_UDP |
 616                                                 MLX5_RX_HASH_DST_PORT_UDP;
 617                         resp.response_length += sizeof(resp.rss_caps);
 618                 }
 619         } else {
 620                 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
 621                         resp.response_length += sizeof(resp.tso_caps);
 622                 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
 623                         resp.response_length += sizeof(resp.rss_caps);
 624         }
 625
 626         if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
 627                 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
 628                 props->device_cap_flags |= IB_DEVICE_UD_TSO;
 629         }
 630
 631         if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
 632             MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
 633                 /* Legacy bit to support old userspace libraries */
 634                 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
 635                 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
 636         }
 637
 638         if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
 639                 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
 640
 641         props->vendor_part_id      = mdev->pdev->device;
 642         props->hw_ver              = mdev->pdev->revision;
 643
 644         props->max_mr_size         = ~0ull;
 645         props->page_size_cap       = ~(min_page_size - 1);
 646         props->max_qp              = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
 647         props->max_qp_wr           = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
 648         max_rq_sg =  MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
 649                      sizeof(struct mlx5_wqe_data_seg);
 650         max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
 651         max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
 652                      sizeof(struct mlx5_wqe_raddr_seg)) /
 653                 sizeof(struct mlx5_wqe_data_seg);
 654         props->max_sge = min(max_rq_sg, max_sq_sg);
 655         props->max_sge_rd          = MLX5_MAX_SGE_RD;
 656         props->max_cq              = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
 657         props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
 658         props->max_mr              = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
 659         props->max_pd              = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
 660         props->max_qp_rd_atom      = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
 661         props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
 662         props->max_srq             = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
 663         props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
 664         props->local_ca_ack_delay  = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
 665         props->max_res_rd_atom     = props->max_qp_rd_atom * props->max_qp;
 666         props->max_srq_sge         = max_rq_sg - 1;
 667         props->max_fast_reg_page_list_len =
 668                 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
 669         get_atomic_caps(dev, props);
 670         props->masked_atomic_cap   = IB_ATOMIC_NONE;
 671         props->max_mcast_grp       = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
 672         props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
 673         props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
 674                                            props->max_mcast_grp;
 675         props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
 676         props->max_ah = INT_MAX;
 677         props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
 678         props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
 679
 680 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
 681         if (MLX5_CAP_GEN(mdev, pg))
 682                 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
 683         props->odp_caps = dev->odp_caps;
 684 #endif
 685
 686         if (MLX5_CAP_GEN(mdev, cd))
 687                 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
 688
 689         if (!mlx5_core_is_pf(mdev))
 690                 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
 691
 692         if (mlx5_ib_port_link_layer(ibdev, 1) ==
 693             IB_LINK_LAYER_ETHERNET) {
 694                 props->rss_caps.max_rwq_indirection_tables =
 695                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
 696                 props->rss_caps.max_rwq_indirection_table_size =
 697                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
 698                 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
 699                 props->max_wq_type_rq =
 700                         1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
 701         }
 702
 703         if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
 704                 resp.cqe_comp_caps.max_num =
 705                         MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
 706                         MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
 707                 resp.cqe_comp_caps.supported_format =
 708                         MLX5_IB_CQE_RES_FORMAT_HASH |
 709                         MLX5_IB_CQE_RES_FORMAT_CSUM;
 710                 resp.response_length += sizeof(resp.cqe_comp_caps);
 711         }
 712
 713         if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
 714                 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
 715                     MLX5_CAP_GEN(mdev, qos)) {
 716                         resp.packet_pacing_caps.qp_rate_limit_max =
 717                                 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
 718                         resp.packet_pacing_caps.qp_rate_limit_min =
 719                                 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
 720                         resp.packet_pacing_caps.supported_qpts |=
 721                                 1 << IB_QPT_RAW_PACKET;
 722                 }
 723                 resp.response_length += sizeof(resp.packet_pacing_caps);
 724         }
 725
 726         if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
 727                         uhw->outlen)) {
 728                 resp.mlx5_ib_support_multi_pkt_send_wqes =
 729                         MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
 730                 resp.response_length +=
 731                         sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
 732         }
 733
 734         if (field_avail(typeof(resp), reserved, uhw->outlen))
 735                 resp.response_length += sizeof(resp.reserved);
 736
 737         if (uhw->outlen) {
 738                 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
 739
 740                 if (err)
 741                         return err;
 742         }
 743
 744         return 0;
 745 }
 746
 747 enum mlx5_ib_width {
 748         MLX5_IB_WIDTH_1X        = 1 << 0,
 749         MLX5_IB_WIDTH_2X        = 1 << 1,
 750         MLX5_IB_WIDTH_4X        = 1 << 2,
 751         MLX5_IB_WIDTH_8X        = 1 << 3,
 752         MLX5_IB_WIDTH_12X       = 1 << 4
 753 };
 754
 755 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
 756                                   u8 *ib_width)
 757 {
 758         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 759         int err = 0;
 760
 761         if (active_width & MLX5_IB_WIDTH_1X) {
 762                 *ib_width = IB_WIDTH_1X;
 763         } else if (active_width & MLX5_IB_WIDTH_2X) {
 764                 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
 765                             (int)active_width);
 766                 err = -EINVAL;
 767         } else if (active_width & MLX5_IB_WIDTH_4X) {
 768                 *ib_width = IB_WIDTH_4X;
 769         } else if (active_width & MLX5_IB_WIDTH_8X) {
 770                 *ib_width = IB_WIDTH_8X;
 771         } else if (active_width & MLX5_IB_WIDTH_12X) {
 772                 *ib_width = IB_WIDTH_12X;
 773         } else {
 774                 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
 775                             (int)active_width);
 776                 err = -EINVAL;
 777         }
 778
 779         return err;
 780 }
 781
 782 static int mlx5_mtu_to_ib_mtu(int mtu)
 783 {
 784         switch (mtu) {
 785         case 256: return 1;
 786         case 512: return 2;
 787         case 1024: return 3;
 788         case 2048: return 4;
 789         case 4096: return 5;
 790         default:
 791                 pr_warn("invalid mtu\n");
 792                 return -1;
 793         }
 794 }
 795
 796 enum ib_max_vl_num {
 797         __IB_MAX_VL_0           = 1,
 798         __IB_MAX_VL_0_1         = 2,
 799         __IB_MAX_VL_0_3         = 3,
 800         __IB_MAX_VL_0_7         = 4,
 801         __IB_MAX_VL_0_14        = 5,
 802 };
 803
 804 enum mlx5_vl_hw_cap {
 805         MLX5_VL_HW_0    = 1,
 806         MLX5_VL_HW_0_1  = 2,
 807         MLX5_VL_HW_0_2  = 3,
 808         MLX5_VL_HW_0_3  = 4,
 809         MLX5_VL_HW_0_4  = 5,
 810         MLX5_VL_HW_0_5  = 6,
 811         MLX5_VL_HW_0_6  = 7,
 812         MLX5_VL_HW_0_7  = 8,
 813         MLX5_VL_HW_0_14 = 15
 814 };
 815
 816 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
 817                                 u8 *max_vl_num)
 818 {
 819         switch (vl_hw_cap) {
 820         case MLX5_VL_HW_0:
 821                 *max_vl_num = __IB_MAX_VL_0;
 822                 break;
 823         case MLX5_VL_HW_0_1:
 824                 *max_vl_num = __IB_MAX_VL_0_1;
 825                 break;
 826         case MLX5_VL_HW_0_3:
 827                 *max_vl_num = __IB_MAX_VL_0_3;
 828                 break;
 829         case MLX5_VL_HW_0_7:
 830                 *max_vl_num = __IB_MAX_VL_0_7;
 831                 break;
 832         case MLX5_VL_HW_0_14:
 833                 *max_vl_num = __IB_MAX_VL_0_14;
 834                 break;
 835
 836         default:
 837                 return -EINVAL;
 838         }
 839
 840         return 0;
 841 }
 842
 843 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
 844                                struct ib_port_attr *props)
 845 {
 846         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 847         struct mlx5_core_dev *mdev = dev->mdev;
 848         struct mlx5_hca_vport_context *rep;
 849         u16 max_mtu;
 850         u16 oper_mtu;
 851         int err;
 852         u8 ib_link_width_oper;
 853         u8 vl_hw_cap;
 854
 855         rep = kzalloc(sizeof(*rep), GFP_KERNEL);
 856         if (!rep) {
 857                 err = -ENOMEM;
 858                 goto out;
 859         }
 860
 861         /* props being zeroed by the caller, avoid zeroing it here */
 862
 863         err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
 864         if (err)
 865                 goto out;
 866
 867         props->lid              = rep->lid;
 868         props->lmc              = rep->lmc;
 869         props->sm_lid           = rep->sm_lid;
 870         props->sm_sl            = rep->sm_sl;
 871         props->state            = rep->vport_state;
 872         props->phys_state       = rep->port_physical_state;
 873         props->port_cap_flags   = rep->cap_mask1;
 874         props->gid_tbl_len      = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
 875         props->max_msg_sz       = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
 876         props->pkey_tbl_len     = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
 877         props->bad_pkey_cntr    = rep->pkey_violation_counter;
 878         props->qkey_viol_cntr   = rep->qkey_violation_counter;
 879         props->subnet_timeout   = rep->subnet_timeout;
 880         props->init_type_reply  = rep->init_type_reply;
 881         props->grh_required     = rep->grh_required;
 882
 883         err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
 884         if (err)
 885                 goto out;
 886
 887         err = translate_active_width(ibdev, ib_link_width_oper,
 888                                      &props->active_width);
 889         if (err)
 890                 goto out;
 891         err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
 892         if (err)
 893                 goto out;
 894
 895         mlx5_query_port_max_mtu(mdev, &max_mtu, port);
 896
 897         props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
 898
 899         mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
 900
 901         props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
 902
 903         err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
 904         if (err)
 905                 goto out;
 906
 907         err = translate_max_vl_num(ibdev, vl_hw_cap,
 908                                    &props->max_vl_num);
 909 out:
 910         kfree(rep);
 911         return err;
 912 }
 913
 914 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
 915                        struct ib_port_attr *props)
 916 {
 917         switch (mlx5_get_vport_access_method(ibdev)) {
 918         case MLX5_VPORT_ACCESS_METHOD_MAD:
 919                 return mlx5_query_mad_ifc_port(ibdev, port, props);
 920
 921         case MLX5_VPORT_ACCESS_METHOD_HCA:
 922                 return mlx5_query_hca_port(ibdev, port, props);
 923
 924         case MLX5_VPORT_ACCESS_METHOD_NIC:
 925                 return mlx5_query_port_roce(ibdev, port, props);
 926
 927         default:
 928                 return -EINVAL;
 929         }
 930 }
 931
 932 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
 933                              union ib_gid *gid)
 934 {
 935         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 936         struct mlx5_core_dev *mdev = dev->mdev;
 937
 938         switch (mlx5_get_vport_access_method(ibdev)) {
 939         case MLX5_VPORT_ACCESS_METHOD_MAD:
 940                 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
 941
 942         case MLX5_VPORT_ACCESS_METHOD_HCA:
 943                 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
 944
 945         default:
 946                 return -EINVAL;
 947         }
 948
 949 }
 950
 951 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
 952                               u16 *pkey)
 953 {
 954         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 955         struct mlx5_core_dev *mdev = dev->mdev;
 956
 957         switch (mlx5_get_vport_access_method(ibdev)) {
 958         case MLX5_VPORT_ACCESS_METHOD_MAD:
 959                 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
 960
 961         case MLX5_VPORT_ACCESS_METHOD_HCA:
 962         case MLX5_VPORT_ACCESS_METHOD_NIC:
 963                 return mlx5_query_hca_vport_pkey(mdev, 0, port,  0, index,
 964                                                  pkey);
 965         default:
 966                 return -EINVAL;
 967         }
 968 }
 969
 970 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
 971                                  struct ib_device_modify *props)
 972 {
 973         struct mlx5_ib_dev *dev = to_mdev(ibdev);
 974         struct mlx5_reg_node_desc in;
 975         struct mlx5_reg_node_desc out;
 976         int err;
 977
 978         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 979                 return -EOPNOTSUPP;
 980
 981         if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
 982                 return 0;
 983
 984         /*
 985          * If possible, pass node desc to FW, so it can generate
 986          * a 144 trap.  If cmd fails, just ignore.
 987          */
 988         memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 989         err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
 990                                    sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
 991         if (err)
 992                 return err;
 993
 994         memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
 995
 996         return err;
 997 }
 998
 999 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1000                                 u32 value)
1001 {
1002         struct mlx5_hca_vport_context ctx = {};
1003         int err;
1004
1005         err = mlx5_query_hca_vport_context(dev->mdev, 0,
1006                                            port_num, 0, &ctx);
1007         if (err)
1008                 return err;
1009
1010         if (~ctx.cap_mask1_perm & mask) {
1011                 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1012                              mask, ctx.cap_mask1_perm);
1013                 return -EINVAL;
1014         }
1015
1016         ctx.cap_mask1 = value;
1017         ctx.cap_mask1_perm = mask;
1018         err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1019                                                  port_num, 0, &ctx);
1020
1021         return err;
1022 }
1023
1024 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1025                                struct ib_port_modify *props)
1026 {
1027         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1028         struct ib_port_attr attr;
1029         u32 tmp;
1030         int err;
1031         u32 change_mask;
1032         u32 value;
1033         bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1034                       IB_LINK_LAYER_INFINIBAND);
1035
1036         if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1037                 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1038                 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1039                 return set_port_caps_atomic(dev, port, change_mask, value);
1040         }
1041
1042         mutex_lock(&dev->cap_mask_mutex);
1043
1044         err = ib_query_port(ibdev, port, &attr);
1045         if (err)
1046                 goto out;
1047
1048         tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1049                 ~props->clr_port_cap_mask;
1050
1051         err = mlx5_set_port_caps(dev->mdev, port, tmp);
1052
1053 out:
1054         mutex_unlock(&dev->cap_mask_mutex);
1055         return err;
1056 }
1057
1058 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1059 {
1060         mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1061                     caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1062 }
1063
1064 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1065                              struct mlx5_ib_alloc_ucontext_req_v2 *req,
1066                              u32 *num_sys_pages)
1067 {
1068         int uars_per_sys_page;
1069         int bfregs_per_sys_page;
1070         int ref_bfregs = req->total_num_bfregs;
1071
1072         if (req->total_num_bfregs == 0)
1073                 return -EINVAL;
1074
1075         BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1076         BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1077
1078         if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1079                 return -ENOMEM;
1080
1081         uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1082         bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1083         req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1084         *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1085
1086         if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1087                 return -EINVAL;
1088
1089         mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1090                     MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1091                     lib_uar_4k ? "yes" : "no", ref_bfregs,
1092                     req->total_num_bfregs, *num_sys_pages);
1093
1094         return 0;
1095 }
1096
1097 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1098 {
1099         struct mlx5_bfreg_info *bfregi;
1100         int err;
1101         int i;
1102
1103         bfregi = &context->bfregi;
1104         for (i = 0; i < bfregi->num_sys_pages; i++) {
1105                 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1106                 if (err)
1107                         goto error;
1108
1109                 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1110         }
1111         return 0;
1112
1113 error:
1114         for (--i; i >= 0; i--)
1115                 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1116                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1117
1118         return err;
1119 }
1120
1121 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1122 {
1123         struct mlx5_bfreg_info *bfregi;
1124         int err;
1125         int i;
1126
1127         bfregi = &context->bfregi;
1128         for (i = 0; i < bfregi->num_sys_pages; i++) {
1129                 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1130                 if (err) {
1131                         mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1132                         return err;
1133                 }
1134         }
1135         return 0;
1136 }
1137
1138 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1139                                                   struct ib_udata *udata)
1140 {
1141         struct mlx5_ib_dev *dev = to_mdev(ibdev);
1142         struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1143         struct mlx5_ib_alloc_ucontext_resp resp = {};
1144         struct mlx5_ib_ucontext *context;
1145         struct mlx5_bfreg_info *bfregi;
1146         int ver;
1147         int err;
1148         size_t reqlen;
1149         size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1150                                      max_cqe_version);
1151         bool lib_uar_4k;
1152
1153         if (!dev->ib_active)
1154                 return ERR_PTR(-EAGAIN);
1155
1156         if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1157                 return ERR_PTR(-EINVAL);
1158
1159         reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1160         if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1161                 ver = 0;
1162         else if (reqlen >= min_req_v2)
1163                 ver = 2;
1164         else
1165                 return ERR_PTR(-EINVAL);
1166
1167         err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1168         if (err)
1169                 return ERR_PTR(err);
1170
1171         if (req.flags)
1172                 return ERR_PTR(-EINVAL);
1173
1174         if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1175                 return ERR_PTR(-EOPNOTSUPP);
1176
1177         req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1178                                     MLX5_NON_FP_BFREGS_PER_UAR);
1179         if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1180                 return ERR_PTR(-EINVAL);
1181
1182         resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1183         if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1184                 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1185         resp.cache_line_size = cache_line_size();
1186         resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1187         resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1188         resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1189         resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1190         resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1191         resp.cqe_version = min_t(__u8,
1192                                  (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1193                                  req.max_cqe_version);
1194         resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1195                                 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1196         resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1197                                         MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1198         resp.response_length = min(offsetof(typeof(resp), response_length) +
1199                                    sizeof(resp.response_length), udata->outlen);
1200
1201         context = kzalloc(sizeof(*context), GFP_KERNEL);
1202         if (!context)
1203                 return ERR_PTR(-ENOMEM);
1204
1205         lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1206         bfregi = &context->bfregi;
1207
1208         /* updates req->total_num_bfregs */
1209         err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1210         if (err)
1211                 goto out_ctx;
1212
1213         mutex_init(&bfregi->lock);
1214         bfregi->lib_uar_4k = lib_uar_4k;
1215         bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1216                                 GFP_KERNEL);
1217         if (!bfregi->count) {
1218                 err = -ENOMEM;
1219                 goto out_ctx;
1220         }
1221
1222         bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1223                                     sizeof(*bfregi->sys_pages),
1224                                     GFP_KERNEL);
1225         if (!bfregi->sys_pages) {
1226                 err = -ENOMEM;
1227                 goto out_count;
1228         }
1229
1230         err = allocate_uars(dev, context);
1231         if (err)
1232                 goto out_sys_pages;
1233
1234 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1235         context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1236 #endif
1237
1238         context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1239         if (!context->upd_xlt_page) {
1240                 err = -ENOMEM;
1241                 goto out_uars;
1242         }
1243         mutex_init(&context->upd_xlt_page_mutex);
1244
1245         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1246                 err = mlx5_core_alloc_transport_domain(dev->mdev,
1247                                                        &context->tdn);
1248                 if (err)
1249                         goto out_page;
1250         }
1251
1252         INIT_LIST_HEAD(&context->vma_private_list);
1253         INIT_LIST_HEAD(&context->db_page_list);
1254         mutex_init(&context->db_page_mutex);
1255
1256         resp.tot_bfregs = req.total_num_bfregs;
1257         resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1258
1259         if (field_avail(typeof(resp), cqe_version, udata->outlen))
1260                 resp.response_length += sizeof(resp.cqe_version);
1261
1262         if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1263                 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1264                                       MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1265                 resp.response_length += sizeof(resp.cmds_supp_uhw);
1266         }
1267
1268         if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1269                 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1270                         mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1271                         resp.eth_min_inline++;
1272                 }
1273                 resp.response_length += sizeof(resp.eth_min_inline);
1274         }
1275
1276         /*
1277          * We don't want to expose information from the PCI bar that is located
1278          * after 4096 bytes, so if the arch only supports larger pages, let's
1279          * pretend we don't support reading the HCA's core clock. This is also
1280          * forced by mmap function.
1281          */
1282         if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1283                 if (PAGE_SIZE <= 4096) {
1284                         resp.comp_mask |=
1285                                 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1286                         resp.hca_core_clock_offset =
1287                                 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1288                 }
1289                 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1290                                         sizeof(resp.reserved2);
1291         }
1292
1293         if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1294                 resp.response_length += sizeof(resp.log_uar_size);
1295
1296         if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1297                 resp.response_length += sizeof(resp.num_uars_per_page);
1298
1299         err = ib_copy_to_udata(udata, &resp, resp.response_length);
1300         if (err)
1301                 goto out_td;
1302
1303         bfregi->ver = ver;
1304         bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1305         context->cqe_version = resp.cqe_version;
1306         context->lib_caps = req.lib_caps;
1307         print_lib_caps(dev, context->lib_caps);
1308
1309         return &context->ibucontext;
1310
1311 out_td:
1312         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1313                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1314
1315 out_page:
1316         free_page(context->upd_xlt_page);
1317
1318 out_uars:
1319         deallocate_uars(dev, context);
1320
1321 out_sys_pages:
1322         kfree(bfregi->sys_pages);
1323
1324 out_count:
1325         kfree(bfregi->count);
1326
1327 out_ctx:
1328         kfree(context);
1329
1330         return ERR_PTR(err);
1331 }
1332
1333 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1334 {
1335         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1336         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1337         struct mlx5_bfreg_info *bfregi;
1338
1339         bfregi = &context->bfregi;
1340         if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1341                 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1342
1343         free_page(context->upd_xlt_page);
1344         deallocate_uars(dev, context);
1345         kfree(bfregi->sys_pages);
1346         kfree(bfregi->count);
1347         kfree(context);
1348
1349         return 0;
1350 }
1351
1352 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1353                                  struct mlx5_bfreg_info *bfregi,
1354                                  int idx)
1355 {
1356         int fw_uars_per_page;
1357
1358         fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1359
1360         return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1361                         bfregi->sys_pages[idx] / fw_uars_per_page;
1362 }
1363
1364 static int get_command(unsigned long offset)
1365 {
1366         return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1367 }
1368
1369 static int get_arg(unsigned long offset)
1370 {
1371         return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1372 }
1373
1374 static int get_index(unsigned long offset)
1375 {
1376         return get_arg(offset);
1377 }
1378
1379 static void  mlx5_ib_vma_open(struct vm_area_struct *area)
1380 {
1381         /* vma_open is called when a new VMA is created on top of our VMA.  This
1382          * is done through either mremap flow or split_vma (usually due to
1383          * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1384          * as this VMA is strongly hardware related.  Therefore we set the
1385          * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1386          * calling us again and trying to do incorrect actions.  We assume that
1387          * the original VMA size is exactly a single page, and therefore all
1388          * "splitting" operation will not happen to it.
1389          */
1390         area->vm_ops = NULL;
1391 }
1392
1393 static void  mlx5_ib_vma_close(struct vm_area_struct *area)
1394 {
1395         struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1396
1397         /* It's guaranteed that all VMAs opened on a FD are closed before the
1398          * file itself is closed, therefore no sync is needed with the regular
1399          * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1400          * However need a sync with accessing the vma as part of
1401          * mlx5_ib_disassociate_ucontext.
1402          * The close operation is usually called under mm->mmap_sem except when
1403          * process is exiting.
1404          * The exiting case is handled explicitly as part of
1405          * mlx5_ib_disassociate_ucontext.
1406          */
1407         mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1408
1409         /* setting the vma context pointer to null in the mlx5_ib driver's
1410          * private data, to protect a race condition in
1411          * mlx5_ib_disassociate_ucontext().
1412          */
1413         mlx5_ib_vma_priv_data->vma = NULL;
1414         list_del(&mlx5_ib_vma_priv_data->list);
1415         kfree(mlx5_ib_vma_priv_data);
1416 }
1417
1418 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1419         .open = mlx5_ib_vma_open,
1420         .close = mlx5_ib_vma_close
1421 };
1422
1423 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1424                                 struct mlx5_ib_ucontext *ctx)
1425 {
1426         struct mlx5_ib_vma_private_data *vma_prv;
1427         struct list_head *vma_head = &ctx->vma_private_list;
1428
1429         vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1430         if (!vma_prv)
1431                 return -ENOMEM;
1432
1433         vma_prv->vma = vma;
1434         vma->vm_private_data = vma_prv;
1435         vma->vm_ops =  &mlx5_ib_vm_ops;
1436
1437         list_add(&vma_prv->list, vma_head);
1438
1439         return 0;
1440 }
1441
1442 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1443 {
1444         int ret;
1445         struct vm_area_struct *vma;
1446         struct mlx5_ib_vma_private_data *vma_private, *n;
1447         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1448         struct task_struct *owning_process  = NULL;
1449         struct mm_struct   *owning_mm       = NULL;
1450
1451         owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1452         if (!owning_process)
1453                 return;
1454
1455         owning_mm = get_task_mm(owning_process);
1456         if (!owning_mm) {
1457                 pr_info("no mm, disassociate ucontext is pending task termination\n");
1458                 while (1) {
1459                         put_task_struct(owning_process);
1460                         usleep_range(1000, 2000);
1461                         owning_process = get_pid_task(ibcontext->tgid,
1462                                                       PIDTYPE_PID);
1463                         if (!owning_process ||
1464                             owning_process->state == TASK_DEAD) {
1465                                 pr_info("disassociate ucontext done, task was terminated\n");
1466                                 /* in case task was dead need to release the
1467                                  * task struct.
1468                                  */
1469                                 if (owning_process)
1470                                         put_task_struct(owning_process);
1471                                 return;
1472                         }
1473                 }
1474         }
1475
1476         /* need to protect from a race on closing the vma as part of
1477          * mlx5_ib_vma_close.
1478          */
1479         down_read(&owning_mm->mmap_sem);
1480         list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1481                                  list) {
1482                 vma = vma_private->vma;
1483                 ret = zap_vma_ptes(vma, vma->vm_start,
1484                                    PAGE_SIZE);
1485                 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1486                 /* context going to be destroyed, should
1487                  * not access ops any more.
1488                  */
1489                 vma->vm_ops = NULL;
1490                 list_del(&vma_private->list);
1491                 kfree(vma_private);
1492         }
1493         up_read(&owning_mm->mmap_sem);
1494         mmput(owning_mm);
1495         put_task_struct(owning_process);
1496 }
1497
1498 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1499 {
1500         switch (cmd) {
1501         case MLX5_IB_MMAP_WC_PAGE:
1502                 return "WC";
1503         case MLX5_IB_MMAP_REGULAR_PAGE:
1504                 return "best effort WC";
1505         case MLX5_IB_MMAP_NC_PAGE:
1506                 return "NC";
1507         default:
1508                 return NULL;
1509         }
1510 }
1511
1512 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1513                     struct vm_area_struct *vma,
1514                     struct mlx5_ib_ucontext *context)
1515 {
1516         struct mlx5_bfreg_info *bfregi = &context->bfregi;
1517         int err;
1518         unsigned long idx;
1519         phys_addr_t pfn, pa;
1520         pgprot_t prot;
1521         int uars_per_page;
1522
1523         if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1524                 return -EINVAL;
1525
1526         uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1527         idx = get_index(vma->vm_pgoff);
1528         if (idx % uars_per_page ||
1529             idx * uars_per_page >= bfregi->num_sys_pages) {
1530                 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1531                 return -EINVAL;
1532         }
1533
1534         switch (cmd) {
1535         case MLX5_IB_MMAP_WC_PAGE:
1536 /* Some architectures don't support WC memory */
1537 #if defined(CONFIG_X86)
1538                 if (!pat_enabled())
1539                         return -EPERM;
1540 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1541                         return -EPERM;
1542 #endif
1543         /* fall through */
1544         case MLX5_IB_MMAP_REGULAR_PAGE:
1545                 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1546                 prot = pgprot_writecombine(vma->vm_page_prot);
1547                 break;
1548         case MLX5_IB_MMAP_NC_PAGE:
1549                 prot = pgprot_noncached(vma->vm_page_prot);
1550                 break;
1551         default:
1552                 return -EINVAL;
1553         }
1554
1555         pfn = uar_index2pfn(dev, bfregi, idx);
1556         mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1557
1558         vma->vm_page_prot = prot;
1559         err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1560                                  PAGE_SIZE, vma->vm_page_prot);
1561         if (err) {
1562                 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1563                             err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1564                 return -EAGAIN;
1565         }
1566
1567         pa = pfn << PAGE_SHIFT;
1568         mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1569                     vma->vm_start, &pa);
1570
1571         return mlx5_ib_set_vma_data(vma, context);
1572 }
1573
1574 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1575 {
1576         struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1577         struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1578         unsigned long command;
1579         phys_addr_t pfn;
1580
1581         command = get_command(vma->vm_pgoff);
1582         switch (command) {
1583         case MLX5_IB_MMAP_WC_PAGE:
1584         case MLX5_IB_MMAP_NC_PAGE:
1585         case MLX5_IB_MMAP_REGULAR_PAGE:
1586                 return uar_mmap(dev, command, vma, context);
1587
1588         case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1589                 return -ENOSYS;
1590
1591         case MLX5_IB_MMAP_CORE_CLOCK:
1592                 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1593                         return -EINVAL;
1594
1595                 if (vma->vm_flags & VM_WRITE)
1596                         return -EPERM;
1597
1598                 /* Don't expose to user-space information it shouldn't have */
1599                 if (PAGE_SIZE > 4096)
1600                         return -EOPNOTSUPP;
1601
1602                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1603                 pfn = (dev->mdev->iseg_base +
1604                        offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1605                         PAGE_SHIFT;
1606                 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1607                                        PAGE_SIZE, vma->vm_page_prot))
1608                         return -EAGAIN;
1609
1610                 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1611                             vma->vm_start,
1612                             (unsigned long long)pfn << PAGE_SHIFT);
1613                 break;
1614
1615         default:
1616                 return -EINVAL;
1617         }
1618
1619         return 0;
1620 }
1621
1622 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1623                                       struct ib_ucontext *context,
1624                                       struct ib_udata *udata)
1625 {
1626         struct mlx5_ib_alloc_pd_resp resp;
1627         struct mlx5_ib_pd *pd;
1628         int err;
1629
1630         pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1631         if (!pd)
1632                 return ERR_PTR(-ENOMEM);
1633
1634         err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1635         if (err) {
1636                 kfree(pd);
1637                 return ERR_PTR(err);
1638         }
1639
1640         if (context) {
1641                 resp.pdn = pd->pdn;
1642                 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1643                         mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1644                         kfree(pd);
1645                         return ERR_PTR(-EFAULT);
1646                 }
1647         }
1648
1649         return &pd->ibpd;
1650 }
1651
1652 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1653 {
1654         struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1655         struct mlx5_ib_pd *mpd = to_mpd(pd);
1656
1657         mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1658         kfree(mpd);
1659
1660         return 0;
1661 }
1662
1663 enum {
1664         MATCH_CRITERIA_ENABLE_OUTER_BIT,
1665         MATCH_CRITERIA_ENABLE_MISC_BIT,
1666         MATCH_CRITERIA_ENABLE_INNER_BIT
1667 };
1668
1669 #define HEADER_IS_ZERO(match_criteria, headers)                            \
1670         !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1671                     0, MLX5_FLD_SZ_BYTES(fte_match_param, headers)))       \
1672
1673 static u8 get_match_criteria_enable(u32 *match_criteria)
1674 {
1675         u8 match_criteria_enable;
1676
1677         match_criteria_enable =
1678                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1679                 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1680         match_criteria_enable |=
1681                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1682                 MATCH_CRITERIA_ENABLE_MISC_BIT;
1683         match_criteria_enable |=
1684                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1685                 MATCH_CRITERIA_ENABLE_INNER_BIT;
1686
1687         return match_criteria_enable;
1688 }
1689
1690 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1691 {
1692         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1693         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1694 }
1695
1696 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1697                            bool inner)
1698 {
1699         if (inner) {
1700                 MLX5_SET(fte_match_set_misc,
1701                          misc_c, inner_ipv6_flow_label, mask);
1702                 MLX5_SET(fte_match_set_misc,
1703                          misc_v, inner_ipv6_flow_label, val);
1704         } else {
1705                 MLX5_SET(fte_match_set_misc,
1706                          misc_c, outer_ipv6_flow_label, mask);
1707                 MLX5_SET(fte_match_set_misc,
1708                          misc_v, outer_ipv6_flow_label, val);
1709         }
1710 }
1711
1712 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1713 {
1714         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1715         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1716         MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1717         MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1718 }
1719
1720 #define LAST_ETH_FIELD vlan_tag
1721 #define LAST_IB_FIELD sl
1722 #define LAST_IPV4_FIELD tos
1723 #define LAST_IPV6_FIELD traffic_class
1724 #define LAST_TCP_UDP_FIELD src_port
1725 #define LAST_TUNNEL_FIELD tunnel_id
1726 #define LAST_FLOW_TAG_FIELD tag_id
1727
1728 /* Field is the last supported field */
1729 #define FIELDS_NOT_SUPPORTED(filter, field)\
1730         memchr_inv((void *)&filter.field  +\
1731                    sizeof(filter.field), 0,\
1732                    sizeof(filter) -\
1733                    offsetof(typeof(filter), field) -\
1734                    sizeof(filter.field))
1735
1736 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1737                            const union ib_flow_spec *ib_spec, u32 *tag_id)
1738 {
1739         void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1740                                            misc_parameters);
1741         void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1742                                            misc_parameters);
1743         void *headers_c;
1744         void *headers_v;
1745
1746         if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1747                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1748                                          inner_headers);
1749                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1750                                          inner_headers);
1751         } else {
1752                 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1753                                          outer_headers);
1754                 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1755                                          outer_headers);
1756         }
1757
1758         switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1759         case IB_FLOW_SPEC_ETH:
1760                 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1761                         return -EOPNOTSUPP;
1762
1763                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1764                                              dmac_47_16),
1765                                 ib_spec->eth.mask.dst_mac);
1766                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1767                                              dmac_47_16),
1768                                 ib_spec->eth.val.dst_mac);
1769
1770                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1771                                              smac_47_16),
1772                                 ib_spec->eth.mask.src_mac);
1773                 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1774                                              smac_47_16),
1775                                 ib_spec->eth.val.src_mac);
1776
1777                 if (ib_spec->eth.mask.vlan_tag) {
1778                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1779                                  cvlan_tag, 1);
1780                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1781                                  cvlan_tag, 1);
1782
1783                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1784                                  first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1785                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1786                                  first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1787
1788                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1789                                  first_cfi,
1790                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1791                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1792                                  first_cfi,
1793                                  ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1794
1795                         MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1796                                  first_prio,
1797                                  ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1798                         MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1799                                  first_prio,
1800                                  ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1801                 }
1802                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1803                          ethertype, ntohs(ib_spec->eth.mask.ether_type));
1804                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1805                          ethertype, ntohs(ib_spec->eth.val.ether_type));
1806                 break;
1807         case IB_FLOW_SPEC_IPV4:
1808                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1809                         return -EOPNOTSUPP;
1810
1811                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1812                          ethertype, 0xffff);
1813                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1814                          ethertype, ETH_P_IP);
1815
1816                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1817                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1818                        &ib_spec->ipv4.mask.src_ip,
1819                        sizeof(ib_spec->ipv4.mask.src_ip));
1820                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1821                                     src_ipv4_src_ipv6.ipv4_layout.ipv4),
1822                        &ib_spec->ipv4.val.src_ip,
1823                        sizeof(ib_spec->ipv4.val.src_ip));
1824                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1825                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1826                        &ib_spec->ipv4.mask.dst_ip,
1827                        sizeof(ib_spec->ipv4.mask.dst_ip));
1828                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1829                                     dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1830                        &ib_spec->ipv4.val.dst_ip,
1831                        sizeof(ib_spec->ipv4.val.dst_ip));
1832
1833                 set_tos(headers_c, headers_v,
1834                         ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1835
1836                 set_proto(headers_c, headers_v,
1837                           ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1838                 break;
1839         case IB_FLOW_SPEC_IPV6:
1840                 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1841                         return -EOPNOTSUPP;
1842
1843                 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1844                          ethertype, 0xffff);
1845                 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1846                          ethertype, ETH_P_IPV6);
1847
1848                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1849                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1850                        &ib_spec->ipv6.mask.src_ip,
1851                        sizeof(ib_spec->ipv6.mask.src_ip));
1852                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1853                                     src_ipv4_src_ipv6.ipv6_layout.ipv6),
1854                        &ib_spec->ipv6.val.src_ip,
1855                        sizeof(ib_spec->ipv6.val.src_ip));
1856                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1857                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1858                        &ib_spec->ipv6.mask.dst_ip,
1859                        sizeof(ib_spec->ipv6.mask.dst_ip));
1860                 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1861                                     dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1862                        &ib_spec->ipv6.val.dst_ip,
1863                        sizeof(ib_spec->ipv6.val.dst_ip));
1864
1865                 set_tos(headers_c, headers_v,
1866                         ib_spec->ipv6.mask.traffic_class,
1867                         ib_spec->ipv6.val.traffic_class);
1868
1869                 set_proto(headers_c, headers_v,
1870                           ib_spec->ipv6.mask.next_hdr,
1871                           ib_spec->ipv6.val.next_hdr);
1872
1873                 set_flow_label(misc_params_c, misc_params_v,
1874                                ntohl(ib_spec->ipv6.mask.flow_label),
1875                                ntohl(ib_spec->ipv6.val.flow_label),
1876                                ib_spec->type & IB_FLOW_SPEC_INNER);
1877
1878                 break;
1879         case IB_FLOW_SPEC_TCP:
1880                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1881                                          LAST_TCP_UDP_FIELD))
1882                         return -EOPNOTSUPP;
1883
1884                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1885                          0xff);
1886                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1887                          IPPROTO_TCP);
1888
1889                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1890                          ntohs(ib_spec->tcp_udp.mask.src_port));
1891                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1892                          ntohs(ib_spec->tcp_udp.val.src_port));
1893
1894                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1895                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1896                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1897                          ntohs(ib_spec->tcp_udp.val.dst_port));
1898                 break;
1899         case IB_FLOW_SPEC_UDP:
1900                 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1901                                          LAST_TCP_UDP_FIELD))
1902                         return -EOPNOTSUPP;
1903
1904                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1905                          0xff);
1906                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1907                          IPPROTO_UDP);
1908
1909                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1910                          ntohs(ib_spec->tcp_udp.mask.src_port));
1911                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1912                          ntohs(ib_spec->tcp_udp.val.src_port));
1913
1914                 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1915                          ntohs(ib_spec->tcp_udp.mask.dst_port));
1916                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1917                          ntohs(ib_spec->tcp_udp.val.dst_port));
1918                 break;
1919         case IB_FLOW_SPEC_VXLAN_TUNNEL:
1920                 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1921                                          LAST_TUNNEL_FIELD))
1922                         return -EOPNOTSUPP;
1923
1924                 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1925                          ntohl(ib_spec->tunnel.mask.tunnel_id));
1926                 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1927                          ntohl(ib_spec->tunnel.val.tunnel_id));
1928                 break;
1929         case IB_FLOW_SPEC_ACTION_TAG:
1930                 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
1931                                          LAST_FLOW_TAG_FIELD))
1932                         return -EOPNOTSUPP;
1933                 if (ib_spec->flow_tag.tag_id >= BIT(24))
1934                         return -EINVAL;
1935
1936                 *tag_id = ib_spec->flow_tag.tag_id;
1937                 break;
1938         default:
1939                 return -EINVAL;
1940         }
1941
1942         return 0;
1943 }
1944
1945 /* If a flow could catch both multicast and unicast packets,
1946  * it won't fall into the multicast flow steering table and this rule
1947  * could steal other multicast packets.
1948  */
1949 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1950 {
1951         struct ib_flow_spec_eth *eth_spec;
1952
1953         if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1954             ib_attr->size < sizeof(struct ib_flow_attr) +
1955             sizeof(struct ib_flow_spec_eth) ||
1956             ib_attr->num_of_specs < 1)
1957                 return false;
1958
1959         eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1960         if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1961             eth_spec->size != sizeof(*eth_spec))
1962                 return false;
1963
1964         return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1965                is_multicast_ether_addr(eth_spec->val.dst_mac);
1966 }
1967
1968 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1969 {
1970         union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1971         bool has_ipv4_spec = false;
1972         bool eth_type_ipv4 = true;
1973         unsigned int spec_index;
1974
1975         /* Validate that ethertype is correct */
1976         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1977                 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1978                     ib_spec->eth.mask.ether_type) {
1979                         if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1980                               ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1981                                 eth_type_ipv4 = false;
1982                 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1983                         has_ipv4_spec = true;
1984                 }
1985                 ib_spec = (void *)ib_spec + ib_spec->size;
1986         }
1987         return !has_ipv4_spec || eth_type_ipv4;
1988 }
1989
1990 static void put_flow_table(struct mlx5_ib_dev *dev,
1991                            struct mlx5_ib_flow_prio *prio, bool ft_added)
1992 {
1993         prio->refcount -= !!ft_added;
1994         if (!prio->refcount) {
1995                 mlx5_destroy_flow_table(prio->flow_table);
1996                 prio->flow_table = NULL;
1997         }
1998 }
1999
2000 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2001 {
2002         struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2003         struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2004                                                           struct mlx5_ib_flow_handler,
2005                                                           ibflow);
2006         struct mlx5_ib_flow_handler *iter, *tmp;
2007
2008         mutex_lock(&dev->flow_db.lock);
2009
2010         list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2011                 mlx5_del_flow_rules(iter->rule);
2012                 put_flow_table(dev, iter->prio, true);
2013                 list_del(&iter->list);
2014                 kfree(iter);
2015         }
2016
2017         mlx5_del_flow_rules(handler->rule);
2018         put_flow_table(dev, handler->prio, true);
2019         mutex_unlock(&dev->flow_db.lock);
2020
2021         kfree(handler);
2022
2023         return 0;
2024 }
2025
2026 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2027 {
2028         priority *= 2;
2029         if (!dont_trap)
2030                 priority++;
2031         return priority;
2032 }
2033
2034 enum flow_table_type {
2035         MLX5_IB_FT_RX,
2036         MLX5_IB_FT_TX
2037 };
2038
2039 #define MLX5_FS_MAX_TYPES        10
2040 #define MLX5_FS_MAX_ENTRIES      32000UL
2041 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2042                                                 struct ib_flow_attr *flow_attr,
2043                                                 enum flow_table_type ft_type)
2044 {
2045         bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2046         struct mlx5_flow_namespace *ns = NULL;
2047         struct mlx5_ib_flow_prio *prio;
2048         struct mlx5_flow_table *ft;
2049         int num_entries;
2050         int num_groups;
2051         int priority;
2052         int err = 0;
2053
2054         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2055                 if (flow_is_multicast_only(flow_attr) &&
2056                     !dont_trap)
2057                         priority = MLX5_IB_FLOW_MCAST_PRIO;
2058                 else
2059                         priority = ib_prio_to_core_prio(flow_attr->priority,
2060                                                         dont_trap);
2061                 ns = mlx5_get_flow_namespace(dev->mdev,
2062                                              MLX5_FLOW_NAMESPACE_BYPASS);
2063                 num_entries = MLX5_FS_MAX_ENTRIES;
2064                 num_groups = MLX5_FS_MAX_TYPES;
2065                 prio = &dev->flow_db.prios[priority];
2066         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2067                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2068                 ns = mlx5_get_flow_namespace(dev->mdev,
2069                                              MLX5_FLOW_NAMESPACE_LEFTOVERS);
2070                 build_leftovers_ft_param(&priority,
2071                                          &num_entries,
2072                                          &num_groups);
2073                 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2074         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2075                 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2076                                         allow_sniffer_and_nic_rx_shared_tir))
2077                         return ERR_PTR(-ENOTSUPP);
2078
2079                 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2080                                              MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2081                                              MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2082
2083                 prio = &dev->flow_db.sniffer[ft_type];
2084                 priority = 0;
2085                 num_entries = 1;
2086                 num_groups = 1;
2087         }
2088
2089         if (!ns)
2090                 return ERR_PTR(-ENOTSUPP);
2091
2092         ft = prio->flow_table;
2093         if (!ft) {
2094                 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2095                                                          num_entries,
2096                                                          num_groups,
2097                                                          0, 0);
2098
2099                 if (!IS_ERR(ft)) {
2100                         prio->refcount = 0;
2101                         prio->flow_table = ft;
2102                 } else {
2103                         err = PTR_ERR(ft);
2104                 }
2105         }
2106
2107         return err ? ERR_PTR(err) : prio;
2108 }
2109
2110 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2111                                                      struct mlx5_ib_flow_prio *ft_prio,
2112                                                      const struct ib_flow_attr *flow_attr,
2113                                                      struct mlx5_flow_destination *dst)
2114 {
2115         struct mlx5_flow_table  *ft = ft_prio->flow_table;
2116         struct mlx5_ib_flow_handler *handler;
2117         struct mlx5_flow_act flow_act = {0};
2118         struct mlx5_flow_spec *spec;
2119         const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2120         unsigned int spec_index;
2121         u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2122         int err = 0;
2123
2124         if (!is_valid_attr(flow_attr))
2125                 return ERR_PTR(-EINVAL);
2126
2127         spec = mlx5_vzalloc(sizeof(*spec));
2128         handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2129         if (!handler || !spec) {
2130                 err = -ENOMEM;
2131                 goto free;
2132         }
2133
2134         INIT_LIST_HEAD(&handler->list);
2135
2136         for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2137                 err = parse_flow_attr(spec->match_criteria,
2138                                       spec->match_value, ib_flow, &flow_tag);
2139                 if (err < 0)
2140                         goto free;
2141
2142                 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2143         }
2144
2145         spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2146         flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2147                 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2148
2149         if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2150             (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2151              flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2152                 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2153                              flow_tag, flow_attr->type);
2154                 err = -EINVAL;
2155                 goto free;
2156         }
2157         flow_act.flow_tag = flow_tag;
2158         handler->rule = mlx5_add_flow_rules(ft, spec,
2159                                             &flow_act,
2160                                             dst, 1);
2161
2162         if (IS_ERR(handler->rule)) {
2163                 err = PTR_ERR(handler->rule);
2164                 goto free;
2165         }
2166
2167         ft_prio->refcount++;
2168         handler->prio = ft_prio;
2169
2170         ft_prio->flow_table = ft;
2171 free:
2172         if (err)
2173                 kfree(handler);
2174         kvfree(spec);
2175         return err ? ERR_PTR(err) : handler;
2176 }
2177
2178 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2179                                                           struct mlx5_ib_flow_prio *ft_prio,
2180                                                           struct ib_flow_attr *flow_attr,
2181                                                           struct mlx5_flow_destination *dst)
2182 {
2183         struct mlx5_ib_flow_handler *handler_dst = NULL;
2184         struct mlx5_ib_flow_handler *handler = NULL;
2185
2186         handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2187         if (!IS_ERR(handler)) {
2188                 handler_dst = create_flow_rule(dev, ft_prio,
2189                                                flow_attr, dst);
2190                 if (IS_ERR(handler_dst)) {
2191                         mlx5_del_flow_rules(handler->rule);
2192                         ft_prio->refcount--;
2193                         kfree(handler);
2194                         handler = handler_dst;
2195                 } else {
2196                         list_add(&handler_dst->list, &handler->list);
2197                 }
2198         }
2199
2200         return handler;
2201 }
2202 enum {
2203         LEFTOVERS_MC,
2204         LEFTOVERS_UC,
2205 };
2206
2207 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2208                                                           struct mlx5_ib_flow_prio *ft_prio,
2209                                                           struct ib_flow_attr *flow_attr,
2210                                                           struct mlx5_flow_destination *dst)
2211 {
2212         struct mlx5_ib_flow_handler *handler_ucast = NULL;
2213         struct mlx5_ib_flow_handler *handler = NULL;
2214
2215         static struct {
2216                 struct ib_flow_attr     flow_attr;
2217                 struct ib_flow_spec_eth eth_flow;
2218         } leftovers_specs[] = {
2219                 [LEFTOVERS_MC] = {
2220                         .flow_attr = {
2221                                 .num_of_specs = 1,
2222                                 .size = sizeof(leftovers_specs[0])
2223                         },
2224                         .eth_flow = {
2225                                 .type = IB_FLOW_SPEC_ETH,
2226                                 .size = sizeof(struct ib_flow_spec_eth),
2227                                 .mask = {.dst_mac = {0x1} },
2228                                 .val =  {.dst_mac = {0x1} }
2229                         }
2230                 },
2231                 [LEFTOVERS_UC] = {
2232                         .flow_attr = {
2233                                 .num_of_specs = 1,
2234                                 .size = sizeof(leftovers_specs[0])
2235                         },
2236                         .eth_flow = {
2237                                 .type = IB_FLOW_SPEC_ETH,
2238                                 .size = sizeof(struct ib_flow_spec_eth),
2239                                 .mask = {.dst_mac = {0x1} },
2240                                 .val = {.dst_mac = {} }
2241                         }
2242                 }
2243         };
2244
2245         handler = create_flow_rule(dev, ft_prio,
2246                                    &leftovers_specs[LEFTOVERS_MC].flow_attr,
2247                                    dst);
2248         if (!IS_ERR(handler) &&
2249             flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2250                 handler_ucast = create_flow_rule(dev, ft_prio,
2251                                                  &leftovers_specs[LEFTOVERS_UC].flow_attr,
2252                                                  dst);
2253                 if (IS_ERR(handler_ucast)) {
2254                         mlx5_del_flow_rules(handler->rule);
2255                         ft_prio->refcount--;
2256                         kfree(handler);
2257                         handler = handler_ucast;
2258                 } else {
2259                         list_add(&handler_ucast->list, &handler->list);
2260                 }
2261         }
2262
2263         return handler;
2264 }
2265
2266 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2267                                                         struct mlx5_ib_flow_prio *ft_rx,
2268                                                         struct mlx5_ib_flow_prio *ft_tx,
2269                                                         struct mlx5_flow_destination *dst)
2270 {
2271         struct mlx5_ib_flow_handler *handler_rx;
2272         struct mlx5_ib_flow_handler *handler_tx;
2273         int err;
2274         static const struct ib_flow_attr flow_attr  = {
2275                 .num_of_specs = 0,
2276                 .size = sizeof(flow_attr)
2277         };
2278
2279         handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2280         if (IS_ERR(handler_rx)) {
2281                 err = PTR_ERR(handler_rx);
2282                 goto err;
2283         }
2284
2285         handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2286         if (IS_ERR(handler_tx)) {
2287                 err = PTR_ERR(handler_tx);
2288                 goto err_tx;
2289         }
2290
2291         list_add(&handler_tx->list, &handler_rx->list);
2292
2293         return handler_rx;
2294
2295 err_tx:
2296         mlx5_del_flow_rules(handler_rx->rule);
2297         ft_rx->refcount--;
2298         kfree(handler_rx);
2299 err:
2300         return ERR_PTR(err);
2301 }
2302
2303 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2304                                            struct ib_flow_attr *flow_attr,
2305                                            int domain)
2306 {
2307         struct mlx5_ib_dev *dev = to_mdev(qp->device);
2308         struct mlx5_ib_qp *mqp = to_mqp(qp);
2309         struct mlx5_ib_flow_handler *handler = NULL;
2310         struct mlx5_flow_destination *dst = NULL;
2311         struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2312         struct mlx5_ib_flow_prio *ft_prio;
2313         int err;
2314
2315         if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2316                 return ERR_PTR(-ENOSPC);
2317
2318         if (domain != IB_FLOW_DOMAIN_USER ||
2319             flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2320             (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2321                 return ERR_PTR(-EINVAL);
2322
2323         dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2324         if (!dst)
2325                 return ERR_PTR(-ENOMEM);
2326
2327         mutex_lock(&dev->flow_db.lock);
2328
2329         ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2330         if (IS_ERR(ft_prio)) {
2331                 err = PTR_ERR(ft_prio);
2332                 goto unlock;
2333         }
2334         if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2335                 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2336                 if (IS_ERR(ft_prio_tx)) {
2337                         err = PTR_ERR(ft_prio_tx);
2338                         ft_prio_tx = NULL;
2339                         goto destroy_ft;
2340                 }
2341         }
2342
2343         dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2344         if (mqp->flags & MLX5_IB_QP_RSS)
2345                 dst->tir_num = mqp->rss_qp.tirn;
2346         else
2347                 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2348
2349         if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2350                 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)  {
2351                         handler = create_dont_trap_rule(dev, ft_prio,
2352                                                         flow_attr, dst);
2353                 } else {
2354                         handler = create_flow_rule(dev, ft_prio, flow_attr,
2355                                                    dst);
2356                 }
2357         } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2358                    flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2359                 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2360                                                 dst);
2361         } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2362                 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2363         } else {
2364                 err = -EINVAL;
2365                 goto destroy_ft;
2366         }
2367
2368         if (IS_ERR(handler)) {
2369                 err = PTR_ERR(handler);
2370                 handler = NULL;
2371                 goto destroy_ft;
2372         }
2373
2374         mutex_unlock(&dev->flow_db.lock);
2375         kfree(dst);
2376
2377         return &handler->ibflow;
2378
2379 destroy_ft:
2380         put_flow_table(dev, ft_prio, false);
2381         if (ft_prio_tx)
2382                 put_flow_table(dev, ft_prio_tx, false);
2383 unlock:
2384         mutex_unlock(&dev->flow_db.lock);
2385         kfree(dst);
2386         kfree(handler);
2387         return ERR_PTR(err);
2388 }
2389
2390 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2391 {
2392         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2393         int err;
2394
2395         err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2396         if (err)
2397                 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2398                              ibqp->qp_num, gid->raw);
2399
2400         return err;
2401 }
2402
2403 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2404 {
2405         struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2406         int err;
2407
2408         err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2409         if (err)
2410                 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2411                              ibqp->qp_num, gid->raw);
2412
2413         return err;
2414 }
2415
2416 static int init_node_data(struct mlx5_ib_dev *dev)
2417 {
2418         int err;
2419
2420         err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2421         if (err)
2422                 return err;
2423
2424         dev->mdev->rev_id = dev->mdev->pdev->revision;
2425
2426         return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2427 }
2428
2429 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2430                              char *buf)
2431 {
2432         struct mlx5_ib_dev *dev =
2433                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2434
2435         return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2436 }
2437
2438 static ssize_t show_reg_pages(struct device *device,
2439                               struct device_attribute *attr, char *buf)
2440 {
2441         struct mlx5_ib_dev *dev =
2442                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2443
2444         return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2445 }
2446
2447 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2448                         char *buf)
2449 {
2450         struct mlx5_ib_dev *dev =
2451                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2452         return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2453 }
2454
2455 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2456                         char *buf)
2457 {
2458         struct mlx5_ib_dev *dev =
2459                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2460         return sprintf(buf, "%x\n", dev->mdev->rev_id);
2461 }
2462
2463 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2464                           char *buf)
2465 {
2466         struct mlx5_ib_dev *dev =
2467                 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2468         return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2469                        dev->mdev->board_id);
2470 }
2471
2472 static DEVICE_ATTR(hw_rev,   S_IRUGO, show_rev,    NULL);
2473 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca,    NULL);
2474 static DEVICE_ATTR(board_id, S_IRUGO, show_board,  NULL);
2475 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2476 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2477
2478 static struct device_attribute *mlx5_class_attributes[] = {
2479         &dev_attr_hw_rev,
2480         &dev_attr_hca_type,
2481         &dev_attr_board_id,
2482         &dev_attr_fw_pages,
2483         &dev_attr_reg_pages,
2484 };
2485
2486 static void pkey_change_handler(struct work_struct *work)
2487 {
2488         struct mlx5_ib_port_resources *ports =
2489                 container_of(work, struct mlx5_ib_port_resources,
2490                              pkey_change_work);
2491
2492         mutex_lock(&ports->devr->mutex);
2493         mlx5_ib_gsi_pkey_change(ports->gsi);
2494         mutex_unlock(&ports->devr->mutex);
2495 }
2496
2497 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2498 {
2499         struct mlx5_ib_qp *mqp;
2500         struct mlx5_ib_cq *send_mcq, *recv_mcq;
2501         struct mlx5_core_cq *mcq;
2502         struct list_head cq_armed_list;
2503         unsigned long flags_qp;
2504         unsigned long flags_cq;
2505         unsigned long flags;
2506
2507         INIT_LIST_HEAD(&cq_armed_list);
2508
2509         /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2510         spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2511         list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2512                 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2513                 if (mqp->sq.tail != mqp->sq.head) {
2514                         send_mcq = to_mcq(mqp->ibqp.send_cq);
2515                         spin_lock_irqsave(&send_mcq->lock, flags_cq);
2516                         if (send_mcq->mcq.comp &&
2517                             mqp->ibqp.send_cq->comp_handler) {
2518                                 if (!send_mcq->mcq.reset_notify_added) {
2519                                         send_mcq->mcq.reset_notify_added = 1;
2520                                         list_add_tail(&send_mcq->mcq.reset_notify,
2521                                                       &cq_armed_list);
2522                                 }
2523                         }
2524                         spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2525                 }
2526                 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2527                 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2528                 /* no handling is needed for SRQ */
2529                 if (!mqp->ibqp.srq) {
2530                         if (mqp->rq.tail != mqp->rq.head) {
2531                                 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2532                                 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2533                                 if (recv_mcq->mcq.comp &&
2534                                     mqp->ibqp.recv_cq->comp_handler) {
2535                                         if (!recv_mcq->mcq.reset_notify_added) {
2536                                                 recv_mcq->mcq.reset_notify_added = 1;
2537                                                 list_add_tail(&recv_mcq->mcq.reset_notify,
2538                                                               &cq_armed_list);
2539                                         }
2540                                 }
2541                                 spin_unlock_irqrestore(&recv_mcq->lock,
2542                                                        flags_cq);
2543                         }
2544                 }
2545                 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2546         }
2547         /*At that point all inflight post send were put to be executed as of we
2548          * lock/unlock above locks Now need to arm all involved CQs.
2549          */
2550         list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2551                 mcq->comp(mcq);
2552         }
2553         spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2554 }
2555
2556 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2557                           enum mlx5_dev_event event, unsigned long param)
2558 {
2559         struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2560         struct ib_event ibev;
2561         bool fatal = false;
2562         u8 port = 0;
2563
2564         switch (event) {
2565         case MLX5_DEV_EVENT_SYS_ERROR:
2566                 ibev.event = IB_EVENT_DEVICE_FATAL;
2567                 mlx5_ib_handle_internal_error(ibdev);
2568                 fatal = true;
2569                 break;
2570
2571         case MLX5_DEV_EVENT_PORT_UP:
2572         case MLX5_DEV_EVENT_PORT_DOWN:
2573         case MLX5_DEV_EVENT_PORT_INITIALIZED:
2574                 port = (u8)param;
2575
2576                 /* In RoCE, port up/down events are handled in
2577                  * mlx5_netdev_event().
2578                  */
2579                 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2580                         IB_LINK_LAYER_ETHERNET)
2581                         return;
2582
2583                 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2584                              IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2585                 break;
2586
2587         case MLX5_DEV_EVENT_LID_CHANGE:
2588                 ibev.event = IB_EVENT_LID_CHANGE;
2589                 port = (u8)param;
2590                 break;
2591
2592         case MLX5_DEV_EVENT_PKEY_CHANGE:
2593                 ibev.event = IB_EVENT_PKEY_CHANGE;
2594                 port = (u8)param;
2595
2596                 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2597                 break;
2598
2599         case MLX5_DEV_EVENT_GUID_CHANGE:
2600                 ibev.event = IB_EVENT_GID_CHANGE;
2601                 port = (u8)param;
2602                 break;
2603
2604         case MLX5_DEV_EVENT_CLIENT_REREG:
2605                 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2606                 port = (u8)param;
2607                 break;
2608         default:
2609                 return;
2610         }
2611
2612         ibev.device           = &ibdev->ib_dev;
2613         ibev.element.port_num = port;
2614
2615         if (port < 1 || port > ibdev->num_ports) {
2616                 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2617                 return;
2618         }
2619
2620         if (ibdev->ib_active)
2621                 ib_dispatch_event(&ibev);
2622
2623         if (fatal)
2624                 ibdev->ib_active = false;
2625 }
2626
2627 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2628 {
2629         struct mlx5_hca_vport_context vport_ctx;
2630         int err;
2631         int port;
2632
2633         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2634                 dev->mdev->port_caps[port - 1].has_smi = false;
2635                 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2636                     MLX5_CAP_PORT_TYPE_IB) {
2637                         if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2638                                 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2639                                                                    port, 0,
2640                                                                    &vport_ctx);
2641                                 if (err) {
2642                                         mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2643                                                     port, err);
2644                                         return err;
2645                                 }
2646                                 dev->mdev->port_caps[port - 1].has_smi =
2647                                         vport_ctx.has_smi;
2648                         } else {
2649                                 dev->mdev->port_caps[port - 1].has_smi = true;
2650                         }
2651                 }
2652         }
2653         return 0;
2654 }
2655
2656 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2657 {
2658         int port;
2659
2660         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2661                 mlx5_query_ext_port_caps(dev, port);
2662 }
2663
2664 static int get_port_caps(struct mlx5_ib_dev *dev)
2665 {
2666         struct ib_device_attr *dprops = NULL;
2667         struct ib_port_attr *pprops = NULL;
2668         int err = -ENOMEM;
2669         int port;
2670         struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2671
2672         pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2673         if (!pprops)
2674                 goto out;
2675
2676         dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2677         if (!dprops)
2678                 goto out;
2679
2680         err = set_has_smi_cap(dev);
2681         if (err)
2682                 goto out;
2683
2684         err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2685         if (err) {
2686                 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2687                 goto out;
2688         }
2689
2690         for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2691                 memset(pprops, 0, sizeof(*pprops));
2692                 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2693                 if (err) {
2694                         mlx5_ib_warn(dev, "query_port %d failed %d\n",
2695                                      port, err);
2696                         break;
2697                 }
2698                 dev->mdev->port_caps[port - 1].pkey_table_len =
2699                                                 dprops->max_pkeys;
2700                 dev->mdev->port_caps[port - 1].gid_table_len =
2701                                                 pprops->gid_tbl_len;
2702                 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2703                             dprops->max_pkeys, pprops->gid_tbl_len);
2704         }
2705
2706 out:
2707         kfree(pprops);
2708         kfree(dprops);
2709
2710         return err;
2711 }
2712
2713 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2714 {
2715         int err;
2716
2717         err = mlx5_mr_cache_cleanup(dev);
2718         if (err)
2719                 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2720
2721         mlx5_ib_destroy_qp(dev->umrc.qp);
2722         ib_free_cq(dev->umrc.cq);
2723         ib_dealloc_pd(dev->umrc.pd);
2724 }
2725
2726 enum {
2727         MAX_UMR_WR = 128,
2728 };
2729
2730 static int create_umr_res(struct mlx5_ib_dev *dev)
2731 {
2732         struct ib_qp_init_attr *init_attr = NULL;
2733         struct ib_qp_attr *attr = NULL;
2734         struct ib_pd *pd;
2735         struct ib_cq *cq;
2736         struct ib_qp *qp;
2737         int ret;
2738
2739         attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2740         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2741         if (!attr || !init_attr) {
2742                 ret = -ENOMEM;
2743                 goto error_0;
2744         }
2745
2746         pd = ib_alloc_pd(&dev->ib_dev, 0);
2747         if (IS_ERR(pd)) {
2748                 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2749                 ret = PTR_ERR(pd);
2750                 goto error_0;
2751         }
2752
2753         cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2754         if (IS_ERR(cq)) {
2755                 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2756                 ret = PTR_ERR(cq);
2757                 goto error_2;
2758         }
2759
2760         init_attr->send_cq = cq;
2761         init_attr->recv_cq = cq;
2762         init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2763         init_attr->cap.max_send_wr = MAX_UMR_WR;
2764         init_attr->cap.max_send_sge = 1;
2765         init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2766         init_attr->port_num = 1;
2767         qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2768         if (IS_ERR(qp)) {
2769                 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2770                 ret = PTR_ERR(qp);
2771                 goto error_3;
2772         }
2773         qp->device     = &dev->ib_dev;
2774         qp->real_qp    = qp;
2775         qp->uobject    = NULL;
2776         qp->qp_type    = MLX5_IB_QPT_REG_UMR;
2777
2778         attr->qp_state = IB_QPS_INIT;
2779         attr->port_num = 1;
2780         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2781                                 IB_QP_PORT, NULL);
2782         if (ret) {
2783                 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2784                 goto error_4;
2785         }
2786
2787         memset(attr, 0, sizeof(*attr));
2788         attr->qp_state = IB_QPS_RTR;
2789         attr->path_mtu = IB_MTU_256;
2790
2791         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2792         if (ret) {
2793                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2794                 goto error_4;
2795         }
2796
2797         memset(attr, 0, sizeof(*attr));
2798         attr->qp_state = IB_QPS_RTS;
2799         ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2800         if (ret) {
2801                 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2802                 goto error_4;
2803         }
2804
2805         dev->umrc.qp = qp;
2806         dev->umrc.cq = cq;
2807         dev->umrc.pd = pd;
2808
2809         sema_init(&dev->umrc.sem, MAX_UMR_WR);
2810         ret = mlx5_mr_cache_init(dev);
2811         if (ret) {
2812                 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2813                 goto error_4;
2814         }
2815
2816         kfree(attr);
2817         kfree(init_attr);
2818
2819         return 0;
2820
2821 error_4:
2822         mlx5_ib_destroy_qp(qp);
2823
2824 error_3:
2825         ib_free_cq(cq);
2826
2827 error_2:
2828         ib_dealloc_pd(pd);
2829
2830 error_0:
2831         kfree(attr);
2832         kfree(init_attr);
2833         return ret;
2834 }
2835
2836 static int create_dev_resources(struct mlx5_ib_resources *devr)
2837 {
2838         struct ib_srq_init_attr attr;
2839         struct mlx5_ib_dev *dev;
2840         struct ib_cq_init_attr cq_attr = {.cqe = 1};
2841         int port;
2842         int ret = 0;
2843
2844         dev = container_of(devr, struct mlx5_ib_dev, devr);
2845
2846         mutex_init(&devr->mutex);
2847
2848         devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2849         if (IS_ERR(devr->p0)) {
2850                 ret = PTR_ERR(devr->p0);
2851                 goto error0;
2852         }
2853         devr->p0->device  = &dev->ib_dev;
2854         devr->p0->uobject = NULL;
2855         atomic_set(&devr->p0->usecnt, 0);
2856
2857         devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2858         if (IS_ERR(devr->c0)) {
2859                 ret = PTR_ERR(devr->c0);
2860                 goto error1;
2861         }
2862         devr->c0->device        = &dev->ib_dev;
2863         devr->c0->uobject       = NULL;
2864         devr->c0->comp_handler  = NULL;
2865         devr->c0->event_handler = NULL;
2866         devr->c0->cq_context    = NULL;
2867         atomic_set(&devr->c0->usecnt, 0);
2868
2869         devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2870         if (IS_ERR(devr->x0)) {
2871                 ret = PTR_ERR(devr->x0);
2872                 goto error2;
2873         }
2874         devr->x0->device = &dev->ib_dev;
2875         devr->x0->inode = NULL;
2876         atomic_set(&devr->x0->usecnt, 0);
2877         mutex_init(&devr->x0->tgt_qp_mutex);
2878         INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2879
2880         devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2881         if (IS_ERR(devr->x1)) {
2882                 ret = PTR_ERR(devr->x1);
2883                 goto error3;
2884         }
2885         devr->x1->device = &dev->ib_dev;
2886         devr->x1->inode = NULL;
2887         atomic_set(&devr->x1->usecnt, 0);
2888         mutex_init(&devr->x1->tgt_qp_mutex);
2889         INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2890
2891         memset(&attr, 0, sizeof(attr));
2892         attr.attr.max_sge = 1;
2893         attr.attr.max_wr = 1;
2894         attr.srq_type = IB_SRQT_XRC;
2895         attr.ext.xrc.cq = devr->c0;
2896         attr.ext.xrc.xrcd = devr->x0;
2897
2898         devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2899         if (IS_ERR(devr->s0)) {
2900                 ret = PTR_ERR(devr->s0);
2901                 goto error4;
2902         }
2903         devr->s0->device        = &dev->ib_dev;
2904         devr->s0->pd            = devr->p0;
2905         devr->s0->uobject       = NULL;
2906         devr->s0->event_handler = NULL;
2907         devr->s0->srq_context   = NULL;
2908         devr->s0->srq_type      = IB_SRQT_XRC;
2909         devr->s0->ext.xrc.xrcd  = devr->x0;
2910         devr->s0->ext.xrc.cq    = devr->c0;
2911         atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2912         atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2913         atomic_inc(&devr->p0->usecnt);
2914         atomic_set(&devr->s0->usecnt, 0);
2915
2916         memset(&attr, 0, sizeof(attr));
2917         attr.attr.max_sge = 1;
2918         attr.attr.max_wr = 1;
2919         attr.srq_type = IB_SRQT_BASIC;
2920         devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2921         if (IS_ERR(devr->s1)) {
2922                 ret = PTR_ERR(devr->s1);
2923                 goto error5;
2924         }
2925         devr->s1->device        = &dev->ib_dev;
2926         devr->s1->pd            = devr->p0;
2927         devr->s1->uobject       = NULL;
2928         devr->s1->event_handler = NULL;
2929         devr->s1->srq_context   = NULL;
2930         devr->s1->srq_type      = IB_SRQT_BASIC;
2931         devr->s1->ext.xrc.cq    = devr->c0;
2932         atomic_inc(&devr->p0->usecnt);
2933         atomic_set(&devr->s0->usecnt, 0);
2934
2935         for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2936                 INIT_WORK(&devr->ports[port].pkey_change_work,
2937                           pkey_change_handler);
2938                 devr->ports[port].devr = devr;
2939         }
2940
2941         return 0;
2942
2943 error5:
2944         mlx5_ib_destroy_srq(devr->s0);
2945 error4:
2946         mlx5_ib_dealloc_xrcd(devr->x1);
2947 error3:
2948         mlx5_ib_dealloc_xrcd(devr->x0);
2949 error2:
2950         mlx5_ib_destroy_cq(devr->c0);
2951 error1:
2952         mlx5_ib_dealloc_pd(devr->p0);
2953 error0:
2954         return ret;
2955 }
2956
2957 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2958 {
2959         struct mlx5_ib_dev *dev =
2960                 container_of(devr, struct mlx5_ib_dev, devr);
2961         int port;
2962
2963         mlx5_ib_destroy_srq(devr->s1);
2964         mlx5_ib_destroy_srq(devr->s0);
2965         mlx5_ib_dealloc_xrcd(devr->x0);
2966         mlx5_ib_dealloc_xrcd(devr->x1);
2967         mlx5_ib_destroy_cq(devr->c0);
2968         mlx5_ib_dealloc_pd(devr->p0);
2969
2970         /* Make sure no change P_Key work items are still executing */
2971         for (port = 0; port < dev->num_ports; ++port)
2972                 cancel_work_sync(&devr->ports[port].pkey_change_work);
2973 }
2974
2975 static u32 get_core_cap_flags(struct ib_device *ibdev)
2976 {
2977         struct mlx5_ib_dev *dev = to_mdev(ibdev);
2978         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2979         u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2980         u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2981         u32 ret = 0;
2982
2983         if (ll == IB_LINK_LAYER_INFINIBAND)
2984                 return RDMA_CORE_PORT_IBA_IB;
2985
2986         ret = RDMA_CORE_PORT_RAW_PACKET;
2987
2988         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2989                 return ret;
2990
2991         if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2992                 return ret;
2993
2994         if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2995                 ret |= RDMA_CORE_PORT_IBA_ROCE;
2996
2997         if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2998                 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2999
3000         return ret;
3001 }
3002
3003 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3004                                struct ib_port_immutable *immutable)
3005 {
3006         struct ib_port_attr attr;
3007         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3008         enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3009         int err;
3010
3011         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3012
3013         err = ib_query_port(ibdev, port_num, &attr);
3014         if (err)
3015                 return err;
3016
3017         immutable->pkey_tbl_len = attr.pkey_tbl_len;
3018         immutable->gid_tbl_len = attr.gid_tbl_len;
3019         immutable->core_cap_flags = get_core_cap_flags(ibdev);
3020         if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3021                 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3022
3023         return 0;
3024 }
3025
3026 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3027                            size_t str_len)
3028 {
3029         struct mlx5_ib_dev *dev =
3030                 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3031         snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3032                        fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3033 }
3034
3035 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3036 {
3037         struct mlx5_core_dev *mdev = dev->mdev;
3038         struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3039                                                                  MLX5_FLOW_NAMESPACE_LAG);
3040         struct mlx5_flow_table *ft;
3041         int err;
3042
3043         if (!ns || !mlx5_lag_is_active(mdev))
3044                 return 0;
3045
3046         err = mlx5_cmd_create_vport_lag(mdev);
3047         if (err)
3048                 return err;
3049
3050         ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3051         if (IS_ERR(ft)) {
3052                 err = PTR_ERR(ft);
3053                 goto err_destroy_vport_lag;
3054         }
3055
3056         dev->flow_db.lag_demux_ft = ft;
3057         return 0;
3058
3059 err_destroy_vport_lag:
3060         mlx5_cmd_destroy_vport_lag(mdev);
3061         return err;
3062 }
3063
3064 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3065 {
3066         struct mlx5_core_dev *mdev = dev->mdev;
3067
3068         if (dev->flow_db.lag_demux_ft) {
3069                 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3070                 dev->flow_db.lag_demux_ft = NULL;
3071
3072                 mlx5_cmd_destroy_vport_lag(mdev);
3073         }
3074 }
3075
3076 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3077 {
3078         int err;
3079
3080         dev->roce.nb.notifier_call = mlx5_netdev_event;
3081         err = register_netdevice_notifier(&dev->roce.nb);
3082         if (err) {
3083                 dev->roce.nb.notifier_call = NULL;
3084                 return err;
3085         }
3086
3087         return 0;
3088 }
3089
3090 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3091 {
3092         if (dev->roce.nb.notifier_call) {
3093                 unregister_netdevice_notifier(&dev->roce.nb);
3094                 dev->roce.nb.notifier_call = NULL;
3095         }
3096 }
3097
3098 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3099 {
3100         int err;
3101
3102         err = mlx5_add_netdev_notifier(dev);
3103         if (err)
3104                 return err;
3105
3106         if (MLX5_CAP_GEN(dev->mdev, roce)) {
3107                 err = mlx5_nic_vport_enable_roce(dev->mdev);
3108                 if (err)
3109                         goto err_unregister_netdevice_notifier;
3110         }
3111
3112         err = mlx5_eth_lag_init(dev);
3113         if (err)
3114                 goto err_disable_roce;
3115
3116         return 0;
3117
3118 err_disable_roce:
3119         if (MLX5_CAP_GEN(dev->mdev, roce))
3120                 mlx5_nic_vport_disable_roce(dev->mdev);
3121
3122 err_unregister_netdevice_notifier:
3123         mlx5_remove_netdev_notifier(dev);
3124         return err;
3125 }
3126
3127 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3128 {
3129         mlx5_eth_lag_cleanup(dev);
3130         if (MLX5_CAP_GEN(dev->mdev, roce))
3131                 mlx5_nic_vport_disable_roce(dev->mdev);
3132 }
3133
3134 struct mlx5_ib_q_counter {
3135         const char *name;
3136         size_t offset;
3137 };
3138
3139 #define INIT_Q_COUNTER(_name)           \
3140         { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3141
3142 static const struct mlx5_ib_q_counter basic_q_cnts[] = {
3143         INIT_Q_COUNTER(rx_write_requests),
3144         INIT_Q_COUNTER(rx_read_requests),
3145         INIT_Q_COUNTER(rx_atomic_requests),
3146         INIT_Q_COUNTER(out_of_buffer),
3147 };
3148
3149 static const struct mlx5_ib_q_counter out_of_seq_q_cnts[] = {
3150         INIT_Q_COUNTER(out_of_sequence),
3151 };
3152
3153 static const struct mlx5_ib_q_counter retrans_q_cnts[] = {
3154         INIT_Q_COUNTER(duplicate_request),
3155         INIT_Q_COUNTER(rnr_nak_retry_err),
3156         INIT_Q_COUNTER(packet_seq_err),
3157         INIT_Q_COUNTER(implied_nak_seq_err),
3158         INIT_Q_COUNTER(local_ack_timeout_err),
3159 };
3160
3161 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
3162 {
3163         unsigned int i;
3164
3165         for (i = 0; i < dev->num_ports; i++) {
3166                 mlx5_core_dealloc_q_counter(dev->mdev,
3167                                             dev->port[i].q_cnts.set_id);
3168                 kfree(dev->port[i].q_cnts.names);
3169                 kfree(dev->port[i].q_cnts.offsets);
3170         }
3171 }
3172
3173 static int __mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev,
3174                                       const char ***names,
3175                                       size_t **offsets,
3176                                       u32 *num)
3177 {
3178         u32 num_counters;
3179
3180         num_counters = ARRAY_SIZE(basic_q_cnts);
3181
3182         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3183                 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3184
3185         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3186                 num_counters += ARRAY_SIZE(retrans_q_cnts);
3187
3188         *names = kcalloc(num_counters, sizeof(**names), GFP_KERNEL);
3189         if (!*names)
3190                 return -ENOMEM;
3191
3192         *offsets = kcalloc(num_counters, sizeof(**offsets), GFP_KERNEL);
3193         if (!*offsets)
3194                 goto err_names;
3195
3196         *num = num_counters;
3197
3198         return 0;
3199
3200 err_names:
3201         kfree(*names);
3202         return -ENOMEM;
3203 }
3204
3205 static void mlx5_ib_fill_q_counters(struct mlx5_ib_dev *dev,
3206                                     const char **names,
3207                                     size_t *offsets)
3208 {
3209         int i;
3210         int j = 0;
3211
3212         for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3213                 names[j] = basic_q_cnts[i].name;
3214                 offsets[j] = basic_q_cnts[i].offset;
3215         }
3216
3217         if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3218                 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3219                         names[j] = out_of_seq_q_cnts[i].name;
3220                         offsets[j] = out_of_seq_q_cnts[i].offset;
3221                 }
3222         }
3223
3224         if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3225                 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3226                         names[j] = retrans_q_cnts[i].name;
3227                         offsets[j] = retrans_q_cnts[i].offset;
3228                 }
3229         }
3230 }
3231
3232 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
3233 {
3234         int i;
3235         int ret;
3236
3237         for (i = 0; i < dev->num_ports; i++) {
3238                 struct mlx5_ib_port *port = &dev->port[i];
3239
3240                 ret = mlx5_core_alloc_q_counter(dev->mdev,
3241                                                 &port->q_cnts.set_id);
3242                 if (ret) {
3243                         mlx5_ib_warn(dev,
3244                                      "couldn't allocate queue counter for port %d, err %d\n",
3245                                      i + 1, ret);
3246                         goto dealloc_counters;
3247                 }
3248
3249                 ret = __mlx5_ib_alloc_q_counters(dev,
3250                                                  &port->q_cnts.names,
3251                                                  &port->q_cnts.offsets,
3252                                                  &port->q_cnts.num_counters);
3253                 if (ret)
3254                         goto dealloc_counters;
3255
3256                 mlx5_ib_fill_q_counters(dev, port->q_cnts.names,
3257                                         port->q_cnts.offsets);
3258         }
3259
3260         return 0;
3261
3262 dealloc_counters:
3263         while (--i >= 0)
3264                 mlx5_core_dealloc_q_counter(dev->mdev,
3265                                             dev->port[i].q_cnts.set_id);
3266
3267         return ret;
3268 }
3269
3270 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3271                                                     u8 port_num)
3272 {
3273         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3274         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3275
3276         /* We support only per port stats */
3277         if (port_num == 0)
3278                 return NULL;
3279
3280         return rdma_alloc_hw_stats_struct(port->q_cnts.names,
3281                                           port->q_cnts.num_counters,
3282                                           RDMA_HW_STATS_DEFAULT_LIFESPAN);
3283 }
3284
3285 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3286                                 struct rdma_hw_stats *stats,
3287                                 u8 port_num, int index)
3288 {
3289         struct mlx5_ib_dev *dev = to_mdev(ibdev);
3290         struct mlx5_ib_port *port = &dev->port[port_num - 1];
3291         int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3292         void *out;
3293         __be32 val;
3294         int ret;
3295         int i;
3296
3297         if (!stats)
3298                 return -ENOSYS;
3299
3300         out = mlx5_vzalloc(outlen);
3301         if (!out)
3302                 return -ENOMEM;
3303
3304         ret = mlx5_core_query_q_counter(dev->mdev,
3305                                         port->q_cnts.set_id, 0,
3306                                         out, outlen);
3307         if (ret)
3308                 goto free;
3309
3310         for (i = 0; i < port->q_cnts.num_counters; i++) {
3311                 val = *(__be32 *)(out + port->q_cnts.offsets[i]);
3312                 stats->value[i] = (u64)be32_to_cpu(val);
3313         }
3314
3315 free:
3316         kvfree(out);
3317         return port->q_cnts.num_counters;
3318 }
3319
3320 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3321 {
3322         struct mlx5_ib_dev *dev;
3323         enum rdma_link_layer ll;
3324         int port_type_cap;
3325         const char *name;
3326         int err;
3327         int i;
3328
3329         port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3330         ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3331
3332         printk_once(KERN_INFO "%s", mlx5_version);
3333
3334         dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3335         if (!dev)
3336                 return NULL;
3337
3338         dev->mdev = mdev;
3339
3340         dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3341                             GFP_KERNEL);
3342         if (!dev->port)
3343                 goto err_dealloc;
3344
3345         rwlock_init(&dev->roce.netdev_lock);
3346         err = get_port_caps(dev);
3347         if (err)
3348                 goto err_free_port;
3349
3350         if (mlx5_use_mad_ifc(dev))
3351                 get_ext_port_caps(dev);
3352
3353         if (!mlx5_lag_is_active(mdev))
3354                 name = "mlx5_%d";
3355         else
3356                 name = "mlx5_bond_%d";
3357
3358         strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3359         dev->ib_dev.owner               = THIS_MODULE;
3360         dev->ib_dev.node_type           = RDMA_NODE_IB_CA;
3361         dev->ib_dev.local_dma_lkey      = 0 /* not supported for now */;
3362         dev->num_ports          = MLX5_CAP_GEN(mdev, num_ports);
3363         dev->ib_dev.phys_port_cnt     = dev->num_ports;
3364         dev->ib_dev.num_comp_vectors    =
3365                 dev->mdev->priv.eq_table.num_comp_vectors;
3366         dev->ib_dev.dma_device  = &mdev->pdev->dev;
3367
3368         dev->ib_dev.uverbs_abi_ver      = MLX5_IB_UVERBS_ABI_VERSION;
3369         dev->ib_dev.uverbs_cmd_mask     =
3370                 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT)         |
3371                 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE)        |
3372                 (1ull << IB_USER_VERBS_CMD_QUERY_PORT)          |
3373                 (1ull << IB_USER_VERBS_CMD_ALLOC_PD)            |
3374                 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD)          |
3375                 (1ull << IB_USER_VERBS_CMD_CREATE_AH)           |
3376                 (1ull << IB_USER_VERBS_CMD_DESTROY_AH)          |
3377                 (1ull << IB_USER_VERBS_CMD_REG_MR)              |
3378                 (1ull << IB_USER_VERBS_CMD_REREG_MR)            |
3379                 (1ull << IB_USER_VERBS_CMD_DEREG_MR)            |
3380                 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3381                 (1ull << IB_USER_VERBS_CMD_CREATE_CQ)           |
3382                 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ)           |
3383                 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ)          |
3384                 (1ull << IB_USER_VERBS_CMD_CREATE_QP)           |
3385                 (1ull << IB_USER_VERBS_CMD_MODIFY_QP)           |
3386                 (1ull << IB_USER_VERBS_CMD_QUERY_QP)            |
3387                 (1ull << IB_USER_VERBS_CMD_DESTROY_QP)          |
3388                 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST)        |
3389                 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST)        |
3390                 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ)          |
3391                 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ)          |
3392                 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ)           |
3393                 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ)         |
3394                 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ)         |
3395                 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3396         dev->ib_dev.uverbs_ex_cmd_mask =
3397                 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE)     |
3398                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ)        |
3399                 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP)        |
3400                 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3401
3402         dev->ib_dev.query_device        = mlx5_ib_query_device;
3403         dev->ib_dev.query_port          = mlx5_ib_query_port;
3404         dev->ib_dev.get_link_layer      = mlx5_ib_port_link_layer;
3405         if (ll == IB_LINK_LAYER_ETHERNET)
3406                 dev->ib_dev.get_netdev  = mlx5_ib_get_netdev;
3407         dev->ib_dev.query_gid           = mlx5_ib_query_gid;
3408         dev->ib_dev.add_gid             = mlx5_ib_add_gid;
3409         dev->ib_dev.del_gid             = mlx5_ib_del_gid;
3410         dev->ib_dev.query_pkey          = mlx5_ib_query_pkey;
3411         dev->ib_dev.modify_device       = mlx5_ib_modify_device;
3412         dev->ib_dev.modify_port         = mlx5_ib_modify_port;
3413         dev->ib_dev.alloc_ucontext      = mlx5_ib_alloc_ucontext;
3414         dev->ib_dev.dealloc_ucontext    = mlx5_ib_dealloc_ucontext;
3415         dev->ib_dev.mmap                = mlx5_ib_mmap;
3416         dev->ib_dev.alloc_pd            = mlx5_ib_alloc_pd;
3417         dev->ib_dev.dealloc_pd          = mlx5_ib_dealloc_pd;
3418         dev->ib_dev.create_ah           = mlx5_ib_create_ah;
3419         dev->ib_dev.query_ah            = mlx5_ib_query_ah;
3420         dev->ib_dev.destroy_ah          = mlx5_ib_destroy_ah;
3421         dev->ib_dev.create_srq          = mlx5_ib_create_srq;
3422         dev->ib_dev.modify_srq          = mlx5_ib_modify_srq;
3423         dev->ib_dev.query_srq           = mlx5_ib_query_srq;
3424         dev->ib_dev.destroy_srq         = mlx5_ib_destroy_srq;
3425         dev->ib_dev.post_srq_recv       = mlx5_ib_post_srq_recv;
3426         dev->ib_dev.create_qp           = mlx5_ib_create_qp;
3427         dev->ib_dev.modify_qp           = mlx5_ib_modify_qp;
3428         dev->ib_dev.query_qp            = mlx5_ib_query_qp;
3429         dev->ib_dev.destroy_qp          = mlx5_ib_destroy_qp;
3430         dev->ib_dev.post_send           = mlx5_ib_post_send;
3431         dev->ib_dev.post_recv           = mlx5_ib_post_recv;
3432         dev->ib_dev.create_cq           = mlx5_ib_create_cq;
3433         dev->ib_dev.modify_cq           = mlx5_ib_modify_cq;
3434         dev->ib_dev.resize_cq           = mlx5_ib_resize_cq;
3435         dev->ib_dev.destroy_cq          = mlx5_ib_destroy_cq;
3436         dev->ib_dev.poll_cq             = mlx5_ib_poll_cq;
3437         dev->ib_dev.req_notify_cq       = mlx5_ib_arm_cq;
3438         dev->ib_dev.get_dma_mr          = mlx5_ib_get_dma_mr;
3439         dev->ib_dev.reg_user_mr         = mlx5_ib_reg_user_mr;
3440         dev->ib_dev.rereg_user_mr       = mlx5_ib_rereg_user_mr;
3441         dev->ib_dev.dereg_mr            = mlx5_ib_dereg_mr;
3442         dev->ib_dev.attach_mcast        = mlx5_ib_mcg_attach;
3443         dev->ib_dev.detach_mcast        = mlx5_ib_mcg_detach;
3444         dev->ib_dev.process_mad         = mlx5_ib_process_mad;
3445         dev->ib_dev.alloc_mr            = mlx5_ib_alloc_mr;
3446         dev->ib_dev.map_mr_sg           = mlx5_ib_map_mr_sg;
3447         dev->ib_dev.check_mr_status     = mlx5_ib_check_mr_status;
3448         dev->ib_dev.get_port_immutable  = mlx5_port_immutable;
3449         dev->ib_dev.get_dev_fw_str      = get_dev_fw_str;
3450         if (mlx5_core_is_pf(mdev)) {
3451                 dev->ib_dev.get_vf_config       = mlx5_ib_get_vf_config;
3452                 dev->ib_dev.set_vf_link_state   = mlx5_ib_set_vf_link_state;
3453                 dev->ib_dev.get_vf_stats        = mlx5_ib_get_vf_stats;
3454                 dev->ib_dev.set_vf_guid         = mlx5_ib_set_vf_guid;
3455         }
3456
3457         dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3458
3459         mlx5_ib_internal_fill_odp_caps(dev);
3460
3461         if (MLX5_CAP_GEN(mdev, imaicl)) {
3462                 dev->ib_dev.alloc_mw            = mlx5_ib_alloc_mw;
3463                 dev->ib_dev.dealloc_mw          = mlx5_ib_dealloc_mw;
3464                 dev->ib_dev.uverbs_cmd_mask |=
3465                         (1ull << IB_USER_VERBS_CMD_ALLOC_MW)    |
3466                         (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3467         }
3468
3469         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3470                 dev->ib_dev.get_hw_stats        = mlx5_ib_get_hw_stats;
3471                 dev->ib_dev.alloc_hw_stats      = mlx5_ib_alloc_hw_stats;
3472         }
3473
3474         if (MLX5_CAP_GEN(mdev, xrc)) {
3475                 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3476                 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3477                 dev->ib_dev.uverbs_cmd_mask |=
3478                         (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3479                         (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3480         }
3481
3482         if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3483             IB_LINK_LAYER_ETHERNET) {
3484                 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3485                 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3486                 dev->ib_dev.create_wq    = mlx5_ib_create_wq;
3487                 dev->ib_dev.modify_wq    = mlx5_ib_modify_wq;
3488                 dev->ib_dev.destroy_wq   = mlx5_ib_destroy_wq;
3489                 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3490                 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3491                 dev->ib_dev.uverbs_ex_cmd_mask |=
3492                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3493                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3494                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3495                         (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3496                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3497                         (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3498                         (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3499         }
3500         err = init_node_data(dev);
3501         if (err)
3502                 goto err_free_port;
3503
3504         mutex_init(&dev->flow_db.lock);
3505         mutex_init(&dev->cap_mask_mutex);
3506         INIT_LIST_HEAD(&dev->qp_list);
3507         spin_lock_init(&dev->reset_flow_resource_lock);
3508
3509         if (ll == IB_LINK_LAYER_ETHERNET) {
3510                 err = mlx5_enable_eth(dev);
3511                 if (err)
3512                         goto err_free_port;
3513         }
3514
3515         err = create_dev_resources(&dev->devr);
3516         if (err)
3517                 goto err_disable_eth;
3518
3519         err = mlx5_ib_odp_init_one(dev);
3520         if (err)
3521                 goto err_rsrc;
3522
3523         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3524                 err = mlx5_ib_alloc_q_counters(dev);
3525                 if (err)
3526                         goto err_odp;
3527         }
3528
3529         dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3530         if (!dev->mdev->priv.uar)
3531                 goto err_q_cnt;
3532
3533         err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3534         if (err)
3535                 goto err_uar_page;
3536
3537         err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3538         if (err)
3539                 goto err_bfreg;
3540
3541         err = ib_register_device(&dev->ib_dev, NULL);
3542         if (err)
3543                 goto err_fp_bfreg;
3544
3545         err = create_umr_res(dev);
3546         if (err)
3547                 goto err_dev;
3548
3549         for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3550                 err = device_create_file(&dev->ib_dev.dev,
3551                                          mlx5_class_attributes[i]);
3552                 if (err)
3553                         goto err_umrc;
3554         }
3555
3556         dev->ib_active = true;
3557
3558         return dev;
3559
3560 err_umrc:
3561         destroy_umrc_res(dev);
3562
3563 err_dev:
3564         ib_unregister_device(&dev->ib_dev);
3565
3566 err_fp_bfreg:
3567         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3568
3569 err_bfreg:
3570         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3571
3572 err_uar_page:
3573         mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3574
3575 err_q_cnt:
3576         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3577                 mlx5_ib_dealloc_q_counters(dev);
3578
3579 err_odp:
3580         mlx5_ib_odp_remove_one(dev);
3581
3582 err_rsrc:
3583         destroy_dev_resources(&dev->devr);
3584
3585 err_disable_eth:
3586         if (ll == IB_LINK_LAYER_ETHERNET) {
3587                 mlx5_disable_eth(dev);
3588                 mlx5_remove_netdev_notifier(dev);
3589         }
3590
3591 err_free_port:
3592         kfree(dev->port);
3593
3594 err_dealloc:
3595         ib_dealloc_device((struct ib_device *)dev);
3596
3597         return NULL;
3598 }
3599
3600 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3601 {
3602         struct mlx5_ib_dev *dev = context;
3603         enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3604
3605         mlx5_remove_netdev_notifier(dev);
3606         ib_unregister_device(&dev->ib_dev);
3607         mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3608         mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3609         mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3610         if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3611                 mlx5_ib_dealloc_q_counters(dev);
3612         destroy_umrc_res(dev);
3613         mlx5_ib_odp_remove_one(dev);
3614         destroy_dev_resources(&dev->devr);
3615         if (ll == IB_LINK_LAYER_ETHERNET)
3616                 mlx5_disable_eth(dev);
3617         kfree(dev->port);
3618         ib_dealloc_device(&dev->ib_dev);
3619 }
3620
3621 static struct mlx5_interface mlx5_ib_interface = {
3622         .add            = mlx5_ib_add,
3623         .remove         = mlx5_ib_remove,
3624         .event          = mlx5_ib_event,
3625 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3626         .pfault         = mlx5_ib_pfault,
3627 #endif
3628         .protocol       = MLX5_INTERFACE_PROTOCOL_IB,
3629 };
3630
3631 static int __init mlx5_ib_init(void)
3632 {
3633         int err;
3634
3635         mlx5_ib_odp_init();
3636
3637         err = mlx5_register_interface(&mlx5_ib_interface);
3638
3639         return err;
3640 }
3641
3642 static void __exit mlx5_ib_cleanup(void)
3643 {
3644         mlx5_unregister_interface(&mlx5_ib_interface);
3645 }
3646
3647 module_init(mlx5_ib_init);
3648 module_exit(mlx5_ib_cleanup);