2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/isa/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 typedef int (*mptable_iter_func)(void *, const void *, int);
174 * this code MUST be enabled here and in mpboot.s.
175 * it follows the very early stages of AP boot by placing values in CMOS ram.
176 * it NORMALLY will never be needed and thus the primitive method for enabling.
179 #if defined(CHECK_POINTS)
180 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
181 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
183 #define CHECK_INIT(D); \
184 CHECK_WRITE(0x34, (D)); \
185 CHECK_WRITE(0x35, (D)); \
186 CHECK_WRITE(0x36, (D)); \
187 CHECK_WRITE(0x37, (D)); \
188 CHECK_WRITE(0x38, (D)); \
189 CHECK_WRITE(0x39, (D));
191 #define CHECK_PRINT(S); \
192 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
201 #else /* CHECK_POINTS */
203 #define CHECK_INIT(D)
204 #define CHECK_PRINT(S)
206 #endif /* CHECK_POINTS */
209 * Values to send to the POST hardware.
211 #define MP_BOOTADDRESS_POST 0x10
212 #define MP_PROBE_POST 0x11
213 #define MPTABLE_PASS1_POST 0x12
215 #define MP_START_POST 0x13
216 #define MP_ENABLE_POST 0x14
217 #define MPTABLE_PASS2_POST 0x15
219 #define START_ALL_APS_POST 0x16
220 #define INSTALL_AP_TRAMP_POST 0x17
221 #define START_AP_POST 0x18
223 #define MP_ANNOUNCE_POST 0x19
225 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
226 int current_postcode;
228 /** XXX FIXME: what system files declare these??? */
229 extern struct region_descriptor r_gdt, r_idt;
231 int mp_naps; /* # of Applications processors */
232 #ifdef SMP /* APIC-IO */
233 static int mp_nbusses; /* # of busses */
234 int mp_napics; /* # of IO APICs */
235 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
236 u_int32_t *io_apic_versions;
240 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
242 extern int64_t tsc_offsets[];
244 extern u_long ebda_addr;
246 #ifdef SMP /* APIC-IO */
247 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
251 * APIC ID logical/physical mapping structures.
252 * We oversize these to simplify boot-time config.
254 int cpu_num_to_apic_id[NAPICID];
255 #ifdef SMP /* APIC-IO */
256 int io_num_to_apic_id[NAPICID];
258 int apic_id_to_logical[NAPICID];
260 /* AP uses this during bootstrap. Do not staticize. */
265 * SMP page table page. Setup by locore to point to a page table
266 * page from which we allocate per-cpu privatespace areas io_apics,
270 #define IO_MAPPING_START_INDEX \
271 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
273 extern pt_entry_t *SMPpt;
275 struct pcb stoppcbs[MAXCPU];
277 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
279 static basetable_entry basetable_entry_types[] =
281 {0, 20, "Processor"},
289 * Local data and functions.
292 static u_int boot_address;
293 static u_int base_memory;
294 static int mp_finish;
296 static void mp_enable(u_int boot_addr);
298 static int mptable_iterate_entries(const mpcth_t,
299 mptable_iter_func, void *);
300 static int mptable_probe(void);
301 static int mptable_search(void);
302 static int mptable_check(vm_paddr_t);
303 static long mptable_search_sig(u_int32_t target, int count);
304 static int mptable_hyperthread_fixup(u_int, int);
305 #ifdef SMP /* APIC-IO */
306 static void mptable_pass1(struct mptable_pos *);
307 static void mptable_pass2(struct mptable_pos *);
308 static void mptable_default(int type);
309 static void mptable_fix(void);
311 static int mptable_map(struct mptable_pos *, vm_paddr_t);
312 static void mptable_unmap(struct mptable_pos *);
313 static void mptable_imcr(struct mptable_pos *);
315 static int mptable_lapic_probe(struct lapic_enumerator *);
316 static void mptable_lapic_enumerate(struct lapic_enumerator *);
317 static void mptable_lapic_default(void);
319 #ifdef SMP /* APIC-IO */
320 static void setup_apic_irq_mapping(void);
321 static int apic_int_is_bus_type(int intr, int bus_type);
323 static int start_all_aps(u_int boot_addr);
325 static void install_ap_tramp(u_int boot_addr);
327 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
328 static int smitest(void);
330 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
331 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
332 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
333 static u_int bootMP_size;
336 * Calculate usable address in base memory for AP trampoline code.
339 mp_bootaddress(u_int basemem)
341 POSTCODE(MP_BOOTADDRESS_POST);
343 base_memory = basemem;
345 bootMP_size = mptramp_end - mptramp_start;
346 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
347 if (((basemem * 1024) - boot_address) < bootMP_size)
348 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
349 /* 3 levels of page table pages */
350 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
352 return mptramp_pagetables;
361 mpfps_paddr = mptable_search();
362 if (mptable_check(mpfps_paddr))
369 * Look for an Intel MP spec table (ie, SMP capable hardware).
378 * Make sure our SMPpt[] page table is big enough to hold all the
381 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
383 POSTCODE(MP_PROBE_POST);
385 /* see if EBDA exists */
386 if (ebda_addr != 0) {
387 /* search first 1K of EBDA */
388 target = (u_int32_t)ebda_addr;
389 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
392 /* last 1K of base memory, effective 'top of base' passed in */
393 target = (u_int32_t)(base_memory - 0x400);
394 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
398 /* search the BIOS */
399 target = (u_int32_t)BIOS_BASE;
400 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
403 /* search the extended BIOS */
404 target = (u_int32_t)BIOS_BASE2;
405 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
412 struct mptable_check_cbarg {
418 mptable_check_callback(void *xarg, const void *pos, int type)
420 const struct PROCENTRY *ent;
421 struct mptable_check_cbarg *arg = xarg;
427 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
431 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
432 if (arg->found_bsp) {
433 kprintf("more than one BSP in base MP table\n");
442 mptable_check(vm_paddr_t mpfps_paddr)
444 struct mptable_pos mpt;
445 struct mptable_check_cbarg arg;
449 if (mpfps_paddr == 0)
452 error = mptable_map(&mpt, mpfps_paddr);
456 if (mpt.mp_fps->mpfb1 != 0)
464 if (cth->apic_address == 0)
467 bzero(&arg, sizeof(arg));
468 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
470 if (arg.cpu_count == 0) {
471 kprintf("MP table contains no processor entries\n");
473 } else if (!arg.found_bsp) {
474 kprintf("MP table does not contains BSP entry\n");
484 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
486 int count, total_size;
487 const void *position;
489 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
490 total_size = cth->base_table_length - sizeof(struct MPCTH);
491 position = (const uint8_t *)cth + sizeof(struct MPCTH);
492 count = cth->entry_count;
497 KKASSERT(total_size >= 0);
498 if (total_size == 0) {
499 kprintf("invalid base MP table, "
500 "entry count and length mismatch\n");
504 type = *(const uint8_t *)position;
506 case 0: /* processor_entry */
507 case 1: /* bus_entry */
508 case 2: /* io_apic_entry */
509 case 3: /* int_entry */
510 case 4: /* int_entry */
513 kprintf("unknown base MP table entry type %d\n", type);
517 if (total_size < basetable_entry_types[type].length) {
518 kprintf("invalid base MP table length, "
519 "does not contain all entries\n");
522 total_size -= basetable_entry_types[type].length;
524 error = func(arg, position, type);
528 position = (const uint8_t *)position +
529 basetable_entry_types[type].length;
536 * Startup the SMP processors.
541 POSTCODE(MP_START_POST);
542 mp_enable(boot_address);
547 * Print various information about the SMP system hardware and setup.
554 POSTCODE(MP_ANNOUNCE_POST);
556 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
557 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
558 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
559 for (x = 1; x <= mp_naps; ++x) {
560 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
561 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
564 if (apic_io_enable) {
565 for (x = 0; x < mp_napics; ++x) {
566 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
567 kprintf("napics %d versions %p address %p\n", mp_napics, io_apic_versions, io_apic_address);
568 kprintf(", version: 0x%08x", io_apic_versions[x]);
569 kprintf(", at 0x%08lx\n", io_apic_address[x]);
572 kprintf(" Warning: APIC I/O disabled\n");
577 * AP cpu's call this to sync up protected mode.
579 * WARNING! %gs is not set up on entry. This routine sets up %gs.
585 int x, myid = bootAP;
587 struct mdglobaldata *md;
588 struct privatespace *ps;
590 ps = &CPU_prvspace[myid];
592 gdt_segs[GPROC0_SEL].ssd_base =
593 (long) &ps->mdglobaldata.gd_common_tss;
594 ps->mdglobaldata.mi.gd_prvspace = ps;
596 /* We fill the 32-bit segment descriptors */
597 for (x = 0; x < NGDT; x++) {
598 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
599 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
601 /* And now a 64-bit one */
602 ssdtosyssd(&gdt_segs[GPROC0_SEL],
603 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
605 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
606 r_gdt.rd_base = (long) &gdt[myid * NGDT];
607 lgdt(&r_gdt); /* does magic intra-segment return */
609 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
610 wrmsr(MSR_FSBASE, 0); /* User value */
611 wrmsr(MSR_GSBASE, (u_int64_t)ps);
612 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
618 mdcpu->gd_currentldt = _default_ldt;
621 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
622 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
624 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
626 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
628 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
630 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
631 md->gd_common_tssd = *md->gd_tss_gdt;
633 /* double fault stack */
634 md->gd_common_tss.tss_ist1 =
635 (long)&md->mi.gd_prvspace->idlestack[
636 sizeof(md->mi.gd_prvspace->idlestack)];
641 * Set to a known state:
642 * Set by mpboot.s: CR0_PG, CR0_PE
643 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
646 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
649 /* Set up the fast syscall stuff */
650 msr = rdmsr(MSR_EFER) | EFER_SCE;
651 wrmsr(MSR_EFER, msr);
652 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
653 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
654 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
655 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
656 wrmsr(MSR_STAR, msr);
657 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
659 pmap_set_opt(); /* PSE/4MB pages, etc */
661 /* Initialize the PAT MSR. */
665 /* set up CPU registers and state */
668 /* set up SSE/NX registers */
671 /* set up FPU state on the AP */
672 npxinit(__INITIAL_NPXCW__);
674 /* disable the APIC, just to be SURE */
675 lapic->svr &= ~APIC_SVR_ENABLE;
677 /* data returned to BSP */
678 cpu_apic_versions[0] = lapic->version;
681 /*******************************************************************
682 * local functions and data
686 * start the SMP system
689 mp_enable(u_int boot_addr)
693 vm_paddr_t mpfps_paddr;
694 struct mptable_pos mpt;
696 POSTCODE(MP_ENABLE_POST);
700 mpfps_paddr = mptable_probe();
702 mptable_map(&mpt, mpfps_paddr);
706 if (apic_io_enable) {
709 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
711 mptable_map(&mpt, mpfps_paddr);
714 * Examine the MP table for needed info
721 /* Post scan cleanup */
724 setup_apic_irq_mapping();
726 /* fill the LOGICAL io_apic_versions table */
727 for (apic = 0; apic < mp_napics; ++apic) {
728 ux = io_apic_read(apic, IOAPIC_VER);
729 io_apic_versions[apic] = ux;
730 io_apic_set_id(apic, IO_TO_ID(apic));
733 /* program each IO APIC in the system */
734 for (apic = 0; apic < mp_napics; ++apic)
735 if (io_apic_setup(apic) < 0)
736 panic("IO APIC setup failure");
741 * These are required for SMP operation
744 /* install a 'Spurious INTerrupt' vector */
745 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
746 SDT_SYSIGT, SEL_KPL, 0);
748 /* install an inter-CPU IPI for TLB invalidation */
749 setidt(XINVLTLB_OFFSET, Xinvltlb,
750 SDT_SYSIGT, SEL_KPL, 0);
752 /* install an inter-CPU IPI for IPIQ messaging */
753 setidt(XIPIQ_OFFSET, Xipiq,
754 SDT_SYSIGT, SEL_KPL, 0);
756 /* install a timer vector */
757 setidt(XTIMER_OFFSET, Xtimer,
758 SDT_SYSIGT, SEL_KPL, 0);
760 /* install an inter-CPU IPI for CPU stop/restart */
761 setidt(XCPUSTOP_OFFSET, Xcpustop,
762 SDT_SYSIGT, SEL_KPL, 0);
764 /* start each Application Processor */
765 start_all_aps(boot_addr);
770 * look for the MP spec signature
773 /* string defined by the Intel MP Spec as identifying the MP table */
774 #define MP_SIG 0x5f504d5f /* _MP_ */
775 #define NEXT(X) ((X) += 4)
777 mptable_search_sig(u_int32_t target, int count)
783 KKASSERT(target != 0);
785 map_size = count * sizeof(u_int32_t);
786 addr = pmap_mapdev((vm_paddr_t)target, map_size);
789 for (x = 0; x < count; NEXT(x)) {
790 if (addr[x] == MP_SIG) {
791 /* make array index a byte index */
792 ret = target + (x * sizeof(u_int32_t));
797 pmap_unmapdev((vm_offset_t)addr, map_size);
802 typedef struct BUSDATA {
804 enum busTypes bus_type;
807 typedef struct INTDATA {
817 typedef struct BUSTYPENAME {
822 static bus_type_name bus_type_table[] =
828 {UNKNOWN_BUSTYPE, "---"},
831 {UNKNOWN_BUSTYPE, "---"},
832 {UNKNOWN_BUSTYPE, "---"},
833 {UNKNOWN_BUSTYPE, "---"},
834 {UNKNOWN_BUSTYPE, "---"},
835 {UNKNOWN_BUSTYPE, "---"},
837 {UNKNOWN_BUSTYPE, "---"},
838 {UNKNOWN_BUSTYPE, "---"},
839 {UNKNOWN_BUSTYPE, "---"},
840 {UNKNOWN_BUSTYPE, "---"},
842 {UNKNOWN_BUSTYPE, "---"}
845 /* from MP spec v1.4, table 5-1 */
846 static int default_data[7][5] =
848 /* nbus, id0, type0, id1, type1 */
849 {1, 0, ISA, 255, 255},
850 {1, 0, EISA, 255, 255},
851 {1, 0, EISA, 255, 255},
852 {1, 0, MCA, 255, 255},
854 {2, 0, EISA, 1, PCI},
859 static bus_datum *bus_data;
861 /* the IO INT data, one entry per possible APIC INTerrupt */
862 static io_int *io_apic_ints;
865 static int processor_entry (const struct PROCENTRY *entry, int cpu);
866 static int bus_entry (const struct BUSENTRY *entry, int bus);
867 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
868 static int int_entry (const struct INTENTRY *entry, int intr);
869 static int lookup_bus_type (char *name);
872 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
874 const struct IOAPICENTRY *ioapic_ent;
877 case 1: /* bus_entry */
881 case 2: /* io_apic_entry */
883 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
884 io_apic_address[mp_napics++] =
885 (vm_offset_t)ioapic_ent->apic_address;
889 case 3: /* int_entry */
897 * 1st pass on motherboard's Intel MP specification table.
906 mptable_pass1(struct mptable_pos *mpt)
911 POSTCODE(MPTABLE_PASS1_POST);
914 KKASSERT(fps != NULL);
916 /* clear various tables */
917 for (x = 0; x < NAPICID; ++x)
918 io_apic_address[x] = ~0; /* IO APIC address table */
924 /* check for use of 'default' configuration */
925 if (fps->mpfb1 != 0) {
926 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
927 mp_nbusses = default_data[fps->mpfb1 - 1][0];
933 error = mptable_iterate_entries(mpt->mp_cth,
934 mptable_ioapic_pass1_callback, NULL);
936 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
940 struct mptable_ioapic2_cbarg {
947 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
949 struct mptable_ioapic2_cbarg *arg = xarg;
953 if (bus_entry(pos, arg->bus))
958 if (io_apic_entry(pos, arg->apic))
963 if (int_entry(pos, arg->intr))
971 * 2nd pass on motherboard's Intel MP specification table.
974 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
975 * IO_TO_ID(N), logical IO to APIC ID table
980 mptable_pass2(struct mptable_pos *mpt)
982 struct mptable_ioapic2_cbarg arg;
986 POSTCODE(MPTABLE_PASS2_POST);
989 KKASSERT(fps != NULL);
991 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
993 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
994 M_DEVBUF, M_WAITOK | M_ZERO);
995 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
997 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
1000 kprintf("xapics %d versions %p address %p\n", mp_napics, io_apic_versions, io_apic_address);
1002 for (x = 0; x < mp_napics; x++)
1003 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
1005 /* clear various tables */
1006 for (x = 0; x < NAPICID; ++x) {
1007 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
1008 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
1011 /* clear bus data table */
1012 for (x = 0; x < mp_nbusses; ++x)
1013 bus_data[x].bus_id = 0xff;
1015 /* clear IO APIC INT table */
1016 for (x = 0; x < (nintrs + 1); ++x) {
1017 io_apic_ints[x].int_type = 0xff;
1018 io_apic_ints[x].int_vector = 0xff;
1021 /* check for use of 'default' configuration */
1022 if (fps->mpfb1 != 0) {
1023 mptable_default(fps->mpfb1);
1027 bzero(&arg, sizeof(arg));
1028 error = mptable_iterate_entries(mpt->mp_cth,
1029 mptable_ioapic_pass2_callback, &arg);
1031 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1035 * Check if we should perform a hyperthreading "fix-up" to
1036 * enumerate any logical CPU's that aren't already listed
1039 * XXX: We assume that all of the physical CPUs in the
1040 * system have the same number of logical CPUs.
1042 * XXX: We assume that APIC ID's are allocated such that
1043 * the APIC ID's for a physical processor are aligned
1044 * with the number of logical CPU's in the processor.
1047 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1049 int i, id, lcpus_max, logical_cpus;
1051 if ((cpu_feature & CPUID_HTT) == 0)
1054 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1058 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
1060 * INSTRUCTION SET REFERENCE, A-M (#253666)
1061 * Page 3-181, Table 3-20
1062 * "The nearest power-of-2 integer that is not smaller
1063 * than EBX[23:16] is the number of unique initial APIC
1064 * IDs reserved for addressing different logical
1065 * processors in a physical package."
1067 for (i = 0; ; ++i) {
1068 if ((1 << i) >= lcpus_max) {
1075 KKASSERT(cpu_count != 0);
1076 if (cpu_count == lcpus_max) {
1077 /* We have nothing to fix */
1079 } else if (cpu_count == 1) {
1080 /* XXX this may be incorrect */
1081 logical_cpus = lcpus_max;
1083 int cur, prev, dist;
1086 * Calculate the distances between two nearest
1087 * APIC IDs. If all such distances are same,
1088 * then it is the number of missing cpus that
1089 * we are going to fill later.
1091 dist = cur = prev = -1;
1092 for (id = 0; id < MAXCPU; ++id) {
1093 if ((id_mask & 1 << id) == 0)
1098 int new_dist = cur - prev;
1104 * Make sure that all distances
1105 * between two nearest APIC IDs
1108 if (dist != new_dist)
1116 /* Must be power of 2 */
1117 if (dist & (dist - 1))
1120 /* Can't exceed CPU package capacity */
1121 if (dist > lcpus_max)
1122 logical_cpus = lcpus_max;
1124 logical_cpus = dist;
1128 * For each APIC ID of a CPU that is set in the mask,
1129 * scan the other candidate APIC ID's for this
1130 * physical processor. If any of those ID's are
1131 * already in the table, then kill the fixup.
1133 for (id = 0; id < MAXCPU; id++) {
1134 if ((id_mask & 1 << id) == 0)
1136 /* First, make sure we are on a logical_cpus boundary. */
1137 if (id % logical_cpus != 0)
1139 for (i = id + 1; i < id + logical_cpus; i++)
1140 if ((id_mask & 1 << i) != 0)
1143 return logical_cpus;
1147 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1151 vm_size_t cth_mapsz = 0;
1153 bzero(mpt, sizeof(*mpt));
1155 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1156 if (fps->pap != 0) {
1158 * Map configuration table header to get
1159 * the base table size
1161 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1162 cth_mapsz = cth->base_table_length;
1163 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1165 if (cth_mapsz < sizeof(*cth)) {
1166 kprintf("invalid base MP table length %d\n",
1168 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1173 * Map the base table
1175 cth = pmap_mapdev(fps->pap, cth_mapsz);
1180 mpt->mp_cth_mapsz = cth_mapsz;
1186 mptable_unmap(struct mptable_pos *mpt)
1188 if (mpt->mp_cth != NULL) {
1189 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1191 mpt->mp_cth_mapsz = 0;
1193 if (mpt->mp_fps != NULL) {
1194 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1200 assign_apic_irq(int apic, int intpin, int irq)
1204 if (int_to_apicintpin[irq].ioapic != -1)
1205 panic("assign_apic_irq: inconsistent table");
1207 int_to_apicintpin[irq].ioapic = apic;
1208 int_to_apicintpin[irq].int_pin = intpin;
1209 int_to_apicintpin[irq].apic_address = ioapic[apic];
1210 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1212 for (x = 0; x < nintrs; x++) {
1213 if ((io_apic_ints[x].int_type == 0 ||
1214 io_apic_ints[x].int_type == 3) &&
1215 io_apic_ints[x].int_vector == 0xff &&
1216 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1217 io_apic_ints[x].dst_apic_int == intpin)
1218 io_apic_ints[x].int_vector = irq;
1223 revoke_apic_irq(int irq)
1229 if (int_to_apicintpin[irq].ioapic == -1)
1230 panic("revoke_apic_irq: inconsistent table");
1232 oldapic = int_to_apicintpin[irq].ioapic;
1233 oldintpin = int_to_apicintpin[irq].int_pin;
1235 int_to_apicintpin[irq].ioapic = -1;
1236 int_to_apicintpin[irq].int_pin = 0;
1237 int_to_apicintpin[irq].apic_address = NULL;
1238 int_to_apicintpin[irq].redirindex = 0;
1240 for (x = 0; x < nintrs; x++) {
1241 if ((io_apic_ints[x].int_type == 0 ||
1242 io_apic_ints[x].int_type == 3) &&
1243 io_apic_ints[x].int_vector != 0xff &&
1244 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1245 io_apic_ints[x].dst_apic_int == oldintpin)
1246 io_apic_ints[x].int_vector = 0xff;
1254 allocate_apic_irq(int intr)
1260 if (io_apic_ints[intr].int_vector != 0xff)
1261 return; /* Interrupt handler already assigned */
1263 if (io_apic_ints[intr].int_type != 0 &&
1264 (io_apic_ints[intr].int_type != 3 ||
1265 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1266 io_apic_ints[intr].dst_apic_int == 0)))
1267 return; /* Not INT or ExtInt on != (0, 0) */
1270 while (irq < APIC_INTMAPSIZE &&
1271 int_to_apicintpin[irq].ioapic != -1)
1274 if (irq >= APIC_INTMAPSIZE)
1275 return; /* No free interrupt handlers */
1277 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1278 intpin = io_apic_ints[intr].dst_apic_int;
1280 assign_apic_irq(apic, intpin, irq);
1285 swap_apic_id(int apic, int oldid, int newid)
1292 return; /* Nothing to do */
1294 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1295 apic, oldid, newid);
1297 /* Swap physical APIC IDs in interrupt entries */
1298 for (x = 0; x < nintrs; x++) {
1299 if (io_apic_ints[x].dst_apic_id == oldid)
1300 io_apic_ints[x].dst_apic_id = newid;
1301 else if (io_apic_ints[x].dst_apic_id == newid)
1302 io_apic_ints[x].dst_apic_id = oldid;
1305 /* Swap physical APIC IDs in IO_TO_ID mappings */
1306 for (oapic = 0; oapic < mp_napics; oapic++)
1307 if (IO_TO_ID(oapic) == newid)
1310 if (oapic < mp_napics) {
1311 kprintf("Changing APIC ID for IO APIC #%d from "
1312 "%d to %d in MP table\n",
1313 oapic, newid, oldid);
1314 IO_TO_ID(oapic) = oldid;
1316 IO_TO_ID(apic) = newid;
1321 fix_id_to_io_mapping(void)
1325 for (x = 0; x < NAPICID; x++)
1328 for (x = 0; x <= mp_naps; x++)
1329 if (CPU_TO_ID(x) < NAPICID)
1330 ID_TO_IO(CPU_TO_ID(x)) = x;
1332 for (x = 0; x < mp_napics; x++)
1333 if (IO_TO_ID(x) < NAPICID)
1334 ID_TO_IO(IO_TO_ID(x)) = x;
1339 first_free_apic_id(void)
1343 for (freeid = 0; freeid < NAPICID; freeid++) {
1344 for (x = 0; x <= mp_naps; x++)
1345 if (CPU_TO_ID(x) == freeid)
1349 for (x = 0; x < mp_napics; x++)
1350 if (IO_TO_ID(x) == freeid)
1361 io_apic_id_acceptable(int apic, int id)
1363 int cpu; /* Logical CPU number */
1364 int oapic; /* Logical IO APIC number for other IO APIC */
1367 return 0; /* Out of range */
1369 for (cpu = 0; cpu <= mp_naps; cpu++)
1370 if (CPU_TO_ID(cpu) == id)
1371 return 0; /* Conflict with CPU */
1373 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1374 if (IO_TO_ID(oapic) == id)
1375 return 0; /* Conflict with other APIC */
1377 return 1; /* ID is acceptable for IO APIC */
1382 io_apic_find_int_entry(int apic, int pin)
1386 /* search each of the possible INTerrupt sources */
1387 for (x = 0; x < nintrs; ++x) {
1388 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1389 (pin == io_apic_ints[x].dst_apic_int))
1390 return (&io_apic_ints[x]);
1396 * parse an Intel MP specification table
1403 int apic; /* IO APIC unit number */
1404 int freeid; /* Free physical APIC ID */
1405 int physid; /* Current physical IO APIC ID */
1407 int bus_0 = 0; /* Stop GCC warning */
1408 int bus_pci = 0; /* Stop GCC warning */
1412 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1413 * did it wrong. The MP spec says that when more than 1 PCI bus
1414 * exists the BIOS must begin with bus entries for the PCI bus and use
1415 * actual PCI bus numbering. This implies that when only 1 PCI bus
1416 * exists the BIOS can choose to ignore this ordering, and indeed many
1417 * MP motherboards do ignore it. This causes a problem when the PCI
1418 * sub-system makes requests of the MP sub-system based on PCI bus
1419 * numbers. So here we look for the situation and renumber the
1420 * busses and associated INTs in an effort to "make it right".
1423 /* find bus 0, PCI bus, count the number of PCI busses */
1424 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1425 if (bus_data[x].bus_id == 0) {
1428 if (bus_data[x].bus_type == PCI) {
1434 * bus_0 == slot of bus with ID of 0
1435 * bus_pci == slot of last PCI bus encountered
1438 /* check the 1 PCI bus case for sanity */
1439 /* if it is number 0 all is well */
1440 if (num_pci_bus == 1 &&
1441 bus_data[bus_pci].bus_id != 0) {
1443 /* mis-numbered, swap with whichever bus uses slot 0 */
1445 /* swap the bus entry types */
1446 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1447 bus_data[bus_0].bus_type = PCI;
1449 /* swap each relavant INTerrupt entry */
1450 id = bus_data[bus_pci].bus_id;
1451 for (x = 0; x < nintrs; ++x) {
1452 if (io_apic_ints[x].src_bus_id == id) {
1453 io_apic_ints[x].src_bus_id = 0;
1455 else if (io_apic_ints[x].src_bus_id == 0) {
1456 io_apic_ints[x].src_bus_id = id;
1461 /* Assign IO APIC IDs.
1463 * First try the existing ID. If a conflict is detected, try
1464 * the ID in the MP table. If a conflict is still detected, find
1467 * We cannot use the ID_TO_IO table before all conflicts has been
1468 * resolved and the table has been corrected.
1470 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1472 /* First try to use the value set by the BIOS */
1473 physid = io_apic_get_id(apic);
1474 if (io_apic_id_acceptable(apic, physid)) {
1475 if (IO_TO_ID(apic) != physid)
1476 swap_apic_id(apic, IO_TO_ID(apic), physid);
1480 /* Then check if the value in the MP table is acceptable */
1481 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1484 /* Last resort, find a free APIC ID and use it */
1485 freeid = first_free_apic_id();
1486 if (freeid >= NAPICID)
1487 panic("No free physical APIC IDs found");
1489 if (io_apic_id_acceptable(apic, freeid)) {
1490 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1493 panic("Free physical APIC ID not usable");
1495 fix_id_to_io_mapping();
1497 /* detect and fix broken Compaq MP table */
1498 if (apic_int_type(0, 0) == -1) {
1499 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1500 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1501 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1502 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1503 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1504 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1506 } else if (apic_int_type(0, 0) == 0) {
1507 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1508 for (x = 0; x < nintrs; ++x)
1509 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1510 (0 == io_apic_ints[x].dst_apic_int)) {
1511 io_apic_ints[x].int_type = 3;
1512 io_apic_ints[x].int_vector = 0xff;
1518 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1519 * controllers universally come in pairs. If IRQ 14 is specified
1520 * as an ISA interrupt, then IRQ 15 had better be too.
1522 * [ Shuttle XPC / AMD Athlon X2 ]
1523 * The MPTable is missing an entry for IRQ 15. Note that the
1524 * ACPI table has an entry for both 14 and 15.
1526 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1527 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1528 io14 = io_apic_find_int_entry(0, 14);
1529 io_apic_ints[nintrs] = *io14;
1530 io_apic_ints[nintrs].src_bus_irq = 15;
1531 io_apic_ints[nintrs].dst_apic_int = 15;
1536 /* Assign low level interrupt handlers */
1538 setup_apic_irq_mapping(void)
1544 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1545 int_to_apicintpin[x].ioapic = -1;
1546 int_to_apicintpin[x].int_pin = 0;
1547 int_to_apicintpin[x].apic_address = NULL;
1548 int_to_apicintpin[x].redirindex = 0;
1550 /* Default to masked */
1551 int_to_apicintpin[x].flags = AIMI_FLAG_MASKED;
1554 /* First assign ISA/EISA interrupts */
1555 for (x = 0; x < nintrs; x++) {
1556 int_vector = io_apic_ints[x].src_bus_irq;
1557 if (int_vector < APIC_INTMAPSIZE &&
1558 io_apic_ints[x].int_vector == 0xff &&
1559 int_to_apicintpin[int_vector].ioapic == -1 &&
1560 (apic_int_is_bus_type(x, ISA) ||
1561 apic_int_is_bus_type(x, EISA)) &&
1562 io_apic_ints[x].int_type == 0) {
1563 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1564 io_apic_ints[x].dst_apic_int,
1569 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1570 for (x = 0; x < nintrs; x++) {
1571 if (io_apic_ints[x].dst_apic_int == 0 &&
1572 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1573 io_apic_ints[x].int_vector == 0xff &&
1574 int_to_apicintpin[0].ioapic == -1 &&
1575 io_apic_ints[x].int_type == 3) {
1576 assign_apic_irq(0, 0, 0);
1581 /* Assign PCI interrupts */
1582 for (x = 0; x < nintrs; ++x) {
1583 if (io_apic_ints[x].int_type == 0 &&
1584 io_apic_ints[x].int_vector == 0xff &&
1585 apic_int_is_bus_type(x, PCI))
1586 allocate_apic_irq(x);
1591 mp_set_cpuids(int cpu_id, int apic_id)
1593 CPU_TO_ID(cpu_id) = apic_id;
1594 ID_TO_CPU(apic_id) = cpu_id;
1598 processor_entry(const struct PROCENTRY *entry, int cpu)
1602 /* check for usability */
1603 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1606 /* check for BSP flag */
1607 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1608 mp_set_cpuids(0, entry->apic_id);
1609 return 0; /* its already been counted */
1612 /* add another AP to list, if less than max number of CPUs */
1613 else if (cpu < MAXCPU) {
1614 mp_set_cpuids(cpu, entry->apic_id);
1622 bus_entry(const struct BUSENTRY *entry, int bus)
1627 /* encode the name into an index */
1628 for (x = 0; x < 6; ++x) {
1629 if ((c = entry->bus_type[x]) == ' ')
1635 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1636 panic("unknown bus type: '%s'", name);
1638 bus_data[bus].bus_id = entry->bus_id;
1639 bus_data[bus].bus_type = x;
1645 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1647 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1650 IO_TO_ID(apic) = entry->apic_id;
1651 ID_TO_IO(entry->apic_id) = apic;
1657 lookup_bus_type(char *name)
1661 for (x = 0; x < MAX_BUSTYPE; ++x)
1662 if (strcmp(bus_type_table[x].name, name) == 0)
1663 return bus_type_table[x].type;
1665 return UNKNOWN_BUSTYPE;
1669 int_entry(const struct INTENTRY *entry, int intr)
1673 io_apic_ints[intr].int_type = entry->int_type;
1674 io_apic_ints[intr].int_flags = entry->int_flags;
1675 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1676 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1677 if (entry->dst_apic_id == 255) {
1678 /* This signal goes to all IO APICS. Select an IO APIC
1679 with sufficient number of interrupt pins */
1680 for (apic = 0; apic < mp_napics; apic++)
1681 if (((io_apic_read(apic, IOAPIC_VER) &
1682 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1683 entry->dst_apic_int)
1685 if (apic < mp_napics)
1686 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1688 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1690 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1691 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1697 apic_int_is_bus_type(int intr, int bus_type)
1701 for (bus = 0; bus < mp_nbusses; ++bus)
1702 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1703 && ((int) bus_data[bus].bus_type == bus_type))
1710 * Given a traditional ISA INT mask, return an APIC mask.
1713 isa_apic_mask(u_int isa_mask)
1718 #if defined(SKIP_IRQ15_REDIRECT)
1719 if (isa_mask == (1 << 15)) {
1720 kprintf("skipping ISA IRQ15 redirect\n");
1723 #endif /* SKIP_IRQ15_REDIRECT */
1725 isa_irq = ffs(isa_mask); /* find its bit position */
1726 if (isa_irq == 0) /* doesn't exist */
1728 --isa_irq; /* make it zero based */
1730 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1734 return (1 << apic_pin); /* convert pin# to a mask */
1738 * Determine which APIC pin an ISA/EISA INT is attached to.
1740 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1741 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1742 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1743 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1745 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1747 isa_apic_irq(int isa_irq)
1751 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1752 if (INTTYPE(intr) == 0) { /* standard INT */
1753 if (SRCBUSIRQ(intr) == isa_irq) {
1754 if (apic_int_is_bus_type(intr, ISA) ||
1755 apic_int_is_bus_type(intr, EISA)) {
1756 if (INTIRQ(intr) == 0xff)
1757 return -1; /* unassigned */
1758 return INTIRQ(intr); /* found */
1763 return -1; /* NOT found */
1768 * Determine which APIC pin a PCI INT is attached to.
1770 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1771 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1772 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1774 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1778 --pciInt; /* zero based */
1780 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1781 if ((INTTYPE(intr) == 0) /* standard INT */
1782 && (SRCBUSID(intr) == pciBus)
1783 && (SRCBUSDEVICE(intr) == pciDevice)
1784 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1785 if (apic_int_is_bus_type(intr, PCI)) {
1786 if (INTIRQ(intr) == 0xff) {
1787 kprintf("IOAPIC: pci_apic_irq() "
1789 return -1; /* unassigned */
1791 return INTIRQ(intr); /* exact match */
1796 return -1; /* NOT found */
1800 next_apic_irq(int irq)
1807 for (intr = 0; intr < nintrs; intr++) {
1808 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1810 bus = SRCBUSID(intr);
1811 bustype = apic_bus_type(bus);
1812 if (bustype != ISA &&
1818 if (intr >= nintrs) {
1821 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1822 if (INTTYPE(ointr) != 0)
1824 if (bus != SRCBUSID(ointr))
1826 if (bustype == PCI) {
1827 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1829 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1832 if (bustype == ISA || bustype == EISA) {
1833 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1836 if (INTPIN(intr) == INTPIN(ointr))
1840 if (ointr >= nintrs) {
1843 return INTIRQ(ointr);
1856 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1859 * Exactly what this means is unclear at this point. It is a solution
1860 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1861 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1862 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1866 undirect_isa_irq(int rirq)
1870 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1871 /** FIXME: tickle the MB redirector chip */
1875 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1882 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1885 undirect_pci_irq(int rirq)
1889 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1891 /** FIXME: tickle the MB redirector chip */
1895 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1903 * given a bus ID, return:
1904 * the bus type if found
1908 apic_bus_type(int id)
1912 for (x = 0; x < mp_nbusses; ++x)
1913 if (bus_data[x].bus_id == id)
1914 return bus_data[x].bus_type;
1920 * given a LOGICAL APIC# and pin#, return:
1921 * the associated src bus ID if found
1925 apic_src_bus_id(int apic, int pin)
1929 /* search each of the possible INTerrupt sources */
1930 for (x = 0; x < nintrs; ++x)
1931 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1932 (pin == io_apic_ints[x].dst_apic_int))
1933 return (io_apic_ints[x].src_bus_id);
1935 return -1; /* NOT found */
1939 * given a LOGICAL APIC# and pin#, return:
1940 * the associated src bus IRQ if found
1944 apic_src_bus_irq(int apic, int pin)
1948 for (x = 0; x < nintrs; x++)
1949 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1950 (pin == io_apic_ints[x].dst_apic_int))
1951 return (io_apic_ints[x].src_bus_irq);
1953 return -1; /* NOT found */
1958 * given a LOGICAL APIC# and pin#, return:
1959 * the associated INTerrupt type if found
1963 apic_int_type(int apic, int pin)
1967 /* search each of the possible INTerrupt sources */
1968 for (x = 0; x < nintrs; ++x) {
1969 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1970 (pin == io_apic_ints[x].dst_apic_int))
1971 return (io_apic_ints[x].int_type);
1973 return -1; /* NOT found */
1977 * Return the IRQ associated with an APIC pin
1980 apic_irq(int apic, int pin)
1985 for (x = 0; x < nintrs; ++x) {
1986 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1987 (pin == io_apic_ints[x].dst_apic_int)) {
1988 res = io_apic_ints[x].int_vector;
1991 if (apic != int_to_apicintpin[res].ioapic)
1992 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1993 if (pin != int_to_apicintpin[res].int_pin)
1994 panic("apic_irq inconsistent table (2)");
2003 * given a LOGICAL APIC# and pin#, return:
2004 * the associated trigger mode if found
2008 apic_trigger(int apic, int pin)
2012 /* search each of the possible INTerrupt sources */
2013 for (x = 0; x < nintrs; ++x)
2014 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2015 (pin == io_apic_ints[x].dst_apic_int))
2016 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
2018 return -1; /* NOT found */
2023 * given a LOGICAL APIC# and pin#, return:
2024 * the associated 'active' level if found
2028 apic_polarity(int apic, int pin)
2032 /* search each of the possible INTerrupt sources */
2033 for (x = 0; x < nintrs; ++x)
2034 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2035 (pin == io_apic_ints[x].dst_apic_int))
2036 return (io_apic_ints[x].int_flags & 0x03);
2038 return -1; /* NOT found */
2042 * set data according to MP defaults
2043 * FIXME: probably not complete yet...
2046 mptable_default(int type)
2052 kprintf(" MP default config type: %d\n", type);
2055 kprintf(" bus: ISA, APIC: 82489DX\n");
2058 kprintf(" bus: EISA, APIC: 82489DX\n");
2061 kprintf(" bus: EISA, APIC: 82489DX\n");
2064 kprintf(" bus: MCA, APIC: 82489DX\n");
2067 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2070 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2073 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2076 kprintf(" future type\n");
2082 /* one and only IO APIC */
2083 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2086 * sanity check, refer to MP spec section 3.6.6, last paragraph
2087 * necessary as some hardware isn't properly setting up the IO APIC
2089 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2090 if (io_apic_id != 2) {
2092 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2093 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2094 io_apic_set_id(0, 2);
2097 IO_TO_ID(0) = io_apic_id;
2098 ID_TO_IO(io_apic_id) = 0;
2100 /* fill out bus entries */
2109 bus_data[0].bus_id = default_data[type - 1][1];
2110 bus_data[0].bus_type = default_data[type - 1][2];
2111 bus_data[1].bus_id = default_data[type - 1][3];
2112 bus_data[1].bus_type = default_data[type - 1][4];
2115 /* case 4: case 7: MCA NOT supported */
2116 default: /* illegal/reserved */
2117 panic("BAD default MP config: %d", type);
2121 /* general cases from MP v1.4, table 5-2 */
2122 for (pin = 0; pin < 16; ++pin) {
2123 io_apic_ints[pin].int_type = 0;
2124 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2125 io_apic_ints[pin].src_bus_id = 0;
2126 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2127 io_apic_ints[pin].dst_apic_id = io_apic_id;
2128 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2131 /* special cases from MP v1.4, table 5-2 */
2133 io_apic_ints[2].int_type = 0xff; /* N/C */
2134 io_apic_ints[13].int_type = 0xff; /* N/C */
2135 #if !defined(APIC_MIXED_MODE)
2137 panic("sorry, can't support type 2 default yet");
2138 #endif /* APIC_MIXED_MODE */
2141 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2144 io_apic_ints[0].int_type = 0xff; /* N/C */
2146 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2150 * Map a physical memory address representing I/O into KVA. The I/O
2151 * block is assumed not to cross a page boundary.
2154 permanent_io_mapping(vm_paddr_t pa)
2156 KKASSERT(pa < 0x100000000LL);
2158 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2162 * start each AP in our list
2165 start_all_aps(u_int boot_addr)
2167 vm_offset_t va = boot_address + KERNBASE;
2168 u_int64_t *pt4, *pt3, *pt2;
2174 u_char mpbiosreason;
2175 u_long mpbioswarmvec;
2176 struct mdglobaldata *gd;
2177 struct privatespace *ps;
2179 POSTCODE(START_ALL_APS_POST);
2181 /* Initialize BSP's local APIC */
2182 apic_initialize(TRUE);
2184 /* install the AP 1st level boot code */
2185 pmap_kenter(va, boot_address);
2186 cpu_invlpg((void *)va); /* JG XXX */
2187 bcopy(mptramp_start, (void *)va, bootMP_size);
2189 /* Locate the page tables, they'll be below the trampoline */
2190 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2191 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2192 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2194 /* Create the initial 1GB replicated page tables */
2195 for (i = 0; i < 512; i++) {
2196 /* Each slot of the level 4 pages points to the same level 3 page */
2197 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2198 pt4[i] |= PG_V | PG_RW | PG_U;
2200 /* Each slot of the level 3 pages points to the same level 2 page */
2201 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2202 pt3[i] |= PG_V | PG_RW | PG_U;
2204 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2205 pt2[i] = i * (2 * 1024 * 1024);
2206 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2209 /* save the current value of the warm-start vector */
2210 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2211 outb(CMOS_REG, BIOS_RESET);
2212 mpbiosreason = inb(CMOS_DATA);
2214 /* setup a vector to our boot code */
2215 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2216 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2217 outb(CMOS_REG, BIOS_RESET);
2218 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2221 * If we have a TSC we can figure out the SMI interrupt rate.
2222 * The SMI does not necessarily use a constant rate. Spend
2223 * up to 250ms trying to figure it out.
2226 if (cpu_feature & CPUID_TSC) {
2227 set_apic_timer(275000);
2228 smilast = read_apic_timer();
2229 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2230 smicount = smitest();
2231 if (smibest == 0 || smilast - smicount < smibest)
2232 smibest = smilast - smicount;
2235 if (smibest > 250000)
2238 smibest = smibest * (int64_t)1000000 /
2239 get_apic_timer_frequency();
2243 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2244 1000000 / smibest, smibest);
2247 for (x = 1; x <= mp_naps; ++x) {
2249 /* This is a bit verbose, it will go away soon. */
2251 /* first page of AP's private space */
2252 pg = x * x86_64_btop(sizeof(struct privatespace));
2254 /* allocate new private data page(s) */
2255 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2256 MDGLOBALDATA_BASEALLOC_SIZE);
2258 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2259 bzero(gd, sizeof(*gd));
2260 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2262 /* prime data page for it to use */
2263 mi_gdinit(&gd->mi, x);
2265 gd->gd_CMAP1 = &SMPpt[pg + 0];
2266 gd->gd_CMAP2 = &SMPpt[pg + 1];
2267 gd->gd_CMAP3 = &SMPpt[pg + 2];
2268 gd->gd_PMAP1 = &SMPpt[pg + 3];
2269 gd->gd_CADDR1 = ps->CPAGE1;
2270 gd->gd_CADDR2 = ps->CPAGE2;
2271 gd->gd_CADDR3 = ps->CPAGE3;
2272 gd->gd_PADDR1 = (pt_entry_t *)ps->PPAGE1;
2273 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2274 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2276 /* setup a vector to our boot code */
2277 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2278 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2279 outb(CMOS_REG, BIOS_RESET);
2280 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2283 * Setup the AP boot stack
2285 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2288 /* attempt to start the Application Processor */
2289 CHECK_INIT(99); /* setup checkpoints */
2290 if (!start_ap(gd, boot_addr, smibest)) {
2291 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2292 CHECK_PRINT("trace"); /* show checkpoints */
2293 /* better panic as the AP may be running loose */
2294 kprintf("panic y/n? [y] ");
2295 if (cngetc() != 'n')
2298 CHECK_PRINT("trace"); /* show checkpoints */
2300 /* record its version info */
2301 cpu_apic_versions[x] = cpu_apic_versions[0];
2304 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2307 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2308 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2311 ncpus2_shift = shift;
2312 ncpus2 = 1 << shift;
2313 ncpus2_mask = ncpus2 - 1;
2315 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2316 if ((1 << shift) < ncpus)
2318 ncpus_fit = 1 << shift;
2319 ncpus_fit_mask = ncpus_fit - 1;
2321 /* build our map of 'other' CPUs */
2322 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2323 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2324 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2326 /* fill in our (BSP) APIC version */
2327 cpu_apic_versions[0] = lapic->version;
2329 /* restore the warmstart vector */
2330 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2331 outb(CMOS_REG, BIOS_RESET);
2332 outb(CMOS_DATA, mpbiosreason);
2335 * NOTE! The idlestack for the BSP was setup by locore. Finish
2336 * up, clean out the P==V mapping we did earlier.
2340 /* number of APs actually started */
2346 * load the 1st level AP boot code into base memory.
2349 /* targets for relocation */
2350 extern void bigJump(void);
2351 extern void bootCodeSeg(void);
2352 extern void bootDataSeg(void);
2353 extern void MPentry(void);
2354 extern u_int MP_GDT;
2355 extern u_int mp_gdtbase;
2360 install_ap_tramp(u_int boot_addr)
2363 int size = *(int *) ((u_long) & bootMP_size);
2364 u_char *src = (u_char *) ((u_long) bootMP);
2365 u_char *dst = (u_char *) boot_addr + KERNBASE;
2366 u_int boot_base = (u_int) bootMP;
2371 POSTCODE(INSTALL_AP_TRAMP_POST);
2373 for (x = 0; x < size; ++x)
2377 * modify addresses in code we just moved to basemem. unfortunately we
2378 * need fairly detailed info about mpboot.s for this to work. changes
2379 * to mpboot.s might require changes here.
2382 /* boot code is located in KERNEL space */
2383 dst = (u_char *) boot_addr + KERNBASE;
2385 /* modify the lgdt arg */
2386 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2387 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2389 /* modify the ljmp target for MPentry() */
2390 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2391 *dst32 = ((u_int) MPentry - KERNBASE);
2393 /* modify the target for boot code segment */
2394 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2395 dst8 = (u_int8_t *) (dst16 + 1);
2396 *dst16 = (u_int) boot_addr & 0xffff;
2397 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2399 /* modify the target for boot data segment */
2400 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2401 dst8 = (u_int8_t *) (dst16 + 1);
2402 *dst16 = (u_int) boot_addr & 0xffff;
2403 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2409 * This function starts the AP (application processor) identified
2410 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2411 * to accomplish this. This is necessary because of the nuances
2412 * of the different hardware we might encounter. It ain't pretty,
2413 * but it seems to work.
2415 * NOTE: eventually an AP gets to ap_init(), which is called just
2416 * before the AP goes into the LWKT scheduler's idle loop.
2419 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2423 u_long icr_lo, icr_hi;
2425 POSTCODE(START_AP_POST);
2427 /* get the PHYSICAL APIC ID# */
2428 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2430 /* calculate the vector */
2431 vector = (boot_addr >> 12) & 0xff;
2433 /* We don't want anything interfering */
2436 /* Make sure the target cpu sees everything */
2440 * Try to detect when a SMI has occurred, wait up to 200ms.
2442 * If a SMI occurs during an AP reset but before we issue
2443 * the STARTUP command, the AP may brick. To work around
2444 * this problem we hold off doing the AP startup until
2445 * after we have detected the SMI. Hopefully another SMI
2446 * will not occur before we finish the AP startup.
2448 * Retries don't seem to help. SMIs have a window of opportunity
2449 * and if USB->legacy keyboard emulation is enabled in the BIOS
2450 * the interrupt rate can be quite high.
2452 * NOTE: Don't worry about the L1 cache load, it might bloat
2453 * ldelta a little but ndelta will be so huge when the SMI
2454 * occurs the detection logic will still work fine.
2457 set_apic_timer(200000);
2462 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2463 * and running the target CPU. OR this INIT IPI might be latched (P5
2464 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2467 * see apic/apicreg.h for icr bit definitions.
2469 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2473 * Setup the address for the target AP. We can setup
2474 * icr_hi once and then just trigger operations with
2477 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2478 icr_hi |= (physical_cpu << 24);
2479 icr_lo = lapic->icr_lo & 0xfff00000;
2480 lapic->icr_hi = icr_hi;
2483 * Do an INIT IPI: assert RESET
2485 * Use edge triggered mode to assert INIT
2487 lapic->icr_lo = icr_lo | 0x00004500;
2488 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2492 * The spec calls for a 10ms delay but we may have to use a
2493 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2494 * interrupt. We have other loops here too and dividing by 2
2495 * doesn't seem to be enough even after subtracting 350us,
2496 * so we divide by 4.
2498 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2499 * interrupt was detected we use the full 10ms.
2503 else if (smibest < 150 * 4 + 350)
2505 else if ((smibest - 350) / 4 < 10000)
2506 u_sleep((smibest - 350) / 4);
2511 * Do an INIT IPI: deassert RESET
2513 * Use level triggered mode to deassert. It is unclear
2514 * why we need to do this.
2516 lapic->icr_lo = icr_lo | 0x00008500;
2517 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2519 u_sleep(150); /* wait 150us */
2522 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2523 * latched, (P5 bug) this 1st STARTUP would then terminate
2524 * immediately, and the previously started INIT IPI would continue. OR
2525 * the previous INIT IPI has already run. and this STARTUP IPI will
2526 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2529 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2530 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2532 u_sleep(200); /* wait ~200uS */
2535 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2536 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2537 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2538 * recognized after hardware RESET or INIT IPI.
2540 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2541 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2544 /* Resume normal operation */
2547 /* wait for it to start, see ap_init() */
2548 set_apic_timer(5000000);/* == 5 seconds */
2549 while (read_apic_timer()) {
2550 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2551 return 1; /* return SUCCESS */
2554 return 0; /* return FAILURE */
2569 while (read_apic_timer()) {
2571 for (count = 0; count < 100; ++count)
2572 ntsc = rdtsc(); /* force loop to occur */
2574 ndelta = ntsc - ltsc;
2575 if (ldelta > ndelta)
2577 if (ndelta > ldelta * 2)
2580 ldelta = ntsc - ltsc;
2583 return(read_apic_timer());
2587 * Synchronously flush the TLB on all other CPU's. The current cpu's
2588 * TLB is not flushed. If the caller wishes to flush the current cpu's
2589 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2591 * NOTE: If for some reason we were unable to start all cpus we cannot
2592 * safely use broadcast IPIs.
2595 static cpumask_t smp_invltlb_req;
2597 #define SMP_INVLTLB_DEBUG
2603 struct mdglobaldata *md = mdcpu;
2604 #ifdef SMP_INVLTLB_DEBUG
2609 crit_enter_gd(&md->mi);
2610 md->gd_invltlb_ret = 0;
2611 ++md->mi.gd_cnt.v_smpinvltlb;
2612 atomic_set_int(&smp_invltlb_req, md->mi.gd_cpumask);
2613 #ifdef SMP_INVLTLB_DEBUG
2616 if (smp_startup_mask == smp_active_mask) {
2617 all_but_self_ipi(XINVLTLB_OFFSET);
2619 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2620 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2623 #ifdef SMP_INVLTLB_DEBUG
2625 kprintf("smp_invltlb: ipi sent\n");
2627 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2628 (smp_active_mask & ~md->mi.gd_cpumask)) {
2631 #ifdef SMP_INVLTLB_DEBUG
2633 if (++count == 400000000) {
2634 print_backtrace(-1);
2635 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2636 "rflags %016jx retry",
2637 (long)md->gd_invltlb_ret,
2638 (long)smp_invltlb_req,
2639 (intmax_t)read_rflags());
2640 __asm __volatile ("sti");
2643 lwkt_process_ipiq();
2645 int bcpu = bsfl(~md->gd_invltlb_ret & ~md->mi.gd_cpumask & smp_active_mask);
2648 kprintf("bcpu %d\n", bcpu);
2649 xgd = globaldata_find(bcpu);
2650 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2653 Debugger("giving up");
2659 atomic_clear_int(&smp_invltlb_req, md->mi.gd_cpumask);
2660 crit_exit_gd(&md->mi);
2667 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2668 * bother to bump the critical section count or nested interrupt count
2669 * so only do very low level operations here.
2672 smp_invltlb_intr(void)
2674 struct mdglobaldata *md = mdcpu;
2675 struct mdglobaldata *omd;
2680 mask = smp_invltlb_req;
2684 mask &= ~(1 << cpu);
2685 omd = (struct mdglobaldata *)globaldata_find(cpu);
2686 atomic_set_int(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2693 * When called the executing CPU will send an IPI to all other CPUs
2694 * requesting that they halt execution.
2696 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2698 * - Signals all CPUs in map to stop.
2699 * - Waits for each to stop.
2706 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2707 * from executing at same time.
2710 stop_cpus(u_int map)
2712 map &= smp_active_mask;
2714 /* send the Xcpustop IPI to all CPUs in map */
2715 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2717 while ((stopped_cpus & map) != map)
2725 * Called by a CPU to restart stopped CPUs.
2727 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2729 * - Signals all CPUs in map to restart.
2730 * - Waits for each to restart.
2738 restart_cpus(u_int map)
2740 /* signal other cpus to restart */
2741 started_cpus = map & smp_active_mask;
2743 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2750 * This is called once the mpboot code has gotten us properly relocated
2751 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2752 * and when it returns the scheduler will call the real cpu_idle() main
2753 * loop for the idlethread. Interrupts are disabled on entry and should
2754 * remain disabled at return.
2762 * Adjust smp_startup_mask to signal the BSP that we have started
2763 * up successfully. Note that we do not yet hold the BGL. The BSP
2764 * is waiting for our signal.
2766 * We can't set our bit in smp_active_mask yet because we are holding
2767 * interrupts physically disabled and remote cpus could deadlock
2768 * trying to send us an IPI.
2770 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2774 * Interlock for finalization. Wait until mp_finish is non-zero,
2775 * then get the MP lock.
2777 * Note: We are in a critical section.
2779 * Note: We have to synchronize td_mpcount to our desired MP state
2780 * before calling cpu_try_mplock().
2782 * Note: we are the idle thread, we can only spin.
2784 * Note: The load fence is memory volatile and prevents the compiler
2785 * from improperly caching mp_finish, and the cpu from improperly
2788 while (mp_finish == 0)
2790 ++curthread->td_mpcount;
2791 while (cpu_try_mplock() == 0)
2794 if (cpu_feature & CPUID_TSC) {
2796 * The BSP is constantly updating tsc0_offset, figure out the
2797 * relative difference to synchronize ktrdump.
2799 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2802 /* BSP may have changed PTD while we're waiting for the lock */
2805 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2809 /* Build our map of 'other' CPUs. */
2810 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2812 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2814 /* A quick check from sanity claus */
2815 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2816 if (mycpu->gd_cpuid != apic_id) {
2817 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2818 kprintf("SMP: apic_id = %d lapicid %d\n",
2819 apic_id, (lapic->id & 0xff000000) >> 24);
2821 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2823 panic("cpuid mismatch! boom!!");
2826 /* Initialize AP's local APIC for irq's */
2827 apic_initialize(FALSE);
2829 /* Set memory range attributes for this CPU to match the BSP */
2830 mem_range_AP_init();
2833 * Once we go active we must process any IPIQ messages that may
2834 * have been queued, because no actual IPI will occur until we
2835 * set our bit in the smp_active_mask. If we don't the IPI
2836 * message interlock could be left set which would also prevent
2839 * The idle loop doesn't expect the BGL to be held and while
2840 * lwkt_switch() normally cleans things up this is a special case
2841 * because we returning almost directly into the idle loop.
2843 * The idle thread is never placed on the runq, make sure
2844 * nothing we've done put it there.
2846 KKASSERT(curthread->td_mpcount == 1);
2847 smp_active_mask |= 1 << mycpu->gd_cpuid;
2850 * Enable interrupts here. idle_restore will also do it, but
2851 * doing it here lets us clean up any strays that got posted to
2852 * the CPU during the AP boot while we are still in a critical
2855 __asm __volatile("sti; pause; pause"::);
2856 mdcpu->gd_fpending = 0;
2858 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2859 lwkt_process_ipiq();
2862 * Releasing the mp lock lets the BSP finish up the SMP init
2865 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2869 * Get SMP fully working before we start initializing devices.
2877 kprintf("Finish MP startup\n");
2878 if (cpu_feature & CPUID_TSC)
2879 tsc0_offset = rdtsc();
2882 while (smp_active_mask != smp_startup_mask) {
2884 if (cpu_feature & CPUID_TSC)
2885 tsc0_offset = rdtsc();
2887 while (try_mplock() == 0)
2890 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2893 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2896 cpu_send_ipiq(int dcpu)
2898 if ((1 << dcpu) & smp_active_mask)
2899 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2902 #if 0 /* single_apic_ipi_passive() not working yet */
2904 * Returns 0 on failure, 1 on success
2907 cpu_send_ipiq_passive(int dcpu)
2910 if ((1 << dcpu) & smp_active_mask) {
2911 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2912 APIC_DELMODE_FIXED);
2918 struct mptable_lapic_cbarg1 {
2921 u_int ht_apicid_mask;
2925 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2927 const struct PROCENTRY *ent;
2928 struct mptable_lapic_cbarg1 *arg = xarg;
2934 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2938 if (ent->apic_id < 32) {
2939 arg->ht_apicid_mask |= 1 << ent->apic_id;
2940 } else if (arg->ht_fixup) {
2941 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2947 struct mptable_lapic_cbarg2 {
2954 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2956 const struct PROCENTRY *ent;
2957 struct mptable_lapic_cbarg2 *arg = xarg;
2963 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2964 KKASSERT(!arg->found_bsp);
2968 if (processor_entry(ent, arg->cpu))
2971 if (arg->logical_cpus) {
2972 struct PROCENTRY proc;
2976 * Create fake mptable processor entries
2977 * and feed them to processor_entry() to
2978 * enumerate the logical CPUs.
2980 bzero(&proc, sizeof(proc));
2982 proc.cpu_flags = PROCENTRY_FLAG_EN;
2983 proc.apic_id = ent->apic_id;
2985 for (i = 1; i < arg->logical_cpus; i++) {
2987 processor_entry(&proc, arg->cpu);
2995 mptable_imcr(struct mptable_pos *mpt)
2997 /* record whether PIC or virtual-wire mode */
2998 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2999 mpt->mp_fps->mpfb2 & 0x80);
3002 struct mptable_lapic_enumerator {
3003 struct lapic_enumerator enumerator;
3004 vm_paddr_t mpfps_paddr;
3008 mptable_lapic_default(void)
3010 int ap_apicid, bsp_apicid;
3012 mp_naps = 1; /* exclude BSP */
3014 /* Map local apic before the id field is accessed */
3015 lapic_init(DEFAULT_APIC_BASE);
3017 bsp_apicid = APIC_ID(lapic->id);
3018 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3021 mp_set_cpuids(0, bsp_apicid);
3022 /* one and only AP */
3023 mp_set_cpuids(1, ap_apicid);
3029 * ID_TO_CPU(N), APIC ID to logical CPU table
3030 * CPU_TO_ID(N), logical CPU to APIC ID table
3033 mptable_lapic_enumerate(struct lapic_enumerator *e)
3035 struct mptable_pos mpt;
3036 struct mptable_lapic_cbarg1 arg1;
3037 struct mptable_lapic_cbarg2 arg2;
3039 int error, logical_cpus = 0;
3040 vm_offset_t lapic_addr;
3041 vm_paddr_t mpfps_paddr;
3043 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
3044 KKASSERT(mpfps_paddr != 0);
3046 error = mptable_map(&mpt, mpfps_paddr);
3048 panic("mptable_lapic_enumerate mptable_map failed\n");
3050 KKASSERT(mpt.mp_fps != NULL);
3053 * Check for use of 'default' configuration
3055 if (mpt.mp_fps->mpfb1 != 0) {
3056 mptable_lapic_default();
3057 mptable_unmap(&mpt);
3062 KKASSERT(cth != NULL);
3064 /* Save local apic address */
3065 lapic_addr = (vm_offset_t)cth->apic_address;
3066 KKASSERT(lapic_addr != 0);
3069 * Find out how many CPUs do we have
3071 bzero(&arg1, sizeof(arg1));
3072 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3074 error = mptable_iterate_entries(cth,
3075 mptable_lapic_pass1_callback, &arg1);
3077 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3078 KKASSERT(arg1.cpu_count != 0);
3080 /* See if we need to fixup HT logical CPUs. */
3081 if (arg1.ht_fixup) {
3082 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3084 if (logical_cpus != 0)
3085 arg1.cpu_count *= logical_cpus;
3087 mp_naps = arg1.cpu_count;
3089 /* Qualify the numbers again, after possible HT fixup */
3090 if (mp_naps > MAXCPU) {
3091 kprintf("Warning: only using %d of %d available CPUs!\n",
3097 --mp_naps; /* subtract the BSP */
3100 * Link logical CPU id to local apic id
3102 bzero(&arg2, sizeof(arg2));
3104 arg2.logical_cpus = logical_cpus;
3106 error = mptable_iterate_entries(cth,
3107 mptable_lapic_pass2_callback, &arg2);
3109 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3110 KKASSERT(arg2.found_bsp);
3112 /* Map local apic */
3113 lapic_init(lapic_addr);
3115 mptable_unmap(&mpt);
3119 mptable_lapic_probe(struct lapic_enumerator *e)
3121 vm_paddr_t mpfps_paddr;
3123 mpfps_paddr = mptable_probe();
3124 if (mpfps_paddr == 0)
3127 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3131 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3133 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3134 .lapic_probe = mptable_lapic_probe,
3135 .lapic_enumerate = mptable_lapic_enumerate
3140 mptable_apic_register(void)
3142 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3144 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);