sys/contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c

   1 /*
   2  * Copyright (c) 2013 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
   9  * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
  10  * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
  11  * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  12  * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  13  * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  14  * PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "opt_ah.h"
  18
  19 #include "ah.h"
  20 #include "ah_internal.h"
  21 #include "ah_devid.h"
  22
  23 #include "ar9300/ar9300desc.h"
  24 #include "ar9300/ar9300.h"
  25 #include "ar9300/ar9300reg.h"
  26 #include "ar9300/ar9300phy.h"
  27 #include "ar9300/ar9300paprd.h"
  28
  29 #include "ar9300/ar9300_stub.h"
  30 #include "ar9300/ar9300_stub_funcs.h"
  31
  32
  33 /* Add static register initialization vectors */
  34 #include "ar9300/ar9300_osprey22.ini"
  35 #include "ar9300/ar9330_11.ini"
  36 #include "ar9300/ar9330_12.ini"
  37 #include "ar9300/ar9340.ini"
  38 #include "ar9300/ar9485.ini"
  39 #include "ar9300/ar9485_1_1.ini"
  40 #include "ar9300/ar9300_jupiter10.ini"
  41 #include "ar9300/ar9300_jupiter20.ini"
  42 #include "ar9300/ar9580.ini"
  43 #include "ar9300/ar955x.ini"
  44 #include "ar9300/ar9300_aphrodite10.ini"
  45
  46
  47 /* Include various freebsd specific HAL methods */
  48 #include "ar9300/ar9300_freebsd.h"
  49
  50 /* XXX duplicate in ar9300_radio.c ? */
  51 static HAL_BOOL ar9300_get_chip_power_limits(struct ath_hal *ah,
  52     struct ieee80211_channel *chan);
  53
  54 static inline HAL_STATUS ar9300_init_mac_addr(struct ath_hal *ah);
  55 static inline HAL_STATUS ar9300_hw_attach(struct ath_hal *ah);
  56 static inline void ar9300_hw_detach(struct ath_hal *ah);
  57 static int16_t ar9300_get_nf_adjust(struct ath_hal *ah,
  58     const HAL_CHANNEL_INTERNAL *c);
  59 #if 0
  60 int ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp,
  61     HAL_CAL_QUERY query);
  62 #endif
  63
  64 #if ATH_TRAFFIC_FAST_RECOVER
  65 unsigned long ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah);
  66 #endif
  67 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid);
  68
  69
  70 static void
  71 ar9300_disable_pcie_phy(struct ath_hal *ah);
  72
  73 static const HAL_PERCAL_DATA iq_cal_single_sample =
  74                           {IQ_MISMATCH_CAL,
  75                           MIN_CAL_SAMPLES,
  76                           PER_MAX_LOG_COUNT,
  77                           ar9300_iq_cal_collect,
  78                           ar9300_iq_calibration};
  79
  80 #if 0
  81 static HAL_CALIBRATION_TIMER ar9300_cals[] =
  82                           { {IQ_MISMATCH_CAL,               /* Cal type */
  83                              1200000,                       /* Cal interval */
  84                              0                              /* Cal timestamp */
  85                             },
  86                           {TEMP_COMP_CAL,
  87                              5000,
  88                              0
  89                             },
  90                           };
  91 #endif
  92
  93 #if ATH_PCIE_ERROR_MONITOR
  94
  95 int ar9300_start_pcie_error_monitor(struct ath_hal *ah, int b_auto_stop)
  96 {
  97     u_int32_t val;
  98
  99     /* Clear the counters */
 100     OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR0, 0);
 101     OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTR1, 0);
 102
 103     /* Read the previous value */
 104     val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL);
 105
 106     /* Set auto_stop */
 107     if (b_auto_stop) {
 108         val |=
 109             RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP |
 110             BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP |
 111             RPLY_NUM_RO_ERR_CTR_AUTO_STOP;
 112     } else {
 113         val &= ~(
 114             RCVD_ERR_CTR_AUTO_STOP | BAD_TLP_ERR_CTR_AUTO_STOP |
 115             BAD_DLLP_ERR_CTR_AUTO_STOP | RPLY_TO_ERR_CTR_AUTO_STOP |
 116             RPLY_NUM_RO_ERR_CTR_AUTO_STOP);
 117     }
 118     OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val );
 119
 120     /*
 121      * Start to run.
 122      * This has to be done separately from the above auto_stop flag setting,
 123      * to avoid a HW race condition.
 124      */
 125     val |=
 126         RCVD_ERR_CTR_RUN | BAD_TLP_ERR_CTR_RUN | BAD_DLLP_ERR_CTR_RUN |
 127         RPLY_TO_ERR_CTR_RUN | RPLY_NUM_RO_ERR_CTR_RUN;
 128     OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val);
 129
 130     return 0;
 131 }
 132
 133 int ar9300_read_pcie_error_monitor(struct ath_hal *ah, void* p_read_counters)
 134 {
 135     u_int32_t val;
 136     ar_pcie_error_moniter_counters *p_counters =
 137         (ar_pcie_error_moniter_counters*) p_read_counters;
 138
 139     val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR0);
 140
 141     p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK);
 142     p_counters->uc_bad_tlp_errors  = MS(val, BAD_TLP_ERR_MASK);
 143     p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK);
 144
 145     val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTR1);
 146
 147     p_counters->uc_replay_timeout_errors        = MS(val, RPLY_TO_ERR_MASK);
 148     p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK);
 149
 150     return 0;
 151 }
 152
 153 int ar9300_stop_pcie_error_monitor(struct ath_hal *ah)
 154 {
 155     u_int32_t val;
 156
 157     /* Read the previous value */
 158     val = OS_REG_READ(ah, PCIE_CO_ERR_CTR_CTRL);
 159
 160     val &= ~(
 161         RCVD_ERR_CTR_RUN |
 162         BAD_TLP_ERR_CTR_RUN |
 163         BAD_DLLP_ERR_CTR_RUN |
 164         RPLY_TO_ERR_CTR_RUN |
 165         RPLY_NUM_RO_ERR_CTR_RUN);
 166
 167     /* Start to stop */
 168     OS_REG_WRITE(ah, PCIE_CO_ERR_CTR_CTRL, val );
 169
 170     return 0;
 171 }
 172
 173 #endif /* ATH_PCIE_ERROR_MONITOR */
 174
 175 #if 0
 176 /* WIN32 does not support C99 */
 177 static const struct ath_hal_private ar9300hal = {
 178     {
 179         ar9300_get_rate_table,             /* ah_get_rate_table */
 180         ar9300_detach,                     /* ah_detach */
 181
 182         /* Reset Functions */
 183         ar9300_reset,                      /* ah_reset */
 184         ar9300_phy_disable,                /* ah_phy_disable */
 185         ar9300_disable,                    /* ah_disable */
 186         ar9300_config_pci_power_save,      /* ah_config_pci_power_save */
 187         ar9300_set_pcu_config,             /* ah_set_pcu_config */
 188         ar9300_calibration,                /* ah_per_calibration */
 189         ar9300_reset_cal_valid,            /* ah_reset_cal_valid */
 190         ar9300_set_tx_power_limit,         /* ah_set_tx_power_limit */
 191
 192 #if ATH_ANT_DIV_COMB
 193         ar9300_ant_ctrl_set_lna_div_use_bt_ant,     /* ah_ant_ctrl_set_lna_div_use_bt_ant */
 194 #endif /* ATH_ANT_DIV_COMB */
 195 #ifdef ATH_SUPPORT_DFS
 196         ar9300_radar_wait,                 /* ah_radar_wait */
 197
 198         /* New DFS functions */
 199         ar9300_check_dfs,                  /* ah_ar_check_dfs */
 200         ar9300_dfs_found,                  /* ah_ar_dfs_found */
 201         ar9300_enable_dfs,                 /* ah_ar_enable_dfs */
 202         ar9300_get_dfs_thresh,             /* ah_ar_get_dfs_thresh */
 203         ar9300_get_dfs_radars,             /* ah_ar_get_dfs_radars */
 204         ar9300_adjust_difs,                /* ah_adjust_difs */
 205         ar9300_dfs_config_fft,             /* ah_dfs_config_fft */
 206         ar9300_dfs_cac_war,                /* ah_dfs_cac_war */
 207         ar9300_cac_tx_quiet,               /* ah_cac_tx_quiet */
 208 #endif
 209         ar9300_get_extension_channel,      /* ah_get_extension_channel */
 210         ar9300_is_fast_clock_enabled,      /* ah_is_fast_clock_enabled */
 211
 212         /* Transmit functions */
 213         ar9300_update_tx_trig_level,       /* ah_update_tx_trig_level */
 214         ar9300_get_tx_trig_level,          /* ah_get_tx_trig_level */
 215         ar9300_setup_tx_queue,             /* ah_setup_tx_queue */
 216         ar9300_set_tx_queue_props,         /* ah_set_tx_queue_props */
 217         ar9300_get_tx_queue_props,         /* ah_get_tx_queue_props */
 218         ar9300_release_tx_queue,           /* ah_release_tx_queue */
 219         ar9300_reset_tx_queue,             /* ah_reset_tx_queue */
 220         ar9300_get_tx_dp,                  /* ah_get_tx_dp */
 221         ar9300_set_tx_dp,                  /* ah_set_tx_dp */
 222         ar9300_num_tx_pending,             /* ah_num_tx_pending */
 223         ar9300_start_tx_dma,               /* ah_start_tx_dma */
 224         ar9300_stop_tx_dma,                /* ah_stop_tx_dma */
 225         ar9300_stop_tx_dma_indv_que,       /* ah_stop_tx_dma_indv_que */
 226         ar9300_abort_tx_dma,               /* ah_abort_tx_dma */
 227         ar9300_fill_tx_desc,               /* ah_fill_tx_desc */
 228         ar9300_set_desc_link,              /* ah_set_desc_link */
 229         ar9300_get_desc_link_ptr,          /* ah_get_desc_link_ptr */
 230         ar9300_clear_tx_desc_status,       /* ah_clear_tx_desc_status */
 231 #ifdef ATH_SWRETRY
 232         ar9300_clear_dest_mask,            /* ah_clear_dest_mask */
 233 #endif
 234         ar9300_proc_tx_desc,               /* ah_proc_tx_desc */
 235         ar9300_get_raw_tx_desc,            /* ah_get_raw_tx_desc */
 236         ar9300_get_tx_rate_code,           /* ah_get_tx_rate_code */
 237         AH_NULL,                           /* ah_get_tx_intr_queue */
 238         ar9300_tx_req_intr_desc,           /* ah_req_tx_intr_desc */
 239         ar9300_calc_tx_airtime,            /* ah_calc_tx_airtime */
 240         ar9300_setup_tx_status_ring,       /* ah_setup_tx_status_ring */
 241
 242         /* RX Functions */
 243         ar9300_get_rx_dp,                  /* ah_get_rx_dp */
 244         ar9300_set_rx_dp,                  /* ah_set_rx_dp */
 245         ar9300_enable_receive,             /* ah_enable_receive */
 246         ar9300_stop_dma_receive,           /* ah_stop_dma_receive */
 247         ar9300_start_pcu_receive,          /* ah_start_pcu_receive */
 248         ar9300_stop_pcu_receive,           /* ah_stop_pcu_receive */
 249         ar9300_set_multicast_filter,       /* ah_set_multicast_filter */
 250         ar9300_get_rx_filter,              /* ah_get_rx_filter */
 251         ar9300_set_rx_filter,              /* ah_set_rx_filter */
 252         ar9300_set_rx_sel_evm,             /* ah_set_rx_sel_evm */
 253         ar9300_set_rx_abort,               /* ah_set_rx_abort */
 254         AH_NULL,                           /* ah_setup_rx_desc */
 255         ar9300_proc_rx_desc,               /* ah_proc_rx_desc */
 256         ar9300_get_rx_key_idx,             /* ah_get_rx_key_idx */
 257         ar9300_proc_rx_desc_fast,          /* ah_proc_rx_desc_fast */
 258         ar9300_ani_ar_poll,                /* ah_rx_monitor */
 259         ar9300_process_mib_intr,           /* ah_proc_mib_event */
 260
 261         /* Misc Functions */
 262         ar9300_get_capability,             /* ah_get_capability */
 263         ar9300_set_capability,             /* ah_set_capability */
 264         ar9300_get_diag_state,             /* ah_get_diag_state */
 265         ar9300_get_mac_address,            /* ah_get_mac_address */
 266         ar9300_set_mac_address,            /* ah_set_mac_address */
 267         ar9300_get_bss_id_mask,            /* ah_get_bss_id_mask */
 268         ar9300_set_bss_id_mask,            /* ah_set_bss_id_mask */
 269         ar9300_set_regulatory_domain,      /* ah_set_regulatory_domain */
 270         ar9300_set_led_state,              /* ah_set_led_state */
 271         ar9300_set_power_led_state,        /* ah_setpowerledstate */
 272         ar9300_set_network_led_state,      /* ah_setnetworkledstate */
 273         ar9300_write_associd,              /* ah_write_associd */
 274         ar9300_force_tsf_sync,             /* ah_force_tsf_sync */
 275         ar9300_gpio_cfg_input,             /* ah_gpio_cfg_input */
 276         ar9300_gpio_cfg_output,            /* ah_gpio_cfg_output */
 277         ar9300_gpio_cfg_output_led_off,    /* ah_gpio_cfg_output_led_off */
 278         ar9300_gpio_get,                   /* ah_gpio_get */
 279         ar9300_gpio_set,                   /* ah_gpio_set */
 280         ar9300_gpio_get_intr,              /* ah_gpio_get_intr */
 281         ar9300_gpio_set_intr,              /* ah_gpio_set_intr */
 282         ar9300_gpio_get_polarity,          /* ah_gpio_get_polarity */
 283         ar9300_gpio_set_polarity,          /* ah_gpio_set_polarity */
 284         ar9300_gpio_get_mask,              /* ah_gpio_get_mask */
 285         ar9300_gpio_set_mask,              /* ah_gpio_set_mask */
 286         ar9300_get_tsf32,                  /* ah_get_tsf32 */
 287         ar9300_get_tsf64,                  /* ah_get_tsf64 */
 288         ar9300_get_tsf2_32,                /* ah_get_tsf2_32 */
 289         ar9300_reset_tsf,                  /* ah_reset_tsf */
 290         ar9300_detect_card_present,        /* ah_detect_card_present */
 291         ar9300_update_mib_mac_stats,       /* ah_update_mib_mac_stats */
 292         ar9300_get_mib_mac_stats,          /* ah_get_mib_mac_stats */
 293         ar9300_get_rfgain,                 /* ah_get_rf_gain */
 294         ar9300_get_def_antenna,            /* ah_get_def_antenna */
 295         ar9300_set_def_antenna,            /* ah_set_def_antenna */
 296         ar9300_set_slot_time,              /* ah_set_slot_time */
 297         ar9300_set_ack_timeout,            /* ah_set_ack_timeout */
 298         ar9300_get_ack_timeout,            /* ah_get_ack_timeout */
 299         ar9300_set_coverage_class,         /* ah_set_coverage_class */
 300         ar9300_set_quiet,                  /* ah_set_quiet */
 301         ar9300_set_antenna_switch,         /* ah_set_antenna_switch */
 302         ar9300_get_desc_info,              /* ah_get_desc_info */
 303         ar9300_select_ant_config,          /* ah_select_ant_config */
 304         ar9300_ant_ctrl_common_get,        /* ah_ant_ctrl_common_get */
 305         ar9300_enable_tpc,                 /* ah_enable_tpc */
 306         AH_NULL,                           /* ah_olpc_temp_compensation */
 307 #if ATH_SUPPORT_CRDC
 308         ar9300_chain_rssi_diff_compensation,/*ah_chain_rssi_diff_compensation*/
 309 #endif
 310         ar9300_disable_phy_restart,        /* ah_disable_phy_restart */
 311         ar9300_enable_keysearch_always,
 312         ar9300_interference_is_present,    /* ah_interference_is_present */
 313         ar9300_disp_tpc_tables,             /* ah_disp_tpc_tables */
 314         ar9300_get_tpc_tables,              /* ah_get_tpc_tables */
 315         /* Key Cache Functions */
 316         ar9300_get_key_cache_size,         /* ah_get_key_cache_size */
 317         ar9300_reset_key_cache_entry,      /* ah_reset_key_cache_entry */
 318         ar9300_is_key_cache_entry_valid,   /* ah_is_key_cache_entry_valid */
 319         ar9300_set_key_cache_entry,        /* ah_set_key_cache_entry */
 320         ar9300_set_key_cache_entry_mac,    /* ah_set_key_cache_entry_mac */
 321         ar9300_print_keycache,             /* ah_print_key_cache */
 322
 323         /* Power Management Functions */
 324         ar9300_set_power_mode,             /* ah_set_power_mode */
 325         ar9300_set_sm_power_mode,          /* ah_set_sm_ps_mode */
 326 #if ATH_WOW
 327         ar9300_wow_apply_pattern,          /* ah_wow_apply_pattern */
 328         ar9300_wow_enable,                 /* ah_wow_enable */
 329         ar9300_wow_wake_up,                /* ah_wow_wake_up */
 330 #if ATH_WOW_OFFLOAD
 331         ar9300_wowoffload_prep,                 /* ah_wow_offload_prep */
 332         ar9300_wowoffload_post,                 /* ah_wow_offload_post */
 333         ar9300_wowoffload_download_rekey_data,  /* ah_wow_offload_download_rekey_data */
 334         ar9300_wowoffload_retrieve_data,        /* ah_wow_offload_retrieve_data */
 335         ar9300_wowoffload_download_acer_magic,  /* ah_wow_offload_download_acer_magic */
 336         ar9300_wowoffload_download_acer_swka,   /* ah_wow_offload_download_acer_swka */
 337         ar9300_wowoffload_download_arp_info,    /* ah_wow_offload_download_arp_info */
 338         ar9300_wowoffload_download_ns_info,     /* ah_wow_offload_download_ns_info */
 339 #endif /* ATH_WOW_OFFLOAD */
 340 #endif
 341
 342         /* Get Channel Noise */
 343         ath_hal_get_chan_noise,            /* ah_get_chan_noise */
 344         ar9300_chain_noise_floor,          /* ah_get_chain_noise_floor */
 345
 346         /* Beacon Functions */
 347         ar9300_beacon_init,                /* ah_beacon_init */
 348         ar9300_set_sta_beacon_timers,      /* ah_set_station_beacon_timers */
 349
 350         /* Interrupt Functions */
 351         ar9300_is_interrupt_pending,       /* ah_is_interrupt_pending */
 352         ar9300_get_pending_interrupts,     /* ah_get_pending_interrupts */
 353         ar9300_get_interrupts,             /* ah_get_interrupts */
 354         ar9300_set_interrupts,             /* ah_set_interrupts */
 355         ar9300_set_intr_mitigation_timer,  /* ah_set_intr_mitigation_timer */
 356         ar9300_get_intr_mitigation_timer,  /* ah_get_intr_mitigation_timer */
 357         ar9300ForceVCS,
 358         ar9300SetDfs3StreamFix,
 359         ar9300Get3StreamSignature,
 360
 361         /* 11n specific functions (NOT applicable to ar9300) */
 362         ar9300_set_11n_tx_desc,            /* ah_set_11n_tx_desc */
 363         /* Update rxchain */
 364         ar9300_set_rx_chainmask,           /*ah_set_rx_chainmask*/
 365         /*Updating locationing register */
 366         ar9300_update_loc_ctl_reg,         /*ah_update_loc_ctl_reg*/
 367         /* Start PAPRD functions  */
 368         ar9300_set_paprd_tx_desc,          /* ah_set_paprd_tx_desc */
 369         ar9300_paprd_init_table,           /* ah_paprd_init_table */
 370         ar9300_paprd_setup_gain_table,     /* ah_paprd_setup_gain_table */
 371         ar9300_paprd_create_curve,         /* ah_paprd_create_curve */
 372         ar9300_paprd_is_done,              /* ah_paprd_is_done */
 373         ar9300_enable_paprd,               /* ah_PAPRDEnable */
 374         ar9300_populate_paprd_single_table,/* ah_paprd_populate_table */
 375         ar9300_is_tx_done,                 /* ah_is_tx_done */
 376         ar9300_paprd_dec_tx_pwr,            /* ah_paprd_dec_tx_pwr*/
 377         ar9300_paprd_thermal_send,         /* ah_paprd_thermal_send */
 378         /* End PAPRD functions */
 379         ar9300_set_11n_rate_scenario,      /* ah_set_11n_rate_scenario */
 380         ar9300_set_11n_aggr_first,         /* ah_set_11n_aggr_first */
 381         ar9300_set_11n_aggr_middle,        /* ah_set_11n_aggr_middle */
 382         ar9300_set_11n_aggr_last,          /* ah_set_11n_aggr_last */
 383         ar9300_clr_11n_aggr,               /* ah_clr_11n_aggr */
 384         ar9300_set_11n_rifs_burst_middle,  /* ah_set_11n_rifs_burst_middle */
 385         ar9300_set_11n_rifs_burst_last,    /* ah_set_11n_rifs_burst_last */
 386         ar9300_clr_11n_rifs_burst,         /* ah_clr_11n_rifs_burst */
 387         ar9300_set_11n_aggr_rifs_burst,    /* ah_set_11n_aggr_rifs_burst */
 388         ar9300_set_11n_rx_rifs,            /* ah_set_11n_rx_rifs */
 389         ar9300_set_smart_antenna,             /* ah_setSmartAntenna */
 390         ar9300_detect_bb_hang,             /* ah_detect_bb_hang */
 391         ar9300_detect_mac_hang,            /* ah_detect_mac_hang */
 392         ar9300_set_immunity,               /* ah_immunity */
 393         ar9300_get_hw_hangs,               /* ah_get_hang_types */
 394         ar9300_set_11n_burst_duration,     /* ah_set_11n_burst_duration */
 395         ar9300_set_11n_virtual_more_frag,  /* ah_set_11n_virtual_more_frag */
 396         ar9300_get_11n_ext_busy,           /* ah_get_11n_ext_busy */
 397         ar9300_set_11n_mac2040,            /* ah_set_11n_mac2040 */
 398         ar9300_get_11n_rx_clear,           /* ah_get_11n_rx_clear */
 399         ar9300_set_11n_rx_clear,           /* ah_set_11n_rx_clear */
 400         ar9300_get_mib_cycle_counts_pct,   /* ah_get_mib_cycle_counts_pct */
 401         ar9300_dma_reg_dump,               /* ah_dma_reg_dump */
 402
 403         /* force_ppm specific functions */
 404         ar9300_ppm_get_rssi_dump,          /* ah_ppm_get_rssi_dump */
 405         ar9300_ppm_arm_trigger,            /* ah_ppm_arm_trigger */
 406         ar9300_ppm_get_trigger,            /* ah_ppm_get_trigger */
 407         ar9300_ppm_force,                  /* ah_ppm_force */
 408         ar9300_ppm_un_force,               /* ah_ppm_un_force */
 409         ar9300_ppm_get_force_state,        /* ah_ppm_get_force_state */
 410
 411         ar9300_get_spur_info,              /* ah_get_spur_info */
 412         ar9300_set_spur_info,              /* ah_get_spur_info */
 413
 414         ar9300_get_min_cca_pwr,            /* ah_ar_get_noise_floor_val */
 415
 416         ar9300_green_ap_ps_on_off,         /* ah_set_rx_green_ap_ps_on_off */
 417         ar9300_is_single_ant_power_save_possible, /* ah_is_single_ant_power_save_possible */
 418
 419         /* radio measurement specific functions */
 420         ar9300_get_mib_cycle_counts,       /* ah_get_mib_cycle_counts */
 421         ar9300_get_vow_stats,              /* ah_get_vow_stats */
 422         ar9300_clear_mib_counters,         /* ah_clear_mib_counters */
 423 #if ATH_GEN_RANDOMNESS
 424         ar9300_get_rssi_chain0,            /* ah_get_rssi_chain0 */
 425 #endif
 426 #ifdef ATH_BT_COEX
 427         /* Bluetooth Coexistence functions */
 428         ar9300_set_bt_coex_info,           /* ah_set_bt_coex_info */
 429         ar9300_bt_coex_config,             /* ah_bt_coex_config */
 430         ar9300_bt_coex_set_qcu_thresh,     /* ah_bt_coex_set_qcu_thresh */
 431         ar9300_bt_coex_set_weights,        /* ah_bt_coex_set_weights */
 432         ar9300_bt_coex_setup_bmiss_thresh, /* ah_bt_coex_set_bmiss_thresh */
 433         ar9300_bt_coex_set_parameter,      /* ah_bt_coex_set_parameter */
 434         ar9300_bt_coex_disable,            /* ah_bt_coex_disable */
 435         ar9300_bt_coex_enable,             /* ah_bt_coex_enable */
 436         ar9300_get_bt_active_gpio,         /* ah_bt_coex_info*/
 437         ar9300_get_wlan_active_gpio,       /* ah__coex_wlan_info*/
 438 #endif
 439         /* Generic Timer functions */
 440         ar9300_alloc_generic_timer,        /* ah_gentimer_alloc */
 441         ar9300_free_generic_timer,         /* ah_gentimer_free */
 442         ar9300_start_generic_timer,        /* ah_gentimer_start */
 443         ar9300_stop_generic_timer,         /* ah_gentimer_stop */
 444         ar9300_get_gen_timer_interrupts,   /* ah_gentimer_get_intr */
 445
 446         ar9300_set_dcs_mode,               /* ah_set_dcs_mode */
 447         ar9300_get_dcs_mode,               /* ah_get_dcs_mode */
 448
 449 #if ATH_ANT_DIV_COMB
 450         ar9300_ant_div_comb_get_config,    /* ah_get_ant_dvi_comb_conf */
 451         ar9300_ant_div_comb_set_config,    /* ah_set_ant_dvi_comb_conf */
 452 #endif
 453
 454         ar9300_get_bb_panic_info,          /* ah_get_bb_panic_info */
 455         ar9300_handle_radar_bb_panic,      /* ah_handle_radar_bb_panic */
 456         ar9300_set_hal_reset_reason,       /* ah_set_hal_reset_reason */
 457
 458 #if ATH_PCIE_ERROR_MONITOR
 459         ar9300_start_pcie_error_monitor,   /* ah_start_pcie_error_monitor */
 460         ar9300_read_pcie_error_monitor,    /* ah_read_pcie_error_monitor*/
 461         ar9300_stop_pcie_error_monitor,    /* ah_stop_pcie_error_monitor*/
 462 #endif /* ATH_PCIE_ERROR_MONITOR */
 463
 464 #if ATH_SUPPORT_SPECTRAL
 465         /* Spectral scan */
 466         ar9300_configure_spectral_scan,    /* ah_ar_configure_spectral */
 467         ar9300_get_spectral_params,        /* ah_ar_get_spectral_config */
 468         ar9300_start_spectral_scan,        /* ah_ar_start_spectral_scan */
 469         ar9300_stop_spectral_scan,         /* ah_ar_stop_spectral_scan */
 470         ar9300_is_spectral_enabled,        /* ah_ar_is_spectral_enabled */
 471         ar9300_is_spectral_active,         /* ah_ar_is_spectral_active */
 472         ar9300_get_ctl_chan_nf,            /* ah_ar_get_ctl_nf */
 473         ar9300_get_ext_chan_nf,            /* ah_ar_get_ext_nf */
 474 #endif  /*  ATH_SUPPORT_SPECTRAL */
 475
 476
 477         ar9300_promisc_mode,               /* ah_promisc_mode */
 478         ar9300_read_pktlog_reg,            /* ah_read_pktlog_reg */
 479         ar9300_write_pktlog_reg,           /* ah_write_pktlog_reg */
 480         ar9300_set_proxy_sta,              /* ah_set_proxy_sta */
 481         ar9300_get_cal_intervals,          /* ah_get_cal_intervals */
 482 #if ATH_TRAFFIC_FAST_RECOVER
 483         ar9300_get_pll3_sqsum_dvc,         /* ah_get_pll3_sqsum_dvc */
 484 #endif
 485 #ifdef ATH_SUPPORT_HTC
 486         AH_NULL,
 487 #endif
 488
 489 #ifdef ATH_TX99_DIAG
 490         /* Tx99 functions */
 491 #ifdef ATH_SUPPORT_HTC
 492         AH_NULL,
 493         AH_NULL,
 494         AH_NULL,
 495         AH_NULL,
 496         AH_NULL,
 497         AH_NULL,
 498         AH_NULL,
 499 #else
 500         AH_NULL,
 501         AH_NULL,
 502         ar9300TX99TgtChannelPwrUpdate,          /* ah_tx99channelpwrupdate */
 503         ar9300TX99TgtStart,                                     /* ah_tx99start */
 504         ar9300TX99TgtStop,                                      /* ah_tx99stop */
 505         ar9300TX99TgtChainmskSetup,                     /* ah_tx99_chainmsk_setup */
 506         ar9300TX99SetSingleCarrier,                     /* ah_tx99_set_single_carrier */
 507 #endif
 508 #endif
 509         ar9300_chk_rssi_update_tx_pwr,
 510         ar9300_is_skip_paprd_by_greentx,   /* ah_is_skip_paprd_by_greentx */
 511         ar9300_hwgreentx_set_pal_spare,    /* ah_hwgreentx_set_pal_spare */
 512 #if ATH_SUPPORT_MCI
 513         /* MCI Coexistence Functions */
 514         ar9300_mci_setup,                   /* ah_mci_setup */
 515         ar9300_mci_send_message,            /* ah_mci_send_message */
 516         ar9300_mci_get_interrupt,           /* ah_mci_get_interrupt */
 517         ar9300_mci_state,                   /* ah_mci_state */
 518         ar9300_mci_detach,                  /* ah_mci_detach */
 519 #endif
 520         ar9300_reset_hw_beacon_proc_crc,   /* ah_reset_hw_beacon_proc_crc */
 521         ar9300_get_hw_beacon_rssi,         /* ah_get_hw_beacon_rssi */
 522         ar9300_set_hw_beacon_rssi_threshold,/*ah_set_hw_beacon_rssi_threshold*/
 523         ar9300_reset_hw_beacon_rssi,       /* ah_reset_hw_beacon_rssi */
 524         ar9300_mat_enable,                 /* ah_mat_enable */
 525         ar9300_dump_keycache,              /* ah_dump_keycache */
 526         ar9300_is_ani_noise_spur,         /* ah_is_ani_noise_spur */
 527         ar9300_set_hw_beacon_proc,         /* ah_set_hw_beacon_proc */
 528     },
 529
 530     ar9300_get_channel_edges,              /* ah_get_channel_edges */
 531     ar9300_get_wireless_modes,             /* ah_get_wireless_modes */
 532     ar9300_eeprom_read_word,               /* ah_eeprom_read */
 533     AH_NULL,
 534     ar9300_eeprom_dump_support,            /* ah_eeprom_dump */
 535     ar9300_get_chip_power_limits,          /* ah_get_chip_power_limits */
 536
 537     ar9300_get_nf_adjust,                  /* ah_get_nf_adjust */
 538     /* rest is zero'd by compiler */
 539 };
 540 #endif
 541
 542 /*
 543  * Read MAC version/revision information from Chip registers and initialize
 544  * local data structures.
 545  */
 546 void
 547 ar9300_read_revisions(struct ath_hal *ah)
 548 {
 549     u_int32_t val;
 550
 551     /* XXX verify if this is the correct way to read revision on Osprey */
 552     /* new SREV format for Sowl and later */
 553     val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV));
 554
 555     if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) {
 556         /* XXX: AR_SREV register in Wasp reads 0 */
 557         AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP;
 558     } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) {
 559         /* XXX: AR_SREV register in Scorpion reads 0 */
 560        AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION;
 561     } else {
 562         /*
 563          * Include 6-bit Chip Type (masked to 0)
 564          * to differentiate from pre-Sowl versions
 565          */
 566         AH_PRIVATE(ah)->ah_macVersion =
 567             (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 568     }
 569
 570
 571
 572
 573
 574 #ifdef AH_SUPPORT_HORNET
 575     /*
 576      *  EV74984, due to Hornet 1.1 didn't update WMAC revision,
 577      *  so that have to read SoC's revision ID instead
 578      */
 579     if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_HORNET) {
 580 #define AR_SOC_RST_REVISION_ID         0xB8060090
 581 #define REG_READ(_reg)                 *((volatile u_int32_t *)(_reg))
 582         if ((REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_HORNET_11_MASK)
 583             == AR_SREV_REVISION_HORNET_11)
 584         {
 585             AH_PRIVATE(ah)->ah_macRev = AR_SREV_REVISION_HORNET_11;
 586         } else {
 587             AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2);
 588         }
 589 #undef REG_READ
 590 #undef AR_SOC_RST_REVISION_ID
 591     } else
 592 #endif
 593     if (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_WASP)
 594     {
 595 #define AR_SOC_RST_REVISION_ID         0xB8060090
 596 #define REG_READ(_reg)                 *((volatile u_int32_t *)(_reg))
 597
 598         AH_PRIVATE(ah)->ah_macRev =
 599             REG_READ(AR_SOC_RST_REVISION_ID) & AR_SREV_REVISION_WASP_MASK;
 600 #undef REG_READ
 601 #undef AR_SOC_RST_REVISION_ID
 602     }
 603     else
 604         AH_PRIVATE(ah)->ah_macRev = MS(val, AR_SREV_REVISION2);
 605
 606     if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
 607         AH_PRIVATE(ah)->ah_ispcie = AH_TRUE;
 608     }
 609     else {
 610         AH_PRIVATE(ah)->ah_ispcie =
 611             (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 612     }
 613
 614 }
 615
 616 /*
 617  * Attach for an AR9300 part.
 618  */
 619 struct ath_hal *
 620 ar9300_attach(u_int16_t devid, HAL_SOFTC sc, HAL_BUS_TAG st,
 621   HAL_BUS_HANDLE sh, uint16_t *eepromdata, HAL_OPS_CONFIG *ah_config,
 622   HAL_STATUS *status)
 623 {
 624     struct ath_hal_9300     *ahp;
 625     struct ath_hal          *ah;
 626     struct ath_hal_private  *ahpriv;
 627     HAL_STATUS              ecode;
 628
 629     HAL_NO_INTERSPERSED_READS;
 630
 631     /* NB: memory is returned zero'd */
 632     ahp = ar9300_new_state(devid, sc, st, sh, eepromdata, ah_config, status);
 633     if (ahp == AH_NULL) {
 634         return AH_NULL;
 635     }
 636     ah = &ahp->ah_priv.h;
 637     ar9300_init_offsets(ah, devid);
 638     ahpriv = AH_PRIVATE(ah);
 639 //    AH_PRIVATE(ah)->ah_bustype = bustype;
 640
 641     /* FreeBSD: to make OTP work for now, provide this.. */
 642     AH9300(ah)->ah_cal_mem = ath_hal_malloc(HOST_CALDATA_SIZE);
 643     if (AH9300(ah)->ah_cal_mem == NULL) {
 644         ath_hal_printf(ah, "%s: caldata malloc failed!\n", __func__);
 645         ecode = HAL_EIO;
 646         goto bad;
 647     }
 648
 649     /*
 650      * If eepromdata is not NULL, copy it it into ah_cal_mem.
 651      */
 652     if (eepromdata != NULL)
 653         OS_MEMCPY(AH9300(ah)->ah_cal_mem, eepromdata, HOST_CALDATA_SIZE);
 654
 655     /* XXX FreeBSD: enable RX mitigation */
 656     ah->ah_config.ath_hal_intr_mitigation_rx = 1;
 657
 658     /* interrupt mitigation */
 659 #ifdef AR5416_INT_MITIGATION
 660     if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) {
 661         ahp->ah_intr_mitigation_rx = AH_TRUE;
 662     }
 663 #else
 664     /* Enable Rx mitigation (default) */
 665     ahp->ah_intr_mitigation_rx = AH_TRUE;
 666     ah->ah_config.ath_hal_intr_mitigation_rx = 1;
 667
 668 #endif
 669 #ifdef HOST_OFFLOAD
 670     /* Reset default Rx mitigation values for Hornet */
 671     if (AR_SREV_HORNET(ah)) {
 672         ahp->ah_intr_mitigation_rx = AH_FALSE;
 673 #ifdef AR5416_INT_MITIGATION
 674         ah->ah_config.ath_hal_intr_mitigation_rx = 0;
 675 #endif
 676     }
 677 #endif
 678
 679     if (ah->ah_config.ath_hal_intr_mitigation_tx != 0) {
 680         ahp->ah_intr_mitigation_tx = AH_TRUE;
 681     }
 682
 683     /*
 684      * Read back AR_WA into a permanent copy and set bits 14 and 17.
 685      * We need to do this to avoid RMW of this register.
 686      * Do this before calling ar9300_set_reset_reg.
 687      * If not, the AR_WA register which was inited via EEPROM
 688      * will get wiped out.
 689      */
 690     ahp->ah_wa_reg_val = OS_REG_READ(ah,  AR_HOSTIF_REG(ah, AR_WA));
 691     /* Set Bits 14 and 17 in the AR_WA register. */
 692     ahp->ah_wa_reg_val |=
 693         AR_WA_D3_TO_L1_DISABLE | AR_WA_ASPM_TIMER_BASED_DISABLE;
 694
 695     if (!ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON)) {    /* reset chip */
 696         HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't reset chip\n", __func__);
 697         ecode = HAL_EIO;
 698         goto bad;
 699     }
 700
 701     if (AR_SREV_JUPITER(ah)
 702 #if ATH_WOW_OFFLOAD
 703         && !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14)
 704 #endif
 705         )
 706     {
 707         /* Jupiter doesn't need bit 14 to be set. */
 708         ahp->ah_wa_reg_val &= ~AR_WA_D3_TO_L1_DISABLE;
 709         OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val);
 710     }
 711
 712 #if ATH_SUPPORT_MCI
 713     if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
 714 #if 0
 715         ah->ah_bt_coex_set_weights = ar9300_mci_bt_coex_set_weights;
 716         ah->ah_bt_coex_disable = ar9300_mci_bt_coex_disable;
 717         ah->ah_bt_coex_enable = ar9300_mci_bt_coex_enable;
 718 #endif
 719         ahp->ah_mci_ready = AH_FALSE;
 720         ahp->ah_mci_bt_state = MCI_BT_SLEEP;
 721         ahp->ah_mci_coex_major_version_wlan = MCI_GPM_COEX_MAJOR_VERSION_WLAN;
 722         ahp->ah_mci_coex_minor_version_wlan = MCI_GPM_COEX_MINOR_VERSION_WLAN;
 723         ahp->ah_mci_coex_major_version_bt = MCI_GPM_COEX_MAJOR_VERSION_DEFAULT;
 724         ahp->ah_mci_coex_minor_version_bt = MCI_GPM_COEX_MINOR_VERSION_DEFAULT;
 725         ahp->ah_mci_coex_bt_version_known = AH_FALSE;
 726         ahp->ah_mci_coex_2g5g_update = AH_TRUE; /* track if 2g5g status sent */
 727         /* will be updated before boot up sequence */
 728         ahp->ah_mci_coex_is_2g = AH_TRUE;
 729         ahp->ah_mci_coex_wlan_channels_update = AH_FALSE;
 730         ahp->ah_mci_coex_wlan_channels[0] = 0x00000000;
 731         ahp->ah_mci_coex_wlan_channels[1] = 0xffffffff;
 732         ahp->ah_mci_coex_wlan_channels[2] = 0xffffffff;
 733         ahp->ah_mci_coex_wlan_channels[3] = 0x7fffffff;
 734         ahp->ah_mci_query_bt = AH_TRUE; /* In case WLAN start after BT */
 735         ahp->ah_mci_unhalt_bt_gpm = AH_TRUE; /* Send UNHALT at beginning */
 736         ahp->ah_mci_halted_bt_gpm = AH_FALSE; /* Allow first HALT */
 737         ahp->ah_mci_need_flush_btinfo = AH_FALSE;
 738         ahp->ah_mci_wlan_cal_seq = 0;
 739         ahp->ah_mci_wlan_cal_done = 0;
 740     }
 741 #endif /* ATH_SUPPORT_MCI */
 742
 743 #if ATH_WOW_OFFLOAD
 744     ahp->ah_mcast_filter_l32_set = 0;
 745     ahp->ah_mcast_filter_u32_set = 0;
 746 #endif
 747
 748     if (AR_SREV_HORNET(ah)) {
 749 #ifdef AH_SUPPORT_HORNET
 750         if (!AR_SREV_HORNET_11(ah)) {
 751             /*
 752              * Do not check bootstrap register, which cannot be trusted
 753              * due to s26 switch issue on CUS164/AP121.
 754              */
 755             ahp->clk_25mhz = 1;
 756             HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n");
 757         } else {
 758             /* check bootstrap clock setting */
 759 #define AR_SOC_SEL_25M_40M         0xB80600AC
 760 #define REG_WRITE(_reg, _val)    *((volatile u_int32_t *)(_reg)) = (_val);
 761 #define REG_READ(_reg)          (*((volatile u_int32_t *)(_reg)))
 762             if (REG_READ(AR_SOC_SEL_25M_40M) & 0x1) {
 763                 ahp->clk_25mhz = 0;
 764                 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
 765                     "Bootstrap clock 40MHz\n");
 766             } else {
 767                 ahp->clk_25mhz = 1;
 768                 HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
 769                     "Bootstrap clock 25MHz\n");
 770             }
 771 #undef REG_READ
 772 #undef REG_WRITE
 773 #undef AR_SOC_SEL_25M_40M
 774         }
 775 #endif /* AH_SUPPORT_HORNET */
 776     }
 777
 778     if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
 779         /* check bootstrap clock setting */
 780 #define AR9340_SOC_SEL_25M_40M         0xB80600B0
 781 #define AR9340_REF_CLK_40              (1 << 4) /* 0 - 25MHz   1 - 40 MHz */
 782 #define REG_READ(_reg)          (*((volatile u_int32_t *)(_reg)))
 783         if (REG_READ(AR9340_SOC_SEL_25M_40M) & AR9340_REF_CLK_40) {
 784             ahp->clk_25mhz = 0;
 785             HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 40MHz\n");
 786         } else {
 787             ahp->clk_25mhz = 1;
 788             HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE, "Bootstrap clock 25MHz\n");
 789         }
 790 #undef REG_READ
 791 #undef AR9340_SOC_SEL_25M_40M
 792 #undef AR9340_REF_CLK_40
 793     }
 794     ar9300_init_pll(ah, AH_NULL);
 795
 796     if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
 797         HALDEBUG(ah, HAL_DEBUG_RESET, "%s: couldn't wakeup chip\n", __func__);
 798         ecode = HAL_EIO;
 799         goto bad;
 800     }
 801
 802     /* No serialization of Register Accesses needed. */
 803     ah->ah_config.ah_serialise_reg_war = SER_REG_MODE_OFF;
 804     HALDEBUG(ah, HAL_DEBUG_RESET, "%s: ah_serialise_reg_war is %d\n",
 805              __func__, ah->ah_config.ah_serialise_reg_war);
 806
 807     /*
 808      * Add mac revision check when needed.
 809      * - Osprey 1.0 and 2.0 no longer supported.
 810      */
 811     if (((ahpriv->ah_macVersion == AR_SREV_VERSION_OSPREY) &&
 812           (ahpriv->ah_macRev <= AR_SREV_REVISION_OSPREY_20)) ||
 813         (ahpriv->ah_macVersion != AR_SREV_VERSION_OSPREY &&
 814         ahpriv->ah_macVersion != AR_SREV_VERSION_WASP &&
 815         ahpriv->ah_macVersion != AR_SREV_VERSION_HORNET &&
 816         ahpriv->ah_macVersion != AR_SREV_VERSION_POSEIDON &&
 817         ahpriv->ah_macVersion != AR_SREV_VERSION_SCORPION &&
 818         ahpriv->ah_macVersion != AR_SREV_VERSION_JUPITER &&
 819         ahpriv->ah_macVersion != AR_SREV_VERSION_APHRODITE) ) {
 820         HALDEBUG(ah, HAL_DEBUG_RESET,
 821             "%s: Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
 822             __func__,
 823             ahpriv->ah_macVersion,
 824             ahpriv->ah_macRev);
 825         ecode = HAL_ENOTSUPP;
 826         goto bad;
 827     }
 828
 829     AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
 830
 831     /* Setup supported calibrations */
 832     ahp->ah_iq_cal_data.cal_data = &iq_cal_single_sample;
 833     ahp->ah_supp_cals = IQ_MISMATCH_CAL;
 834
 835     /* Enable ANI */
 836     ahp->ah_ani_function = HAL_ANI_ALL;
 837
 838     /* Enable RIFS */
 839     ahp->ah_rifs_enabled = AH_TRUE;
 840
 841     HALDEBUG(ah, HAL_DEBUG_RESET,
 842         "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
 843         ahpriv->ah_macVersion,
 844         ahpriv->ah_macRev);
 845
 846     if (AR_SREV_HORNET_12(ah)) {
 847         /* mac */
 848         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
 849         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
 850             ar9331_hornet1_2_mac_core,
 851             ARRAY_LENGTH(ar9331_hornet1_2_mac_core), 2);
 852         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
 853             ar9331_hornet1_2_mac_postamble,
 854             ARRAY_LENGTH(ar9331_hornet1_2_mac_postamble), 5);
 855
 856         /* bb */
 857         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
 858         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
 859             ar9331_hornet1_2_baseband_core,
 860             ARRAY_LENGTH(ar9331_hornet1_2_baseband_core), 2);
 861         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
 862             ar9331_hornet1_2_baseband_postamble,
 863             ARRAY_LENGTH(ar9331_hornet1_2_baseband_postamble), 5);
 864
 865         /* radio */
 866         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
 867         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
 868             ar9331_hornet1_2_radio_core,
 869             ARRAY_LENGTH(ar9331_hornet1_2_radio_core), 2);
 870         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0);
 871
 872         /* soc */
 873         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
 874             ar9331_hornet1_2_soc_preamble,
 875             ARRAY_LENGTH(ar9331_hornet1_2_soc_preamble), 2);
 876         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
 877         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
 878             ar9331_hornet1_2_soc_postamble,
 879             ARRAY_LENGTH(ar9331_hornet1_2_soc_postamble), 2);
 880
 881         /* rx/tx gain */
 882         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
 883             ar9331_common_rx_gain_hornet1_2,
 884             ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2);
 885         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
 886             ar9331_modes_lowest_ob_db_tx_gain_hornet1_2,
 887             ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5);
 888
 889         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
 890
 891         /* Japan 2484Mhz CCK settings */
 892         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
 893             ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484,
 894             ARRAY_LENGTH(
 895                 ar9331_hornet1_2_baseband_core_txfir_coeff_japan_2484), 2);
 896
 897 #if 0 /* ATH_WOW */
 898         /* SerDes values during WOW sleep */
 899         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
 900                 ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
 901 #endif
 902
 903         /* additional clock settings */
 904         if (AH9300(ah)->clk_25mhz) {
 905             INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
 906                 ar9331_hornet1_2_xtal_25M,
 907                 ARRAY_LENGTH(ar9331_hornet1_2_xtal_25M), 2);
 908         } else {
 909             INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
 910                 ar9331_hornet1_2_xtal_40M,
 911                 ARRAY_LENGTH(ar9331_hornet1_2_xtal_40M), 2);
 912         }
 913
 914     } else if (AR_SREV_HORNET_11(ah)) {
 915         /* mac */
 916         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
 917         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
 918             ar9331_hornet1_1_mac_core,
 919             ARRAY_LENGTH(ar9331_hornet1_1_mac_core), 2);
 920         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
 921             ar9331_hornet1_1_mac_postamble,
 922             ARRAY_LENGTH(ar9331_hornet1_1_mac_postamble), 5);
 923
 924         /* bb */
 925         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
 926         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
 927             ar9331_hornet1_1_baseband_core,
 928             ARRAY_LENGTH(ar9331_hornet1_1_baseband_core), 2);
 929         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
 930             ar9331_hornet1_1_baseband_postamble,
 931             ARRAY_LENGTH(ar9331_hornet1_1_baseband_postamble), 5);
 932
 933         /* radio */
 934         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
 935         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
 936             ar9331_hornet1_1_radio_core,
 937             ARRAY_LENGTH(ar9331_hornet1_1_radio_core), 2);
 938         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST], NULL, 0, 0);
 939
 940         /* soc */
 941         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
 942             ar9331_hornet1_1_soc_preamble,
 943             ARRAY_LENGTH(ar9331_hornet1_1_soc_preamble), 2);
 944         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
 945         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
 946             ar9331_hornet1_1_soc_postamble,
 947             ARRAY_LENGTH(ar9331_hornet1_1_soc_postamble), 2);
 948
 949         /* rx/tx gain */
 950         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
 951             ar9331_common_rx_gain_hornet1_1,
 952             ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2);
 953         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
 954             ar9331_modes_lowest_ob_db_tx_gain_hornet1_1,
 955             ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5);
 956
 957         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
 958
 959         /* Japan 2484Mhz CCK settings */
 960         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
 961             ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484,
 962             ARRAY_LENGTH(
 963                 ar9331_hornet1_1_baseband_core_txfir_coeff_japan_2484), 2);
 964
 965 #if 0 /* ATH_WOW */
 966         /* SerDes values during WOW sleep */
 967         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
 968                        N(ar9300_pcie_phy_awow), 2);
 969 #endif
 970
 971         /* additional clock settings */
 972         if (AH9300(ah)->clk_25mhz) {
 973             INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
 974                 ar9331_hornet1_1_xtal_25M,
 975                 ARRAY_LENGTH(ar9331_hornet1_1_xtal_25M), 2);
 976         } else {
 977             INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
 978                 ar9331_hornet1_1_xtal_40M,
 979                 ARRAY_LENGTH(ar9331_hornet1_1_xtal_40M), 2);
 980         }
 981
 982        } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
 983         /* mac */
 984         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
 985         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
 986             ar9485_poseidon1_1_mac_core,
 987             ARRAY_LENGTH( ar9485_poseidon1_1_mac_core), 2);
 988         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
 989             ar9485_poseidon1_1_mac_postamble,
 990             ARRAY_LENGTH(ar9485_poseidon1_1_mac_postamble), 5);
 991
 992         /* bb */
 993         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE],
 994             ar9485_poseidon1_1, ARRAY_LENGTH(ar9485_poseidon1_1), 2);
 995         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
 996             ar9485_poseidon1_1_baseband_core,
 997             ARRAY_LENGTH(ar9485_poseidon1_1_baseband_core), 2);
 998         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
 999             ar9485_poseidon1_1_baseband_postamble,
1000             ARRAY_LENGTH(ar9485_poseidon1_1_baseband_postamble), 5);
1001
1002         /* radio */
1003         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1004         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1005             ar9485_poseidon1_1_radio_core,
1006             ARRAY_LENGTH(ar9485_poseidon1_1_radio_core), 2);
1007         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1008             ar9485_poseidon1_1_radio_postamble,
1009             ARRAY_LENGTH(ar9485_poseidon1_1_radio_postamble), 2);
1010
1011         /* soc */
1012         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1013             ar9485_poseidon1_1_soc_preamble,
1014             ARRAY_LENGTH(ar9485_poseidon1_1_soc_preamble), 2);
1015
1016         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1017         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0);
1018
1019         /* rx/tx gain */
1020         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1021             ar9485_common_wo_xlna_rx_gain_poseidon1_1,
1022             ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2);
1023         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1024             ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1,
1025             ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5);
1026
1027         /* Japan 2484Mhz CCK settings */
1028         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1029             ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484,
1030             ARRAY_LENGTH(
1031                 ar9485_poseidon1_1_baseband_core_txfir_coeff_japan_2484), 2);
1032
1033         /* Load PCIE SERDES settings from INI */
1034         if (ah->ah_config.ath_hal_pcie_clock_req) {
1035             /* Pci-e Clock Request = 1 */
1036             if (ah->ah_config.ath_hal_pll_pwr_save
1037                 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1038             {
1039                 /* Sleep Setting */
1040                 if (ah->ah_config.ath_hal_pll_pwr_save &
1041                     AR_PCIE_PLL_PWRSAVE_ON_D3)
1042                 {
1043                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1044                         ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1045                         ARRAY_LENGTH(
1046                            ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1047                         2);
1048                 } else {
1049                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1050                         ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1,
1051                         ARRAY_LENGTH(
1052                            ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1),
1053                         2);
1054                 }
1055                 /* Awake Setting */
1056                 if (ah->ah_config.ath_hal_pll_pwr_save &
1057                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1058                 {
1059                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1060                         ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1061                         ARRAY_LENGTH(
1062                            ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1063                         2);
1064                 } else {
1065                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1066                         ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1,
1067                         ARRAY_LENGTH(
1068                            ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_enable_L1),
1069                         2);
1070                 }
1071
1072             } else {
1073                 /*Use driver default setting*/
1074                 /* Sleep Setting */
1075                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1076                     ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1077                     ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1078                     2);
1079                 /* Awake Setting */
1080                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1081                     ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1,
1082                     ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_enable_L1),
1083                     2);
1084             }
1085         } else {
1086             /* Pci-e Clock Request = 0 */
1087             if (ah->ah_config.ath_hal_pll_pwr_save
1088                 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1089             {
1090                 /* Sleep Setting */
1091                 if (ah->ah_config.ath_hal_pll_pwr_save &
1092                     AR_PCIE_PLL_PWRSAVE_ON_D3)
1093                 {
1094                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1095                         ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1096                         ARRAY_LENGTH(
1097                           ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1098                         2);
1099                 } else {
1100                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1101                         ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1,
1102                         ARRAY_LENGTH(
1103                           ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1),
1104                         2);
1105                 }
1106                 /* Awake Setting */
1107                 if (ah->ah_config.ath_hal_pll_pwr_save &
1108                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1109                 {
1110                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1111                         ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1112                         ARRAY_LENGTH(
1113                           ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1114                         2);
1115                 } else {
1116                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1117                         ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1,
1118                         ARRAY_LENGTH(
1119                           ar9485_poseidon1_1_pcie_phy_pll_on_clkreq_disable_L1),
1120                         2);
1121                 }
1122
1123             } else {
1124                 /*Use driver default setting*/
1125                 /* Sleep Setting */
1126                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1127                     ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1128                     ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1129                     2);
1130                 /* Awake Setting */
1131                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1132                     ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1,
1133                     ARRAY_LENGTH(ar9485_poseidon1_1_pcie_phy_clkreq_disable_L1),
1134                     2);
1135             }
1136         }
1137         /* pcie ps setting will honor registry setting, default is 0 */
1138         //ah->ah_config.ath_hal_pciePowerSaveEnable = 0;
1139    } else if (AR_SREV_POSEIDON(ah)) {
1140         /* mac */
1141         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1142         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1143             ar9485_poseidon1_0_mac_core,
1144             ARRAY_LENGTH(ar9485_poseidon1_0_mac_core), 2);
1145         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1146             ar9485_poseidon1_0_mac_postamble,
1147             ARRAY_LENGTH(ar9485_poseidon1_0_mac_postamble), 5);
1148
1149         /* bb */
1150         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE],
1151             ar9485_poseidon1_0,
1152             ARRAY_LENGTH(ar9485_poseidon1_0), 2);
1153         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1154             ar9485_poseidon1_0_baseband_core,
1155             ARRAY_LENGTH(ar9485_poseidon1_0_baseband_core), 2);
1156         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1157             ar9485_poseidon1_0_baseband_postamble,
1158             ARRAY_LENGTH(ar9485_poseidon1_0_baseband_postamble), 5);
1159
1160         /* radio */
1161         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1162         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1163             ar9485_poseidon1_0_radio_core,
1164             ARRAY_LENGTH(ar9485_poseidon1_0_radio_core), 2);
1165         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1166             ar9485_poseidon1_0_radio_postamble,
1167             ARRAY_LENGTH(ar9485_poseidon1_0_radio_postamble), 2);
1168
1169         /* soc */
1170         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1171             ar9485_poseidon1_0_soc_preamble,
1172             ARRAY_LENGTH(ar9485_poseidon1_0_soc_preamble), 2);
1173         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1174         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST], NULL, 0, 0);
1175
1176         /* rx/tx gain */
1177         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1178             ar9485Common_wo_xlna_rx_gain_poseidon1_0,
1179             ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2);
1180         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1181             ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0,
1182             ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5);
1183
1184         /* Japan 2484Mhz CCK settings */
1185         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1186             ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484,
1187             ARRAY_LENGTH(
1188                 ar9485_poseidon1_0_baseband_core_txfir_coeff_japan_2484), 2);
1189
1190         /* Load PCIE SERDES settings from INI */
1191         if (ah->ah_config.ath_hal_pcie_clock_req) {
1192             /* Pci-e Clock Request = 1 */
1193             if (ah->ah_config.ath_hal_pll_pwr_save
1194                 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1195             {
1196                 /* Sleep Setting */
1197                 if (ah->ah_config.ath_hal_pll_pwr_save &
1198                     AR_PCIE_PLL_PWRSAVE_ON_D3)
1199                 {
1200                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1201                         ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1,
1202                         ARRAY_LENGTH(
1203                            ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1),
1204                         2);
1205                 } else {
1206                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1207                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1208                         ARRAY_LENGTH(
1209                            ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1210                         2);
1211                 }
1212                 /* Awake Setting */
1213                 if (ah->ah_config.ath_hal_pll_pwr_save &
1214                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1215                 {
1216                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1217                         ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1,
1218                         ARRAY_LENGTH(
1219                            ar9485_poseidon1_0_pcie_phy_clkreq_enable_L1),
1220                         2);
1221                 } else {
1222                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1223                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1224                         ARRAY_LENGTH(
1225                            ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1226                         2);
1227                 }
1228
1229             } else {
1230                 /*Use driver default setting*/
1231                 /* Sleep Setting */
1232                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1233                     ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1234                     ARRAY_LENGTH(
1235                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1236                     2);
1237                 /* Awake Setting */
1238                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1239                     ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1,
1240                     ARRAY_LENGTH(
1241                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_enable_L1),
1242                     2);
1243             }
1244         } else {
1245             /* Pci-e Clock Request = 0 */
1246             if (ah->ah_config.ath_hal_pll_pwr_save
1247                 & AR_PCIE_PLL_PWRSAVE_CONTROL)
1248             {
1249                 /* Sleep Setting */
1250                 if (ah->ah_config.ath_hal_pll_pwr_save &
1251                     AR_PCIE_PLL_PWRSAVE_ON_D3)
1252                 {
1253                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1254                         ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1,
1255                         ARRAY_LENGTH(
1256                           ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1),
1257                         2);
1258                 } else {
1259                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1260                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1261                         ARRAY_LENGTH(
1262                           ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1263                         2);
1264                 }
1265                 /* Awake Setting */
1266                 if (ah->ah_config.ath_hal_pll_pwr_save &
1267                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1268                 {
1269                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1270                         ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1,
1271                         ARRAY_LENGTH(
1272                           ar9485_poseidon1_0_pcie_phy_clkreq_disable_L1),
1273                         2);
1274                 } else {
1275                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1276                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1277                         ARRAY_LENGTH(
1278                           ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1279                         2);
1280                 }
1281
1282             } else {
1283                 /*Use driver default setting*/
1284                 /* Sleep Setting */
1285                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1286                     ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1287                     ARRAY_LENGTH(
1288                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1289                     2);
1290                 /* Awake Setting */
1291                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1292                     ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1,
1293                     ARRAY_LENGTH(
1294                         ar9485_poseidon1_0_pcie_phy_pll_on_clkreq_disable_L1),
1295                     2);
1296             }
1297         }
1298         /* pcie ps setting will honor registry setting, default is 0 */
1299         /*ah->ah_config.ath_hal_pcie_power_save_enable = 0;*/
1300
1301 #if 0 /* ATH_WOW */
1302         /* SerDes values during WOW sleep */
1303         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
1304                        ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
1305 #endif
1306
1307     } else if (AR_SREV_WASP(ah)) {
1308         /* mac */
1309         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1310         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1311             ar9340_wasp_1p0_mac_core,
1312             ARRAY_LENGTH(ar9340_wasp_1p0_mac_core), 2);
1313         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1314             ar9340_wasp_1p0_mac_postamble,
1315             ARRAY_LENGTH(ar9340_wasp_1p0_mac_postamble), 5);
1316
1317         /* bb */
1318         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1319         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1320             ar9340_wasp_1p0_baseband_core,
1321             ARRAY_LENGTH(ar9340_wasp_1p0_baseband_core), 2);
1322         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1323             ar9340_wasp_1p0_baseband_postamble,
1324             ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble), 5);
1325
1326         /* radio */
1327         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1328         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1329             ar9340_wasp_1p0_radio_core,
1330             ARRAY_LENGTH(ar9340_wasp_1p0_radio_core), 2);
1331         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1332             ar9340_wasp_1p0_radio_postamble,
1333             ARRAY_LENGTH(ar9340_wasp_1p0_radio_postamble), 5);
1334
1335         /* soc */
1336         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1337             ar9340_wasp_1p0_soc_preamble,
1338             ARRAY_LENGTH(ar9340_wasp_1p0_soc_preamble), 2);
1339         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1340         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1341             ar9340_wasp_1p0_soc_postamble,
1342             ARRAY_LENGTH(ar9340_wasp_1p0_soc_postamble), 5);
1343
1344         /* rx/tx gain */
1345         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1346             ar9340Common_wo_xlna_rx_gain_table_wasp_1p0,
1347             ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2);
1348         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1349             ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0,
1350             ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5);
1351
1352         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1353
1354         /* Fast clock modal settings */
1355         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1356             ar9340Modes_fast_clock_wasp_1p0,
1357             ARRAY_LENGTH(ar9340Modes_fast_clock_wasp_1p0), 3);
1358
1359         /* Additional setttings for 40Mhz */
1360         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40mhz,
1361             ar9340_wasp_1p0_radio_core_40M,
1362             ARRAY_LENGTH(ar9340_wasp_1p0_radio_core_40M), 2);
1363
1364         /* DFS */
1365         INIT_INI_ARRAY(&ahp->ah_ini_dfs,
1366             ar9340_wasp_1p0_baseband_postamble_dfs_channel,
1367             ARRAY_LENGTH(ar9340_wasp_1p0_baseband_postamble_dfs_channel), 3);
1368     } else if (AR_SREV_SCORPION(ah)) {
1369         /* mac */
1370         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1371         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1372                         ar955x_scorpion_1p0_mac_core,
1373                         ARRAY_LENGTH(ar955x_scorpion_1p0_mac_core), 2);
1374         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1375                         ar955x_scorpion_1p0_mac_postamble,
1376                         ARRAY_LENGTH(ar955x_scorpion_1p0_mac_postamble), 5);
1377
1378         /* bb */
1379         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1380         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1381                         ar955x_scorpion_1p0_baseband_core,
1382                         ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_core), 2);
1383         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1384                         ar955x_scorpion_1p0_baseband_postamble,
1385                         ARRAY_LENGTH(ar955x_scorpion_1p0_baseband_postamble), 5);
1386
1387         /* radio */
1388         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1389         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1390                         ar955x_scorpion_1p0_radio_core,
1391                         ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core), 2);
1392         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1393                         ar955x_scorpion_1p0_radio_postamble,
1394                         ARRAY_LENGTH(ar955x_scorpion_1p0_radio_postamble), 5);
1395
1396         /* soc */
1397         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1398                         ar955x_scorpion_1p0_soc_preamble,
1399                         ARRAY_LENGTH(ar955x_scorpion_1p0_soc_preamble), 2);
1400         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1401         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1402                         ar955x_scorpion_1p0_soc_postamble,
1403                         ARRAY_LENGTH(ar955x_scorpion_1p0_soc_postamble), 5);
1404
1405         /* rx/tx gain */
1406         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1407                         ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0,
1408                         ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2);
1409         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
1410                         ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0,
1411                         ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5);
1412         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1413                         ar955xModes_no_xpa_tx_gain_table_scorpion_1p0,
1414                         ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 5);
1415
1416         /*ath_hal_pciePowerSaveEnable should be 2 for OWL/Condor and 0 for merlin */
1417         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1418
1419         /* Fast clock modal settings */
1420         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1421                         ar955xModes_fast_clock_scorpion_1p0,
1422                         ARRAY_LENGTH(ar955xModes_fast_clock_scorpion_1p0), 3);
1423
1424         /* Additional setttings for 40Mhz */
1425         //INIT_INI_ARRAY(&ahp->ah_ini_modes_additional_40M,
1426         //                ar955x_scorpion_1p0_radio_core_40M,
1427         //                ARRAY_LENGTH(ar955x_scorpion_1p0_radio_core_40M), 2);
1428     } else if (AR_SREV_JUPITER_10(ah)) {
1429         /* Jupiter: new INI format (pre, core, post arrays per subsystem) */
1430
1431         /* mac */
1432         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1433         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1434             ar9300_jupiter_1p0_mac_core,
1435             ARRAY_LENGTH(ar9300_jupiter_1p0_mac_core), 2);
1436         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1437             ar9300_jupiter_1p0_mac_postamble,
1438             ARRAY_LENGTH(ar9300_jupiter_1p0_mac_postamble), 5);
1439
1440         /* bb */
1441         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1442         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1443             ar9300_jupiter_1p0_baseband_core,
1444             ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_core), 2);
1445         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1446             ar9300_jupiter_1p0_baseband_postamble,
1447             ARRAY_LENGTH(ar9300_jupiter_1p0_baseband_postamble), 5);
1448
1449         /* radio */
1450         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1451         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1452             ar9300_jupiter_1p0_radio_core,
1453             ARRAY_LENGTH(ar9300_jupiter_1p0_radio_core), 2);
1454         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1455             ar9300_jupiter_1p0_radio_postamble,
1456             ARRAY_LENGTH(ar9300_jupiter_1p0_radio_postamble), 5);
1457
1458         /* soc */
1459         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1460             ar9300_jupiter_1p0_soc_preamble,
1461             ARRAY_LENGTH(ar9300_jupiter_1p0_soc_preamble), 2);
1462         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1463         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1464             ar9300_jupiter_1p0_soc_postamble,
1465             ARRAY_LENGTH(ar9300_jupiter_1p0_soc_postamble), 5);
1466
1467         /* rx/tx gain */
1468         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1469             ar9300_common_rx_gain_table_jupiter_1p0,
1470             ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2);
1471
1472         /* Load PCIE SERDES settings from INI */
1473         if (ah->ah_config.ath_hal_pcie_clock_req) {
1474             /* Pci-e Clock Request = 1 */
1475             /*
1476              * PLL ON + clkreq enable is not a valid combination,
1477              * thus to ignore ath_hal_pll_pwr_save, use PLL OFF.
1478              */
1479             {
1480                 /*Use driver default setting*/
1481                 /* Awake -> Sleep Setting */
1482                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1483                     ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0,
1484                     ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0),
1485                     2);
1486                 /* Sleep -> Awake Setting */
1487                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1488                     ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0,
1489                     ARRAY_LENGTH(ar9300_pcie_phy_clkreq_enable_L1_jupiter_1p0),
1490                     2);
1491             }
1492         }
1493         else {
1494             /*
1495              * Since Jupiter 1.0 and 2.0 share the same device id and will be
1496              * installed with same INF, but Jupiter 1.0 has issue with PLL OFF.
1497              *
1498              * Force Jupiter 1.0 to use ON/ON setting.
1499              */
1500             ah->ah_config.ath_hal_pll_pwr_save = 0;
1501             /* Pci-e Clock Request = 0 */
1502             if (ah->ah_config.ath_hal_pll_pwr_save &
1503                 AR_PCIE_PLL_PWRSAVE_CONTROL)
1504             {
1505                 /* Awake -> Sleep Setting */
1506                 if (ah->ah_config.ath_hal_pll_pwr_save &
1507                      AR_PCIE_PLL_PWRSAVE_ON_D3)
1508                 {
1509                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1510                         ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0,
1511                         ARRAY_LENGTH(
1512                             ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0),
1513                         2);
1514                 }
1515                 else {
1516                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1517                         ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1518                         ARRAY_LENGTH(
1519                           ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1520                         2);
1521                 }
1522                 /* Sleep -> Awake Setting */
1523                 if (ah->ah_config.ath_hal_pll_pwr_save &
1524                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1525                 {
1526                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1527                         ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0,
1528                         ARRAY_LENGTH(
1529                             ar9300_pcie_phy_clkreq_disable_L1_jupiter_1p0),
1530                         2);
1531                 }
1532                 else {
1533                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1534                         ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1535                         ARRAY_LENGTH(
1536                           ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1537                         2);
1538                 }
1539
1540             }
1541             else {
1542                 /*Use driver default setting*/
1543                 /* Awake -> Sleep Setting */
1544                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1545                     ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1546                     ARRAY_LENGTH(
1547                         ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1548                     2);
1549                 /* Sleep -> Awake Setting */
1550                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1551                     ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0,
1552                     ARRAY_LENGTH(
1553                         ar9300_pcie_phy_pll_on_clkreq_disable_L1_jupiter_1p0),
1554                     2);
1555             }
1556         }
1557         /*
1558          * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and
1559          * 0 for merlin
1560          */
1561         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1562
1563 #if 0 // ATH_WOW
1564         /* SerDes values during WOW sleep */
1565         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW,
1566             ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2);
1567 #endif
1568
1569         /* Fast clock modal settings */
1570         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1571             ar9300_modes_fast_clock_jupiter_1p0,
1572             ARRAY_LENGTH(ar9300_modes_fast_clock_jupiter_1p0), 3);
1573         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1574             ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484,
1575             ARRAY_LENGTH(
1576             ar9300_jupiter_1p0_baseband_core_txfir_coeff_japan_2484), 2);
1577
1578     }
1579     else if (AR_SREV_JUPITER_20(ah)) {
1580         /* Jupiter: new INI format (pre, core, post arrays per subsystem) */
1581
1582         /* mac */
1583         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1584         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1585             ar9300_jupiter_2p0_mac_core,
1586             ARRAY_LENGTH(ar9300_jupiter_2p0_mac_core), 2);
1587         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1588             ar9300_jupiter_2p0_mac_postamble,
1589             ARRAY_LENGTH(ar9300_jupiter_2p0_mac_postamble), 5);
1590
1591         /* bb */
1592         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1593         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1594             ar9300_jupiter_2p0_baseband_core,
1595             ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_core), 2);
1596         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1597             ar9300_jupiter_2p0_baseband_postamble,
1598             ARRAY_LENGTH(ar9300_jupiter_2p0_baseband_postamble), 5);
1599
1600         /* radio */
1601         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1602         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1603             ar9300_jupiter_2p0_radio_core,
1604             ARRAY_LENGTH(ar9300_jupiter_2p0_radio_core), 2);
1605         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1606             ar9300_jupiter_2p0_radio_postamble,
1607             ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble), 5);
1608         INIT_INI_ARRAY(&ahp->ah_ini_radio_post_sys2ant,
1609             ar9300_jupiter_2p0_radio_postamble_sys2ant,
1610             ARRAY_LENGTH(ar9300_jupiter_2p0_radio_postamble_sys2ant), 5);
1611
1612         /* soc */
1613         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1614             ar9300_jupiter_2p0_soc_preamble,
1615             ARRAY_LENGTH(ar9300_jupiter_2p0_soc_preamble), 2);
1616         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1617         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1618             ar9300_jupiter_2p0_soc_postamble,
1619             ARRAY_LENGTH(ar9300_jupiter_2p0_soc_postamble), 5);
1620
1621         /* rx/tx gain */
1622         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1623             ar9300Common_rx_gain_table_jupiter_2p0,
1624             ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2);
1625
1626         /* BTCOEX */
1627         INIT_INI_ARRAY(&ahp->ah_ini_BTCOEX_MAX_TXPWR,
1628             ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table,
1629             ARRAY_LENGTH(ar9300_jupiter_2p0_BTCOEX_MAX_TXPWR_table), 2);
1630
1631         /* Load PCIE SERDES settings from INI */
1632         if (ah->ah_config.ath_hal_pcie_clock_req) {
1633             /* Pci-e Clock Request = 1 */
1634             /*
1635              * PLL ON + clkreq enable is not a valid combination,
1636              * thus to ignore ath_hal_pll_pwr_save, use PLL OFF.
1637              */
1638             {
1639                 /*Use driver default setting*/
1640                 /* Awake -> Sleep Setting */
1641                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1642                     ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0,
1643                     ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0),
1644                     2);
1645                 /* Sleep -> Awake Setting */
1646                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1647                     ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0,
1648                     ARRAY_LENGTH(ar9300_PciePhy_clkreq_enable_L1_jupiter_2p0),
1649                     2);
1650             }
1651         }
1652         else {
1653             /* Pci-e Clock Request = 0 */
1654             if (ah->ah_config.ath_hal_pll_pwr_save &
1655                 AR_PCIE_PLL_PWRSAVE_CONTROL)
1656             {
1657                 /* Awake -> Sleep Setting */
1658                 if (ah->ah_config.ath_hal_pll_pwr_save &
1659                      AR_PCIE_PLL_PWRSAVE_ON_D3)
1660                 {
1661                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1662                         ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0,
1663                         ARRAY_LENGTH(
1664                             ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0),
1665                         2);
1666                 }
1667                 else {
1668                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1669                         ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1670                         ARRAY_LENGTH(
1671                           ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1672                         2);
1673                 }
1674                 /* Sleep -> Awake Setting */
1675                 if (ah->ah_config.ath_hal_pll_pwr_save &
1676                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1677                 {
1678                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1679                         ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0,
1680                         ARRAY_LENGTH(
1681                             ar9300_PciePhy_clkreq_disable_L1_jupiter_2p0),
1682                         2);
1683                 }
1684                 else {
1685                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1686                         ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1687                         ARRAY_LENGTH(
1688                           ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1689                         2);
1690                 }
1691
1692             }
1693             else {
1694                 /*Use driver default setting*/
1695                 /* Awake -> Sleep Setting */
1696                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1697                     ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1698                     ARRAY_LENGTH(
1699                         ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1700                     2);
1701                 /* Sleep -> Awake Setting */
1702                 INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1703                     ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0,
1704                     ARRAY_LENGTH(
1705                         ar9300_PciePhy_pll_on_clkreq_disable_L1_jupiter_2p0),
1706                     2);
1707             }
1708         }
1709
1710         /*
1711          * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and
1712          * 0 for merlin
1713          */
1714         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1715
1716 #if 0 // ATH_WOW
1717         /* SerDes values during WOW sleep */
1718         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW,
1719             ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2);
1720 #endif
1721
1722         /* Fast clock modal settings */
1723         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1724             ar9300Modes_fast_clock_jupiter_2p0,
1725             ARRAY_LENGTH(ar9300Modes_fast_clock_jupiter_2p0), 3);
1726         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1727             ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484,
1728             ARRAY_LENGTH(
1729             ar9300_jupiter_2p0_baseband_core_txfir_coeff_japan_2484), 2);
1730
1731     } else if (AR_SREV_APHRODITE(ah)) {
1732         /* Aphrodite: new INI format (pre, core, post arrays per subsystem) */
1733
1734         /* mac */
1735         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1736         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1737             ar956X_aphrodite_1p0_mac_core,
1738             ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_core), 2);
1739         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1740             ar956X_aphrodite_1p0_mac_postamble,
1741             ARRAY_LENGTH(ar956X_aphrodite_1p0_mac_postamble), 5);
1742
1743         /* bb */
1744         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1745         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1746             ar956X_aphrodite_1p0_baseband_core,
1747             ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_core), 2);
1748         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1749             ar956X_aphrodite_1p0_baseband_postamble,
1750             ARRAY_LENGTH(ar956X_aphrodite_1p0_baseband_postamble), 5);
1751
1752 //mark jupiter have but aphrodite don't have
1753 //        /* radio */
1754 //        INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1755 //        INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1756 //            ar9300_aphrodite_1p0_radio_core,
1757 //            ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_core), 2);
1758 //        INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1759 //            ar9300_aphrodite_1p0_radio_postamble,
1760 //            ARRAY_LENGTH(ar9300_aphrodite_1p0_radio_postamble), 5);
1761
1762         /* soc */
1763         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1764             ar956X_aphrodite_1p0_soc_preamble,
1765             ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_preamble), 2);
1766         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1767         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1768             ar956X_aphrodite_1p0_soc_postamble,
1769             ARRAY_LENGTH(ar956X_aphrodite_1p0_soc_postamble), 5);
1770
1771         /* rx/tx gain */
1772         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1773             ar956XCommon_rx_gain_table_aphrodite_1p0,
1774             ARRAY_LENGTH(ar956XCommon_rx_gain_table_aphrodite_1p0), 2);
1775         //INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1776         //    ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0,
1777         //    ARRAY_LENGTH(ar956XModes_lowest_ob_db_tx_gain_table_aphrodite_1p0),
1778         //    5);
1779
1780
1781         /*
1782          * ath_hal_pcie_power_save_enable should be 2 for OWL/Condor and
1783          * 0 for merlin
1784          */
1785         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1786
1787 #if 0 // ATH_WOW
1788         /* SerDes values during WOW sleep */
1789         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_AWOW,
1790             ARRAY_LENGTH(ar9300_pcie_phy_AWOW), 2);
1791 #endif
1792        /* Fast clock modal settings */
1793        INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1794             ar956XModes_fast_clock_aphrodite_1p0,
1795             ARRAY_LENGTH(ar956XModes_fast_clock_aphrodite_1p0), 3);
1796
1797     } else if (AR_SREV_AR9580(ah)) {
1798         /*
1799          * AR9580/Peacock -
1800          * new INI format (pre, core, post arrays per subsystem)
1801          */
1802
1803         /* mac */
1804         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1805         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1806             ar9300_ar9580_1p0_mac_core,
1807             ARRAY_LENGTH(ar9300_ar9580_1p0_mac_core), 2);
1808         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1809             ar9300_ar9580_1p0_mac_postamble,
1810             ARRAY_LENGTH(ar9300_ar9580_1p0_mac_postamble), 5);
1811
1812         /* bb */
1813         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
1814         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
1815             ar9300_ar9580_1p0_baseband_core,
1816             ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_core), 2);
1817         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
1818             ar9300_ar9580_1p0_baseband_postamble,
1819             ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble), 5);
1820
1821         /* radio */
1822         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
1823         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
1824             ar9300_ar9580_1p0_radio_core,
1825             ARRAY_LENGTH(ar9300_ar9580_1p0_radio_core), 2);
1826         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
1827             ar9300_ar9580_1p0_radio_postamble,
1828             ARRAY_LENGTH(ar9300_ar9580_1p0_radio_postamble), 5);
1829
1830         /* soc */
1831         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
1832             ar9300_ar9580_1p0_soc_preamble,
1833             ARRAY_LENGTH(ar9300_ar9580_1p0_soc_preamble), 2);
1834         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
1835         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
1836             ar9300_ar9580_1p0_soc_postamble,
1837             ARRAY_LENGTH(ar9300_ar9580_1p0_soc_postamble), 5);
1838
1839         /* rx/tx gain */
1840         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
1841             ar9300_common_rx_gain_table_ar9580_1p0,
1842             ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2);
1843         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
1844             ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0,
1845             ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0), 5);
1846
1847         /* DFS */
1848         INIT_INI_ARRAY(&ahp->ah_ini_dfs,
1849             ar9300_ar9580_1p0_baseband_postamble_dfs_channel,
1850             ARRAY_LENGTH(ar9300_ar9580_1p0_baseband_postamble_dfs_channel), 3);
1851
1852
1853         /* Load PCIE SERDES settings from INI */
1854
1855         /*D3 Setting */
1856         if  (ah->ah_config.ath_hal_pcie_clock_req) {
1857             if (ah->ah_config.ath_hal_pll_pwr_save &
1858                 AR_PCIE_PLL_PWRSAVE_CONTROL)
1859             { //registry control
1860                 if (ah->ah_config.ath_hal_pll_pwr_save &
1861                     AR_PCIE_PLL_PWRSAVE_ON_D3)
1862                 { //bit1, in to D3
1863                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1864                         ar9300PciePhy_clkreq_enable_L1_ar9580_1p0,
1865                         ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0),
1866                     2);
1867                 } else {
1868                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1869                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1870                         ARRAY_LENGTH(
1871                             ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1872                     2);
1873                 }
1874             } else {//no registry control, default is pll on
1875                 INIT_INI_ARRAY(
1876                     &ahp->ah_ini_pcie_serdes,
1877                     ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1878                     ARRAY_LENGTH(
1879                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1880                     2);
1881             }
1882         } else {
1883             if (ah->ah_config.ath_hal_pll_pwr_save &
1884                 AR_PCIE_PLL_PWRSAVE_CONTROL)
1885             { //registry control
1886                 if (ah->ah_config.ath_hal_pll_pwr_save &
1887                     AR_PCIE_PLL_PWRSAVE_ON_D3)
1888                 { //bit1, in to D3
1889                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1890                         ar9300PciePhy_clkreq_disable_L1_ar9580_1p0,
1891                         ARRAY_LENGTH(
1892                             ar9300PciePhy_clkreq_disable_L1_ar9580_1p0),
1893                         2);
1894                 } else {
1895                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
1896                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1897                         ARRAY_LENGTH(
1898                             ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1899                         2);
1900                 }
1901             } else {//no registry control, default is pll on
1902                 INIT_INI_ARRAY(
1903                     &ahp->ah_ini_pcie_serdes,
1904                     ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1905                     ARRAY_LENGTH(
1906                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1907                     2);
1908             }
1909         }
1910
1911         /*D0 Setting */
1912         if  (ah->ah_config.ath_hal_pcie_clock_req) {
1913              if (ah->ah_config.ath_hal_pll_pwr_save &
1914                 AR_PCIE_PLL_PWRSAVE_CONTROL)
1915              { //registry control
1916                 if (ah->ah_config.ath_hal_pll_pwr_save &
1917                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1918                 { //bit2, out of D3
1919                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1920                         ar9300PciePhy_clkreq_enable_L1_ar9580_1p0,
1921                         ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_ar9580_1p0),
1922                     2);
1923
1924                 } else {
1925                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1926                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1927                         ARRAY_LENGTH(
1928                             ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1929                     2);
1930                 }
1931             } else { //no registry control, default is pll on
1932                 INIT_INI_ARRAY(
1933                     &ahp->ah_ini_pcie_serdes_low_power,
1934                     ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1935                     ARRAY_LENGTH(
1936                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1937                     2);
1938             }
1939         } else {
1940             if (ah->ah_config.ath_hal_pll_pwr_save &
1941                 AR_PCIE_PLL_PWRSAVE_CONTROL)
1942             {//registry control
1943                 if (ah->ah_config.ath_hal_pll_pwr_save &
1944                     AR_PCIE_PLL_PWRSAVE_ON_D0)
1945                 {//bit2, out of D3
1946                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1947                         ar9300PciePhy_clkreq_disable_L1_ar9580_1p0,
1948                        ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_ar9580_1p0),
1949                     2);
1950                 } else {
1951                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
1952                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1953                         ARRAY_LENGTH(
1954                             ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1955                     2);
1956                 }
1957             } else { //no registry control, default is pll on
1958                 INIT_INI_ARRAY(
1959                     &ahp->ah_ini_pcie_serdes_low_power,
1960                     ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0,
1961                     ARRAY_LENGTH(
1962                         ar9300PciePhy_pll_on_clkreq_disable_L1_ar9580_1p0),
1963                     2);
1964             }
1965         }
1966
1967         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
1968
1969 #if 0 /* ATH_WOW */
1970         /* SerDes values during WOW sleep */
1971         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
1972                        ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
1973 #endif
1974
1975         /* Fast clock modal settings */
1976         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
1977             ar9300Modes_fast_clock_ar9580_1p0,
1978             ARRAY_LENGTH(ar9300Modes_fast_clock_ar9580_1p0), 3);
1979         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
1980             ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484,
1981             ARRAY_LENGTH(
1982                 ar9300_ar9580_1p0_baseband_core_txfir_coeff_japan_2484), 2);
1983
1984     } else {
1985         /*
1986          * Osprey 2.2 -  new INI format (pre, core, post arrays per subsystem)
1987          */
1988
1989         /* mac */
1990         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_PRE], NULL, 0, 0);
1991         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_CORE],
1992             ar9300_osprey_2p2_mac_core,
1993             ARRAY_LENGTH(ar9300_osprey_2p2_mac_core), 2);
1994         INIT_INI_ARRAY(&ahp->ah_ini_mac[ATH_INI_POST],
1995             ar9300_osprey_2p2_mac_postamble,
1996             ARRAY_LENGTH(ar9300_osprey_2p2_mac_postamble), 5);
1997
1998         /* bb */
1999         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_PRE], NULL, 0, 0);
2000         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_CORE],
2001             ar9300_osprey_2p2_baseband_core,
2002             ARRAY_LENGTH(ar9300_osprey_2p2_baseband_core), 2);
2003         INIT_INI_ARRAY(&ahp->ah_ini_bb[ATH_INI_POST],
2004             ar9300_osprey_2p2_baseband_postamble,
2005             ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble), 5);
2006
2007         /* radio */
2008         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_PRE], NULL, 0, 0);
2009         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_CORE],
2010             ar9300_osprey_2p2_radio_core,
2011             ARRAY_LENGTH(ar9300_osprey_2p2_radio_core), 2);
2012         INIT_INI_ARRAY(&ahp->ah_ini_radio[ATH_INI_POST],
2013             ar9300_osprey_2p2_radio_postamble,
2014             ARRAY_LENGTH(ar9300_osprey_2p2_radio_postamble), 5);
2015
2016         /* soc */
2017         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_PRE],
2018             ar9300_osprey_2p2_soc_preamble,
2019             ARRAY_LENGTH(ar9300_osprey_2p2_soc_preamble), 2);
2020         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_CORE], NULL, 0, 0);
2021         INIT_INI_ARRAY(&ahp->ah_ini_soc[ATH_INI_POST],
2022             ar9300_osprey_2p2_soc_postamble,
2023             ARRAY_LENGTH(ar9300_osprey_2p2_soc_postamble), 5);
2024
2025         /* rx/tx gain */
2026         INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
2027             ar9300_common_rx_gain_table_osprey_2p2,
2028             ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2);
2029         INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
2030             ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2,
2031             ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2), 5);
2032
2033         /* DFS */
2034         INIT_INI_ARRAY(&ahp->ah_ini_dfs,
2035             ar9300_osprey_2p2_baseband_postamble_dfs_channel,
2036             ARRAY_LENGTH(ar9300_osprey_2p2_baseband_postamble_dfs_channel), 3);
2037
2038         /* Load PCIE SERDES settings from INI */
2039
2040         /*D3 Setting */
2041         if  (ah->ah_config.ath_hal_pcie_clock_req) {
2042             if (ah->ah_config.ath_hal_pll_pwr_save &
2043                 AR_PCIE_PLL_PWRSAVE_CONTROL)
2044             { //registry control
2045                 if (ah->ah_config.ath_hal_pll_pwr_save &
2046                     AR_PCIE_PLL_PWRSAVE_ON_D3)
2047                 { //bit1, in to D3
2048                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2049                         ar9300PciePhy_clkreq_enable_L1_osprey_2p2,
2050                         ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2),
2051                     2);
2052                 } else {
2053                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2054                         ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2055                         ARRAY_LENGTH(
2056                             ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2057                     2);
2058                 }
2059              } else {//no registry control, default is pll on
2060 #ifndef ATH_BUS_PM
2061                     INIT_INI_ARRAY(
2062                         &ahp->ah_ini_pcie_serdes,
2063                         ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2064                         ARRAY_LENGTH(
2065                             ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2066                     2);
2067 #else
2068         //no registry control, default is pll off
2069         INIT_INI_ARRAY(
2070                 &ahp->ah_ini_pcie_serdes,
2071                 ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2072                 ARRAY_LENGTH(
2073                     ar9300PciePhy_clkreq_disable_L1_osprey_2p2),
2074                   2);
2075 #endif
2076
2077             }
2078         } else {
2079             if (ah->ah_config.ath_hal_pll_pwr_save &
2080                 AR_PCIE_PLL_PWRSAVE_CONTROL)
2081             { //registry control
2082                 if (ah->ah_config.ath_hal_pll_pwr_save &
2083                     AR_PCIE_PLL_PWRSAVE_ON_D3)
2084                 { //bit1, in to D3
2085                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2086                         ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2087                         ARRAY_LENGTH(
2088                             ar9300PciePhy_clkreq_disable_L1_osprey_2p2),
2089                         2);
2090                 } else {
2091                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes,
2092                        ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2093                        ARRAY_LENGTH(
2094                            ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2095                        2);
2096                 }
2097              } else {
2098 #ifndef ATH_BUS_PM
2099         //no registry control, default is pll on
2100                 INIT_INI_ARRAY(
2101                     &ahp->ah_ini_pcie_serdes,
2102                     ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2103                     ARRAY_LENGTH(
2104                         ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2105                     2);
2106 #else
2107         //no registry control, default is pll off
2108         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes, ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2109                            ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2), 2);
2110 #endif
2111             }
2112         }
2113
2114         /*D0 Setting */
2115         if  (ah->ah_config.ath_hal_pcie_clock_req) {
2116              if (ah->ah_config.ath_hal_pll_pwr_save &
2117                 AR_PCIE_PLL_PWRSAVE_CONTROL)
2118              { //registry control
2119                 if (ah->ah_config.ath_hal_pll_pwr_save &
2120                     AR_PCIE_PLL_PWRSAVE_ON_D0)
2121                 { //bit2, out of D3
2122                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2123                         ar9300PciePhy_clkreq_enable_L1_osprey_2p2,
2124                         ARRAY_LENGTH(ar9300PciePhy_clkreq_enable_L1_osprey_2p2),
2125                     2);
2126
2127                 } else {
2128                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2129                         ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2130                         ARRAY_LENGTH(
2131                             ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2132                     2);
2133                 }
2134             } else { //no registry control, default is pll on
2135                 INIT_INI_ARRAY(
2136                     &ahp->ah_ini_pcie_serdes_low_power,
2137                     ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2138                     ARRAY_LENGTH(
2139                         ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2140                     2);
2141             }
2142         } else {
2143             if (ah->ah_config.ath_hal_pll_pwr_save &
2144                 AR_PCIE_PLL_PWRSAVE_CONTROL)
2145             {//registry control
2146                 if (ah->ah_config.ath_hal_pll_pwr_save &
2147                     AR_PCIE_PLL_PWRSAVE_ON_D0)
2148                 {//bit2, out of D3
2149                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2150                         ar9300PciePhy_clkreq_disable_L1_osprey_2p2,
2151                        ARRAY_LENGTH(ar9300PciePhy_clkreq_disable_L1_osprey_2p2),
2152                     2);
2153                 } else {
2154                     INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_low_power,
2155                         ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2156                         ARRAY_LENGTH(
2157                             ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2158                     2);
2159                 }
2160             } else { //no registry control, default is pll on
2161                 INIT_INI_ARRAY(
2162                     &ahp->ah_ini_pcie_serdes_low_power,
2163                     ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2,
2164                     ARRAY_LENGTH(
2165                         ar9300PciePhy_pll_on_clkreq_disable_L1_osprey_2p2),
2166                     2);
2167             }
2168         }
2169
2170         ah->ah_config.ath_hal_pcie_power_save_enable = 0;
2171
2172 #ifdef ATH_BUS_PM
2173         /*Use HAL to config PCI powersave by writing into the SerDes Registers */
2174         ah->ah_config.ath_hal_pcie_ser_des_write = 1;
2175 #endif
2176
2177 #if 0 /* ATH_WOW */
2178         /* SerDes values during WOW sleep */
2179         INIT_INI_ARRAY(&ahp->ah_ini_pcie_serdes_wow, ar9300_pcie_phy_awow,
2180                        ARRAY_LENGTH(ar9300_pcie_phy_awow), 2);
2181 #endif
2182
2183         /* Fast clock modal settings */
2184         INIT_INI_ARRAY(&ahp->ah_ini_modes_additional,
2185             ar9300Modes_fast_clock_osprey_2p2,
2186             ARRAY_LENGTH(ar9300Modes_fast_clock_osprey_2p2), 3);
2187         INIT_INI_ARRAY(&ahp->ah_ini_japan2484,
2188             ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484,
2189             ARRAY_LENGTH(
2190                 ar9300_osprey_2p2_baseband_core_txfir_coeff_japan_2484), 2);
2191
2192     }
2193
2194     if(AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah))
2195     {
2196 #define AR_SOC_RST_OTP_INTF  0xB80600B4
2197 #define REG_READ(_reg)       *((volatile u_int32_t *)(_reg))
2198
2199         ahp->ah_enterprise_mode = REG_READ(AR_SOC_RST_OTP_INTF);
2200         if (AR_SREV_SCORPION(ah)) {
2201             ahp->ah_enterprise_mode = ahp->ah_enterprise_mode << 12;
2202         }
2203         ath_hal_printf (ah, "Enterprise mode: 0x%08x\n", ahp->ah_enterprise_mode);
2204 #undef REG_READ
2205 #undef AR_SOC_RST_OTP_INTF
2206     } else {
2207         ahp->ah_enterprise_mode = OS_REG_READ(ah, AR_ENT_OTP);
2208     }
2209
2210
2211     if (ahpriv->ah_ispcie) {
2212         ar9300_config_pci_power_save(ah, 0, 0);
2213     } else {
2214         ar9300_disable_pcie_phy(ah);
2215     }
2216     ath_hal_printf(ah, "%s: calling ar9300_hw_attach\n", __func__);
2217     ecode = ar9300_hw_attach(ah);
2218     if (ecode != HAL_OK) {
2219         goto bad;
2220     }
2221
2222     /* set gain table pointers according to values read from the eeprom */
2223     ar9300_tx_gain_table_apply(ah);
2224     ar9300_rx_gain_table_apply(ah);
2225
2226     /*
2227     **
2228     ** Got everything we need now to setup the capabilities.
2229     */
2230
2231     if (!ar9300_fill_capability_info(ah)) {
2232         HALDEBUG(ah, HAL_DEBUG_RESET,
2233             "%s:failed ar9300_fill_capability_info\n", __func__);
2234         ecode = HAL_EEREAD;
2235         goto bad;
2236     }
2237     ecode = ar9300_init_mac_addr(ah);
2238     if (ecode != HAL_OK) {
2239         HALDEBUG(ah, HAL_DEBUG_RESET,
2240             "%s: failed initializing mac address\n", __func__);
2241         goto bad;
2242     }
2243
2244     /*
2245      * Initialize receive buffer size to MAC default
2246      */
2247     ahp->rx_buf_size = HAL_RXBUFSIZE_DEFAULT;
2248
2249 #if ATH_WOW
2250 #if 0
2251     /*
2252      * Needs to be removed once we stop using XB92 XXX
2253      * FIXME: Check with latest boards too - SriniK
2254      */
2255     ar9300_wow_set_gpio_reset_low(ah);
2256 #endif
2257
2258     /*
2259      * Clear the Wow Status.
2260      */
2261     OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL),
2262         OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL)) |
2263         AR_PMCTRL_WOW_PME_CLR);
2264     OS_REG_WRITE(ah, AR_WOW_PATTERN_REG,
2265         AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG)));
2266 #endif
2267
2268     /*
2269      * Set the cur_trig_level to a value that works all modes - 11a/b/g or 11n
2270      * with aggregation enabled or disabled.
2271      */
2272     ahp->ah_tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
2273
2274     if (AR_SREV_HORNET(ah)) {
2275         ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_HORNET_2GHZ;
2276         ahp->nf_2GHz.max     = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ;
2277         ahp->nf_2GHz.min     = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ;
2278         ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ;
2279         ahp->nf_5GHz.max     = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ;
2280         ahp->nf_5GHz.min     = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ;
2281         ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA;
2282     } else if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
2283         ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_2GHZ;
2284         ahp->nf_2GHz.max     = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ;
2285         ahp->nf_2GHz.min     = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_2GHZ;
2286         ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_JUPITER_5GHZ;
2287         ahp->nf_5GHz.max     = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ;
2288         ahp->nf_5GHz.min     = AR_PHY_CCA_MIN_GOOD_VAL_JUPITER_5GHZ;
2289         ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA;
2290     }   else {
2291         ahp->nf_2GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_2GHZ;
2292         ahp->nf_2GHz.max     = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_2GHZ;
2293         ahp->nf_2GHz.min     = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_2GHZ;
2294         if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
2295             ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_PEACOCK_5GHZ;
2296         } else {
2297             ahp->nf_5GHz.nominal = AR_PHY_CCA_NOM_VAL_OSPREY_5GHZ;
2298         }
2299         ahp->nf_5GHz.max     = AR_PHY_CCA_MAX_GOOD_VAL_OSPREY_5GHZ;
2300         ahp->nf_5GHz.min     = AR_PHY_CCA_MIN_GOOD_VAL_OSPREY_5GHZ;
2301         ahp->nf_cw_int_delta = AR_PHY_CCA_CW_INT_DELTA;
2302      }
2303
2304
2305
2306
2307     /* init BB Panic Watchdog timeout */
2308     if (AR_SREV_HORNET(ah)) {
2309         ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO_HORNET;
2310     } else {
2311         ahp->ah_bb_panic_timeout_ms = HAL_BB_PANIC_WD_TMO;
2312     }
2313
2314
2315     /*
2316      * Determine whether tx IQ calibration HW should be enabled,
2317      * and whether tx IQ calibration should be performed during
2318      * AGC calibration, or separately.
2319      */
2320     if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
2321         /*
2322          * Register not initialized yet. This flag will be re-initialized
2323          * after INI loading following each reset.
2324          */
2325         ahp->tx_iq_cal_enable = 1;
2326         /* if tx IQ cal is enabled, do it together with AGC cal */
2327         ahp->tx_iq_cal_during_agc_cal = 1;
2328     } else if (AR_SREV_POSEIDON_OR_LATER(ah) && !AR_SREV_WASP(ah)) {
2329         ahp->tx_iq_cal_enable = 1;
2330         ahp->tx_iq_cal_during_agc_cal = 1;
2331     } else {
2332         /* osprey, hornet, wasp */
2333         ahp->tx_iq_cal_enable = 1;
2334         ahp->tx_iq_cal_during_agc_cal = 0;
2335     }
2336     return ah;
2337
2338 bad:
2339     if (ahp) {
2340         ar9300_detach((struct ath_hal *) ahp);
2341     }
2342     if (status) {
2343         *status = ecode;
2344     }
2345     return AH_NULL;
2346 }
2347
2348 void
2349 ar9300_detach(struct ath_hal *ah)
2350 {
2351     HALASSERT(ah != AH_NULL);
2352     HALASSERT(ah->ah_magic == AR9300_MAGIC);
2353
2354     /* Make sure that chip is awake before writing to it */
2355     if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
2356         HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
2357                  "%s: failed to wake up chip\n",
2358                  __func__);
2359     }
2360
2361     ar9300_hw_detach(ah);
2362     ar9300_set_power_mode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
2363
2364 //    ath_hal_hdprintf_deregister(ah);
2365
2366     if (AH9300(ah)->ah_cal_mem)
2367         ath_hal_free(AH9300(ah)->ah_cal_mem);
2368     AH9300(ah)->ah_cal_mem = AH_NULL;
2369
2370     ath_hal_free(ah);
2371 }
2372
2373 struct ath_hal_9300 *
2374 ar9300_new_state(u_int16_t devid, HAL_SOFTC sc,
2375     HAL_BUS_TAG st, HAL_BUS_HANDLE sh,
2376     uint16_t *eepromdata,
2377     HAL_OPS_CONFIG *ah_config,
2378     HAL_STATUS *status)
2379 {
2380     static const u_int8_t defbssidmask[IEEE80211_ADDR_LEN] =
2381         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
2382     struct ath_hal_9300 *ahp;
2383     struct ath_hal *ah;
2384
2385     /* NB: memory is returned zero'd */
2386     ahp = ath_hal_malloc(sizeof(struct ath_hal_9300));
2387     if (ahp == AH_NULL) {
2388         HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
2389                  "%s: cannot allocate memory for state block\n",
2390                  __func__);
2391         *status = HAL_ENOMEM;
2392         return AH_NULL;
2393     }
2394
2395     ah = &ahp->ah_priv.h;
2396     /* set initial values */
2397
2398     /* stub everything first */
2399     ar9300_set_stub_functions(ah);
2400
2401     /* setup the FreeBSD HAL methods */
2402     ar9300_attach_freebsd_ops(ah);
2403
2404     /* These are private to this particular file, so .. */
2405     ah->ah_disablePCIE = ar9300_disable_pcie_phy;
2406     AH_PRIVATE(ah)->ah_getNfAdjust = ar9300_get_nf_adjust;
2407     AH_PRIVATE(ah)->ah_getChipPowerLimits = ar9300_get_chip_power_limits;
2408
2409 #if 0
2410     /* Attach Osprey structure as default hal structure */
2411     OS_MEMCPY(&ahp->ah_priv.priv, &ar9300hal, sizeof(ahp->ah_priv.priv));
2412 #endif
2413
2414 #if 0
2415     AH_PRIVATE(ah)->amem_handle = amem_handle;
2416     AH_PRIVATE(ah)->ah_osdev = osdev;
2417 #endif
2418     ah->ah_sc = sc;
2419     ah->ah_st = st;
2420     ah->ah_sh = sh;
2421     ah->ah_magic = AR9300_MAGIC;
2422     AH_PRIVATE(ah)->ah_devid = devid;
2423
2424     AH_PRIVATE(ah)->ah_flags = 0;
2425
2426     /*
2427     ** Initialize factory defaults in the private space
2428     */
2429 //    ath_hal_factory_defaults(AH_PRIVATE(ah), hal_conf_parm);
2430     ar9300_config_defaults_freebsd(ah, ah_config);
2431
2432     /* XXX FreeBSD: cal is always in EEPROM */
2433 #if 0
2434     if (!hal_conf_parm->calInFlash) {
2435         AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM;
2436     }
2437 #endif
2438     AH_PRIVATE(ah)->ah_flags |= AH_USE_EEPROM;
2439
2440 #if 0
2441     if (ar9300_eep_data_in_flash(ah)) {
2442         ahp->ah_priv.priv.ah_eeprom_read  = ar9300_flash_read;
2443         ahp->ah_priv.priv.ah_eeprom_dump  = AH_NULL;
2444     } else {
2445         ahp->ah_priv.priv.ah_eeprom_read  = ar9300_eeprom_read_word;
2446     }
2447 #endif
2448
2449     /* XXX FreeBSD - for now, just supports EEPROM reading */
2450     ahp->ah_priv.ah_eepromRead = ar9300_eeprom_read_word;
2451
2452     AH_PRIVATE(ah)->ah_powerLimit = MAX_RATE_POWER;
2453     AH_PRIVATE(ah)->ah_tpScale = HAL_TP_SCALE_MAX;  /* no scaling */
2454
2455     ahp->ah_atim_window = 0;         /* [0..1000] */
2456
2457     ahp->ah_diversity_control =
2458         ah->ah_config.ath_hal_diversity_control;
2459     ahp->ah_antenna_switch_swap =
2460         ah->ah_config.ath_hal_antenna_switch_swap;
2461
2462     /*
2463      * Enable MIC handling.
2464      */
2465     ahp->ah_sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
2466     ahp->ah_enable32k_hz_clock = DONT_USE_32KHZ;/* XXX */
2467     ahp->ah_slot_time = (u_int) -1;
2468     ahp->ah_ack_timeout = (u_int) -1;
2469     OS_MEMCPY(&ahp->ah_bssid_mask, defbssidmask, IEEE80211_ADDR_LEN);
2470
2471     /*
2472      * 11g-specific stuff
2473      */
2474     ahp->ah_g_beacon_rate = 0;        /* adhoc beacon fixed rate */
2475
2476     /* SM power mode: Attach time, disable any setting */
2477     ahp->ah_sm_power_mode = HAL_SMPS_DEFAULT;
2478
2479     return ahp;
2480 }
2481
2482 HAL_BOOL
2483 ar9300_chip_test(struct ath_hal *ah)
2484 {
2485     /*u_int32_t reg_addr[2] = { AR_STA_ID0, AR_PHY_BASE+(8 << 2) };*/
2486     u_int32_t reg_addr[2] = { AR_STA_ID0 };
2487     u_int32_t reg_hold[2];
2488     u_int32_t pattern_data[4] =
2489         { 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 };
2490     int i, j;
2491
2492     /* Test PHY & MAC registers */
2493     for (i = 0; i < 1; i++) {
2494         u_int32_t addr = reg_addr[i];
2495         u_int32_t wr_data, rd_data;
2496
2497         reg_hold[i] = OS_REG_READ(ah, addr);
2498         for (j = 0; j < 0x100; j++) {
2499             wr_data = (j << 16) | j;
2500             OS_REG_WRITE(ah, addr, wr_data);
2501             rd_data = OS_REG_READ(ah, addr);
2502             if (rd_data != wr_data) {
2503                 HALDEBUG(ah, HAL_DEBUG_REGIO,
2504                     "%s: address test failed addr: "
2505                     "0x%08x - wr:0x%08x != rd:0x%08x\n",
2506                     __func__, addr, wr_data, rd_data);
2507                 return AH_FALSE;
2508             }
2509         }
2510         for (j = 0; j < 4; j++) {
2511             wr_data = pattern_data[j];
2512             OS_REG_WRITE(ah, addr, wr_data);
2513             rd_data = OS_REG_READ(ah, addr);
2514             if (wr_data != rd_data) {
2515                 HALDEBUG(ah, HAL_DEBUG_REGIO,
2516                     "%s: address test failed addr: "
2517                     "0x%08x - wr:0x%08x != rd:0x%08x\n",
2518                     __func__, addr, wr_data, rd_data);
2519                 return AH_FALSE;
2520             }
2521         }
2522         OS_REG_WRITE(ah, reg_addr[i], reg_hold[i]);
2523     }
2524     OS_DELAY(100);
2525     return AH_TRUE;
2526 }
2527
2528 /*
2529  * Store the channel edges for the requested operational mode
2530  */
2531 HAL_BOOL
2532 ar9300_get_channel_edges(struct ath_hal *ah,
2533     u_int16_t flags, u_int16_t *low, u_int16_t *high)
2534 {
2535     struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2536     HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2537
2538     if (flags & IEEE80211_CHAN_5GHZ) {
2539         *low = p_cap->halLow5GhzChan;
2540         *high = p_cap->halHigh5GhzChan;
2541         return AH_TRUE;
2542     }
2543     if ((flags & IEEE80211_CHAN_2GHZ)) {
2544         *low = p_cap->halLow2GhzChan;
2545         *high = p_cap->halHigh2GhzChan;
2546
2547         return AH_TRUE;
2548     }
2549     return AH_FALSE;
2550 }
2551
2552 HAL_BOOL
2553 ar9300_regulatory_domain_override(struct ath_hal *ah, u_int16_t regdmn)
2554 {
2555     AH_PRIVATE(ah)->ah_currentRD = regdmn;
2556     return AH_TRUE;
2557 }
2558
2559 /*
2560  * Fill all software cached or static hardware state information.
2561  * Return failure if capabilities are to come from EEPROM and
2562  * cannot be read.
2563  */
2564 HAL_BOOL
2565 ar9300_fill_capability_info(struct ath_hal *ah)
2566 {
2567 #define AR_KEYTABLE_SIZE    128
2568     struct ath_hal_9300 *ahp = AH9300(ah);
2569     struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2570     HAL_CAPABILITIES *p_cap = &ahpriv->ah_caps;
2571     u_int16_t cap_field = 0, eeval;
2572
2573     ahpriv->ah_devType = (u_int16_t)ar9300_eeprom_get(ahp, EEP_DEV_TYPE);
2574     eeval = ar9300_eeprom_get(ahp, EEP_REG_0);
2575
2576     /* XXX record serial number */
2577     AH_PRIVATE(ah)->ah_currentRD = eeval;
2578
2579     /* Always enable fast clock; leave it up to EEPROM and channel */
2580     p_cap->halSupportsFastClock5GHz = AH_TRUE;
2581
2582     p_cap->halIntrMitigation = AH_TRUE;
2583     eeval = ar9300_eeprom_get(ahp, EEP_REG_1);
2584     AH_PRIVATE(ah)->ah_currentRDext = eeval | AR9300_RDEXT_DEFAULT;
2585
2586     /* Read the capability EEPROM location */
2587     cap_field = ar9300_eeprom_get(ahp, EEP_OP_CAP);
2588
2589     /* Construct wireless mode from EEPROM */
2590     p_cap->halWirelessModes = 0;
2591     eeval = ar9300_eeprom_get(ahp, EEP_OP_MODE);
2592
2593     /*
2594      * XXX FreeBSD specific: for now, set ath_hal_ht_enable to 1,
2595      * or we won't have 11n support.
2596      */
2597     ah->ah_config.ath_hal_ht_enable = 1;
2598
2599     if (eeval & AR9300_OPFLAGS_11A) {
2600         p_cap->halWirelessModes |= HAL_MODE_11A |
2601             ((!ah->ah_config.ath_hal_ht_enable ||
2602               (eeval & AR9300_OPFLAGS_N_5G_HT20)) ?  0 :
2603              (HAL_MODE_11NA_HT20 | ((eeval & AR9300_OPFLAGS_N_5G_HT40) ? 0 :
2604                                     (HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS))));
2605     }
2606     if (eeval & AR9300_OPFLAGS_11G) {
2607         p_cap->halWirelessModes |= HAL_MODE_11B | HAL_MODE_11G |
2608             ((!ah->ah_config.ath_hal_ht_enable ||
2609               (eeval & AR9300_OPFLAGS_N_2G_HT20)) ?  0 :
2610              (HAL_MODE_11NG_HT20 | ((eeval & AR9300_OPFLAGS_N_2G_HT40) ? 0 :
2611                                     (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS))));
2612     }
2613
2614     /* Get chainamsks from eeprom */
2615     p_cap->halTxChainMask = ar9300_eeprom_get(ahp, EEP_TX_MASK);
2616     p_cap->halRxChainMask = ar9300_eeprom_get(ahp, EEP_RX_MASK);
2617
2618
2619
2620 #define owl_get_ntxchains(_txchainmask) \
2621     (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
2622
2623     /* FreeBSD: Update number of TX/RX streams */
2624     p_cap->halTxStreams = owl_get_ntxchains(p_cap->halTxChainMask);
2625     p_cap->halRxStreams = owl_get_ntxchains(p_cap->halRxChainMask);
2626
2627
2628     /*
2629      * This being a newer chip supports TKIP non-splitmic mode.
2630      *
2631      */
2632     ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2633     p_cap->halTkipMicTxRxKeySupport = AH_TRUE;
2634
2635     p_cap->halLow2GhzChan = 2312;
2636     p_cap->halHigh2GhzChan = 2732;
2637
2638     p_cap->halLow5GhzChan = 4920;
2639     p_cap->halHigh5GhzChan = 6100;
2640
2641     p_cap->halCipherCkipSupport = AH_FALSE;
2642     p_cap->halCipherTkipSupport = AH_TRUE;
2643     p_cap->halCipherAesCcmSupport = AH_TRUE;
2644
2645     p_cap->halMicCkipSupport = AH_FALSE;
2646     p_cap->halMicTkipSupport = AH_TRUE;
2647     p_cap->halMicAesCcmSupport = AH_TRUE;
2648
2649     p_cap->halChanSpreadSupport = AH_TRUE;
2650     p_cap->halSleepAfterBeaconBroken = AH_TRUE;
2651
2652     p_cap->halBurstSupport = AH_TRUE;
2653     p_cap->halChapTuningSupport = AH_TRUE;
2654     p_cap->halTurboPrimeSupport = AH_TRUE;
2655     p_cap->halFastFramesSupport = AH_FALSE;
2656
2657     p_cap->halTurboGSupport = p_cap->halWirelessModes & HAL_MODE_108G;
2658
2659 //    p_cap->hal_xr_support = AH_FALSE;
2660
2661     p_cap->halHTSupport =
2662         ah->ah_config.ath_hal_ht_enable ?  AH_TRUE : AH_FALSE;
2663
2664     p_cap->halGTTSupport = AH_TRUE;
2665     p_cap->halPSPollBroken = AH_TRUE;    /* XXX fixed in later revs? */
2666     p_cap->halNumMRRetries = 4;         /* Hardware supports 4 MRR */
2667     p_cap->halHTSGI20Support = AH_TRUE;
2668     p_cap->halVEOLSupport = AH_TRUE;
2669     p_cap->halBssIdMaskSupport = AH_TRUE;
2670     /* Bug 26802, fixed in later revs? */
2671     p_cap->halMcastKeySrchSupport = AH_TRUE;
2672     p_cap->halTsfAddSupport = AH_TRUE;
2673
2674     if (cap_field & AR_EEPROM_EEPCAP_MAXQCU) {
2675         p_cap->halTotalQueues = MS(cap_field, AR_EEPROM_EEPCAP_MAXQCU);
2676     } else {
2677         p_cap->halTotalQueues = HAL_NUM_TX_QUEUES;
2678     }
2679
2680     if (cap_field & AR_EEPROM_EEPCAP_KC_ENTRIES) {
2681         p_cap->halKeyCacheSize =
2682             1 << MS(cap_field, AR_EEPROM_EEPCAP_KC_ENTRIES);
2683     } else {
2684         p_cap->halKeyCacheSize = AR_KEYTABLE_SIZE;
2685     }
2686     p_cap->halFastCCSupport = AH_TRUE;
2687 //    p_cap->hal_num_mr_retries = 4;
2688 //    ahp->hal_tx_trig_level_max = MAX_TX_FIFO_THRESHOLD;
2689
2690     p_cap->halNumGpioPins = AR9382_MAX_GPIO_PIN_NUM;
2691
2692 #if 0
2693     /* XXX Verify support in Osprey */
2694     if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
2695         p_cap->halWowSupport = AH_TRUE;
2696         p_cap->hal_wow_match_pattern_exact = AH_TRUE;
2697         if (AR_SREV_MERLIN(ah)) {
2698             p_cap->hal_wow_pattern_match_dword = AH_TRUE;
2699         }
2700     } else {
2701         p_cap->halWowSupport = AH_FALSE;
2702         p_cap->hal_wow_match_pattern_exact = AH_FALSE;
2703     }
2704 #endif
2705     p_cap->halWowSupport = AH_TRUE;
2706     p_cap->halWowMatchPatternExact = AH_TRUE;
2707     if (AR_SREV_POSEIDON(ah)) {
2708         p_cap->halWowMatchPatternExact = AH_TRUE;
2709     }
2710
2711     p_cap->halCSTSupport = AH_TRUE;
2712
2713     p_cap->halRifsRxSupport = AH_TRUE;
2714     p_cap->halRifsTxSupport = AH_TRUE;
2715
2716 #define IEEE80211_AMPDU_LIMIT_MAX (65536)
2717     p_cap->halRtsAggrLimit = IEEE80211_AMPDU_LIMIT_MAX;
2718 #undef IEEE80211_AMPDU_LIMIT_MAX
2719
2720     p_cap->halMfpSupport = ah->ah_config.ath_hal_mfp_support;
2721
2722     p_cap->halForcePpmSupport = AH_TRUE;
2723     p_cap->halHwBeaconProcSupport = AH_TRUE;
2724
2725     /* ar9300 - has the HW UAPSD trigger support,
2726      * but it has the following limitations
2727      * The power state change from the following
2728      * frames are not put in High priority queue.
2729      *     i) Mgmt frames
2730      *     ii) NoN QoS frames
2731      *     iii) QoS frames form the access categories for which
2732      *          UAPSD is not enabled.
2733      * so we can not enable this feature currently.
2734      * could be enabled, if these limitations are fixed
2735      * in later versions of ar9300 chips
2736      */
2737     p_cap->halHasUapsdSupport = AH_FALSE;
2738
2739     /* Number of buffers that can be help in a single TxD */
2740     p_cap->halNumTxMaps = 4;
2741
2742     p_cap->halTxDescLen = sizeof(struct ar9300_txc);
2743     p_cap->halTxStatusLen = sizeof(struct ar9300_txs);
2744     p_cap->halRxStatusLen = sizeof(struct ar9300_rxs);
2745
2746     p_cap->halRxHpFifoDepth = HAL_HP_RXFIFO_DEPTH;
2747     p_cap->halRxLpFifoDepth = HAL_LP_RXFIFO_DEPTH;
2748
2749     /* Enable extension channel DFS support */
2750     p_cap->halUseCombinedRadarRssi = AH_TRUE;
2751     p_cap->halExtChanDfsSupport = AH_TRUE;
2752 #if ATH_SUPPORT_SPECTRAL
2753     p_cap->halSpectralScanSupport = AH_TRUE;
2754 #endif
2755
2756     ahpriv->ah_rfsilent = ar9300_eeprom_get(ahp, EEP_RF_SILENT);
2757     if (ahpriv->ah_rfsilent & EEP_RFSILENT_ENABLED) {
2758         ahp->ah_gpio_select = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
2759         ahp->ah_polarity   = MS(ahpriv->ah_rfsilent, EEP_RFSILENT_POLARITY);
2760
2761         ath_hal_enable_rfkill(ah, AH_TRUE);
2762         p_cap->halRfSilentSupport = AH_TRUE;
2763     }
2764
2765     /* XXX */
2766     p_cap->halWpsPushButtonSupport = AH_FALSE;
2767
2768 #ifdef ATH_BT_COEX
2769     p_cap->halBtCoexSupport = AH_TRUE;
2770     p_cap->halBtCoexApsmWar = AH_FALSE;
2771 #endif
2772
2773     p_cap->halGenTimerSupport = AH_TRUE;
2774     ahp->ah_avail_gen_timers = ~((1 << AR_FIRST_NDP_TIMER) - 1);
2775     ahp->ah_avail_gen_timers &= (1 << AR_NUM_GEN_TIMERS) - 1;
2776     /*
2777      * According to Kyungwan, generic timer 0 and 8 are special
2778      * timers. Remove timer 8 from the available gen timer list.
2779      * Jupiter testing shows timer won't trigger with timer 8.
2780      */
2781     ahp->ah_avail_gen_timers &= ~(1 << AR_GEN_TIMER_RESERVED);
2782
2783     if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
2784 #if ATH_SUPPORT_MCI
2785         if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_DISABLE_MCI)
2786         {
2787             p_cap->halMciSupport = AH_FALSE;
2788         }
2789         else
2790 #endif
2791         {
2792             p_cap->halMciSupport = (ahp->ah_enterprise_mode &
2793                             AR_ENT_OTP_49GHZ_DISABLE) ? AH_FALSE: AH_TRUE;
2794         }
2795         HALDEBUG(AH_NULL, HAL_DEBUG_UNMASKABLE,
2796                  "%s: (MCI) MCI support = %d\n",
2797                  __func__, p_cap->halMciSupport);
2798     }
2799     else {
2800         p_cap->halMciSupport = AH_FALSE;
2801     }
2802
2803     if (AR_SREV_JUPITER_20(ah)) {
2804         p_cap->halRadioRetentionSupport = AH_TRUE;
2805     } else {
2806         p_cap->halRadioRetentionSupport = AH_FALSE;
2807     }
2808
2809     p_cap->halAutoSleepSupport = AH_TRUE;
2810
2811     p_cap->halMbssidAggrSupport = AH_TRUE;
2812 //    p_cap->hal_proxy_sta_support = AH_TRUE;
2813
2814     /* XXX Mark it true after it is verfied as fixed */
2815     p_cap->hal4kbSplitTransSupport = AH_FALSE;
2816
2817     /* Read regulatory domain flag */
2818     if (AH_PRIVATE(ah)->ah_currentRDext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2819         /*
2820          * If REG_EXT_JAPAN_MIDBAND is set, turn on U1 EVEN, U2, and MIDBAND.
2821          */
2822         p_cap->halRegCap =
2823             AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2824             AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2825             AR_EEPROM_EEREGCAP_EN_KK_U2      |
2826             AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2827     } else {
2828         p_cap->halRegCap =
2829             AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2830     }
2831
2832     /* For AR9300 and above, midband channels are always supported */
2833     p_cap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2834
2835     p_cap->halNumAntCfg5GHz =
2836         ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ);
2837     p_cap->halNumAntCfg2GHz =
2838         ar9300_eeprom_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ);
2839
2840     /* STBC supported */
2841     p_cap->halRxStbcSupport = 1; /* number of streams for STBC recieve. */
2842     if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
2843         p_cap->halTxStbcSupport = 0;
2844     } else {
2845         p_cap->halTxStbcSupport = 1;
2846     }
2847
2848     p_cap->halEnhancedDmaSupport = AH_TRUE;
2849     p_cap->halEnhancedDfsSupport = AH_TRUE;
2850
2851     /*
2852      *  EV61133 (missing interrupts due to AR_ISR_RAC).
2853      *  Fixed in Osprey 2.0.
2854      */
2855     p_cap->halIsrRacSupport = AH_TRUE;
2856
2857     /* XXX FreeBSD won't support TKIP and WEP aggregation */
2858 #if 0
2859     p_cap->hal_wep_tkip_aggr_support = AH_TRUE;
2860     p_cap->hal_wep_tkip_aggr_num_tx_delim = 10;    /* TBD */
2861     p_cap->hal_wep_tkip_aggr_num_rx_delim = 10;    /* TBD */
2862     p_cap->hal_wep_tkip_max_ht_rate = 15;         /* TBD */
2863 #endif
2864
2865     /*
2866      * XXX FreeBSD won't need these; but eventually add them
2867      * and add the WARs - AGGR extra delim WAR is useful to know
2868      * about.
2869      */
2870 #if 0
2871     p_cap->hal_cfend_fix_support = AH_FALSE;
2872     p_cap->hal_aggr_extra_delim_war = AH_FALSE;
2873 #endif
2874     p_cap->halHasLongRxDescTsf = AH_TRUE;
2875 //    p_cap->hal_rx_desc_timestamp_bits = 32;
2876     p_cap->halRxTxAbortSupport = AH_TRUE;
2877     p_cap->hal_ani_poll_interval = AR9300_ANI_POLLINTERVAL;
2878     p_cap->hal_channel_switch_time_usec = AR9300_CHANNEL_SWITCH_TIME_USEC;
2879
2880     /* Transmit Beamforming supported, fill capabilities */
2881     p_cap->halPaprdEnabled = ar9300_eeprom_get(ahp, EEP_PAPRD_ENABLED);
2882     p_cap->halChanHalfRate =
2883         !(ahp->ah_enterprise_mode & AR_ENT_OTP_10MHZ_DISABLE);
2884     p_cap->halChanQuarterRate =
2885         !(ahp->ah_enterprise_mode & AR_ENT_OTP_5MHZ_DISABLE);
2886
2887     if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
2888         /* There is no AR_ENT_OTP_49GHZ_DISABLE feature in Jupiter, now the bit is used to disable BT. */
2889         p_cap->hal49GhzSupport = 1;
2890     } else {
2891         p_cap->hal49GhzSupport = !(ahp->ah_enterprise_mode & AR_ENT_OTP_49GHZ_DISABLE);
2892     }
2893
2894     if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah) || AR_SREV_APHRODITE(ah)) {
2895         /* LDPC supported */
2896         /* Poseidon doesn't support LDPC, or it will cause receiver CRC Error */
2897         p_cap->halLDPCSupport = AH_FALSE;
2898         /* PCI_E LCR offset */
2899         if (AR_SREV_POSEIDON(ah)) {
2900             p_cap->hal_pcie_lcr_offset = 0x80; /*for Poseidon*/
2901         }
2902         /*WAR method for APSM L0s with Poseidon 1.0*/
2903         if (AR_SREV_POSEIDON_10(ah)) {
2904             p_cap->hal_pcie_lcr_extsync_en = AH_TRUE;
2905         }
2906     } else {
2907         p_cap->halLDPCSupport = AH_TRUE;
2908     }
2909
2910     /* XXX is this a flag, or a chainmask number? */
2911     p_cap->halApmEnable = !! ar9300_eeprom_get(ahp, EEP_CHAIN_MASK_REDUCE);
2912 #if ATH_ANT_DIV_COMB
2913     if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) {
2914         if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) {
2915             u_int8_t ant_div_control1 =
2916                 ar9300_eeprom_get(ahp, EEP_ANTDIV_control);
2917             /* if enable_lnadiv is 0x1 and enable_fast_div is 0x1,
2918              * we enable the diversity-combining algorithm.
2919              */
2920             if ((ant_div_control1 >> 0x6) == 0x3) {
2921                 p_cap->halAntDivCombSupport = AH_TRUE;
2922             }
2923             p_cap->halAntDivCombSupportOrg = p_cap->halAntDivCombSupport;
2924         }
2925     }
2926 #endif /* ATH_ANT_DIV_COMB */
2927
2928     /*
2929      * FreeBSD: enable LNA mixing if the chip is Hornet or Poseidon.
2930      */
2931     if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON_11_OR_LATER(ah)) {
2932         p_cap->halRxUsingLnaMixing = AH_TRUE;
2933     }
2934
2935     /*
2936      * AR5416 and later NICs support MYBEACON filtering.
2937      */
2938     p_cap->halRxDoMyBeacon = AH_TRUE;
2939
2940 #if ATH_WOW_OFFLOAD
2941     if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
2942         p_cap->hal_wow_gtk_offload_support    = AH_TRUE;
2943         p_cap->hal_wow_arp_offload_support    = AH_TRUE;
2944         p_cap->hal_wow_ns_offload_support     = AH_TRUE;
2945         p_cap->hal_wow_4way_hs_wakeup_support = AH_TRUE;
2946         p_cap->hal_wow_acer_magic_support     = AH_TRUE;
2947         p_cap->hal_wow_acer_swka_support      = AH_TRUE;
2948     } else {
2949         p_cap->hal_wow_gtk_offload_support    = AH_FALSE;
2950         p_cap->hal_wow_arp_offload_support    = AH_FALSE;
2951         p_cap->hal_wow_ns_offload_support     = AH_FALSE;
2952         p_cap->hal_wow_4way_hs_wakeup_support = AH_FALSE;
2953         p_cap->hal_wow_acer_magic_support     = AH_FALSE;
2954         p_cap->hal_wow_acer_swka_support      = AH_FALSE;
2955     }
2956 #endif /* ATH_WOW_OFFLOAD */
2957
2958
2959     return AH_TRUE;
2960 #undef AR_KEYTABLE_SIZE
2961 }
2962
2963 #if 0
2964 static HAL_BOOL
2965 ar9300_get_chip_power_limits(struct ath_hal *ah, HAL_CHANNEL *chans,
2966     u_int32_t nchans)
2967 {
2968     struct ath_hal_9300 *ahp = AH9300(ah);
2969
2970     return ahp->ah_rf_hal.get_chip_power_lim(ah, chans, nchans);
2971 }
2972 #endif
2973 /* XXX FreeBSD */
2974
2975 static HAL_BOOL
2976 ar9300_get_chip_power_limits(struct ath_hal *ah,
2977     struct ieee80211_channel *chan)
2978 {
2979
2980         chan->ic_maxpower = AR9300_MAX_RATE_POWER;
2981         chan->ic_minpower = 0;
2982
2983         return AH_TRUE;
2984 }
2985
2986 /*
2987  * Disable PLL when in L0s as well as receiver clock when in L1.
2988  * This power saving option must be enabled through the Serdes.
2989  *
2990  * Programming the Serdes must go through the same 288 bit serial shift
2991  * register as the other analog registers.  Hence the 9 writes.
2992  *
2993  * XXX Clean up the magic numbers.
2994  */
2995 void
2996 ar9300_config_pci_power_save(struct ath_hal *ah, int restore, int power_off)
2997 {
2998     struct ath_hal_9300 *ahp = AH9300(ah);
2999     int i;
3000
3001     if (AH_PRIVATE(ah)->ah_ispcie != AH_TRUE) {
3002         return;
3003     }
3004
3005     /*
3006      * Increase L1 Entry Latency. Some WB222 boards don't have
3007      * this change in eeprom/OTP.
3008      */
3009     if (AR_SREV_JUPITER(ah)) {
3010         u_int32_t val = ah->ah_config.ath_hal_war70c;
3011         if ((val & 0xff000000) == 0x17000000) {
3012             val &= 0x00ffffff;
3013             val |= 0x27000000;
3014             OS_REG_WRITE(ah, 0x570c, val);
3015         }
3016     }
3017
3018     /* Do not touch SERDES registers */
3019     if (ah->ah_config.ath_hal_pcie_power_save_enable == 2) {
3020         return;
3021     }
3022
3023     /* Nothing to do on restore for 11N */
3024     if (!restore) {
3025         /* set bit 19 to allow forcing of pcie core into L1 state */
3026         OS_REG_SET_BIT(ah,
3027             AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), AR_PCIE_PM_CTRL_ENA);
3028
3029         /*
3030          * Set PCIE workaround config only if requested, else use the reset
3031          * value of this register.
3032          */
3033         if (ah->ah_config.ath_hal_pcie_waen) {
3034             OS_REG_WRITE(ah,
3035                 AR_HOSTIF_REG(ah, AR_WA),
3036                 ah->ah_config.ath_hal_pcie_waen);
3037         } else {
3038             /* Set Bits 17 and 14 in the AR_WA register. */
3039             OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val);
3040         }
3041     }
3042
3043     /* Configure PCIE after Ini init. SERDES values now come from ini file */
3044     if (ah->ah_config.ath_hal_pcie_ser_des_write) {
3045         if (power_off) {
3046             for (i = 0; i < ahp->ah_ini_pcie_serdes.ia_rows; i++) {
3047                 OS_REG_WRITE(ah,
3048                     INI_RA(&ahp->ah_ini_pcie_serdes, i, 0),
3049                     INI_RA(&ahp->ah_ini_pcie_serdes, i, 1));
3050             }
3051         } else {
3052             for (i = 0; i < ahp->ah_ini_pcie_serdes_low_power.ia_rows; i++) {
3053                 OS_REG_WRITE(ah,
3054                     INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 0),
3055                     INI_RA(&ahp->ah_ini_pcie_serdes_low_power, i, 1));
3056             }
3057         }
3058     }
3059
3060 }
3061
3062 /*
3063  * Recipe from charles to turn off PCIe PHY in PCI mode for power savings
3064  */
3065 void
3066 ar9300_disable_pcie_phy(struct ath_hal *ah)
3067 {
3068     /* Osprey does not support PCI mode */
3069 }
3070
3071 static inline HAL_STATUS
3072 ar9300_init_mac_addr(struct ath_hal *ah)
3073 {
3074     u_int32_t sum;
3075     int i;
3076     u_int16_t eeval;
3077     struct ath_hal_9300 *ahp = AH9300(ah);
3078     u_int32_t EEP_MAC [] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
3079
3080     sum = 0;
3081     for (i = 0; i < 3; i++) {
3082         eeval = ar9300_eeprom_get(ahp, EEP_MAC[i]);
3083         sum += eeval;
3084         ahp->ah_macaddr[2*i] = eeval >> 8;
3085         ahp->ah_macaddr[2*i + 1] = eeval & 0xff;
3086     }
3087     if (sum == 0 || sum == 0xffff*3) {
3088         HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: mac address read failed: %s\n",
3089             __func__, ath_hal_ether_sprintf(ahp->ah_macaddr));
3090         return HAL_EEBADMAC;
3091     }
3092
3093     return HAL_OK;
3094 }
3095
3096 /*
3097  * Code for the "real" chip i.e. non-emulation. Review and revisit
3098  * when actual hardware is at hand.
3099  */
3100 static inline HAL_STATUS
3101 ar9300_hw_attach(struct ath_hal *ah)
3102 {
3103     HAL_STATUS ecode;
3104
3105     if (!ar9300_chip_test(ah)) {
3106         HALDEBUG(ah, HAL_DEBUG_REGIO,
3107             "%s: hardware self-test failed\n", __func__);
3108         return HAL_ESELFTEST;
3109     }
3110
3111     ath_hal_printf(ah, "%s: calling ar9300_eeprom_attach\n", __func__);
3112     ecode = ar9300_eeprom_attach(ah);
3113     ath_hal_printf(ah, "%s: ar9300_eeprom_attach returned %d\n", __func__, ecode);
3114     if (ecode != HAL_OK) {
3115         return ecode;
3116     }
3117     if (!ar9300_rf_attach(ah, &ecode)) {
3118         HALDEBUG(ah, HAL_DEBUG_RESET, "%s: RF setup failed, status %u\n",
3119             __func__, ecode);
3120     }
3121
3122     if (ecode != HAL_OK) {
3123         return ecode;
3124     }
3125     ar9300_ani_attach(ah);
3126
3127     return HAL_OK;
3128 }
3129
3130 static inline void
3131 ar9300_hw_detach(struct ath_hal *ah)
3132 {
3133     /* XXX EEPROM allocated state */
3134     ar9300_ani_detach(ah);
3135 }
3136
3137 static int16_t
3138 ar9300_get_nf_adjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
3139 {
3140     return 0;
3141 }
3142
3143 void
3144 ar9300_set_immunity(struct ath_hal *ah, HAL_BOOL enable)
3145 {
3146     struct ath_hal_9300 *ahp = AH9300(ah);
3147     u_int32_t m1_thresh_low = enable ? 127 : ahp->ah_immunity_vals[0],
3148               m2_thresh_low = enable ? 127 : ahp->ah_immunity_vals[1],
3149               m1_thresh = enable ? 127 : ahp->ah_immunity_vals[2],
3150               m2_thresh = enable ? 127 : ahp->ah_immunity_vals[3],
3151               m2_count_thr = enable ? 31 : ahp->ah_immunity_vals[4],
3152               m2_count_thr_low = enable ? 63 : ahp->ah_immunity_vals[5];
3153
3154     if (ahp->ah_immunity_on == enable) {
3155         return;
3156     }
3157
3158     ahp->ah_immunity_on = enable;
3159
3160     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3161                      AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1_thresh_low);
3162     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3163                      AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2_thresh_low);
3164     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3165                      AR_PHY_SFCORR_M1_THRESH, m1_thresh);
3166     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3167                      AR_PHY_SFCORR_M2_THRESH, m2_thresh);
3168     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
3169                      AR_PHY_SFCORR_M2COUNT_THR, m2_count_thr);
3170     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
3171                      AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2_count_thr_low);
3172
3173     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3174                      AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1_thresh_low);
3175     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3176                      AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2_thresh_low);
3177     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3178                      AR_PHY_SFCORR_EXT_M1_THRESH, m1_thresh);
3179     OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
3180                      AR_PHY_SFCORR_EXT_M2_THRESH, m2_thresh);
3181
3182     if (!enable) {
3183         OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
3184                        AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
3185     } else {
3186         OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
3187                        AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
3188     }
3189 }
3190
3191 /* XXX FreeBSD: I'm not sure how to implement this.. */
3192 #if 0
3193 int
3194 ar9300_get_cal_intervals(struct ath_hal *ah, HAL_CALIBRATION_TIMER **timerp,
3195     HAL_CAL_QUERY query)
3196 {
3197 #define AR9300_IS_CHAIN_RX_IQCAL_INVALID(_ah, _reg) \
3198     ((OS_REG_READ((_ah), _reg) & 0x3fff) == 0)
3199 #define AR9300_IS_RX_IQCAL_DISABLED(_ah) \
3200     (!(OS_REG_READ((_ah), AR_PHY_RX_IQCAL_CORR_B0) & \
3201     AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE))
3202 /* Avoid comilation warnings. Variables are not used when EMULATION. */
3203     struct ath_hal_9300 *ahp = AH9300(ah);
3204     u_int8_t rxchainmask = ahp->ah_rx_chainmask, i;
3205     int rx_iqcal_invalid = 0, num_chains = 0;
3206     static const u_int32_t offset_array[3] = {
3207         AR_PHY_RX_IQCAL_CORR_B0,
3208         AR_PHY_RX_IQCAL_CORR_B1,
3209         AR_PHY_RX_IQCAL_CORR_B2};
3210
3211     *timerp = ar9300_cals;
3212
3213     switch (query) {
3214     case HAL_QUERY_CALS:
3215         return AR9300_NUM_CAL_TYPES;
3216     case HAL_QUERY_RERUN_CALS:
3217         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
3218             if (rxchainmask & (1 << i)) {
3219                 num_chains++;
3220             }
3221         }
3222         for (i = 0; i < num_chains; i++) {
3223             if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
3224                 HALASSERT(num_chains == 0x1);
3225             }
3226             if (AR9300_IS_CHAIN_RX_IQCAL_INVALID(ah, offset_array[i])) {
3227                 rx_iqcal_invalid = 1;
3228             }
3229         }
3230         if (AR9300_IS_RX_IQCAL_DISABLED(ah)) {
3231             rx_iqcal_invalid = 1;
3232         }
3233
3234         return rx_iqcal_invalid;
3235     default:
3236         HALASSERT(0);
3237     }
3238     return 0;
3239 }
3240 #endif
3241
3242 #if ATH_TRAFFIC_FAST_RECOVER
3243 #define PLL3              0x16188
3244 #define PLL3_DO_MEAS_MASK 0x40000000
3245 #define PLL4              0x1618c
3246 #define PLL4_MEAS_DONE    0x8
3247 #define SQSUM_DVC_MASK    0x007ffff8
3248 unsigned long
3249 ar9300_get_pll3_sqsum_dvc(struct ath_hal *ah)
3250 {
3251     if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
3252         OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK)));
3253         OS_DELAY(100);
3254         OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK));
3255
3256         while ( (OS_REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
3257             OS_DELAY(100);
3258         }
3259
3260         return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3);
3261     } else {
3262         HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
3263                  "%s: unable to get pll3_sqsum_dvc\n",
3264                  __func__);
3265         return 0;
3266     }
3267 }
3268 #endif
3269
3270
3271 #define RX_GAIN_TABLE_LENGTH    128
3272 // this will be called if rfGainCAP is enabled and rfGainCAP setting is changed,
3273 // or rxGainTable setting is changed
3274 HAL_BOOL ar9300_rf_gain_cap_apply(struct ath_hal *ah, int is_2GHz)
3275 {
3276         int i, done = 0, i_rx_gain = 32;
3277     u_int32_t rf_gain_cap;
3278     u_int32_t rx_gain_value, a_Byte, rx_gain_value_caped;
3279         static u_int32_t  rx_gain_table[RX_GAIN_TABLE_LENGTH * 2][2];
3280     ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom;
3281     struct ath_hal_9300 *ahp = AH9300(ah);
3282
3283     if ( !((eep->base_eep_header.misc_configuration & 0x80) >> 7) )
3284         return AH_FALSE;
3285
3286     if (is_2GHz)
3287     {
3288         rf_gain_cap = (u_int32_t) eep->modal_header_2g.rf_gain_cap;
3289     }
3290     else
3291     {
3292         rf_gain_cap = (u_int32_t) eep->modal_header_5g.rf_gain_cap;
3293         }
3294
3295         if (rf_gain_cap == 0)
3296         return AH_FALSE;
3297
3298         for (i = 0; i< RX_GAIN_TABLE_LENGTH * 2; i++)
3299         {
3300         if (AR_SREV_AR9580(ah))
3301         {
3302             // BB_rx_ocgain2
3303             i_rx_gain = 128 + 32;
3304             switch (ar9300_rx_gain_index_get(ah))
3305             {
3306             case 0:
3307                 rx_gain_table[i][0] =
3308                                         ar9300_common_rx_gain_table_ar9580_1p0[i][0];
3309                 rx_gain_table[i][1] =
3310                                         ar9300_common_rx_gain_table_ar9580_1p0[i][1];
3311                 break;
3312             case 1:
3313                 rx_gain_table[i][0] =
3314                                         ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][0];
3315                 rx_gain_table[i][1] =
3316                                         ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0[i][1];
3317                 break;
3318                         }
3319         }
3320         else if (AR_SREV_OSPREY_22(ah))
3321         {
3322             i_rx_gain = 128 + 32;
3323             switch (ar9300_rx_gain_index_get(ah))
3324             {
3325             case 0:
3326                 rx_gain_table[i][0] = ar9300_common_rx_gain_table_osprey_2p2[i][0];
3327                 rx_gain_table[i][1] = ar9300_common_rx_gain_table_osprey_2p2[i][1];
3328                 break;
3329             case 1:
3330                 rx_gain_table[i][0] =
3331                                         ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][0];
3332                 rx_gain_table[i][1] =
3333                                         ar9300Common_wo_xlna_rx_gain_table_osprey_2p2[i][1];
3334                 break;
3335                         }
3336         }
3337         else
3338         {
3339             return AH_FALSE;
3340         }
3341     }
3342
3343     while (1)
3344         {
3345         rx_gain_value = rx_gain_table[i_rx_gain][1];
3346         rx_gain_value_caped = rx_gain_value;
3347         a_Byte = rx_gain_value & (0x000000FF);
3348         if (a_Byte>rf_gain_cap)
3349         {
3350                 rx_gain_value_caped = (rx_gain_value_caped &
3351                                 (0xFFFFFF00)) + rf_gain_cap;
3352         }
3353         a_Byte = rx_gain_value & (0x0000FF00);
3354         if ( a_Byte > ( rf_gain_cap << 8 ) )
3355         {
3356                 rx_gain_value_caped = (rx_gain_value_caped &
3357                                 (0xFFFF00FF)) + (rf_gain_cap<<8);
3358         }
3359         a_Byte = rx_gain_value & (0x00FF0000);
3360         if ( a_Byte > ( rf_gain_cap << 16 ) )
3361         {
3362                 rx_gain_value_caped = (rx_gain_value_caped &
3363                                 (0xFF00FFFF)) + (rf_gain_cap<<16);
3364         }
3365         a_Byte = rx_gain_value & (0xFF000000);
3366         if ( a_Byte > ( rf_gain_cap << 24 ) )
3367         {
3368                 rx_gain_value_caped = (rx_gain_value_caped &
3369                                 (0x00FFFFFF)) + (rf_gain_cap<<24);
3370         }
3371         else
3372         {
3373             done = 1;
3374         }
3375                 HALDEBUG(ah, HAL_DEBUG_RESET,
3376                         "%s: rx_gain_address: %x, rx_gain_value: %x     rx_gain_value_caped: %x\n",
3377                         __func__, rx_gain_table[i_rx_gain][0], rx_gain_value, rx_gain_value_caped);
3378         if (rx_gain_value_caped != rx_gain_value)
3379                 {
3380             rx_gain_table[i_rx_gain][1] = rx_gain_value_caped;
3381                 }
3382         if (done == 1)
3383             break;
3384         i_rx_gain ++;
3385         }
3386     INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain, rx_gain_table, ARRAY_LENGTH(rx_gain_table), 2);
3387     return AH_TRUE;
3388 }
3389
3390
3391 void ar9300_rx_gain_table_apply(struct ath_hal *ah)
3392 {
3393     struct ath_hal_9300 *ahp = AH9300(ah);
3394 //struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
3395     u_int32_t xlan_gpio_cfg;
3396     u_int8_t  i;
3397
3398     if (AR_SREV_OSPREY(ah) || AR_SREV_AR9580(ah))
3399     {
3400                 // this will be called if rxGainTable setting is changed
3401         if (ar9300_rf_gain_cap_apply(ah, 1))
3402             return;
3403         }
3404
3405     switch (ar9300_rx_gain_index_get(ah))
3406     {
3407     case 2:
3408         if (AR_SREV_JUPITER_10(ah)) {
3409             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3410                 ar9300_common_mixed_rx_gain_table_jupiter_1p0,
3411                 ARRAY_LENGTH(ar9300_common_mixed_rx_gain_table_jupiter_1p0), 2);
3412             break;
3413         }
3414         else if (AR_SREV_JUPITER_20(ah)) {
3415             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3416                 ar9300Common_mixed_rx_gain_table_jupiter_2p0,
3417                 ARRAY_LENGTH(ar9300Common_mixed_rx_gain_table_jupiter_2p0), 2);
3418             break;
3419         }
3420     case 0:
3421     default:
3422         if (AR_SREV_HORNET_12(ah)) {
3423             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3424                 ar9331_common_rx_gain_hornet1_2,
3425                 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_2), 2);
3426         } else if (AR_SREV_HORNET_11(ah)) {
3427             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3428                 ar9331_common_rx_gain_hornet1_1,
3429                 ARRAY_LENGTH(ar9331_common_rx_gain_hornet1_1), 2);
3430         } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3431             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3432                 ar9485_common_wo_xlna_rx_gain_poseidon1_1,
3433                 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2);
3434             /* XXX FreeBSD: this needs to be revisited!! */
3435             xlan_gpio_cfg = ah->ah_config.ath_hal_ext_lna_ctl_gpio;
3436             if (xlan_gpio_cfg) {
3437                 for (i = 0; i < 32; i++) {
3438                     if (xlan_gpio_cfg & (1 << i)) {
3439                         /*
3440                          * XXX FreeBSD: definitely make sure this
3441                          * results in the correct value being written
3442                          * to the hardware, or weird crap is very likely
3443                          * to occur!
3444                          */
3445                         ath_hal_gpioCfgOutput(ah, i,
3446                             HAL_GPIO_OUTPUT_MUX_PCIE_ATTENTION_LED);
3447                     }
3448                 }
3449             }
3450
3451         } else if (AR_SREV_POSEIDON(ah)) {
3452             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3453                 ar9485Common_wo_xlna_rx_gain_poseidon1_0,
3454                 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2);
3455         } else if (AR_SREV_JUPITER_10(ah)) {
3456             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3457                 ar9300_common_rx_gain_table_jupiter_1p0,
3458                 ARRAY_LENGTH(ar9300_common_rx_gain_table_jupiter_1p0), 2);
3459         } else if (AR_SREV_JUPITER_20(ah)) {
3460             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3461                 ar9300Common_rx_gain_table_jupiter_2p0,
3462                 ARRAY_LENGTH(ar9300Common_rx_gain_table_jupiter_2p0), 2);
3463         } else if (AR_SREV_AR9580(ah)) {
3464             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3465                 ar9300_common_rx_gain_table_ar9580_1p0,
3466                 ARRAY_LENGTH(ar9300_common_rx_gain_table_ar9580_1p0), 2);
3467         } else if (AR_SREV_WASP(ah)) {
3468             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3469                 ar9340Common_rx_gain_table_wasp_1p0,
3470                 ARRAY_LENGTH(ar9340Common_rx_gain_table_wasp_1p0), 2);
3471         } else if (AR_SREV_SCORPION(ah)) {
3472             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3473                 ar955xCommon_rx_gain_table_scorpion_1p0,
3474                 ARRAY_LENGTH(ar955xCommon_rx_gain_table_scorpion_1p0), 2);
3475             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
3476                 ar955xCommon_rx_gain_bounds_scorpion_1p0,
3477                 ARRAY_LENGTH(ar955xCommon_rx_gain_bounds_scorpion_1p0), 5);
3478         } else {
3479             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3480                 ar9300_common_rx_gain_table_osprey_2p2,
3481                 ARRAY_LENGTH(ar9300_common_rx_gain_table_osprey_2p2), 2);
3482         }
3483         break;
3484     case 1:
3485         if (AR_SREV_HORNET_12(ah)) {
3486             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3487                 ar9331_common_wo_xlna_rx_gain_hornet1_2,
3488                 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_2), 2);
3489         } else if (AR_SREV_HORNET_11(ah)) {
3490             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3491                 ar9331_common_wo_xlna_rx_gain_hornet1_1,
3492                 ARRAY_LENGTH(ar9331_common_wo_xlna_rx_gain_hornet1_1), 2);
3493         } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3494             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3495                 ar9485_common_wo_xlna_rx_gain_poseidon1_1,
3496                 ARRAY_LENGTH(ar9485_common_wo_xlna_rx_gain_poseidon1_1), 2);
3497         } else if (AR_SREV_POSEIDON(ah)) {
3498             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3499                 ar9485Common_wo_xlna_rx_gain_poseidon1_0,
3500                 ARRAY_LENGTH(ar9485Common_wo_xlna_rx_gain_poseidon1_0), 2);
3501         } else if (AR_SREV_JUPITER_10(ah)) {
3502             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3503                 ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0,
3504                 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_jupiter_1p0),
3505                 2);
3506         } else if (AR_SREV_JUPITER_20(ah)) {
3507             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3508                 ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0,
3509                 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_jupiter_2p0),
3510                 2);
3511         } else if (AR_SREV_APHRODITE(ah)) {
3512             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3513                 ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0,
3514                 ARRAY_LENGTH(ar956XCommon_wo_xlna_rx_gain_table_aphrodite_1p0),
3515                 2);
3516         } else if (AR_SREV_AR9580(ah)) {
3517             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3518                 ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0,
3519                 ARRAY_LENGTH(ar9300_common_wo_xlna_rx_gain_table_ar9580_1p0), 2);
3520         } else if (AR_SREV_WASP(ah)) {
3521             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3522                 ar9340Common_wo_xlna_rx_gain_table_wasp_1p0,
3523                 ARRAY_LENGTH(ar9340Common_wo_xlna_rx_gain_table_wasp_1p0), 2);
3524         } else if (AR_SREV_SCORPION(ah)) {
3525             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3526                 ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0,
3527                 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_table_scorpion_1p0), 2);
3528             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain_bounds,
3529                 ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0,
3530                 ARRAY_LENGTH(ar955xCommon_wo_xlna_rx_gain_bounds_scorpion_1p0), 5);
3531         } else {
3532             INIT_INI_ARRAY(&ahp->ah_ini_modes_rxgain,
3533                 ar9300Common_wo_xlna_rx_gain_table_osprey_2p2,
3534                 ARRAY_LENGTH(ar9300Common_wo_xlna_rx_gain_table_osprey_2p2), 2);
3535         }
3536         break;
3537     }
3538 }
3539
3540 void ar9300_tx_gain_table_apply(struct ath_hal *ah)
3541 {
3542     struct ath_hal_9300 *ahp = AH9300(ah);
3543
3544     switch (ar9300_tx_gain_index_get(ah))
3545     {
3546     case 0:
3547     default:
3548         if (AR_SREV_HORNET_12(ah)) {
3549             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3550                 ar9331_modes_lowest_ob_db_tx_gain_hornet1_2,
3551                 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_2), 5);
3552         } else if (AR_SREV_HORNET_11(ah)) {
3553             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3554                 ar9331_modes_lowest_ob_db_tx_gain_hornet1_1,
3555                 ARRAY_LENGTH(ar9331_modes_lowest_ob_db_tx_gain_hornet1_1), 5);
3556         } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3557             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3558                 ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1,
3559                 ARRAY_LENGTH(ar9485_modes_lowest_ob_db_tx_gain_poseidon1_1), 5);
3560         } else if (AR_SREV_POSEIDON(ah)) {
3561             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3562                 ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0,
3563                 ARRAY_LENGTH(ar9485Modes_lowest_ob_db_tx_gain_poseidon1_0), 5);
3564         } else if (AR_SREV_AR9580(ah)) {
3565             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3566                 ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0,
3567                 ARRAY_LENGTH(ar9300Modes_lowest_ob_db_tx_gain_table_ar9580_1p0),
3568                 5);
3569         } else if (AR_SREV_WASP(ah)) {
3570             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3571                 ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0,
3572                 ARRAY_LENGTH(ar9340Modes_lowest_ob_db_tx_gain_table_wasp_1p0),
3573                 5);
3574         } else if (AR_SREV_SCORPION(ah)) {
3575             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3576                 ar955xModes_xpa_tx_gain_table_scorpion_1p0,
3577                 ARRAY_LENGTH(ar955xModes_xpa_tx_gain_table_scorpion_1p0),
3578                 9);
3579         } else if (AR_SREV_JUPITER_10(ah)) {
3580             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3581                 ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0,
3582                 ARRAY_LENGTH(ar9300_modes_low_ob_db_tx_gain_table_jupiter_1p0),
3583                 5);
3584         } else if (AR_SREV_JUPITER_20(ah)) {
3585             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3586                 ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0,
3587                 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_jupiter_2p0),
3588                 5);
3589         } else if (AR_SREV_APHRODITE(ah)) {
3590             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3591                 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0,
3592                 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0),
3593                 5);
3594         } else {
3595             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3596                 ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2,
3597                 ARRAY_LENGTH(ar9300_modes_lowest_ob_db_tx_gain_table_osprey_2p2),
3598                 5);
3599         }
3600         break;
3601     case 1:
3602         if (AR_SREV_HORNET_12(ah)) {
3603             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3604                 ar9331_modes_high_ob_db_tx_gain_hornet1_2,
3605                 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_2), 5);
3606         } else if (AR_SREV_HORNET_11(ah)) {
3607             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3608                 ar9331_modes_high_ob_db_tx_gain_hornet1_1,
3609                 ARRAY_LENGTH(ar9331_modes_high_ob_db_tx_gain_hornet1_1), 5);
3610         } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3611             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3612                 ar9485_modes_high_ob_db_tx_gain_poseidon1_1,
3613                 ARRAY_LENGTH(ar9485_modes_high_ob_db_tx_gain_poseidon1_1), 5);
3614         } else if (AR_SREV_POSEIDON(ah)) {
3615             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3616                 ar9485Modes_high_ob_db_tx_gain_poseidon1_0,
3617                 ARRAY_LENGTH(ar9485Modes_high_ob_db_tx_gain_poseidon1_0), 5);
3618         } else if (AR_SREV_AR9580(ah)) {
3619             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3620                 ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0,
3621                 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_ar9580_1p0),
3622                 5);
3623         } else if (AR_SREV_WASP(ah)) {
3624             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3625                 ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0,
3626                 ARRAY_LENGTH(ar9340Modes_high_ob_db_tx_gain_table_wasp_1p0), 5);
3627         } else if (AR_SREV_SCORPION(ah)) {
3628             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3629                 ar955xModes_no_xpa_tx_gain_table_scorpion_1p0,
3630                 ARRAY_LENGTH(ar955xModes_no_xpa_tx_gain_table_scorpion_1p0), 9);
3631         } else if (AR_SREV_JUPITER_10(ah)) {
3632             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3633                 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0,
3634                 ARRAY_LENGTH(
3635                 ar9300_modes_high_ob_db_tx_gain_table_jupiter_1p0), 5);
3636         } else if (AR_SREV_JUPITER_20(ah)) {
3637             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3638                 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0,
3639                 ARRAY_LENGTH(
3640                 ar9300Modes_high_ob_db_tx_gain_table_jupiter_2p0), 5);
3641         } else if (AR_SREV_APHRODITE(ah)) {
3642             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3643                 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0,
3644                 ARRAY_LENGTH(
3645                 ar956XModes_high_ob_db_tx_gain_table_aphrodite_1p0), 5);
3646         } else {
3647             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3648                 ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2,
3649                 ARRAY_LENGTH(ar9300Modes_high_ob_db_tx_gain_table_osprey_2p2),
3650                 5);
3651         }
3652         break;
3653     case 2:
3654         if (AR_SREV_HORNET_12(ah)) {
3655             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3656                 ar9331_modes_low_ob_db_tx_gain_hornet1_2,
3657                 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_2), 5);
3658         } else if (AR_SREV_HORNET_11(ah)) {
3659             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3660                 ar9331_modes_low_ob_db_tx_gain_hornet1_1,
3661                 ARRAY_LENGTH(ar9331_modes_low_ob_db_tx_gain_hornet1_1), 5);
3662         } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3663             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3664                 ar9485_modes_low_ob_db_tx_gain_poseidon1_1,
3665                 ARRAY_LENGTH(ar9485_modes_low_ob_db_tx_gain_poseidon1_1), 5);
3666         } else if (AR_SREV_POSEIDON(ah)) {
3667             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3668                 ar9485Modes_low_ob_db_tx_gain_poseidon1_0,
3669                 ARRAY_LENGTH(ar9485Modes_low_ob_db_tx_gain_poseidon1_0), 5);
3670         } else if (AR_SREV_AR9580(ah)) {
3671             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3672                 ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0,
3673                 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_ar9580_1p0),
3674                 5);
3675         } else if (AR_SREV_WASP(ah)) {
3676             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3677                 ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0,
3678                 ARRAY_LENGTH(ar9340Modes_low_ob_db_tx_gain_table_wasp_1p0), 5);
3679         } else if (AR_SREV_APHRODITE(ah)) {
3680             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3681                 ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0,
3682                 ARRAY_LENGTH(ar956XModes_low_ob_db_tx_gain_table_aphrodite_1p0), 5);
3683         } else {
3684             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3685                 ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2,
3686                 ARRAY_LENGTH(ar9300Modes_low_ob_db_tx_gain_table_osprey_2p2),
3687                 5);
3688         }
3689         break;
3690     case 3:
3691         if (AR_SREV_HORNET_12(ah)) {
3692             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3693                 ar9331_modes_high_power_tx_gain_hornet1_2,
3694                 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_2), 5);
3695         } else if (AR_SREV_HORNET_11(ah)) {
3696             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3697                 ar9331_modes_high_power_tx_gain_hornet1_1,
3698                 ARRAY_LENGTH(ar9331_modes_high_power_tx_gain_hornet1_1), 5);
3699         } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3700             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3701                 ar9485_modes_high_power_tx_gain_poseidon1_1,
3702                 ARRAY_LENGTH(ar9485_modes_high_power_tx_gain_poseidon1_1), 5);
3703         } else if (AR_SREV_POSEIDON(ah)) {
3704             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3705                 ar9485Modes_high_power_tx_gain_poseidon1_0,
3706                 ARRAY_LENGTH(ar9485Modes_high_power_tx_gain_poseidon1_0), 5);
3707         } else if (AR_SREV_AR9580(ah)) {
3708             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3709                 ar9300Modes_high_power_tx_gain_table_ar9580_1p0,
3710                 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_ar9580_1p0),
3711                 5);
3712         } else if (AR_SREV_WASP(ah)) {
3713             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3714                 ar9340Modes_high_power_tx_gain_table_wasp_1p0,
3715                 ARRAY_LENGTH(ar9340Modes_high_power_tx_gain_table_wasp_1p0),
3716                 5);
3717         } else if (AR_SREV_APHRODITE(ah)) {
3718             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3719                 ar956XModes_high_power_tx_gain_table_aphrodite_1p0,
3720                 ARRAY_LENGTH(ar956XModes_high_power_tx_gain_table_aphrodite_1p0), 5);
3721         } else {
3722             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3723                 ar9300Modes_high_power_tx_gain_table_osprey_2p2,
3724                 ARRAY_LENGTH(ar9300Modes_high_power_tx_gain_table_osprey_2p2),
3725                 5);
3726         }
3727         break;
3728     case 4:
3729         if (AR_SREV_WASP(ah)) {
3730             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3731                 ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0,
3732                 ARRAY_LENGTH(ar9340Modes_mixed_ob_db_tx_gain_table_wasp_1p0),
3733                 5);
3734         } else if (AR_SREV_AR9580(ah)) {
3735             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3736                 ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0,
3737                 ARRAY_LENGTH(ar9300_modes_mixed_ob_db_tx_gain_table_ar9580_1p0),
3738                 5);
3739         } else {
3740             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3741                 ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2,
3742                 ARRAY_LENGTH(ar9300Modes_mixed_ob_db_tx_gain_table_osprey_2p2),
3743                  5);
3744         }
3745         break;
3746     case 5:
3747         /* HW Green TX */
3748         if (AR_SREV_POSEIDON(ah)) {
3749             if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3750                 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3751                     ar9485_modes_green_ob_db_tx_gain_poseidon1_1,
3752                     sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1) /
3753                     sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_1[0]), 5);
3754             } else {
3755                 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3756                     ar9485_modes_green_ob_db_tx_gain_poseidon1_0,
3757                     sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0) /
3758                     sizeof(ar9485_modes_green_ob_db_tx_gain_poseidon1_0[0]), 5);
3759             }
3760             ahp->ah_hw_green_tx_enable = 1;
3761         }
3762         else if (AR_SREV_WASP(ah)) {
3763             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3764             ar9340_modes_ub124_tx_gain_table_wasp_1p0,
3765             sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0) /
3766             sizeof(ar9340_modes_ub124_tx_gain_table_wasp_1p0[0]), 5);
3767         }
3768         else if (AR_SREV_AR9580(ah)) {
3769             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3770                 ar9300_modes_type5_tx_gain_table_ar9580_1p0,
3771                 ARRAY_LENGTH( ar9300_modes_type5_tx_gain_table_ar9580_1p0),
3772                 5);
3773         }
3774         else if (AR_SREV_OSPREY_22(ah)) {
3775             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3776                 ar9300_modes_number_5_tx_gain_table_osprey_2p2,
3777                 ARRAY_LENGTH( ar9300_modes_number_5_tx_gain_table_osprey_2p2),
3778                 5);
3779         }
3780         break;
3781         case 6:
3782         if (AR_SREV_WASP(ah)) {
3783             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3784             ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0,
3785             sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0) /
3786             sizeof(ar9340_modes_low_ob_db_and_spur_tx_gain_table_wasp_1p0[0]), 5);
3787         }
3788         /* HW Green TX */
3789         else if (AR_SREV_POSEIDON(ah)) {
3790             if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3791                 INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3792                 ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1,
3793                 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1) /
3794                 sizeof(ar9485_modes_green_spur_ob_db_tx_gain_poseidon1_1[0]),
3795                 5);
3796             }
3797             ahp->ah_hw_green_tx_enable = 1;
3798         }
3799         else if (AR_SREV_AR9580(ah)) {
3800             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3801                 ar9300_modes_type6_tx_gain_table_ar9580_1p0,
3802                 ARRAY_LENGTH( ar9300_modes_type6_tx_gain_table_ar9580_1p0),
3803                 5);
3804         }
3805         break;
3806         case 7:
3807                 if (AR_SREV_WASP(ah)) {
3808             INIT_INI_ARRAY(&ahp->ah_ini_modes_txgain,
3809             ar9340Modes_cus227_tx_gain_table_wasp_1p0,
3810             sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0) /
3811             sizeof(ar9340Modes_cus227_tx_gain_table_wasp_1p0[0]), 5);
3812                 }
3813                 break;
3814     }
3815 }
3816
3817 #if ATH_ANT_DIV_COMB
3818 void
3819 ar9300_ant_div_comb_get_config(struct ath_hal *ah,
3820     HAL_ANT_COMB_CONFIG *div_comb_conf)
3821 {
3822     u_int32_t reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3823     div_comb_conf->main_lna_conf =
3824         MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(reg_val);
3825     div_comb_conf->alt_lna_conf =
3826         MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(reg_val);
3827     div_comb_conf->fast_div_bias =
3828         MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(reg_val);
3829     if (AR_SREV_HORNET_11(ah)) {
3830         div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_1;
3831     } else if (AR_SREV_POSEIDON_11_OR_LATER(ah)) {
3832         div_comb_conf->antdiv_configgroup = HAL_ANTDIV_CONFIG_GROUP_2;
3833     } else {
3834         div_comb_conf->antdiv_configgroup = DEFAULT_ANTDIV_CONFIG_GROUP;
3835     }
3836
3837     /*
3838      * XXX TODO: allow the HAL to override the rssithres and fast_div_bias
3839      * values (eg CUS198.)
3840      */
3841 }
3842
3843 void
3844 ar9300_ant_div_comb_set_config(struct ath_hal *ah,
3845     HAL_ANT_COMB_CONFIG *div_comb_conf)
3846 {
3847     u_int32_t reg_val;
3848     struct ath_hal_9300 *ahp = AH9300(ah);
3849
3850     /* DO NOTHING when set to fixed antenna for manufacturing purpose */
3851     if (AR_SREV_POSEIDON(ah) && ( ahp->ah_diversity_control == HAL_ANT_FIXED_A
3852          || ahp->ah_diversity_control == HAL_ANT_FIXED_B)) {
3853         return;
3854     }
3855     reg_val = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3856     reg_val &= ~(MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MASK    |
3857                 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MASK     |
3858                 MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MASK       |
3859                 MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MASK     |
3860                 MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MASK );
3861     reg_val |=
3862         MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(
3863         div_comb_conf->main_gaintb);
3864     reg_val |=
3865         MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(
3866         div_comb_conf->alt_gaintb);
3867     reg_val |=
3868         MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(
3869         div_comb_conf->main_lna_conf);
3870     reg_val |=
3871         MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(
3872         div_comb_conf->alt_lna_conf);
3873     reg_val |=
3874         MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(
3875         div_comb_conf->fast_div_bias);
3876     OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, reg_val);
3877
3878 }
3879 #endif /* ATH_ANT_DIV_COMB */
3880
3881 static void
3882 ar9300_init_hostif_offsets(struct ath_hal *ah)
3883 {
3884     AR_HOSTIF_REG(ah, AR_RC) =
3885         AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL);
3886     AR_HOSTIF_REG(ah, AR_WA) =
3887         AR9300_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND);
3888     AR_HOSTIF_REG(ah, AR_PM_STATE) =
3889         AR9300_HOSTIF_OFFSET(HOST_INTF_PM_STATE);
3890     AR_HOSTIF_REG(ah, AR_H_INFOL) =
3891         AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOL);
3892     AR_HOSTIF_REG(ah, AR_H_INFOH) =
3893         AR9300_HOSTIF_OFFSET(HOST_INTF_CXPL_DEBUG_INFOH);
3894     AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) =
3895         AR9300_HOSTIF_OFFSET(HOST_INTF_PM_CTRL);
3896     AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) =
3897         AR9300_HOSTIF_OFFSET(HOST_INTF_TIMEOUT);
3898     AR_HOSTIF_REG(ah, AR_EEPROM) =
3899         AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_CTRL);
3900     AR_HOSTIF_REG(ah, AR_SREV) =
3901         AR9300_HOSTIF_OFFSET(HOST_INTF_SREV);
3902     AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) =
3903         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
3904     AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) =
3905         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
3906     AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) =
3907         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE);
3908     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) =
3909         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK);
3910     AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) =
3911         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK);
3912     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) =
3913         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
3914     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) =
3915         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
3916     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) =
3917         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE);
3918     AR_HOSTIF_REG(ah, AR_PCIE_SERDES) =
3919         AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_RW);
3920     AR_HOSTIF_REG(ah, AR_PCIE_SERDES2) =
3921         AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LOAD);
3922     AR_HOSTIF_REG(ah, AR_GPIO_OUT) =
3923         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT);
3924     AR_HOSTIF_REG(ah, AR_GPIO_IN) =
3925         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_IN);
3926     AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) =
3927         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE);
3928     AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) =
3929         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1);
3930     AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) =
3931         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR);
3932     AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) =
3933         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE);
3934     AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) =
3935         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1);
3936     AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) =
3937         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2);
3938     AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) =
3939         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1);
3940     AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) =
3941         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2);
3942     AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) =
3943         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3);
3944     AR_HOSTIF_REG(ah, AR_INPUT_STATE) =
3945         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE);
3946     AR_HOSTIF_REG(ah, AR_SPARE) =
3947         AR9300_HOSTIF_OFFSET(HOST_INTF_SPARE);
3948     AR_HOSTIF_REG(ah, AR_PCIE_CORE_RESET_EN) =
3949         AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_CORE_RST_EN);
3950     AR_HOSTIF_REG(ah, AR_CLKRUN) =
3951         AR9300_HOSTIF_OFFSET(HOST_INTF_CLKRUN);
3952     AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) =
3953         AR9300_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS);
3954     AR_HOSTIF_REG(ah, AR_OBS) =
3955         AR9300_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL);
3956     AR_HOSTIF_REG(ah, AR_RFSILENT) =
3957         AR9300_HOSTIF_OFFSET(HOST_INTF_RFSILENT);
3958     AR_HOSTIF_REG(ah, AR_GPIO_PDPU) =
3959         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_PDPU);
3960     AR_HOSTIF_REG(ah, AR_GPIO_DS) =
3961         AR9300_HOSTIF_OFFSET(HOST_INTF_GPIO_DS);
3962     AR_HOSTIF_REG(ah, AR_MISC) =
3963         AR9300_HOSTIF_OFFSET(HOST_INTF_MISC);
3964     AR_HOSTIF_REG(ah, AR_PCIE_MSI) =
3965         AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI);
3966 #if 0   /* Offsets are not defined in reg_map structure */
3967     AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_ACTIVE) =
3968         AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_ACTIVE);
3969     AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_PRIORITY) =
3970         AR9300_HOSTIF_OFFSET(HOST_INTF_TSF_SNAPSHOT_BT_PRIORITY);
3971     AR_HOSTIF_REG(ah, AR_TSF_SNAPSHOT_BT_CNTL) =
3972         AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TSF_SNAPSHOT_BT_CNTL);
3973 #endif
3974     AR_HOSTIF_REG(ah, AR_PCIE_PHY_LATENCY_NFTS_ADJ) =
3975         AR9300_HOSTIF_OFFSET(HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ);
3976     AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) =
3977         AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL);
3978     AR_HOSTIF_REG(ah, AR_TXAPSYNC) =
3979         AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC);
3980     AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) =
3981         AR9300_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR);
3982     AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) =
3983         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE);
3984     AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) =
3985         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE);
3986     AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) =
3987         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK);
3988     AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) =
3989         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK);
3990     AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) =
3991         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE);
3992     AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) =
3993         AR9300_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE);
3994 }
3995
3996 static void
3997 ar9340_init_hostif_offsets(struct ath_hal *ah)
3998 {
3999     AR_HOSTIF_REG(ah, AR_RC) =
4000         AR9340_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL);
4001     AR_HOSTIF_REG(ah, AR_WA) =
4002         AR9340_HOSTIF_OFFSET(HOST_INTF_WORK_AROUND);
4003     AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL) =
4004         AR9340_HOSTIF_OFFSET(HOST_INTF_PM_CTRL);
4005     AR_HOSTIF_REG(ah, AR_HOST_TIMEOUT) =
4006         AR9340_HOSTIF_OFFSET(HOST_INTF_TIMEOUT);
4007     AR_HOSTIF_REG(ah, AR_SREV) =
4008         AR9340_HOSTIF_OFFSET(HOST_INTF_SREV);
4009     AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE) =
4010         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4011     AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR) =
4012         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_CAUSE);
4013     AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE) =
4014         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_ENABLE);
4015     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK) =
4016         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_MASK);
4017     AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK) =
4018         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_SYNC_MASK);
4019     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE_CLR) =
4020         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4021     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE) =
4022         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_CAUSE);
4023     AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE) =
4024         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_ASYNC_ENABLE);
4025     AR_HOSTIF_REG(ah, AR_GPIO_OUT) =
4026         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUT);
4027     AR_HOSTIF_REG(ah, AR_GPIO_IN) =
4028         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_IN);
4029     AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT) =
4030         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE);
4031     AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT) =
4032         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OE1);
4033     AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL) =
4034         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INTR_POLAR);
4035     AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL) =
4036         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_VALUE);
4037     AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1) =
4038         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX1);
4039     AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2) =
4040         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_MUX2);
4041     AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1) =
4042         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX1);
4043     AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2) =
4044         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX2);
4045     AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3) =
4046         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_OUTPUT_MUX3);
4047     AR_HOSTIF_REG(ah, AR_INPUT_STATE) =
4048         AR9340_HOSTIF_OFFSET(HOST_INTF_GPIO_INPUT_STATE);
4049     AR_HOSTIF_REG(ah, AR_CLKRUN) =
4050         AR9340_HOSTIF_OFFSET(HOST_INTF_CLKRUN);
4051     AR_HOSTIF_REG(ah, AR_EEPROM_STATUS_DATA) =
4052         AR9340_HOSTIF_OFFSET(HOST_INTF_EEPROM_STS);
4053     AR_HOSTIF_REG(ah, AR_OBS) =
4054         AR9340_HOSTIF_OFFSET(HOST_INTF_OBS_CTRL);
4055     AR_HOSTIF_REG(ah, AR_RFSILENT) =
4056         AR9340_HOSTIF_OFFSET(HOST_INTF_RFSILENT);
4057     AR_HOSTIF_REG(ah, AR_MISC) =
4058         AR9340_HOSTIF_OFFSET(HOST_INTF_MISC);
4059     AR_HOSTIF_REG(ah, AR_PCIE_MSI) =
4060         AR9340_HOSTIF_OFFSET(HOST_INTF_PCIE_MSI);
4061     AR_HOSTIF_REG(ah, AR_TDMA_CCA_CNTL) =
4062         AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TDMA_CCA_CNTL);
4063     AR_HOSTIF_REG(ah, AR_TXAPSYNC) =
4064         AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXAPSYNC);
4065     AR_HOSTIF_REG(ah, AR_TXSYNC_INIT_SYNC_TMR) =
4066         AR9340_HOSTIF_OFFSET(HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR);
4067     AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_CAUSE) =
4068         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_CAUSE);
4069     AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE) =
4070         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_ENABLE);
4071     AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK) =
4072         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_MASK);
4073     AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK) =
4074         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_SYNC_MASK);
4075     AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_CAUSE) =
4076         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE);
4077     AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE) =
4078         AR9340_HOSTIF_OFFSET(HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE);
4079 }
4080
4081 /*
4082  * Host interface register offsets are different for Osprey and Wasp
4083  * and hence store the offsets in hal structure
4084  */
4085 static int ar9300_init_offsets(struct ath_hal *ah, u_int16_t devid)
4086 {
4087     if (devid == AR9300_DEVID_AR9340) {
4088         ar9340_init_hostif_offsets(ah);
4089     } else {
4090         ar9300_init_hostif_offsets(ah);
4091     }
4092     return 0;
4093 }
4094
4095
4096 static const char*
4097 ar9300_probe(uint16_t vendorid, uint16_t devid)
4098 {
4099     if (vendorid != ATHEROS_VENDOR_ID)
4100         return AH_NULL;
4101
4102     switch (devid) {
4103     case AR9300_DEVID_AR9380_PCIE: /* PCIE (Osprey) */
4104         return "Atheros AR938x";
4105     case AR9300_DEVID_AR9340: /* Wasp */
4106         return "Atheros AR934x";
4107     case AR9300_DEVID_AR9485_PCIE: /* Poseidon */
4108         return "Atheros AR9485";
4109     case AR9300_DEVID_AR9580_PCIE: /* Peacock */
4110         return "Atheros AR9580";
4111     case AR9300_DEVID_AR946X_PCIE: /* AR9462, AR9463, AR9482 */
4112         return "Atheros AR946x/AR948x";
4113     case AR9300_DEVID_AR9330: /* Hornet */
4114         return "Atheros AR933x";
4115     case AR9300_DEVID_QCA955X: /* Scorpion */
4116         return "Qualcomm Atheros QCA955x";
4117     case AR9300_DEVID_QCA9565: /* Aphrodite */
4118          return "Qualcomm Atheros AR9565";
4119     case AR9300_DEVID_AR1111_PCIE:
4120          return "Atheros AR1111";
4121     default:
4122         return AH_NULL;
4123     }
4124
4125     return AH_NULL;
4126 }
4127
4128 AH_CHIP(AR9300, ar9300_probe, ar9300_attach);
4129