2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * $FreeBSD: src/sys/pci/pci.c,v 1.141.2.15 2002/04/30 17:48:18 tmm Exp $
27 * $DragonFly: src/sys/bus/pci/pci.c,v 1.43 2007/11/24 03:42:24 sephe Exp $
34 #include "opt_compat_oldpci.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/fcntl.h>
42 #include <sys/kernel.h>
43 #include <sys/queue.h>
44 #include <sys/types.h>
49 #include <vm/vm_extern.h>
53 #include <machine/smp.h>
55 #include <bus/pci/i386/pci_cfgreg.h>
58 #include <sys/pciio.h>
61 #include "pci_private.h"
65 devclass_t pci_devclass;
66 const char *pcib_owner;
68 static void pci_read_extcap(device_t dev, pcicfgregs *cfg);
71 u_int32_t devid; /* Vendor/device of the card */
73 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
78 struct pci_quirk pci_quirks[] = {
80 * The Intel 82371AB and 82443MX has a map register at offset 0x90.
82 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
83 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
84 /* As does the Serverworks OSB4 (the SMBus mapping register) */
85 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
90 /* map register information */
91 #define PCI_MAPMEM 0x01 /* memory map */
92 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
93 #define PCI_MAPPORT 0x04 /* port map */
95 static STAILQ_HEAD(devlist, pci_devinfo) pci_devq;
96 u_int32_t pci_numdevs = 0;
97 static u_int32_t pci_generation = 0;
100 pci_find_bsf (u_int8_t bus, u_int8_t slot, u_int8_t func)
102 struct pci_devinfo *dinfo;
104 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
105 if ((dinfo->cfg.bus == bus) &&
106 (dinfo->cfg.slot == slot) &&
107 (dinfo->cfg.func == func)) {
108 return (dinfo->cfg.dev);
116 pci_find_device (u_int16_t vendor, u_int16_t device)
118 struct pci_devinfo *dinfo;
120 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
121 if ((dinfo->cfg.vendor == vendor) &&
122 (dinfo->cfg.device == device)) {
123 return (dinfo->cfg.dev);
130 /* return base address of memory or port map */
133 pci_mapbase(unsigned mapreg)
136 if ((mapreg & 0x01) == 0)
138 return (mapreg & ~mask);
141 /* return map type of memory or port map */
144 pci_maptype(unsigned mapreg)
146 static u_int8_t maptype[0x10] = {
147 PCI_MAPMEM, PCI_MAPPORT,
149 PCI_MAPMEM, PCI_MAPPORT,
151 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
152 PCI_MAPMEM|PCI_MAPMEMP, 0,
153 PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
157 return maptype[mapreg & 0x0f];
160 /* return log2 of map size decoded for memory or port map */
163 pci_mapsize(unsigned testval)
167 testval = pci_mapbase(testval);
170 while ((testval & 1) == 0)
179 /* return log2 of address range supported by map register */
182 pci_maprange(unsigned mapreg)
185 switch (mapreg & 0x07) {
201 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
204 pci_fixancient(pcicfgregs *cfg)
206 if (cfg->hdrtype != 0)
209 /* PCI to PCI bridges use header type 1 */
210 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
214 /* read config data specific to header type 1 device (PCI to PCI bridge) */
217 pci_readppb(device_t pcib, int b, int s, int f)
221 p = kmalloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
225 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_1, 2);
226 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_1, 2);
228 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_1, 1);
230 p->iobase = PCI_PPBIOBASE (PCIB_READ_CONFIG(pcib, b, s, f,
232 PCIB_READ_CONFIG(pcib, b, s, f,
234 p->iolimit = PCI_PPBIOLIMIT (PCIB_READ_CONFIG(pcib, b, s, f,
236 PCIB_READ_CONFIG(pcib, b, s, f,
237 PCIR_IOLIMITL_1, 1));
239 p->membase = PCI_PPBMEMBASE (0,
240 PCIB_READ_CONFIG(pcib, b, s, f,
242 p->memlimit = PCI_PPBMEMLIMIT (0,
243 PCIB_READ_CONFIG(pcib, b, s, f,
244 PCIR_MEMLIMIT_1, 2));
246 p->pmembase = PCI_PPBMEMBASE (
247 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEH_1, 4),
248 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMBASEL_1, 2));
250 p->pmemlimit = PCI_PPBMEMLIMIT (
251 (pci_addr_t)PCIB_READ_CONFIG(pcib, b, s, f,
253 PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PMLIMITL_1, 2));
258 /* read config data specific to header type 2 device (PCI to CardBus bridge) */
261 pci_readpcb(device_t pcib, int b, int s, int f)
265 p = kmalloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK | M_ZERO);
269 p->secstat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECSTAT_2, 2);
270 p->bridgectl = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_BRIDGECTL_2, 2);
272 p->seclat = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_SECLAT_2, 1);
274 p->membase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE0_2, 4);
275 p->memlimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT0_2, 4);
276 p->membase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMBASE1_2, 4);
277 p->memlimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_MEMLIMIT1_2, 4);
279 p->iobase0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE0_2, 4);
280 p->iolimit0 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT0_2, 4);
281 p->iobase1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOBASE1_2, 4);
282 p->iolimit1 = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_IOLIMIT1_2, 4);
284 p->pccardif = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_PCCARDIF_2, 4);
288 /* extract header type specific config data */
291 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
293 #define REG(n,w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
294 switch (cfg->hdrtype) {
296 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
297 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
298 cfg->nummaps = PCI_MAXMAPS_0;
301 cfg->subvendor = REG(PCIR_SUBVEND_1, 2);
302 cfg->subdevice = REG(PCIR_SUBDEV_1, 2);
303 cfg->secondarybus = REG(PCIR_SECBUS_1, 1);
304 cfg->subordinatebus = REG(PCIR_SUBBUS_1, 1);
305 cfg->nummaps = PCI_MAXMAPS_1;
306 cfg->hdrspec = pci_readppb(pcib, b, s, f);
309 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
310 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
311 cfg->secondarybus = REG(PCIR_SECBUS_2, 1);
312 cfg->subordinatebus = REG(PCIR_SUBBUS_2, 1);
313 cfg->nummaps = PCI_MAXMAPS_2;
314 cfg->hdrspec = pci_readpcb(pcib, b, s, f);
320 /* read configuration header into pcicfgrect structure */
323 pci_read_device(device_t pcib, int b, int s, int f, size_t size)
325 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
327 pcicfgregs *cfg = NULL;
328 struct pci_devinfo *devlist_entry;
329 struct devlist *devlist_head;
331 devlist_head = &pci_devq;
333 devlist_entry = NULL;
335 if (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVVENDOR, 4) != -1) {
337 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
338 if (devlist_entry == NULL)
341 cfg = &devlist_entry->cfg;
346 cfg->vendor = REG(PCIR_VENDOR, 2);
347 cfg->device = REG(PCIR_DEVICE, 2);
348 cfg->cmdreg = REG(PCIR_COMMAND, 2);
349 cfg->statreg = REG(PCIR_STATUS, 2);
350 cfg->baseclass = REG(PCIR_CLASS, 1);
351 cfg->subclass = REG(PCIR_SUBCLASS, 1);
352 cfg->progif = REG(PCIR_PROGIF, 1);
353 cfg->revid = REG(PCIR_REVID, 1);
354 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
355 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
356 cfg->lattimer = REG(PCIR_LATTIMER, 1);
357 cfg->intpin = REG(PCIR_INTPIN, 1);
358 cfg->intline = REG(PCIR_INTLINE, 1);
362 * If using the APIC the intpin is probably wrong, since it
363 * is often setup by the BIOS with the PIC in mind.
365 if (cfg->intpin != 0) {
368 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
370 /* PCI specific entry found in MP table */
371 if (airq != cfg->intline) {
372 undirect_pci_irq(cfg->intline);
377 * PCI interrupts might be redirected to the
378 * ISA bus according to some MP tables. Use the
379 * same methods as used by the ISA devices
380 * devices to find the proper IOAPIC int pin.
382 airq = isa_apic_irq(cfg->intline);
383 if ((airq >= 0) && (airq != cfg->intline)) {
384 /* XXX: undirect_pci_irq() ? */
385 undirect_isa_irq(cfg->intline);
392 cfg->mingnt = REG(PCIR_MINGNT, 1);
393 cfg->maxlat = REG(PCIR_MAXLAT, 1);
395 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
396 cfg->hdrtype &= ~PCIM_MFDEV;
399 pci_hdrtypedata(pcib, b, s, f, cfg);
400 pci_read_extcap(pcib, cfg);
402 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
404 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
405 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
406 devlist_entry->conf.pc_sel.pc_func = cfg->func;
407 devlist_entry->conf.pc_hdr = cfg->hdrtype;
409 devlist_entry->conf.pc_subvendor = cfg->subvendor;
410 devlist_entry->conf.pc_subdevice = cfg->subdevice;
411 devlist_entry->conf.pc_vendor = cfg->vendor;
412 devlist_entry->conf.pc_device = cfg->device;
414 devlist_entry->conf.pc_class = cfg->baseclass;
415 devlist_entry->conf.pc_subclass = cfg->subclass;
416 devlist_entry->conf.pc_progif = cfg->progif;
417 devlist_entry->conf.pc_revid = cfg->revid;
422 return (devlist_entry);
427 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
429 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
430 int ptr, nextptr, ptrptr;
432 if ((REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT) == 0) {
433 /* No capabilities */
437 switch (cfg->hdrtype) {
440 ptrptr = PCIR_CAP_PTR;
443 ptrptr = PCIR_CAP_PTR_2;
446 return; /* No capabilities support */
448 nextptr = REG(ptrptr, 1);
451 * Read capability entries.
454 /* "Next pointer" is only one byte */
455 KASSERT(nextptr <= 0xff, ("Illegal next pointer %d\n", nextptr));
460 * PCI local bus spec 3.0:
462 * "... The bottom two bits of all pointers are
463 * reserved and must be implemented as 00b
464 * although software must mask them to allow
465 * for future uses of these bits ..."
468 kprintf("Illegal PCI extended capability "
469 "offset, adjust 0x%02x -> 0x%02x\n",
470 nextptr, nextptr & ~0x3);
475 if (nextptr < 0x40) {
477 kprintf("Illegal PCI extended capability "
478 "offset 0x%02x", nextptr);
483 /* Find the next entry */
485 nextptr = REG(ptr + 1, 1);
487 /* Process this entry */
488 switch (REG(ptr, 1)) {
489 case PCIY_PMG: /* PCI power management */
490 if (cfg->pmgt.pp_cap == 0) {
491 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
493 pmgt->pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
494 pmgt->pp_status = ptr + PCIR_POWER_STATUS;
495 pmgt->pp_pmcsr = ptr + PCIR_POWER_PMCSR;
496 if ((nextptr - ptr) > PCIR_POWER_DATA)
497 pmgt->pp_data = ptr + PCIR_POWER_DATA;
507 /* free pcicfgregs structure and all depending data structures */
510 pci_freecfg(struct pci_devinfo *dinfo)
512 struct devlist *devlist_head;
514 devlist_head = &pci_devq;
516 if (dinfo->cfg.hdrspec != NULL)
517 kfree(dinfo->cfg.hdrspec, M_DEVBUF);
518 /* XXX this hasn't been tested */
519 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
520 kfree(dinfo, M_DEVBUF);
522 /* increment the generation count */
525 /* we're losing one device */
532 * PCI power manangement
535 pci_set_powerstate_method(device_t dev, device_t child, int state)
537 struct pci_devinfo *dinfo = device_get_ivars(child);
538 pcicfgregs *cfg = &dinfo->cfg;
539 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
543 if (pmgt->pp_cap != 0) {
544 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2) & ~PCIM_PSTAT_DMASK;
547 case PCI_POWERSTATE_D0:
548 status |= PCIM_PSTAT_D0;
550 case PCI_POWERSTATE_D1:
551 if (pmgt->pp_cap & PCIM_PCAP_D1SUPP) {
552 status |= PCIM_PSTAT_D1;
557 case PCI_POWERSTATE_D2:
558 if (pmgt->pp_cap & PCIM_PCAP_D2SUPP) {
559 status |= PCIM_PSTAT_D2;
564 case PCI_POWERSTATE_D3:
565 status |= PCIM_PSTAT_D3;
571 PCI_WRITE_CONFIG(dev, child, pmgt->pp_status, status, 2);
579 pci_get_powerstate_method(device_t dev, device_t child)
581 struct pci_devinfo *dinfo = device_get_ivars(child);
582 pcicfgregs *cfg = &dinfo->cfg;
583 struct pcicfg_pmgt *pmgt = &cfg->pmgt;
587 if (pmgt->pp_cap != 0) {
588 status = PCI_READ_CONFIG(dev, child, pmgt->pp_status, 2);
589 switch (status & PCIM_PSTAT_DMASK) {
591 result = PCI_POWERSTATE_D0;
594 result = PCI_POWERSTATE_D1;
597 result = PCI_POWERSTATE_D2;
600 result = PCI_POWERSTATE_D3;
603 result = PCI_POWERSTATE_UNKNOWN;
607 /* No support, device is always at D0 */
608 result = PCI_POWERSTATE_D0;
614 * Some convenience functions for PCI device drivers.
618 pci_set_command_bit(device_t dev, device_t child, u_int16_t bit)
622 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
624 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
628 pci_clear_command_bit(device_t dev, device_t child, u_int16_t bit)
632 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
634 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
638 pci_enable_busmaster_method(device_t dev, device_t child)
640 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
645 pci_disable_busmaster_method(device_t dev, device_t child)
647 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
652 pci_enable_io_method(device_t dev, device_t child, int space)
663 bit = PCIM_CMD_PORTEN;
667 bit = PCIM_CMD_MEMEN;
673 pci_set_command_bit(dev, child, bit);
674 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
677 device_printf(child, "failed to enable %s mapping!\n", error);
682 pci_disable_io_method(device_t dev, device_t child, int space)
693 bit = PCIM_CMD_PORTEN;
697 bit = PCIM_CMD_MEMEN;
703 pci_clear_command_bit(dev, child, bit);
704 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
706 device_printf(child, "failed to disable %s mapping!\n", error);
713 * This is the user interface to PCI configuration space.
717 pci_open(struct dev_open_args *ap)
719 if ((ap->a_oflags & FWRITE) && securelevel > 0) {
726 pci_close(struct dev_close_args *ap)
732 * Match a single pci_conf structure against an array of pci_match_conf
733 * structures. The first argument, 'matches', is an array of num_matches
734 * pci_match_conf structures. match_buf is a pointer to the pci_conf
735 * structure that will be compared to every entry in the matches array.
736 * This function returns 1 on failure, 0 on success.
739 pci_conf_match(struct pci_match_conf *matches, int num_matches,
740 struct pci_conf *match_buf)
744 if ((matches == NULL) || (match_buf == NULL) || (num_matches <= 0))
747 for (i = 0; i < num_matches; i++) {
749 * I'm not sure why someone would do this...but...
751 if (matches[i].flags == PCI_GETCONF_NO_MATCH)
755 * Look at each of the match flags. If it's set, do the
756 * comparison. If the comparison fails, we don't have a
757 * match, go on to the next item if there is one.
759 if (((matches[i].flags & PCI_GETCONF_MATCH_BUS) != 0)
760 && (match_buf->pc_sel.pc_bus != matches[i].pc_sel.pc_bus))
763 if (((matches[i].flags & PCI_GETCONF_MATCH_DEV) != 0)
764 && (match_buf->pc_sel.pc_dev != matches[i].pc_sel.pc_dev))
767 if (((matches[i].flags & PCI_GETCONF_MATCH_FUNC) != 0)
768 && (match_buf->pc_sel.pc_func != matches[i].pc_sel.pc_func))
771 if (((matches[i].flags & PCI_GETCONF_MATCH_VENDOR) != 0)
772 && (match_buf->pc_vendor != matches[i].pc_vendor))
775 if (((matches[i].flags & PCI_GETCONF_MATCH_DEVICE) != 0)
776 && (match_buf->pc_device != matches[i].pc_device))
779 if (((matches[i].flags & PCI_GETCONF_MATCH_CLASS) != 0)
780 && (match_buf->pc_class != matches[i].pc_class))
783 if (((matches[i].flags & PCI_GETCONF_MATCH_UNIT) != 0)
784 && (match_buf->pd_unit != matches[i].pd_unit))
787 if (((matches[i].flags & PCI_GETCONF_MATCH_NAME) != 0)
788 && (strncmp(matches[i].pd_name, match_buf->pd_name,
789 sizeof(match_buf->pd_name)) != 0))
799 * Locate the parent of a PCI device by scanning the PCI devlist
800 * and return the entry for the parent.
801 * For devices on PCI Bus 0 (the host bus), this is the PCI Host.
802 * For devices on secondary PCI busses, this is that bus' PCI-PCI Bridge.
806 pci_devlist_get_parent(pcicfgregs *cfg)
808 struct devlist *devlist_head;
809 struct pci_devinfo *dinfo;
810 pcicfgregs *bridge_cfg;
813 dinfo = STAILQ_FIRST(devlist_head = &pci_devq);
815 /* If the device is on PCI bus 0, look for the host */
817 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
818 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
819 bridge_cfg = &dinfo->cfg;
820 if (bridge_cfg->baseclass == PCIC_BRIDGE
821 && bridge_cfg->subclass == PCIS_BRIDGE_HOST
822 && bridge_cfg->bus == cfg->bus) {
828 /* If the device is not on PCI bus 0, look for the PCI-PCI bridge */
830 for (i = 0; (dinfo != NULL) && (i < pci_numdevs);
831 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
832 bridge_cfg = &dinfo->cfg;
833 if (bridge_cfg->baseclass == PCIC_BRIDGE
834 && bridge_cfg->subclass == PCIS_BRIDGE_PCI
835 && bridge_cfg->secondarybus == cfg->bus) {
845 pci_ioctl(struct dev_ioctl_args *ap)
852 if (!(ap->a_fflag & FWRITE))
858 struct pci_devinfo *dinfo;
859 struct pci_conf_io *cio;
860 struct devlist *devlist_head;
861 struct pci_match_conf *pattern_buf;
866 cio = (struct pci_conf_io *)ap->a_data;
872 * Hopefully the user won't pass in a null pointer, but it
873 * can't hurt to check.
881 * If the user specified an offset into the device list,
882 * but the list has changed since they last called this
883 * ioctl, tell them that the list has changed. They will
884 * have to get the list from the beginning.
886 if ((cio->offset != 0)
887 && (cio->generation != pci_generation)){
888 cio->num_matches = 0;
889 cio->status = PCI_GETCONF_LIST_CHANGED;
895 * Check to see whether the user has asked for an offset
896 * past the end of our list.
898 if (cio->offset >= pci_numdevs) {
899 cio->num_matches = 0;
900 cio->status = PCI_GETCONF_LAST_DEVICE;
905 /* get the head of the device queue */
906 devlist_head = &pci_devq;
909 * Determine how much room we have for pci_conf structures.
910 * Round the user's buffer size down to the nearest
911 * multiple of sizeof(struct pci_conf) in case the user
912 * didn't specify a multiple of that size.
914 iolen = min(cio->match_buf_len -
915 (cio->match_buf_len % sizeof(struct pci_conf)),
916 pci_numdevs * sizeof(struct pci_conf));
919 * Since we know that iolen is a multiple of the size of
920 * the pciconf union, it's okay to do this.
922 ionum = iolen / sizeof(struct pci_conf);
925 * If this test is true, the user wants the pci_conf
926 * structures returned to match the supplied entries.
928 if ((cio->num_patterns > 0)
929 && (cio->pat_buf_len > 0)) {
931 * pat_buf_len needs to be:
932 * num_patterns * sizeof(struct pci_match_conf)
933 * While it is certainly possible the user just
934 * allocated a large buffer, but set the number of
935 * matches correctly, it is far more likely that
936 * their kernel doesn't match the userland utility
937 * they're using. It's also possible that the user
938 * forgot to initialize some variables. Yes, this
939 * may be overly picky, but I hazard to guess that
940 * it's far more likely to just catch folks that
941 * updated their kernel but not their userland.
943 if ((cio->num_patterns *
944 sizeof(struct pci_match_conf)) != cio->pat_buf_len){
945 /* The user made a mistake, return an error*/
946 cio->status = PCI_GETCONF_ERROR;
947 kprintf("pci_ioctl: pat_buf_len %d != "
948 "num_patterns (%d) * sizeof(struct "
949 "pci_match_conf) (%d)\npci_ioctl: "
950 "pat_buf_len should be = %d\n",
951 cio->pat_buf_len, cio->num_patterns,
952 (int)sizeof(struct pci_match_conf),
953 (int)sizeof(struct pci_match_conf) *
955 kprintf("pci_ioctl: do your headers match your "
957 cio->num_matches = 0;
963 * Check the user's buffer to make sure it's readable.
965 if (!useracc((caddr_t)cio->patterns,
966 cio->pat_buf_len, VM_PROT_READ)) {
967 kprintf("pci_ioctl: pattern buffer %p, "
968 "length %u isn't user accessible for"
969 " READ\n", cio->patterns,
975 * Allocate a buffer to hold the patterns.
977 pattern_buf = kmalloc(cio->pat_buf_len, M_TEMP,
979 error = copyin(cio->patterns, pattern_buf,
983 num_patterns = cio->num_patterns;
985 } else if ((cio->num_patterns > 0)
986 || (cio->pat_buf_len > 0)) {
988 * The user made a mistake, spit out an error.
990 cio->status = PCI_GETCONF_ERROR;
991 cio->num_matches = 0;
992 kprintf("pci_ioctl: invalid GETCONF arguments\n");
999 * Make sure we can write to the match buffer.
1001 if (!useracc((caddr_t)cio->matches,
1002 cio->match_buf_len, VM_PROT_WRITE)) {
1003 kprintf("pci_ioctl: match buffer %p, length %u "
1004 "isn't user accessible for WRITE\n",
1005 cio->matches, cio->match_buf_len);
1011 * Go through the list of devices and copy out the devices
1012 * that match the user's criteria.
1014 for (cio->num_matches = 0, error = 0, i = 0,
1015 dinfo = STAILQ_FIRST(devlist_head);
1016 (dinfo != NULL) && (cio->num_matches < ionum)
1017 && (error == 0) && (i < pci_numdevs);
1018 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
1020 if (i < cio->offset)
1023 /* Populate pd_name and pd_unit */
1025 if (dinfo->cfg.dev && dinfo->conf.pd_name[0] == '\0')
1026 name = device_get_name(dinfo->cfg.dev);
1028 strncpy(dinfo->conf.pd_name, name,
1029 sizeof(dinfo->conf.pd_name));
1030 dinfo->conf.pd_name[PCI_MAXNAMELEN] = 0;
1031 dinfo->conf.pd_unit =
1032 device_get_unit(dinfo->cfg.dev);
1035 if ((pattern_buf == NULL) ||
1036 (pci_conf_match(pattern_buf, num_patterns,
1037 &dinfo->conf) == 0)) {
1040 * If we've filled up the user's buffer,
1041 * break out at this point. Since we've
1042 * got a match here, we'll pick right back
1043 * up at the matching entry. We can also
1044 * tell the user that there are more matches
1047 if (cio->num_matches >= ionum)
1050 error = copyout(&dinfo->conf,
1051 &cio->matches[cio->num_matches],
1052 sizeof(struct pci_conf));
1058 * Set the pointer into the list, so if the user is getting
1059 * n records at a time, where n < pci_numdevs,
1064 * Set the generation, the user will need this if they make
1065 * another ioctl call with offset != 0.
1067 cio->generation = pci_generation;
1070 * If this is the last device, inform the user so he won't
1071 * bother asking for more devices. If dinfo isn't NULL, we
1072 * know that there are more matches in the list because of
1073 * the way the traversal is done.
1076 cio->status = PCI_GETCONF_LAST_DEVICE;
1078 cio->status = PCI_GETCONF_MORE_DEVS;
1080 if (pattern_buf != NULL)
1081 kfree(pattern_buf, M_TEMP);
1086 io = (struct pci_io *)ap->a_data;
1087 switch(io->pi_width) {
1092 * Assume that the user-level bus number is
1093 * actually the pciN instance number. We map
1094 * from that to the real pcib+bus combination.
1096 pci = devclass_get_device(pci_devclass,
1100 * pci is the pci device and may contain
1101 * several children (for each function code).
1102 * The governing pci bus is the parent to
1107 pcib = device_get_parent(pci);
1108 b = pcib_get_bus(pcib);
1110 PCIB_READ_CONFIG(pcib,
1128 io = (struct pci_io *)ap->a_data;
1129 switch(io->pi_width) {
1134 * Assume that the user-level bus number is
1135 * actually the pciN instance number. We map
1136 * from that to the real pcib+bus combination.
1138 pci = devclass_get_device(pci_devclass,
1142 * pci is the pci device and may contain
1143 * several children (for each function code).
1144 * The governing pci bus is the parent to
1149 pcib = device_get_parent(pci);
1150 b = pcib_get_bus(pcib);
1151 PCIB_WRITE_CONFIG(pcib,
1179 static struct dev_ops pcic_ops = {
1180 { "pci", PCI_CDEV, 0 },
1182 .d_close = pci_close,
1183 .d_ioctl = pci_ioctl,
1189 * New style pci driver. Parent device is either a pci-host-bridge or a
1190 * pci-pci-bridge. Both kinds are represented by instances of pcib.
1193 pci_class_to_string(int baseclass)
1210 case PCIC_MULTIMEDIA:
1211 name = "MULTIMEDIA";
1219 case PCIC_SIMPLECOMM:
1220 name = "SIMPLECOMM";
1222 case PCIC_BASEPERIPH:
1223 name = "BASEPERIPH";
1231 case PCIC_PROCESSOR:
1234 case PCIC_SERIALBUS:
1243 case PCIC_SATELLITE:
1263 pci_print_verbose(struct pci_devinfo *dinfo)
1266 pcicfgregs *cfg = &dinfo->cfg;
1268 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
1269 cfg->vendor, cfg->device, cfg->revid);
1270 kprintf("\tbus=%d, slot=%d, func=%d\n",
1271 cfg->bus, cfg->slot, cfg->func);
1272 kprintf("\tclass=[%s]%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
1273 pci_class_to_string(cfg->baseclass),
1274 cfg->baseclass, cfg->subclass, cfg->progif,
1275 cfg->hdrtype, cfg->mfdev);
1276 kprintf("\tsubordinatebus=%x \tsecondarybus=%x\n",
1277 cfg->subordinatebus, cfg->secondarybus);
1279 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
1280 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
1281 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
1282 cfg->lattimer, cfg->lattimer * 30,
1283 cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
1284 #endif /* PCI_DEBUG */
1285 if (cfg->intpin > 0)
1286 kprintf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
1291 pci_porten(device_t pcib, int b, int s, int f)
1293 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1294 & PCIM_CMD_PORTEN) != 0;
1298 pci_memen(device_t pcib, int b, int s, int f)
1300 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
1301 & PCIM_CMD_MEMEN) != 0;
1305 * Add a resource based on a pci map register. Return 1 if the map
1306 * register is a 32bit map register or 2 if it is a 64bit register.
1309 pci_add_map(device_t pcib, int b, int s, int f, int reg,
1310 struct resource_list *rl)
1319 #ifdef PCI_ENABLE_IO_MODES
1324 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1326 if (map == 0 || map == 0xffffffff)
1327 return 1; /* skip invalid entry */
1329 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
1330 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
1331 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
1333 base = pci_mapbase(map);
1334 if (pci_maptype(map) & PCI_MAPMEM)
1335 type = SYS_RES_MEMORY;
1337 type = SYS_RES_IOPORT;
1338 ln2size = pci_mapsize(testval);
1339 ln2range = pci_maprange(testval);
1340 if (ln2range == 64) {
1341 /* Read the other half of a 64bit map register */
1342 base |= (u_int64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg+4, 4);
1346 * This code theoretically does the right thing, but has
1347 * undesirable side effects in some cases where
1348 * peripherals respond oddly to having these bits
1349 * enabled. Leave them alone by default.
1351 #ifdef PCI_ENABLE_IO_MODES
1352 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
1353 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1354 cmd |= PCIM_CMD_PORTEN;
1355 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1357 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
1358 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
1359 cmd |= PCIM_CMD_MEMEN;
1360 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
1363 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
1365 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
1369 resource_list_add(rl, type, reg,
1370 base, base + (1 << ln2size) - 1,
1374 kprintf("\tmap[%02x]: type %x, range %2d, base %08x, size %2d\n",
1375 reg, pci_maptype(base), ln2range,
1376 (unsigned int) base, ln2size);
1379 return (ln2range == 64) ? 2 : 1;
1382 #ifdef PCI_MAP_FIXUP
1384 * For ATA devices we need to decide early on what addressing mode to use.
1385 * Legacy demands that the primary and secondary ATA ports sits on the
1386 * same addresses that old ISA hardware did. This dictates that we use
1387 * those addresses and ignore the BARs if we cannot set PCI native
1391 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b, int s, int f,
1392 struct resource_list *rl)
1394 int rid, type, progif;
1396 /* if this device supports PCI native addressing use it */
1397 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1398 if ((progif &0x8a) == 0x8a) {
1399 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
1400 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
1401 kprintf("Trying ATA native PCI addressing mode\n");
1402 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
1407 * Because we return any preallocated resources for lazy
1408 * allocation for PCI devices in pci_alloc_resource(), we can
1409 * allocate our legacy resources here.
1411 progif = pci_read_config(dev, PCIR_PROGIF, 1);
1412 type = SYS_RES_IOPORT;
1413 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
1414 pci_add_map(pcib, b, s, f, PCIR_BAR(0), rl);
1415 pci_add_map(pcib, b, s, f, PCIR_BAR(1), rl);
1418 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
1419 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
1422 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
1423 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
1426 if (progif & PCIP_STORAGE_IDE_MODESEC) {
1427 pci_add_map(pcib, b, s, f, PCIR_BAR(2), rl);
1428 pci_add_map(pcib, b, s, f, PCIR_BAR(3), rl);
1431 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
1432 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
1435 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
1436 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
1439 pci_add_map(pcib, b, s, f, PCIR_BAR(4), rl);
1440 pci_add_map(pcib, b, s, f, PCIR_BAR(5), rl);
1442 #endif /* PCI_MAP_FIXUP */
1445 pci_add_resources(device_t pcib, device_t bus, device_t dev)
1447 struct pci_devinfo *dinfo = device_get_ivars(dev);
1448 pcicfgregs *cfg = &dinfo->cfg;
1449 struct resource_list *rl = &dinfo->resources;
1450 struct pci_quirk *q;
1452 #if 0 /* WILL BE USED WITH ADDITIONAL IMPORT FROM FREEBSD-5 XXX */
1459 #ifdef PCI_MAP_FIXUP
1460 /* atapci devices in legacy mode need special map treatment */
1461 if ((pci_get_class(dev) == PCIC_STORAGE) &&
1462 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
1463 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
1464 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
1465 !pci_read_config(dev, PCIR_BAR(2), 4))) )
1466 pci_ata_maps(pcib, bus, dev, b, s, f, rl);
1468 #endif /* PCI_MAP_FIXUP */
1469 for (i = 0; i < cfg->nummaps;) {
1470 i += pci_add_map(pcib, b, s, f, PCIR_BAR(i),rl);
1473 for (q = &pci_quirks[0]; q->devid; q++) {
1474 if (q->devid == ((cfg->device << 16) | cfg->vendor)
1475 && q->type == PCI_QUIRK_MAP_REG)
1476 pci_add_map(pcib, b, s, f, q->arg1, rl);
1479 if (cfg->intpin > 0 && cfg->intline != 255)
1480 resource_list_add(rl, SYS_RES_IRQ, 0,
1481 cfg->intline, cfg->intline, 1);
1485 pci_add_children(device_t dev, int busno, size_t dinfo_size)
1487 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
1488 device_t pcib = device_get_parent(dev);
1489 struct pci_devinfo *dinfo;
1491 int s, f, pcifunchigh;
1494 KKASSERT(dinfo_size >= sizeof(struct pci_devinfo));
1496 maxslots = PCIB_MAXSLOTS(pcib);
1498 for (s = 0; s <= maxslots; s++) {
1501 hdrtype = REG(PCIR_HDRTYPE, 1);
1502 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
1504 if (hdrtype & PCIM_MFDEV)
1505 pcifunchigh = PCI_FUNCMAX;
1506 for (f = 0; f <= pcifunchigh; f++) {
1507 dinfo = pci_read_device(pcib, busno, s, f, dinfo_size);
1508 if (dinfo != NULL) {
1509 pci_add_child(dev, dinfo);
1517 * The actual PCI child that we add has a NULL driver whos parent
1518 * device will be "pci". The child contains the ivars, not the parent.
1521 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
1525 pcib = device_get_parent(bus);
1526 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
1527 device_set_ivars(dinfo->cfg.dev, dinfo);
1528 pci_add_resources(pcib, bus, dinfo->cfg.dev);
1529 pci_print_verbose(dinfo);
1533 * Probe the PCI bus. Note: probe code is not supposed to add children
1537 pci_probe(device_t dev)
1539 device_set_desc(dev, "PCI bus");
1541 /* Allow other subclasses to override this driver */
1546 pci_attach(device_t dev)
1549 int lunit = device_get_unit(dev);
1551 dev_ops_add(&pcic_ops, -1, lunit);
1552 make_dev(&pcic_ops, lunit, UID_ROOT, GID_WHEEL, 0644, "pci%d", lunit);
1555 * Since there can be multiple independantly numbered PCI
1556 * busses on some large alpha systems, we can't use the unit
1557 * number to decide what bus we are probing. We ask the parent
1558 * pcib what our bus number is.
1560 * pcib_get_bus() must act on the pci bus device, not on the pci
1561 * device, because it uses badly hacked nexus-based ivars to
1562 * store and retrieve the physical bus number. XXX
1564 busno = pcib_get_bus(device_get_parent(dev));
1566 device_printf(dev, "pci_attach() physical bus=%d\n", busno);
1568 pci_add_children(dev, busno, sizeof(struct pci_devinfo));
1570 return (bus_generic_attach(dev));
1574 pci_print_resources(struct resource_list *rl, const char *name, int type,
1577 struct resource_list_entry *rle;
1578 int printed, retval;
1582 /* Yes, this is kinda cheating */
1583 SLIST_FOREACH(rle, rl, link) {
1584 if (rle->type == type) {
1586 retval += kprintf(" %s ", name);
1587 else if (printed > 0)
1588 retval += kprintf(",");
1590 retval += kprintf(format, rle->start);
1591 if (rle->count > 1) {
1592 retval += kprintf("-");
1593 retval += kprintf(format, rle->start +
1602 pci_print_child(device_t dev, device_t child)
1604 struct pci_devinfo *dinfo;
1605 struct resource_list *rl;
1609 dinfo = device_get_ivars(child);
1611 rl = &dinfo->resources;
1613 retval += bus_print_child_header(dev, child);
1615 retval += pci_print_resources(rl, "port", SYS_RES_IOPORT, "%#lx");
1616 retval += pci_print_resources(rl, "mem", SYS_RES_MEMORY, "%#lx");
1617 retval += pci_print_resources(rl, "irq", SYS_RES_IRQ, "%ld");
1618 if (device_get_flags(dev))
1619 retval += kprintf(" flags %#x", device_get_flags(dev));
1621 retval += kprintf(" at device %d.%d", pci_get_slot(child),
1622 pci_get_function(child));
1624 retval += bus_print_child_footer(dev, child);
1630 pci_probe_nomatch(device_t dev, device_t child)
1632 struct pci_devinfo *dinfo;
1638 dinfo = device_get_ivars(child);
1640 desc = pci_ata_match(child);
1641 if (!desc) desc = pci_usb_match(child);
1642 if (!desc) desc = pci_vga_match(child);
1643 if (!desc) desc = pci_chip_match(child);
1645 desc = "unknown card";
1648 device_printf(dev, "<%s>", desc);
1649 if (bootverbose || unknown) {
1650 kprintf(" (vendor=0x%04x, dev=0x%04x)",
1654 kprintf(" at %d.%d",
1655 pci_get_slot(child),
1656 pci_get_function(child));
1657 if (cfg->intpin > 0 && cfg->intline != 255) {
1658 kprintf(" irq %d", cfg->intline);
1666 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1668 struct pci_devinfo *dinfo;
1671 dinfo = device_get_ivars(child);
1675 case PCI_IVAR_SUBVENDOR:
1676 *result = cfg->subvendor;
1678 case PCI_IVAR_SUBDEVICE:
1679 *result = cfg->subdevice;
1681 case PCI_IVAR_VENDOR:
1682 *result = cfg->vendor;
1684 case PCI_IVAR_DEVICE:
1685 *result = cfg->device;
1687 case PCI_IVAR_DEVID:
1688 *result = (cfg->device << 16) | cfg->vendor;
1690 case PCI_IVAR_CLASS:
1691 *result = cfg->baseclass;
1693 case PCI_IVAR_SUBCLASS:
1694 *result = cfg->subclass;
1696 case PCI_IVAR_PROGIF:
1697 *result = cfg->progif;
1699 case PCI_IVAR_REVID:
1700 *result = cfg->revid;
1702 case PCI_IVAR_INTPIN:
1703 *result = cfg->intpin;
1706 *result = cfg->intline;
1712 *result = cfg->slot;
1714 case PCI_IVAR_FUNCTION:
1715 *result = cfg->func;
1717 case PCI_IVAR_SECONDARYBUS:
1718 *result = cfg->secondarybus;
1720 case PCI_IVAR_SUBORDINATEBUS:
1721 *result = cfg->subordinatebus;
1723 case PCI_IVAR_ETHADDR:
1725 * The generic accessor doesn't deal with failure, so
1726 * we set the return value, then return an error.
1737 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1739 struct pci_devinfo *dinfo;
1742 dinfo = device_get_ivars(child);
1746 case PCI_IVAR_SUBVENDOR:
1747 case PCI_IVAR_SUBDEVICE:
1748 case PCI_IVAR_VENDOR:
1749 case PCI_IVAR_DEVICE:
1750 case PCI_IVAR_DEVID:
1751 case PCI_IVAR_CLASS:
1752 case PCI_IVAR_SUBCLASS:
1753 case PCI_IVAR_PROGIF:
1754 case PCI_IVAR_REVID:
1755 case PCI_IVAR_INTPIN:
1759 case PCI_IVAR_FUNCTION:
1760 case PCI_IVAR_ETHADDR:
1761 return EINVAL; /* disallow for now */
1763 case PCI_IVAR_SECONDARYBUS:
1764 cfg->secondarybus = value;
1766 case PCI_IVAR_SUBORDINATEBUS:
1767 cfg->subordinatebus = value;
1775 #ifdef PCI_MAP_FIXUP
1776 static struct resource *
1777 pci_alloc_map(device_t dev, device_t child, int type, int *rid, u_long start,
1778 u_long end, u_long count, u_int flags)
1780 struct pci_devinfo *dinfo = device_get_ivars(child);
1781 struct resource_list *rl = &dinfo->resources;
1782 struct resource_list_entry *rle;
1783 struct resource *res;
1784 uint32_t map, testval;
1788 * Weed out the bogons, and figure out how large the BAR/map
1789 * is. BARs that read back 0 here are bogus and unimplemented.
1791 * Note: atapci in legacy mode are special and handled elsewhere
1792 * in the code. If you have an atapci device in legacy mode and
1793 * it fails here, that other code is broken.
1796 map = pci_read_config(child, *rid, 4);
1797 pci_write_config(child, *rid, 0xffffffff, 4);
1798 testval = pci_read_config(child, *rid, 4);
1799 if (pci_mapbase(testval) == 0)
1801 if (pci_maptype(testval) & PCI_MAPMEM) {
1802 if (type != SYS_RES_MEMORY) {
1804 device_printf(dev, "child %s requested type %d"
1805 " for rid %#x, but the BAR says "
1807 device_get_nameunit(child), type,
1812 if (type != SYS_RES_IOPORT) {
1814 device_printf(dev, "child %s requested type %d"
1815 " for rid %#x, but the BAR says "
1816 "it is an ioport\n",
1817 device_get_nameunit(child), type,
1823 * For real BARs, we need to override the size that
1824 * the driver requests, because that's what the BAR
1825 * actually uses and we would otherwise have a
1826 * situation where we might allocate the excess to
1827 * another driver, which won't work.
1829 mapsize = pci_mapsize(testval);
1830 count = 1 << mapsize;
1831 if (RF_ALIGNMENT(flags) < mapsize)
1832 flags = (flags & ~RF_ALIGNMENT_MASK) |
1833 RF_ALIGNMENT_LOG2(mapsize);
1835 * Allocate enough resource, and then write back the
1836 * appropriate BAR for that resource.
1838 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
1839 start, end, count, flags);
1841 device_printf(child, "%#lx bytes at rid %#x res %d failed "
1842 "(%#lx, %#lx)\n", count, *rid, type, start, end);
1845 resource_list_add(rl, type, *rid, start, end, count);
1846 rle = resource_list_find(rl, type, *rid);
1848 panic("pci_alloc_map: unexpectedly can't find resource.");
1850 rle->start = rman_get_start(res);
1851 rle->end = rman_get_end(res);
1854 device_printf(child, "lazy allocation of %#lx bytes rid %#x "
1855 "type %d at %#lx\n", count, *rid, type,
1856 rman_get_start(res));
1857 map = rman_get_start(res);
1859 pci_write_config(child, *rid, map, 4);
1862 #endif /* PCI_MAP_FIXUP */
1865 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
1866 u_long start, u_long end, u_long count, u_int flags)
1868 struct pci_devinfo *dinfo = device_get_ivars(child);
1869 struct resource_list *rl = &dinfo->resources;
1870 #ifdef PCI_MAP_FIXUP
1871 struct resource_list_entry *rle;
1872 #endif /* PCI_MAP_FIXUP */
1873 pcicfgregs *cfg = &dinfo->cfg;
1876 * Perform lazy resource allocation
1878 if (device_get_parent(child) == dev) {
1883 * If device doesn't have an interrupt routed, and is
1884 * deserving of an interrupt, try to assign it one.
1886 if ((cfg->intline == 255 || cfg->intline == 0) &&
1887 (cfg->intpin != 0) &&
1888 (start == 0) && (end == ~0UL)) {
1889 cfg->intline = PCIB_ROUTE_INTERRUPT(
1890 device_get_parent(dev), child,
1892 if (cfg->intline != 255) {
1893 pci_write_config(child, PCIR_INTLINE,
1895 resource_list_add(rl, SYS_RES_IRQ, 0,
1896 cfg->intline, cfg->intline, 1);
1901 case SYS_RES_IOPORT:
1903 case SYS_RES_MEMORY:
1904 if (*rid < PCIR_BAR(cfg->nummaps)) {
1906 * Enable the I/O mode. We should
1907 * also be assigning resources too
1908 * when none are present. The
1909 * resource_list_alloc kind of sorta does
1912 if (PCI_ENABLE_IO(dev, child, type))
1915 #ifdef PCI_MAP_FIXUP
1916 rle = resource_list_find(rl, type, *rid);
1918 return pci_alloc_map(dev, child, type, rid,
1919 start, end, count, flags);
1920 #endif /* PCI_MAP_FIXUP */
1923 #ifdef PCI_MAP_FIXUP
1925 * If we've already allocated the resource, then
1926 * return it now. But first we may need to activate
1927 * it, since we don't allocate the resource as active
1928 * above. Normally this would be done down in the
1929 * nexus, but since we short-circuit that path we have
1930 * to do its job here. Not sure if we should free the
1931 * resource if it fails to activate.
1933 * Note: this also finds and returns resources for
1934 * atapci devices in legacy mode as allocated in
1937 rle = resource_list_find(rl, type, *rid);
1938 if (rle != NULL && rle->res != NULL) {
1940 device_printf(child, "reserved %#lx bytes for "
1941 "rid %#x type %d at %#lx\n",
1942 rman_get_size(rle->res), *rid,
1943 type, rman_get_start(rle->res));
1944 if ((flags & RF_ACTIVE) &&
1945 bus_generic_activate_resource(dev, child, type,
1946 *rid, rle->res) != 0)
1950 #endif /* PCI_MAP_FIXUP */
1952 return resource_list_alloc(rl, dev, child, type, rid,
1953 start, end, count, flags);
1957 pci_release_resource(device_t dev, device_t child, int type, int rid,
1960 struct pci_devinfo *dinfo = device_get_ivars(child);
1961 struct resource_list *rl = &dinfo->resources;
1963 return resource_list_release(rl, dev, child, type, rid, r);
1967 pci_set_resource(device_t dev, device_t child, int type, int rid,
1968 u_long start, u_long count)
1970 struct pci_devinfo *dinfo = device_get_ivars(child);
1971 struct resource_list *rl = &dinfo->resources;
1973 resource_list_add(rl, type, rid, start, start + count - 1, count);
1978 pci_get_resource(device_t dev, device_t child, int type, int rid,
1979 u_long *startp, u_long *countp)
1981 struct pci_devinfo *dinfo = device_get_ivars(child);
1982 struct resource_list *rl = &dinfo->resources;
1983 struct resource_list_entry *rle;
1985 rle = resource_list_find(rl, type, rid);
1990 *startp = rle->start;
1992 *countp = rle->count;
1998 pci_delete_resource(device_t dev, device_t child, int type, int rid)
2000 kprintf("pci_delete_resource: PCI resources can not be deleted\n");
2003 struct resource_list *
2004 pci_get_resource_list (device_t dev, device_t child)
2006 struct pci_devinfo *dinfo = device_get_ivars(child);
2010 return (&dinfo->resources);
2014 pci_read_config_method(device_t dev, device_t child, int reg, int width)
2016 struct pci_devinfo *dinfo = device_get_ivars(child);
2017 pcicfgregs *cfg = &dinfo->cfg;
2019 return PCIB_READ_CONFIG(device_get_parent(dev),
2020 cfg->bus, cfg->slot, cfg->func,
2025 pci_write_config_method(device_t dev, device_t child, int reg,
2026 u_int32_t val, int width)
2028 struct pci_devinfo *dinfo = device_get_ivars(child);
2029 pcicfgregs *cfg = &dinfo->cfg;
2031 PCIB_WRITE_CONFIG(device_get_parent(dev),
2032 cfg->bus, cfg->slot, cfg->func,
2037 pci_child_location_str_method(device_t cbdev, device_t child, char *buf,
2040 struct pci_devinfo *dinfo;
2042 dinfo = device_get_ivars(child);
2043 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
2044 pci_get_function(child));
2049 pci_child_pnpinfo_str_method(device_t cbdev, device_t child, char *buf,
2052 struct pci_devinfo *dinfo;
2055 dinfo = device_get_ivars(child);
2057 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
2058 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
2059 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
2065 pci_assign_interrupt_method(device_t dev, device_t child)
2067 struct pci_devinfo *dinfo = device_get_ivars(child);
2068 pcicfgregs *cfg = &dinfo->cfg;
2070 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
2075 pci_modevent(module_t mod, int what, void *arg)
2079 STAILQ_INIT(&pci_devq);
2089 pci_resume(device_t dev)
2095 struct pci_devinfo *dinfo;
2098 device_get_children(dev, &children, &numdevs);
2100 for (i = 0; i < numdevs; i++) {
2101 child = children[i];
2103 dinfo = device_get_ivars(child);
2105 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2106 cfg->intline = PCI_ASSIGN_INTERRUPT(dev, child);
2107 if (PCI_INTERRUPT_VALID(cfg->intline)) {
2108 pci_write_config(child, PCIR_INTLINE,
2114 kfree(children, M_TEMP);
2116 return (bus_generic_resume(dev));
2119 static device_method_t pci_methods[] = {
2120 /* Device interface */
2121 DEVMETHOD(device_probe, pci_probe),
2122 DEVMETHOD(device_attach, pci_attach),
2123 DEVMETHOD(device_shutdown, bus_generic_shutdown),
2124 DEVMETHOD(device_suspend, bus_generic_suspend),
2125 DEVMETHOD(device_resume, pci_resume),
2128 DEVMETHOD(bus_print_child, pci_print_child),
2129 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
2130 DEVMETHOD(bus_read_ivar, pci_read_ivar),
2131 DEVMETHOD(bus_write_ivar, pci_write_ivar),
2132 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
2133 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
2134 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
2136 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
2137 DEVMETHOD(bus_set_resource, pci_set_resource),
2138 DEVMETHOD(bus_get_resource, pci_get_resource),
2139 DEVMETHOD(bus_delete_resource, pci_delete_resource),
2140 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
2141 DEVMETHOD(bus_release_resource, pci_release_resource),
2142 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
2143 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
2144 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
2145 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
2148 DEVMETHOD(pci_read_config, pci_read_config_method),
2149 DEVMETHOD(pci_write_config, pci_write_config_method),
2150 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
2151 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
2152 DEVMETHOD(pci_enable_io, pci_enable_io_method),
2153 DEVMETHOD(pci_disable_io, pci_disable_io_method),
2154 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
2155 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
2156 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
2161 driver_t pci_driver = {
2167 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
2168 MODULE_VERSION(pci, 1);