2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
28 * $DragonFly: src/sys/dev/netif/jme/if_jme.c,v 1.12 2008/11/26 11:55:18 sephe Exp $
31 #include <sys/param.h>
32 #include <sys/endian.h>
33 #include <sys/kernel.h>
35 #include <sys/interrupt.h>
36 #include <sys/malloc.h>
39 #include <sys/serialize.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
44 #include <net/ethernet.h>
47 #include <net/if_arp.h>
48 #include <net/if_dl.h>
49 #include <net/if_media.h>
50 #include <net/ifq_var.h>
51 #include <net/vlan/if_vlan_var.h>
52 #include <net/vlan/if_vlan_ether.h>
54 #include <dev/netif/mii_layer/miivar.h>
55 #include <dev/netif/mii_layer/jmphyreg.h>
57 #include <bus/pci/pcireg.h>
58 #include <bus/pci/pcivar.h>
59 #include <bus/pci/pcidevs.h>
61 #include <dev/netif/jme/if_jmereg.h>
62 #include <dev/netif/jme/if_jmevar.h>
64 #include "miibus_if.h"
66 /* Define the following to disable printing Rx errors. */
67 #undef JME_SHOW_ERRORS
69 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
71 static int jme_probe(device_t);
72 static int jme_attach(device_t);
73 static int jme_detach(device_t);
74 static int jme_shutdown(device_t);
75 static int jme_suspend(device_t);
76 static int jme_resume(device_t);
78 static int jme_miibus_readreg(device_t, int, int);
79 static int jme_miibus_writereg(device_t, int, int, int);
80 static void jme_miibus_statchg(device_t);
82 static void jme_init(void *);
83 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
84 static void jme_start(struct ifnet *);
85 static void jme_watchdog(struct ifnet *);
86 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
87 static int jme_mediachange(struct ifnet *);
89 static void jme_intr(void *);
90 static void jme_txeof(struct jme_softc *);
91 static void jme_rxeof(struct jme_softc *);
93 static int jme_dma_alloc(struct jme_softc *);
94 static void jme_dma_free(struct jme_softc *);
95 static void jme_dmamap_ring_cb(void *, bus_dma_segment_t *, int, int);
96 static void jme_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
98 static int jme_init_rx_ring(struct jme_softc *);
99 static void jme_init_tx_ring(struct jme_softc *);
100 static void jme_init_ssb(struct jme_softc *);
101 static int jme_newbuf(struct jme_softc *, struct jme_rxdesc *, int);
102 static int jme_encap(struct jme_softc *, struct mbuf **);
103 static void jme_rxpkt(struct jme_softc *);
105 static void jme_tick(void *);
106 static void jme_stop(struct jme_softc *);
107 static void jme_reset(struct jme_softc *);
108 static void jme_set_vlan(struct jme_softc *);
109 static void jme_set_filter(struct jme_softc *);
110 static void jme_stop_tx(struct jme_softc *);
111 static void jme_stop_rx(struct jme_softc *);
112 static void jme_mac_config(struct jme_softc *);
113 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
114 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
115 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
117 static void jme_setwol(struct jme_softc *);
118 static void jme_setlinkspeed(struct jme_softc *);
120 static void jme_set_tx_coal(struct jme_softc *);
121 static void jme_set_rx_coal(struct jme_softc *);
123 static void jme_sysctl_node(struct jme_softc *);
124 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
125 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
126 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
127 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
130 * Devices supported by this driver.
132 static const struct jme_dev {
133 uint16_t jme_vendorid;
134 uint16_t jme_deviceid;
136 const char *jme_name;
138 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
140 "JMicron Inc, JMC250 Gigabit Ethernet" },
141 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
143 "JMicron Inc, JMC260 Fast Ethernet" },
147 static device_method_t jme_methods[] = {
148 /* Device interface. */
149 DEVMETHOD(device_probe, jme_probe),
150 DEVMETHOD(device_attach, jme_attach),
151 DEVMETHOD(device_detach, jme_detach),
152 DEVMETHOD(device_shutdown, jme_shutdown),
153 DEVMETHOD(device_suspend, jme_suspend),
154 DEVMETHOD(device_resume, jme_resume),
157 DEVMETHOD(bus_print_child, bus_generic_print_child),
158 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
161 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
162 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
163 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
168 static driver_t jme_driver = {
171 sizeof(struct jme_softc)
174 static devclass_t jme_devclass;
176 DECLARE_DUMMY_MODULE(if_jme);
177 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
178 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, 0, 0);
179 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0);
182 * Read a PHY register on the MII of the JMC250.
185 jme_miibus_readreg(device_t dev, int phy, int reg)
187 struct jme_softc *sc = device_get_softc(dev);
191 /* For FPGA version, PHY address 0 should be ignored. */
192 if (sc->jme_caps & JME_CAP_FPGA) {
196 if (sc->jme_phyaddr != phy)
200 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
201 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
203 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
205 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
209 device_printf(sc->jme_dev, "phy read timeout: "
210 "phy %d, reg %d\n", phy, reg);
214 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
218 * Write a PHY register on the MII of the JMC250.
221 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
223 struct jme_softc *sc = device_get_softc(dev);
226 /* For FPGA version, PHY address 0 should be ignored. */
227 if (sc->jme_caps & JME_CAP_FPGA) {
231 if (sc->jme_phyaddr != phy)
235 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
236 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
237 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
239 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
241 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
245 device_printf(sc->jme_dev, "phy write timeout: "
246 "phy %d, reg %d\n", phy, reg);
253 * Callback from MII layer when media changes.
256 jme_miibus_statchg(device_t dev)
258 struct jme_softc *sc = device_get_softc(dev);
259 struct ifnet *ifp = &sc->arpcom.ac_if;
260 struct mii_data *mii;
261 struct jme_txdesc *txd;
265 ASSERT_SERIALIZED(ifp->if_serializer);
267 if ((ifp->if_flags & IFF_RUNNING) == 0)
270 mii = device_get_softc(sc->jme_miibus);
272 sc->jme_flags &= ~JME_FLAG_LINK;
273 if ((mii->mii_media_status & IFM_AVALID) != 0) {
274 switch (IFM_SUBTYPE(mii->mii_media_active)) {
277 sc->jme_flags |= JME_FLAG_LINK;
280 if (sc->jme_caps & JME_CAP_FASTETH)
282 sc->jme_flags |= JME_FLAG_LINK;
290 * Disabling Rx/Tx MACs have a side-effect of resetting
291 * JME_TXNDA/JME_RXNDA register to the first address of
292 * Tx/Rx descriptor address. So driver should reset its
293 * internal procucer/consumer pointer and reclaim any
294 * allocated resources. Note, just saving the value of
295 * JME_TXNDA and JME_RXNDA registers before stopping MAC
296 * and restoring JME_TXNDA/JME_RXNDA register is not
297 * sufficient to make sure correct MAC state because
298 * stopping MAC operation can take a while and hardware
299 * might have updated JME_TXNDA/JME_RXNDA registers
300 * during the stop operation.
303 /* Disable interrupts */
304 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
307 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
309 callout_stop(&sc->jme_tick_ch);
311 /* Stop receiver/transmitter. */
316 if (sc->jme_cdata.jme_rxhead != NULL)
317 m_freem(sc->jme_cdata.jme_rxhead);
318 JME_RXCHAIN_RESET(sc);
321 if (sc->jme_cdata.jme_tx_cnt != 0) {
322 /* Remove queued packets for transmit. */
323 for (i = 0; i < JME_TX_RING_CNT; i++) {
324 txd = &sc->jme_cdata.jme_txdesc[i];
325 if (txd->tx_m != NULL) {
327 sc->jme_cdata.jme_tx_tag,
338 * Reuse configured Rx descriptors and reset
339 * procuder/consumer index.
341 sc->jme_cdata.jme_rx_cons = 0;
343 jme_init_tx_ring(sc);
345 /* Initialize shadow status block. */
348 /* Program MAC with resolved speed/duplex/flow-control. */
349 if (sc->jme_flags & JME_FLAG_LINK) {
352 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
353 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
355 /* Set Tx ring address to the hardware. */
356 paddr = JME_TX_RING_ADDR(sc, 0);
357 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
358 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
360 /* Set Rx ring address to the hardware. */
361 paddr = JME_RX_RING_ADDR(sc, 0);
362 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
363 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
365 /* Restart receiver/transmitter. */
366 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
368 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
371 ifp->if_flags |= IFF_RUNNING;
372 ifp->if_flags &= ~IFF_OACTIVE;
373 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
375 /* Reenable interrupts. */
376 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
380 * Get the current interface media status.
383 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
385 struct jme_softc *sc = ifp->if_softc;
386 struct mii_data *mii = device_get_softc(sc->jme_miibus);
388 ASSERT_SERIALIZED(ifp->if_serializer);
391 ifmr->ifm_status = mii->mii_media_status;
392 ifmr->ifm_active = mii->mii_media_active;
396 * Set hardware to newly-selected media.
399 jme_mediachange(struct ifnet *ifp)
401 struct jme_softc *sc = ifp->if_softc;
402 struct mii_data *mii = device_get_softc(sc->jme_miibus);
405 ASSERT_SERIALIZED(ifp->if_serializer);
407 if (mii->mii_instance != 0) {
408 struct mii_softc *miisc;
410 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
411 mii_phy_reset(miisc);
413 error = mii_mediachg(mii);
419 jme_probe(device_t dev)
421 const struct jme_dev *sp;
424 vid = pci_get_vendor(dev);
425 did = pci_get_device(dev);
426 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
427 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
428 struct jme_softc *sc = device_get_softc(dev);
430 sc->jme_caps = sp->jme_caps;
431 device_set_desc(dev, sp->jme_name);
439 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
445 for (i = JME_TIMEOUT; i > 0; i--) {
446 reg = CSR_READ_4(sc, JME_SMBCSR);
447 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
453 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
457 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
458 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
459 for (i = JME_TIMEOUT; i > 0; i--) {
461 reg = CSR_READ_4(sc, JME_SMBINTF);
462 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
467 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
471 reg = CSR_READ_4(sc, JME_SMBINTF);
472 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
478 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
480 uint8_t fup, reg, val;
485 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
486 fup != JME_EEPROM_SIG0)
488 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
489 fup != JME_EEPROM_SIG1)
493 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
495 /* Check for the end of EEPROM descriptor. */
496 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
498 if ((uint8_t)JME_EEPROM_MKDESC(JME_EEPROM_FUNC0,
499 JME_EEPROM_PAGE_BAR1) == fup) {
500 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
502 if (reg >= JME_PAR0 &&
503 reg < JME_PAR0 + ETHER_ADDR_LEN) {
504 if (jme_eeprom_read_byte(sc, offset + 2,
507 eaddr[reg - JME_PAR0] = val;
511 /* Try next eeprom descriptor. */
512 offset += JME_EEPROM_DESC_BYTES;
513 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
515 if (match == ETHER_ADDR_LEN)
522 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
526 /* Read station address. */
527 par0 = CSR_READ_4(sc, JME_PAR0);
528 par1 = CSR_READ_4(sc, JME_PAR1);
530 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
531 device_printf(sc->jme_dev,
532 "generating fake ethernet address.\n");
533 par0 = karc4random();
534 /* Set OUI to JMicron. */
538 eaddr[3] = (par0 >> 16) & 0xff;
539 eaddr[4] = (par0 >> 8) & 0xff;
540 eaddr[5] = par0 & 0xff;
542 eaddr[0] = (par0 >> 0) & 0xFF;
543 eaddr[1] = (par0 >> 8) & 0xFF;
544 eaddr[2] = (par0 >> 16) & 0xFF;
545 eaddr[3] = (par0 >> 24) & 0xFF;
546 eaddr[4] = (par1 >> 0) & 0xFF;
547 eaddr[5] = (par1 >> 8) & 0xFF;
552 jme_attach(device_t dev)
554 struct jme_softc *sc = device_get_softc(dev);
555 struct ifnet *ifp = &sc->arpcom.ac_if;
558 uint8_t pcie_ptr, rev;
560 uint8_t eaddr[ETHER_ADDR_LEN];
563 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
565 ifp = &sc->arpcom.ac_if;
566 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
568 callout_init(&sc->jme_tick_ch);
571 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
574 irq = pci_read_config(dev, PCIR_INTLINE, 4);
575 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
577 device_printf(dev, "chip is in D%d power mode "
578 "-- setting to D0\n", pci_get_powerstate(dev));
580 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
582 pci_write_config(dev, PCIR_INTLINE, irq, 4);
583 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
585 #endif /* !BURN_BRIDGE */
587 /* Enable bus mastering */
588 pci_enable_busmaster(dev);
593 * JMC250 supports both memory mapped and I/O register space
594 * access. Because I/O register access should use different
595 * BARs to access registers it's waste of time to use I/O
596 * register spce access. JMC250 uses 16K to map entire memory
599 sc->jme_mem_rid = JME_PCIR_BAR;
600 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
601 &sc->jme_mem_rid, RF_ACTIVE);
602 if (sc->jme_mem_res == NULL) {
603 device_printf(dev, "can't allocate IO memory\n");
606 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
607 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
613 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
615 RF_SHAREABLE | RF_ACTIVE);
616 if (sc->jme_irq_res == NULL) {
617 device_printf(dev, "can't allocate irq\n");
625 reg = CSR_READ_4(sc, JME_CHIPMODE);
626 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
628 sc->jme_caps |= JME_CAP_FPGA;
630 device_printf(dev, "FPGA revision: 0x%04x\n",
631 (reg & CHIPMODE_FPGA_REV_MASK) >>
632 CHIPMODE_FPGA_REV_SHIFT);
636 /* NOTE: FM revision is put in the upper 4 bits */
637 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
638 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
640 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
642 did = pci_get_device(dev);
644 case PCI_PRODUCT_JMICRON_JMC250:
645 if (rev == JME_REV1_A2)
646 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
649 case PCI_PRODUCT_JMICRON_JMC260:
651 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
655 panic("unknown device id 0x%04x\n", did);
657 if (rev >= JME_REV2) {
658 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
659 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
660 GHC_TXMAC_CLKSRC_1000;
663 /* Reset the ethernet controller. */
666 /* Get station address. */
667 reg = CSR_READ_4(sc, JME_SMBCSR);
668 if (reg & SMBCSR_EEPROM_PRESENT)
669 error = jme_eeprom_macaddr(sc, eaddr);
670 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
671 if (error != 0 && (bootverbose)) {
672 device_printf(dev, "ethernet hardware address "
673 "not found in EEPROM.\n");
675 jme_reg_macaddr(sc, eaddr);
680 * Integrated JR0211 has fixed PHY address whereas FPGA version
681 * requires PHY probing to get correct PHY address.
683 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
684 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
685 GPREG0_PHY_ADDR_MASK;
687 device_printf(dev, "PHY is at address %d.\n",
694 /* Set max allowable DMA size. */
695 pcie_ptr = pci_get_pciecap_ptr(dev);
699 sc->jme_caps |= JME_CAP_PCIE;
700 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
702 device_printf(dev, "Read request size : %d bytes.\n",
703 128 << ((ctrl >> 12) & 0x07));
704 device_printf(dev, "TLP payload size : %d bytes.\n",
705 128 << ((ctrl >> 5) & 0x07));
707 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
708 case PCIEM_DEVCTL_MAX_READRQ_128:
709 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
711 case PCIEM_DEVCTL_MAX_READRQ_256:
712 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
715 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
718 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
720 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
721 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
725 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
726 sc->jme_caps |= JME_CAP_PMCAP;
734 /* Allocate DMA stuffs */
735 error = jme_dma_alloc(sc);
740 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
741 ifp->if_init = jme_init;
742 ifp->if_ioctl = jme_ioctl;
743 ifp->if_start = jme_start;
744 ifp->if_watchdog = jme_watchdog;
745 ifq_set_maxlen(&ifp->if_snd, JME_TX_RING_CNT - 1);
746 ifq_set_ready(&ifp->if_snd);
748 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
749 ifp->if_capabilities = IFCAP_HWCSUM |
751 IFCAP_VLAN_HWTAGGING;
752 ifp->if_hwassist = JME_CSUM_FEATURES;
753 ifp->if_capenable = ifp->if_capabilities;
755 /* Set up MII bus. */
756 error = mii_phy_probe(dev, &sc->jme_miibus,
757 jme_mediachange, jme_mediastatus);
759 device_printf(dev, "no PHY found!\n");
764 * Save PHYADDR for FPGA mode PHY.
766 if (sc->jme_caps & JME_CAP_FPGA) {
767 struct mii_data *mii = device_get_softc(sc->jme_miibus);
769 if (mii->mii_instance != 0) {
770 struct mii_softc *miisc;
772 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
773 if (miisc->mii_phy != 0) {
774 sc->jme_phyaddr = miisc->mii_phy;
778 if (sc->jme_phyaddr != 0) {
779 device_printf(sc->jme_dev,
780 "FPGA PHY is at %d\n", sc->jme_phyaddr);
782 jme_miibus_writereg(dev, sc->jme_phyaddr,
783 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
785 /* XXX should we clear JME_WA_EXTFIFO */
790 ether_ifattach(ifp, eaddr, NULL);
792 /* Tell the upper layer(s) we support long frames. */
793 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
795 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE, jme_intr, sc,
796 &sc->jme_irq_handle, ifp->if_serializer);
798 device_printf(dev, "could not set up interrupt handler.\n");
803 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->jme_irq_res));
804 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
812 jme_detach(device_t dev)
814 struct jme_softc *sc = device_get_softc(dev);
816 if (device_is_attached(dev)) {
817 struct ifnet *ifp = &sc->arpcom.ac_if;
819 lwkt_serialize_enter(ifp->if_serializer);
821 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
822 lwkt_serialize_exit(ifp->if_serializer);
827 if (sc->jme_sysctl_tree != NULL)
828 sysctl_ctx_free(&sc->jme_sysctl_ctx);
830 if (sc->jme_miibus != NULL)
831 device_delete_child(dev, sc->jme_miibus);
832 bus_generic_detach(dev);
834 if (sc->jme_irq_res != NULL) {
835 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
839 if (sc->jme_mem_res != NULL) {
840 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
850 jme_sysctl_node(struct jme_softc *sc)
852 sysctl_ctx_init(&sc->jme_sysctl_ctx);
853 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
854 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
855 device_get_nameunit(sc->jme_dev),
857 if (sc->jme_sysctl_tree == NULL) {
858 device_printf(sc->jme_dev, "can't add sysctl node\n");
862 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
863 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
864 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
865 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
867 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
868 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
869 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
870 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
872 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
873 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
874 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
875 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
877 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
878 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
879 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
880 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
882 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
883 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
884 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
885 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
889 jme_dmamap_ring_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
894 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
895 *((bus_addr_t *)arg) = segs->ds_addr;
899 jme_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
900 bus_size_t mapsz __unused, int error)
902 struct jme_dmamap_ctx *ctx = xctx;
908 if (nsegs > ctx->nsegs) {
914 for (i = 0; i < nsegs; ++i)
915 ctx->segs[i] = segs[i];
919 jme_dma_alloc(struct jme_softc *sc)
921 struct jme_txdesc *txd;
922 struct jme_rxdesc *rxd;
923 bus_addr_t busaddr, lowaddr;
926 lowaddr = sc->jme_lowaddr;
928 /* Create parent ring tag. */
929 error = bus_dma_tag_create(NULL,/* parent */
930 1, 0, /* algnmnt, boundary */
931 lowaddr, /* lowaddr */
932 BUS_SPACE_MAXADDR, /* highaddr */
933 NULL, NULL, /* filter, filterarg */
934 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
936 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
938 &sc->jme_cdata.jme_ring_tag);
940 device_printf(sc->jme_dev,
941 "could not create parent ring DMA tag.\n");
946 * Create DMA stuffs for TX ring
949 /* Create tag for Tx ring. */
950 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
951 JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */
952 lowaddr, /* lowaddr */
953 BUS_SPACE_MAXADDR, /* highaddr */
954 NULL, NULL, /* filter, filterarg */
955 JME_TX_RING_SIZE, /* maxsize */
957 JME_TX_RING_SIZE, /* maxsegsize */
959 &sc->jme_cdata.jme_tx_ring_tag);
961 device_printf(sc->jme_dev,
962 "could not allocate Tx ring DMA tag.\n");
966 /* Allocate DMA'able memory for TX ring */
967 error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag,
968 (void **)&sc->jme_rdata.jme_tx_ring,
969 BUS_DMA_WAITOK | BUS_DMA_ZERO,
970 &sc->jme_cdata.jme_tx_ring_map);
972 device_printf(sc->jme_dev,
973 "could not allocate DMA'able memory for Tx ring.\n");
974 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
975 sc->jme_cdata.jme_tx_ring_tag = NULL;
979 /* Load the DMA map for Tx ring. */
980 error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag,
981 sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring,
982 JME_TX_RING_SIZE, jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
984 device_printf(sc->jme_dev,
985 "could not load DMA'able memory for Tx ring.\n");
986 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
987 sc->jme_rdata.jme_tx_ring,
988 sc->jme_cdata.jme_tx_ring_map);
989 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
990 sc->jme_cdata.jme_tx_ring_tag = NULL;
993 sc->jme_rdata.jme_tx_ring_paddr = busaddr;
996 * Create DMA stuffs for RX ring
999 /* Create tag for Rx ring. */
1000 error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */
1001 JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */
1002 lowaddr, /* lowaddr */
1003 BUS_SPACE_MAXADDR, /* highaddr */
1004 NULL, NULL, /* filter, filterarg */
1005 JME_RX_RING_SIZE, /* maxsize */
1007 JME_RX_RING_SIZE, /* maxsegsize */
1009 &sc->jme_cdata.jme_rx_ring_tag);
1011 device_printf(sc->jme_dev,
1012 "could not allocate Rx ring DMA tag.\n");
1016 /* Allocate DMA'able memory for RX ring */
1017 error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag,
1018 (void **)&sc->jme_rdata.jme_rx_ring,
1019 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1020 &sc->jme_cdata.jme_rx_ring_map);
1022 device_printf(sc->jme_dev,
1023 "could not allocate DMA'able memory for Rx ring.\n");
1024 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1025 sc->jme_cdata.jme_rx_ring_tag = NULL;
1029 /* Load the DMA map for Rx ring. */
1030 error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag,
1031 sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring,
1032 JME_RX_RING_SIZE, jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1034 device_printf(sc->jme_dev,
1035 "could not load DMA'able memory for Rx ring.\n");
1036 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1037 sc->jme_rdata.jme_rx_ring,
1038 sc->jme_cdata.jme_rx_ring_map);
1039 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1040 sc->jme_cdata.jme_rx_ring_tag = NULL;
1043 sc->jme_rdata.jme_rx_ring_paddr = busaddr;
1045 if (lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1046 bus_addr_t rx_ring_end, tx_ring_end;
1048 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
1049 tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr +
1051 rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr +
1053 if ((JME_ADDR_HI(tx_ring_end) !=
1054 JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) ||
1055 (JME_ADDR_HI(rx_ring_end) !=
1056 JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) {
1057 device_printf(sc->jme_dev, "4GB boundary crossed, "
1058 "switching to 32bit DMA address mode.\n");
1060 /* Limit DMA address space to 32bit and try again. */
1061 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1066 /* Create parent buffer tag. */
1067 error = bus_dma_tag_create(NULL,/* parent */
1068 1, 0, /* algnmnt, boundary */
1069 sc->jme_lowaddr, /* lowaddr */
1070 BUS_SPACE_MAXADDR, /* highaddr */
1071 NULL, NULL, /* filter, filterarg */
1072 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1074 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1076 &sc->jme_cdata.jme_buffer_tag);
1078 device_printf(sc->jme_dev,
1079 "could not create parent buffer DMA tag.\n");
1084 * Create DMA stuffs for shadow status block
1087 /* Create shadow status block tag. */
1088 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1089 JME_SSB_ALIGN, 0, /* algnmnt, boundary */
1090 sc->jme_lowaddr, /* lowaddr */
1091 BUS_SPACE_MAXADDR, /* highaddr */
1092 NULL, NULL, /* filter, filterarg */
1093 JME_SSB_SIZE, /* maxsize */
1095 JME_SSB_SIZE, /* maxsegsize */
1097 &sc->jme_cdata.jme_ssb_tag);
1099 device_printf(sc->jme_dev,
1100 "could not create shared status block DMA tag.\n");
1104 /* Allocate DMA'able memory for shared status block. */
1105 error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag,
1106 (void **)&sc->jme_rdata.jme_ssb_block,
1107 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1108 &sc->jme_cdata.jme_ssb_map);
1110 device_printf(sc->jme_dev, "could not allocate DMA'able "
1111 "memory for shared status block.\n");
1112 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1113 sc->jme_cdata.jme_ssb_tag = NULL;
1117 /* Load the DMA map for shared status block */
1118 error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag,
1119 sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block,
1120 JME_SSB_SIZE, jme_dmamap_ring_cb, &busaddr, BUS_DMA_NOWAIT);
1122 device_printf(sc->jme_dev, "could not load DMA'able memory "
1123 "for shared status block.\n");
1124 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1125 sc->jme_rdata.jme_ssb_block,
1126 sc->jme_cdata.jme_ssb_map);
1127 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1128 sc->jme_cdata.jme_ssb_tag = NULL;
1131 sc->jme_rdata.jme_ssb_block_paddr = busaddr;
1134 * Create DMA stuffs for TX buffers
1137 /* Create tag for Tx buffers. */
1138 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1139 1, 0, /* algnmnt, boundary */
1140 sc->jme_lowaddr, /* lowaddr */
1141 BUS_SPACE_MAXADDR, /* highaddr */
1142 NULL, NULL, /* filter, filterarg */
1143 JME_TSO_MAXSIZE, /* maxsize */
1144 JME_MAXTXSEGS, /* nsegments */
1145 JME_TSO_MAXSEGSIZE, /* maxsegsize */
1147 &sc->jme_cdata.jme_tx_tag);
1149 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1153 /* Create DMA maps for Tx buffers. */
1154 for (i = 0; i < JME_TX_RING_CNT; i++) {
1155 txd = &sc->jme_cdata.jme_txdesc[i];
1156 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0,
1161 device_printf(sc->jme_dev,
1162 "could not create %dth Tx dmamap.\n", i);
1164 for (j = 0; j < i; ++j) {
1165 txd = &sc->jme_cdata.jme_txdesc[j];
1166 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1169 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1170 sc->jme_cdata.jme_tx_tag = NULL;
1176 * Create DMA stuffs for RX buffers
1179 /* Create tag for Rx buffers. */
1180 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1181 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
1182 sc->jme_lowaddr, /* lowaddr */
1183 BUS_SPACE_MAXADDR, /* highaddr */
1184 NULL, NULL, /* filter, filterarg */
1185 MCLBYTES, /* maxsize */
1187 MCLBYTES, /* maxsegsize */
1189 &sc->jme_cdata.jme_rx_tag);
1191 device_printf(sc->jme_dev, "could not create Rx DMA tag.\n");
1195 /* Create DMA maps for Rx buffers. */
1196 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1197 &sc->jme_cdata.jme_rx_sparemap);
1199 device_printf(sc->jme_dev,
1200 "could not create spare Rx dmamap.\n");
1201 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1202 sc->jme_cdata.jme_rx_tag = NULL;
1205 for (i = 0; i < JME_RX_RING_CNT; i++) {
1206 rxd = &sc->jme_cdata.jme_rxdesc[i];
1207 error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0,
1212 device_printf(sc->jme_dev,
1213 "could not create %dth Rx dmamap.\n", i);
1215 for (j = 0; j < i; ++j) {
1216 rxd = &sc->jme_cdata.jme_rxdesc[j];
1217 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1220 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1221 sc->jme_cdata.jme_rx_sparemap);
1222 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1223 sc->jme_cdata.jme_rx_tag = NULL;
1231 jme_dma_free(struct jme_softc *sc)
1233 struct jme_txdesc *txd;
1234 struct jme_rxdesc *rxd;
1238 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1239 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1240 sc->jme_cdata.jme_tx_ring_map);
1241 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1242 sc->jme_rdata.jme_tx_ring,
1243 sc->jme_cdata.jme_tx_ring_map);
1244 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1245 sc->jme_cdata.jme_tx_ring_tag = NULL;
1249 if (sc->jme_cdata.jme_rx_ring_tag != NULL) {
1250 bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag,
1251 sc->jme_cdata.jme_rx_ring_map);
1252 bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag,
1253 sc->jme_rdata.jme_rx_ring,
1254 sc->jme_cdata.jme_rx_ring_map);
1255 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag);
1256 sc->jme_cdata.jme_rx_ring_tag = NULL;
1260 if (sc->jme_cdata.jme_tx_tag != NULL) {
1261 for (i = 0; i < JME_TX_RING_CNT; i++) {
1262 txd = &sc->jme_cdata.jme_txdesc[i];
1263 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1266 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1267 sc->jme_cdata.jme_tx_tag = NULL;
1271 if (sc->jme_cdata.jme_rx_tag != NULL) {
1272 for (i = 0; i < JME_RX_RING_CNT; i++) {
1273 rxd = &sc->jme_cdata.jme_rxdesc[i];
1274 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1277 bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag,
1278 sc->jme_cdata.jme_rx_sparemap);
1279 bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag);
1280 sc->jme_cdata.jme_rx_tag = NULL;
1283 /* Shadow status block. */
1284 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1285 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1286 sc->jme_cdata.jme_ssb_map);
1287 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1288 sc->jme_rdata.jme_ssb_block,
1289 sc->jme_cdata.jme_ssb_map);
1290 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1291 sc->jme_cdata.jme_ssb_tag = NULL;
1294 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1295 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1296 sc->jme_cdata.jme_buffer_tag = NULL;
1298 if (sc->jme_cdata.jme_ring_tag != NULL) {
1299 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1300 sc->jme_cdata.jme_ring_tag = NULL;
1305 * Make sure the interface is stopped at reboot time.
1308 jme_shutdown(device_t dev)
1310 return jme_suspend(dev);
1315 * Unlike other ethernet controllers, JMC250 requires
1316 * explicit resetting link speed to 10/100Mbps as gigabit
1317 * link will cunsume more power than 375mA.
1318 * Note, we reset the link speed to 10/100Mbps with
1319 * auto-negotiation but we don't know whether that operation
1320 * would succeed or not as we have no control after powering
1321 * off. If the renegotiation fail WOL may not work. Running
1322 * at 1Gbps draws more power than 375mA at 3.3V which is
1323 * specified in PCI specification and that would result in
1324 * complete shutdowning power to ethernet controller.
1327 * Save current negotiated media speed/duplex/flow-control
1328 * to softc and restore the same link again after resuming.
1329 * PHY handling such as power down/resetting to 100Mbps
1330 * may be better handled in suspend method in phy driver.
1333 jme_setlinkspeed(struct jme_softc *sc)
1335 struct mii_data *mii;
1338 JME_LOCK_ASSERT(sc);
1340 mii = device_get_softc(sc->jme_miibus);
1343 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1344 switch IFM_SUBTYPE(mii->mii_media_active) {
1354 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1355 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1356 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1357 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1358 BMCR_AUTOEN | BMCR_STARTNEG);
1361 /* Poll link state until jme(4) get a 10/100 link. */
1362 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1364 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1365 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1375 pause("jmelnk", hz);
1378 if (i == MII_ANEGTICKS_GIGE)
1379 device_printf(sc->jme_dev, "establishing link failed, "
1380 "WOL may not work!");
1383 * No link, force MAC to have 100Mbps, full-duplex link.
1384 * This is the last resort and may/may not work.
1386 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1387 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1392 jme_setwol(struct jme_softc *sc)
1394 struct ifnet *ifp = &sc->arpcom.ac_if;
1399 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1400 /* No PME capability, PHY power down. */
1401 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1402 MII_BMCR, BMCR_PDOWN);
1406 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1407 pmcs = CSR_READ_4(sc, JME_PMCS);
1408 pmcs &= ~PMCS_WOL_ENB_MASK;
1409 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1410 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1411 /* Enable PME message. */
1412 gpr |= GPREG0_PME_ENB;
1413 /* For gigabit controllers, reset link speed to 10/100. */
1414 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1415 jme_setlinkspeed(sc);
1418 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1419 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1422 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1423 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1424 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1425 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1426 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1427 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1428 /* No WOL, PHY power down. */
1429 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1430 MII_BMCR, BMCR_PDOWN);
1436 jme_suspend(device_t dev)
1438 struct jme_softc *sc = device_get_softc(dev);
1439 struct ifnet *ifp = &sc->arpcom.ac_if;
1441 lwkt_serialize_enter(ifp->if_serializer);
1446 lwkt_serialize_exit(ifp->if_serializer);
1452 jme_resume(device_t dev)
1454 struct jme_softc *sc = device_get_softc(dev);
1455 struct ifnet *ifp = &sc->arpcom.ac_if;
1460 lwkt_serialize_enter(ifp->if_serializer);
1463 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1466 pmstat = pci_read_config(sc->jme_dev,
1467 pmc + PCIR_POWER_STATUS, 2);
1468 /* Disable PME clear PME status. */
1469 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1470 pci_write_config(sc->jme_dev,
1471 pmc + PCIR_POWER_STATUS, pmstat, 2);
1475 if (ifp->if_flags & IFF_UP)
1478 lwkt_serialize_exit(ifp->if_serializer);
1484 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1486 struct jme_txdesc *txd;
1487 struct jme_desc *desc;
1489 struct jme_dmamap_ctx ctx;
1490 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1495 M_ASSERTPKTHDR((*m_head));
1497 prod = sc->jme_cdata.jme_tx_prod;
1498 txd = &sc->jme_cdata.jme_txdesc[prod];
1500 maxsegs = (JME_TX_RING_CNT - sc->jme_cdata.jme_tx_cnt) -
1502 if (maxsegs > JME_MAXTXSEGS)
1503 maxsegs = JME_MAXTXSEGS;
1504 KASSERT(maxsegs >= (sc->jme_txd_spare - 1),
1505 ("not enough segments %d\n", maxsegs));
1507 ctx.nsegs = maxsegs;
1509 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1510 *m_head, jme_dmamap_buf_cb, &ctx,
1512 if (!error && ctx.nsegs == 0) {
1513 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
1516 if (error == EFBIG) {
1517 m = m_defrag(*m_head, MB_DONTWAIT);
1519 if_printf(&sc->arpcom.ac_if,
1520 "could not defrag TX mbuf\n");
1527 ctx.nsegs = maxsegs;
1529 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_tx_tag,
1530 txd->tx_dmamap, *m_head,
1531 jme_dmamap_buf_cb, &ctx,
1533 if (error || ctx.nsegs == 0) {
1534 if_printf(&sc->arpcom.ac_if,
1535 "could not load defragged TX mbuf\n");
1537 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
1546 if_printf(&sc->arpcom.ac_if, "could not load TX mbuf\n");
1553 /* Configure checksum offload. */
1554 if (m->m_pkthdr.csum_flags & CSUM_IP)
1555 cflags |= JME_TD_IPCSUM;
1556 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1557 cflags |= JME_TD_TCPCSUM;
1558 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1559 cflags |= JME_TD_UDPCSUM;
1561 /* Configure VLAN. */
1562 if (m->m_flags & M_VLANTAG) {
1563 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1564 cflags |= JME_TD_VLAN_TAG;
1567 desc = &sc->jme_rdata.jme_tx_ring[prod];
1568 desc->flags = htole32(cflags);
1570 desc->addr_hi = htole32(m->m_pkthdr.len);
1572 sc->jme_cdata.jme_tx_cnt++;
1573 KKASSERT(sc->jme_cdata.jme_tx_cnt < JME_TX_RING_CNT - JME_TXD_RSVD);
1574 JME_DESC_INC(prod, JME_TX_RING_CNT);
1575 for (i = 0; i < ctx.nsegs; i++) {
1576 desc = &sc->jme_rdata.jme_tx_ring[prod];
1577 desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT);
1578 desc->buflen = htole32(txsegs[i].ds_len);
1579 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1580 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1582 sc->jme_cdata.jme_tx_cnt++;
1583 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1584 JME_TX_RING_CNT - JME_TXD_RSVD);
1585 JME_DESC_INC(prod, JME_TX_RING_CNT);
1588 /* Update producer index. */
1589 sc->jme_cdata.jme_tx_prod = prod;
1591 * Finally request interrupt and give the first descriptor
1592 * owenership to hardware.
1594 desc = txd->tx_desc;
1595 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1598 txd->tx_ndesc = ctx.nsegs + 1;
1600 /* Sync descriptors. */
1601 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1602 BUS_DMASYNC_PREWRITE);
1603 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1604 sc->jme_cdata.jme_tx_ring_map, BUS_DMASYNC_PREWRITE);
1609 jme_start(struct ifnet *ifp)
1611 struct jme_softc *sc = ifp->if_softc;
1612 struct mbuf *m_head;
1615 ASSERT_SERIALIZED(ifp->if_serializer);
1617 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1618 ifq_purge(&ifp->if_snd);
1622 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1625 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT)
1628 while (!ifq_is_empty(&ifp->if_snd)) {
1630 * Check number of available TX descs, always
1631 * leave JME_TXD_RSVD free TX descs.
1633 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1634 JME_TX_RING_CNT - JME_TXD_RSVD) {
1635 ifp->if_flags |= IFF_OACTIVE;
1639 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1644 * Pack the data into the transmit ring. If we
1645 * don't have room, set the OACTIVE flag and wait
1646 * for the NIC to drain the ring.
1648 if (jme_encap(sc, &m_head)) {
1649 if (m_head == NULL) {
1653 ifq_prepend(&ifp->if_snd, m_head);
1654 ifp->if_flags |= IFF_OACTIVE;
1660 * If there's a BPF listener, bounce a copy of this frame
1663 ETHER_BPF_MTAP(ifp, m_head);
1668 * Reading TXCSR takes very long time under heavy load
1669 * so cache TXCSR value and writes the ORed value with
1670 * the kick command to the TXCSR. This saves one register
1673 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1674 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1675 /* Set a timeout in case the chip goes out to lunch. */
1676 ifp->if_timer = JME_TX_TIMEOUT;
1681 jme_watchdog(struct ifnet *ifp)
1683 struct jme_softc *sc = ifp->if_softc;
1685 ASSERT_SERIALIZED(ifp->if_serializer);
1687 if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1688 if_printf(ifp, "watchdog timeout (missed link)\n");
1695 if (sc->jme_cdata.jme_tx_cnt == 0) {
1696 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1698 if (!ifq_is_empty(&ifp->if_snd))
1703 if_printf(ifp, "watchdog timeout\n");
1706 if (!ifq_is_empty(&ifp->if_snd))
1711 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1713 struct jme_softc *sc = ifp->if_softc;
1714 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1715 struct ifreq *ifr = (struct ifreq *)data;
1716 int error = 0, mask;
1718 ASSERT_SERIALIZED(ifp->if_serializer);
1722 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1723 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1724 ifr->ifr_mtu > JME_MAX_MTU)) {
1729 if (ifp->if_mtu != ifr->ifr_mtu) {
1731 * No special configuration is required when interface
1732 * MTU is changed but availability of Tx checksum
1733 * offload should be chcked against new MTU size as
1734 * FIFO size is just 2K.
1736 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1737 ifp->if_capenable &= ~IFCAP_TXCSUM;
1738 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1740 ifp->if_mtu = ifr->ifr_mtu;
1741 if (ifp->if_flags & IFF_RUNNING)
1747 if (ifp->if_flags & IFF_UP) {
1748 if (ifp->if_flags & IFF_RUNNING) {
1749 if ((ifp->if_flags ^ sc->jme_if_flags) &
1750 (IFF_PROMISC | IFF_ALLMULTI))
1756 if (ifp->if_flags & IFF_RUNNING)
1759 sc->jme_if_flags = ifp->if_flags;
1764 if (ifp->if_flags & IFF_RUNNING)
1770 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1774 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1776 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1777 if (IFCAP_TXCSUM & ifp->if_capabilities) {
1778 ifp->if_capenable ^= IFCAP_TXCSUM;
1779 if (IFCAP_TXCSUM & ifp->if_capenable)
1780 ifp->if_hwassist |= JME_CSUM_FEATURES;
1782 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1785 if ((mask & IFCAP_RXCSUM) &&
1786 (IFCAP_RXCSUM & ifp->if_capabilities)) {
1789 ifp->if_capenable ^= IFCAP_RXCSUM;
1790 reg = CSR_READ_4(sc, JME_RXMAC);
1791 reg &= ~RXMAC_CSUM_ENB;
1792 if (ifp->if_capenable & IFCAP_RXCSUM)
1793 reg |= RXMAC_CSUM_ENB;
1794 CSR_WRITE_4(sc, JME_RXMAC, reg);
1797 if ((mask & IFCAP_VLAN_HWTAGGING) &&
1798 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities)) {
1799 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1805 error = ether_ioctl(ifp, cmd, data);
1812 jme_mac_config(struct jme_softc *sc)
1814 struct mii_data *mii;
1815 uint32_t ghc, rxmac, txmac, txpause, gp1;
1816 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1818 mii = device_get_softc(sc->jme_miibus);
1820 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1822 CSR_WRITE_4(sc, JME_GHC, 0);
1824 rxmac = CSR_READ_4(sc, JME_RXMAC);
1825 rxmac &= ~RXMAC_FC_ENB;
1826 txmac = CSR_READ_4(sc, JME_TXMAC);
1827 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1828 txpause = CSR_READ_4(sc, JME_TXPFC);
1829 txpause &= ~TXPFC_PAUSE_ENB;
1830 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1831 ghc |= GHC_FULL_DUPLEX;
1832 rxmac &= ~RXMAC_COLL_DET_ENB;
1833 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1834 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1837 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1838 txpause |= TXPFC_PAUSE_ENB;
1839 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1840 rxmac |= RXMAC_FC_ENB;
1842 /* Disable retry transmit timer/retry limit. */
1843 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1844 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1846 rxmac |= RXMAC_COLL_DET_ENB;
1847 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1848 /* Enable retry transmit timer/retry limit. */
1849 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1850 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1854 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1856 gp1 = CSR_READ_4(sc, JME_GPREG1);
1857 gp1 &= ~GPREG1_WA_HDX;
1859 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1862 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1864 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1866 gp1 |= GPREG1_WA_HDX;
1870 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1872 gp1 |= GPREG1_WA_HDX;
1875 * Use extended FIFO depth to workaround CRC errors
1876 * emitted by chips before JMC250B
1878 phyconf = JMPHY_CONF_EXTFIFO;
1882 if (sc->jme_caps & JME_CAP_FASTETH)
1885 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1887 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1893 CSR_WRITE_4(sc, JME_GHC, ghc);
1894 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1895 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1896 CSR_WRITE_4(sc, JME_TXPFC, txpause);
1898 if (sc->jme_workaround & JME_WA_EXTFIFO) {
1899 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1900 JMPHY_CONF, phyconf);
1902 if (sc->jme_workaround & JME_WA_HDX)
1903 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1909 struct jme_softc *sc = xsc;
1910 struct ifnet *ifp = &sc->arpcom.ac_if;
1913 ASSERT_SERIALIZED(ifp->if_serializer);
1915 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1916 if (status == 0 || status == 0xFFFFFFFF)
1919 /* Disable interrupts. */
1920 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1922 status = CSR_READ_4(sc, JME_INTR_STATUS);
1923 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1926 /* Reset PCC counter/timer and Ack interrupts. */
1927 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1928 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1929 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1930 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1931 status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP;
1932 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1934 if (ifp->if_flags & IFF_RUNNING) {
1935 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1938 if (status & INTR_RXQ_DESC_EMPTY) {
1940 * Notify hardware availability of new Rx buffers.
1941 * Reading RXCSR takes very long time under heavy
1942 * load so cache RXCSR value and writes the ORed
1943 * value with the kick command to the RXCSR. This
1944 * saves one register access cycle.
1946 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1947 RXCSR_RX_ENB | RXCSR_RXQ_START);
1950 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1952 if (!ifq_is_empty(&ifp->if_snd))
1957 /* Reenable interrupts. */
1958 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1962 jme_txeof(struct jme_softc *sc)
1964 struct ifnet *ifp = &sc->arpcom.ac_if;
1965 struct jme_txdesc *txd;
1969 cons = sc->jme_cdata.jme_tx_cons;
1970 if (cons == sc->jme_cdata.jme_tx_prod)
1973 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
1974 sc->jme_cdata.jme_tx_ring_map,
1975 BUS_DMASYNC_POSTREAD);
1978 * Go through our Tx list and free mbufs for those
1979 * frames which have been transmitted.
1981 while (cons != sc->jme_cdata.jme_tx_prod) {
1982 txd = &sc->jme_cdata.jme_txdesc[cons];
1983 KASSERT(txd->tx_m != NULL,
1984 ("%s: freeing NULL mbuf!\n", __func__));
1986 status = le32toh(txd->tx_desc->flags);
1987 if ((status & JME_TD_OWN) == JME_TD_OWN)
1990 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
1994 if (status & JME_TD_COLLISION) {
1995 ifp->if_collisions +=
1996 le32toh(txd->tx_desc->buflen) &
1997 JME_TD_BUF_LEN_MASK;
2002 * Only the first descriptor of multi-descriptor
2003 * transmission is updated so driver have to skip entire
2004 * chained buffers for the transmiited frame. In other
2005 * words, JME_TD_OWN bit is valid only at the first
2006 * descriptor of a multi-descriptor transmission.
2008 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2009 sc->jme_rdata.jme_tx_ring[cons].flags = 0;
2010 JME_DESC_INC(cons, JME_TX_RING_CNT);
2013 /* Reclaim transferred mbufs. */
2014 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2017 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2018 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2019 ("%s: Active Tx desc counter was garbled\n", __func__));
2022 sc->jme_cdata.jme_tx_cons = cons;
2024 if (sc->jme_cdata.jme_tx_cnt == 0)
2027 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2028 JME_TX_RING_CNT - JME_TXD_RSVD)
2029 ifp->if_flags &= ~IFF_OACTIVE;
2031 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2032 sc->jme_cdata.jme_tx_ring_map,
2033 BUS_DMASYNC_PREWRITE);
2036 static __inline void
2037 jme_discard_rxbufs(struct jme_softc *sc, int cons, int count)
2041 for (i = 0; i < count; ++i) {
2042 struct jme_desc *desc = &sc->jme_rdata.jme_rx_ring[cons];
2044 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2045 desc->buflen = htole32(MCLBYTES);
2046 JME_DESC_INC(cons, JME_RX_RING_CNT);
2050 /* Receive a frame. */
2052 jme_rxpkt(struct jme_softc *sc)
2054 struct ifnet *ifp = &sc->arpcom.ac_if;
2055 struct jme_desc *desc;
2056 struct jme_rxdesc *rxd;
2057 struct mbuf *mp, *m;
2058 uint32_t flags, status;
2059 int cons, count, nsegs;
2061 cons = sc->jme_cdata.jme_rx_cons;
2062 desc = &sc->jme_rdata.jme_rx_ring[cons];
2063 flags = le32toh(desc->flags);
2064 status = le32toh(desc->buflen);
2065 nsegs = JME_RX_NSEGS(status);
2067 if (status & JME_RX_ERR_STAT) {
2069 jme_discard_rxbufs(sc, cons, nsegs);
2070 #ifdef JME_SHOW_ERRORS
2071 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2072 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2074 sc->jme_cdata.jme_rx_cons += nsegs;
2075 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2079 sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2080 for (count = 0; count < nsegs; count++,
2081 JME_DESC_INC(cons, JME_RX_RING_CNT)) {
2082 rxd = &sc->jme_cdata.jme_rxdesc[cons];
2085 /* Add a new receive buffer to the ring. */
2086 if (jme_newbuf(sc, rxd, 0) != 0) {
2089 jme_discard_rxbufs(sc, cons, nsegs - count);
2090 if (sc->jme_cdata.jme_rxhead != NULL) {
2091 m_freem(sc->jme_cdata.jme_rxhead);
2092 JME_RXCHAIN_RESET(sc);
2098 * Assume we've received a full sized frame.
2099 * Actual size is fixed when we encounter the end of
2100 * multi-segmented frame.
2102 mp->m_len = MCLBYTES;
2104 /* Chain received mbufs. */
2105 if (sc->jme_cdata.jme_rxhead == NULL) {
2106 sc->jme_cdata.jme_rxhead = mp;
2107 sc->jme_cdata.jme_rxtail = mp;
2110 * Receive processor can receive a maximum frame
2111 * size of 65535 bytes.
2113 mp->m_flags &= ~M_PKTHDR;
2114 sc->jme_cdata.jme_rxtail->m_next = mp;
2115 sc->jme_cdata.jme_rxtail = mp;
2118 if (count == nsegs - 1) {
2119 /* Last desc. for this frame. */
2120 m = sc->jme_cdata.jme_rxhead;
2121 /* XXX assert PKTHDR? */
2122 m->m_flags |= M_PKTHDR;
2123 m->m_pkthdr.len = sc->jme_cdata.jme_rxlen;
2125 /* Set first mbuf size. */
2126 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2127 /* Set last mbuf size. */
2128 mp->m_len = sc->jme_cdata.jme_rxlen -
2129 ((MCLBYTES - JME_RX_PAD_BYTES) +
2130 (MCLBYTES * (nsegs - 2)));
2132 m->m_len = sc->jme_cdata.jme_rxlen;
2134 m->m_pkthdr.rcvif = ifp;
2137 * Account for 10bytes auto padding which is used
2138 * to align IP header on 32bit boundary. Also note,
2139 * CRC bytes is automatically removed by the
2142 m->m_data += JME_RX_PAD_BYTES;
2144 /* Set checksum information. */
2145 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2146 (flags & JME_RD_IPV4)) {
2147 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2148 if (flags & JME_RD_IPCSUM)
2149 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2150 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2151 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2152 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2153 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2154 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2155 m->m_pkthdr.csum_flags |=
2156 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2157 m->m_pkthdr.csum_data = 0xffff;
2161 /* Check for VLAN tagged packets. */
2162 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2163 (flags & JME_RD_VLAN_TAG)) {
2164 m->m_pkthdr.ether_vlantag =
2165 flags & JME_RD_VLAN_MASK;
2166 m->m_flags |= M_VLANTAG;
2171 ifp->if_input(ifp, m);
2173 /* Reset mbuf chains. */
2174 JME_RXCHAIN_RESET(sc);
2178 sc->jme_cdata.jme_rx_cons += nsegs;
2179 sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT;
2183 jme_rxeof(struct jme_softc *sc)
2185 struct jme_desc *desc;
2186 int nsegs, prog, pktlen;
2188 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2189 sc->jme_cdata.jme_rx_ring_map,
2190 BUS_DMASYNC_POSTREAD);
2194 desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons];
2195 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2197 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2201 * Check number of segments against received bytes.
2202 * Non-matching value would indicate that hardware
2203 * is still trying to update Rx descriptors. I'm not
2204 * sure whether this check is needed.
2206 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2207 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2208 if (nsegs != howmany(pktlen, MCLBYTES)) {
2209 if_printf(&sc->arpcom.ac_if, "RX fragment count(%d) "
2210 "and packet size(%d) mismach\n",
2215 /* Received a frame. */
2221 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2222 sc->jme_cdata.jme_rx_ring_map,
2223 BUS_DMASYNC_PREWRITE);
2230 struct jme_softc *sc = xsc;
2231 struct ifnet *ifp = &sc->arpcom.ac_if;
2232 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2234 lwkt_serialize_enter(ifp->if_serializer);
2237 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2239 lwkt_serialize_exit(ifp->if_serializer);
2243 jme_reset(struct jme_softc *sc)
2246 /* Stop receiver, transmitter. */
2250 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2252 CSR_WRITE_4(sc, JME_GHC, 0);
2258 struct jme_softc *sc = xsc;
2259 struct ifnet *ifp = &sc->arpcom.ac_if;
2260 struct mii_data *mii;
2261 uint8_t eaddr[ETHER_ADDR_LEN];
2266 ASSERT_SERIALIZED(ifp->if_serializer);
2269 * Cancel any pending I/O.
2274 * Reset the chip to a known state.
2279 * Since we always use 64bit address mode for transmitting,
2280 * each Tx request requires one more dummy descriptor.
2283 howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES) + 1;
2284 KKASSERT(sc->jme_txd_spare >= 2);
2286 /* Init descriptors. */
2287 error = jme_init_rx_ring(sc);
2289 device_printf(sc->jme_dev,
2290 "%s: initialization failed: no memory for Rx buffers.\n",
2295 jme_init_tx_ring(sc);
2297 /* Initialize shadow status block. */
2300 /* Reprogram the station address. */
2301 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2302 CSR_WRITE_4(sc, JME_PAR0,
2303 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2304 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2307 * Configure Tx queue.
2308 * Tx priority queue weight value : 0
2309 * Tx FIFO threshold for processing next packet : 16QW
2310 * Maximum Tx DMA length : 512
2311 * Allow Tx DMA burst.
2313 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2314 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2315 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2316 sc->jme_txcsr |= sc->jme_tx_dma_size;
2317 sc->jme_txcsr |= TXCSR_DMA_BURST;
2318 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2320 /* Set Tx descriptor counter. */
2321 CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT);
2323 /* Set Tx ring address to the hardware. */
2324 paddr = JME_TX_RING_ADDR(sc, 0);
2325 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2326 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2328 /* Configure TxMAC parameters. */
2329 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2330 reg |= TXMAC_THRESH_1_PKT;
2331 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2332 CSR_WRITE_4(sc, JME_TXMAC, reg);
2335 * Configure Rx queue.
2336 * FIFO full threshold for transmitting Tx pause packet : 128T
2337 * FIFO threshold for processing next packet : 128QW
2339 * Max Rx DMA length : 128
2340 * Rx descriptor retry : 32
2341 * Rx descriptor retry time gap : 256ns
2342 * Don't receive runt/bad frame.
2344 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2346 * Since Rx FIFO size is 4K bytes, receiving frames larger
2347 * than 4K bytes will suffer from Rx FIFO overruns. So
2348 * decrease FIFO threshold to reduce the FIFO overruns for
2349 * frames larger than 4000 bytes.
2350 * For best performance of standard MTU sized frames use
2351 * maximum allowable FIFO threshold, 128QW.
2353 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2355 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2357 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2358 sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0);
2359 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2360 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2361 /* XXX TODO DROP_BAD */
2362 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr);
2364 /* Set Rx descriptor counter. */
2365 CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT);
2367 /* Set Rx ring address to the hardware. */
2368 paddr = JME_RX_RING_ADDR(sc, 0);
2369 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2370 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2372 /* Clear receive filter. */
2373 CSR_WRITE_4(sc, JME_RXMAC, 0);
2375 /* Set up the receive filter. */
2380 * Disable all WOL bits as WOL can interfere normal Rx
2381 * operation. Also clear WOL detection status bits.
2383 reg = CSR_READ_4(sc, JME_PMCS);
2384 reg &= ~PMCS_WOL_ENB_MASK;
2385 CSR_WRITE_4(sc, JME_PMCS, reg);
2388 * Pad 10bytes right before received frame. This will greatly
2389 * help Rx performance on strict-alignment architectures as
2390 * it does not need to copy the frame to align the payload.
2392 reg = CSR_READ_4(sc, JME_RXMAC);
2393 reg |= RXMAC_PAD_10BYTES;
2395 if (ifp->if_capenable & IFCAP_RXCSUM)
2396 reg |= RXMAC_CSUM_ENB;
2397 CSR_WRITE_4(sc, JME_RXMAC, reg);
2399 /* Configure general purpose reg0 */
2400 reg = CSR_READ_4(sc, JME_GPREG0);
2401 reg &= ~GPREG0_PCC_UNIT_MASK;
2402 /* Set PCC timer resolution to micro-seconds unit. */
2403 reg |= GPREG0_PCC_UNIT_US;
2405 * Disable all shadow register posting as we have to read
2406 * JME_INTR_STATUS register in jme_intr. Also it seems
2407 * that it's hard to synchronize interrupt status between
2408 * hardware and software with shadow posting due to
2409 * requirements of bus_dmamap_sync(9).
2411 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2412 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2413 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2414 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2415 /* Disable posting of DW0. */
2416 reg &= ~GPREG0_POST_DW0_ENB;
2417 /* Clear PME message. */
2418 reg &= ~GPREG0_PME_ENB;
2419 /* Set PHY address. */
2420 reg &= ~GPREG0_PHY_ADDR_MASK;
2421 reg |= sc->jme_phyaddr;
2422 CSR_WRITE_4(sc, JME_GPREG0, reg);
2424 /* Configure Tx queue 0 packet completion coalescing. */
2425 jme_set_tx_coal(sc);
2427 /* Configure Rx queue 0 packet completion coalescing. */
2428 jme_set_rx_coal(sc);
2430 /* Configure shadow status block but don't enable posting. */
2431 paddr = sc->jme_rdata.jme_ssb_block_paddr;
2432 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2433 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2435 /* Disable Timer 1 and Timer 2. */
2436 CSR_WRITE_4(sc, JME_TIMER1, 0);
2437 CSR_WRITE_4(sc, JME_TIMER2, 0);
2439 /* Configure retry transmit period, retry limit value. */
2440 CSR_WRITE_4(sc, JME_TXTRHD,
2441 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2442 TXTRHD_RT_PERIOD_MASK) |
2443 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2444 TXTRHD_RT_LIMIT_SHIFT));
2447 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
2449 /* Initialize the interrupt mask. */
2450 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2451 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2454 * Enabling Tx/Rx DMA engines and Rx queue processing is
2455 * done after detection of valid link in jme_miibus_statchg.
2457 sc->jme_flags &= ~JME_FLAG_LINK;
2459 /* Set the current media. */
2460 mii = device_get_softc(sc->jme_miibus);
2463 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2465 ifp->if_flags |= IFF_RUNNING;
2466 ifp->if_flags &= ~IFF_OACTIVE;
2470 jme_stop(struct jme_softc *sc)
2472 struct ifnet *ifp = &sc->arpcom.ac_if;
2473 struct jme_txdesc *txd;
2474 struct jme_rxdesc *rxd;
2477 ASSERT_SERIALIZED(ifp->if_serializer);
2480 * Mark the interface down and cancel the watchdog timer.
2482 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2485 callout_stop(&sc->jme_tick_ch);
2486 sc->jme_flags &= ~JME_FLAG_LINK;
2489 * Disable interrupts.
2491 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2492 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2494 /* Disable updating shadow status block. */
2495 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2496 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2498 /* Stop receiver, transmitter. */
2503 /* Reclaim Rx/Tx buffers that have been completed. */
2505 if (sc->jme_cdata.jme_rxhead != NULL)
2506 m_freem(sc->jme_cdata.jme_rxhead);
2507 JME_RXCHAIN_RESET(sc);
2512 * Free partial finished RX segments
2514 if (sc->jme_cdata.jme_rxhead != NULL)
2515 m_freem(sc->jme_cdata.jme_rxhead);
2516 JME_RXCHAIN_RESET(sc);
2519 * Free RX and TX mbufs still in the queues.
2521 for (i = 0; i < JME_RX_RING_CNT; i++) {
2522 rxd = &sc->jme_cdata.jme_rxdesc[i];
2523 if (rxd->rx_m != NULL) {
2524 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2530 for (i = 0; i < JME_TX_RING_CNT; i++) {
2531 txd = &sc->jme_cdata.jme_txdesc[i];
2532 if (txd->tx_m != NULL) {
2533 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2543 jme_stop_tx(struct jme_softc *sc)
2548 reg = CSR_READ_4(sc, JME_TXCSR);
2549 if ((reg & TXCSR_TX_ENB) == 0)
2551 reg &= ~TXCSR_TX_ENB;
2552 CSR_WRITE_4(sc, JME_TXCSR, reg);
2553 for (i = JME_TIMEOUT; i > 0; i--) {
2555 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2559 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2563 jme_stop_rx(struct jme_softc *sc)
2568 reg = CSR_READ_4(sc, JME_RXCSR);
2569 if ((reg & RXCSR_RX_ENB) == 0)
2571 reg &= ~RXCSR_RX_ENB;
2572 CSR_WRITE_4(sc, JME_RXCSR, reg);
2573 for (i = JME_TIMEOUT; i > 0; i--) {
2575 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2579 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2583 jme_init_tx_ring(struct jme_softc *sc)
2585 struct jme_ring_data *rd;
2586 struct jme_txdesc *txd;
2589 sc->jme_cdata.jme_tx_prod = 0;
2590 sc->jme_cdata.jme_tx_cons = 0;
2591 sc->jme_cdata.jme_tx_cnt = 0;
2593 rd = &sc->jme_rdata;
2594 bzero(rd->jme_tx_ring, JME_TX_RING_SIZE);
2595 for (i = 0; i < JME_TX_RING_CNT; i++) {
2596 txd = &sc->jme_cdata.jme_txdesc[i];
2598 txd->tx_desc = &rd->jme_tx_ring[i];
2602 bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag,
2603 sc->jme_cdata.jme_tx_ring_map,
2604 BUS_DMASYNC_PREWRITE);
2608 jme_init_ssb(struct jme_softc *sc)
2610 struct jme_ring_data *rd;
2612 rd = &sc->jme_rdata;
2613 bzero(rd->jme_ssb_block, JME_SSB_SIZE);
2614 bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map,
2615 BUS_DMASYNC_PREWRITE);
2619 jme_init_rx_ring(struct jme_softc *sc)
2621 struct jme_ring_data *rd;
2622 struct jme_rxdesc *rxd;
2625 KKASSERT(sc->jme_cdata.jme_rxhead == NULL &&
2626 sc->jme_cdata.jme_rxtail == NULL &&
2627 sc->jme_cdata.jme_rxlen == 0);
2628 sc->jme_cdata.jme_rx_cons = 0;
2630 rd = &sc->jme_rdata;
2631 bzero(rd->jme_rx_ring, JME_RX_RING_SIZE);
2632 for (i = 0; i < JME_RX_RING_CNT; i++) {
2635 rxd = &sc->jme_cdata.jme_rxdesc[i];
2637 rxd->rx_desc = &rd->jme_rx_ring[i];
2638 error = jme_newbuf(sc, rxd, 1);
2643 bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag,
2644 sc->jme_cdata.jme_rx_ring_map,
2645 BUS_DMASYNC_PREWRITE);
2650 jme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd, int init)
2652 struct jme_desc *desc;
2654 struct jme_dmamap_ctx ctx;
2655 bus_dma_segment_t segs;
2659 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2663 * JMC250 has 64bit boundary alignment limitation so jme(4)
2664 * takes advantage of 10 bytes padding feature of hardware
2665 * in order not to copy entire frame to align IP header on
2668 m->m_len = m->m_pkthdr.len = MCLBYTES;
2672 error = bus_dmamap_load_mbuf(sc->jme_cdata.jme_rx_tag,
2673 sc->jme_cdata.jme_rx_sparemap,
2674 m, jme_dmamap_buf_cb, &ctx,
2676 if (error || ctx.nsegs == 0) {
2678 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag,
2679 sc->jme_cdata.jme_rx_sparemap);
2681 if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
2686 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2690 if (rxd->rx_m != NULL) {
2691 bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap,
2692 BUS_DMASYNC_POSTREAD);
2693 bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap);
2695 map = rxd->rx_dmamap;
2696 rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap;
2697 sc->jme_cdata.jme_rx_sparemap = map;
2700 desc = rxd->rx_desc;
2701 desc->buflen = htole32(segs.ds_len);
2702 desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2703 desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2704 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2710 jme_set_vlan(struct jme_softc *sc)
2712 struct ifnet *ifp = &sc->arpcom.ac_if;
2715 ASSERT_SERIALIZED(ifp->if_serializer);
2717 reg = CSR_READ_4(sc, JME_RXMAC);
2718 reg &= ~RXMAC_VLAN_ENB;
2719 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2720 reg |= RXMAC_VLAN_ENB;
2721 CSR_WRITE_4(sc, JME_RXMAC, reg);
2725 jme_set_filter(struct jme_softc *sc)
2727 struct ifnet *ifp = &sc->arpcom.ac_if;
2728 struct ifmultiaddr *ifma;
2733 ASSERT_SERIALIZED(ifp->if_serializer);
2735 rxcfg = CSR_READ_4(sc, JME_RXMAC);
2736 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2740 * Always accept frames destined to our station address.
2741 * Always accept broadcast frames.
2743 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2745 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2746 if (ifp->if_flags & IFF_PROMISC)
2747 rxcfg |= RXMAC_PROMISC;
2748 if (ifp->if_flags & IFF_ALLMULTI)
2749 rxcfg |= RXMAC_ALLMULTI;
2750 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2751 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2752 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2757 * Set up the multicast address filter by passing all multicast
2758 * addresses through a CRC generator, and then using the low-order
2759 * 6 bits as an index into the 64 bit multicast hash table. The
2760 * high order bits select the register, while the rest of the bits
2761 * select the bit within the register.
2763 rxcfg |= RXMAC_MULTICAST;
2764 bzero(mchash, sizeof(mchash));
2766 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2767 if (ifma->ifma_addr->sa_family != AF_LINK)
2769 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2770 ifma->ifma_addr), ETHER_ADDR_LEN);
2772 /* Just want the 6 least significant bits. */
2775 /* Set the corresponding bit in the hash table. */
2776 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2779 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2780 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2781 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2785 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2787 struct jme_softc *sc = arg1;
2788 struct ifnet *ifp = &sc->arpcom.ac_if;
2791 lwkt_serialize_enter(ifp->if_serializer);
2793 v = sc->jme_tx_coal_to;
2794 error = sysctl_handle_int(oidp, &v, 0, req);
2795 if (error || req->newptr == NULL)
2798 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2803 if (v != sc->jme_tx_coal_to) {
2804 sc->jme_tx_coal_to = v;
2805 if (ifp->if_flags & IFF_RUNNING)
2806 jme_set_tx_coal(sc);
2809 lwkt_serialize_exit(ifp->if_serializer);
2814 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2816 struct jme_softc *sc = arg1;
2817 struct ifnet *ifp = &sc->arpcom.ac_if;
2820 lwkt_serialize_enter(ifp->if_serializer);
2822 v = sc->jme_tx_coal_pkt;
2823 error = sysctl_handle_int(oidp, &v, 0, req);
2824 if (error || req->newptr == NULL)
2827 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2832 if (v != sc->jme_tx_coal_pkt) {
2833 sc->jme_tx_coal_pkt = v;
2834 if (ifp->if_flags & IFF_RUNNING)
2835 jme_set_tx_coal(sc);
2838 lwkt_serialize_exit(ifp->if_serializer);
2843 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2845 struct jme_softc *sc = arg1;
2846 struct ifnet *ifp = &sc->arpcom.ac_if;
2849 lwkt_serialize_enter(ifp->if_serializer);
2851 v = sc->jme_rx_coal_to;
2852 error = sysctl_handle_int(oidp, &v, 0, req);
2853 if (error || req->newptr == NULL)
2856 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2861 if (v != sc->jme_rx_coal_to) {
2862 sc->jme_rx_coal_to = v;
2863 if (ifp->if_flags & IFF_RUNNING)
2864 jme_set_rx_coal(sc);
2867 lwkt_serialize_exit(ifp->if_serializer);
2872 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2874 struct jme_softc *sc = arg1;
2875 struct ifnet *ifp = &sc->arpcom.ac_if;
2878 lwkt_serialize_enter(ifp->if_serializer);
2880 v = sc->jme_rx_coal_pkt;
2881 error = sysctl_handle_int(oidp, &v, 0, req);
2882 if (error || req->newptr == NULL)
2885 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
2890 if (v != sc->jme_rx_coal_pkt) {
2891 sc->jme_rx_coal_pkt = v;
2892 if (ifp->if_flags & IFF_RUNNING)
2893 jme_set_rx_coal(sc);
2896 lwkt_serialize_exit(ifp->if_serializer);
2901 jme_set_tx_coal(struct jme_softc *sc)
2905 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
2907 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
2908 PCCTX_COAL_PKT_MASK;
2909 reg |= PCCTX_COAL_TXQ0;
2910 CSR_WRITE_4(sc, JME_PCCTX, reg);
2914 jme_set_rx_coal(struct jme_softc *sc)
2918 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
2920 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
2921 PCCRX_COAL_PKT_MASK;
2922 CSR_WRITE_4(sc, JME_PCCRX0, reg);