2 * Copyright (c) 2004, Joerg Sonnenberger <joerg@bec.de>
4 * Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $DragonFly: src/sys/bus/pci/pci_pcib.c,v 1.8 2007/11/28 11:35:40 sephe Exp $
34 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
40 #include <sys/systm.h>
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
45 #include "pcib_private.h"
47 static devclass_t pcib_devclass;
50 * Attach a pci bus device to a motherboard or pci-to-pci bridge bus.
51 * Due to probe recursion it is possible for pci-to-pci bridges (such as
52 * on the DELL2550) to attach before all the motherboard bridges have
53 * attached. We must call device_add_child() with the secondary id
54 * rather then -1 in order to ensure that we do not accidently use
55 * a motherboard PCI id, otherwise the device probe will believe that
56 * the later motherboard bridge bus has already been probed and refuse
57 * to probe it. The result: disappearing busses!
59 * Bridges will cause recursions or duplicate attach attempts. If
60 * we have already attached this bus we don't do it again!
62 * NOTE THE DEVICE TOPOLOGY!
64 * [pcibX]->[pciX]->[pciX.Y]
67 * When attaching a new bus device note that the PCI methods are
68 * based in the parent device, but the device ivars for those methods
69 * are based in our sub-device. The PCI accessor functions all assume
70 * you are passing-in the sub-device.
73 pcib_attach_common(device_t dev)
75 struct pcib_softc *sc;
78 sc = device_get_softc(dev);
82 * Get current bridge configuration.
84 sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
85 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
86 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
87 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
88 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
89 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
92 * Determine current I/O decode.
94 if (sc->command & PCIM_CMD_PORTEN) {
95 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
96 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
97 sc->iobase = PCI_PPBIOBASE(pci_read_config(dev, PCIR_IOBASEH_1, 2),
98 pci_read_config(dev, PCIR_IOBASEL_1, 1));
100 sc->iobase = PCI_PPBIOBASE(0, pci_read_config(dev, PCIR_IOBASEL_1, 1));
103 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
104 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
105 sc->iolimit = PCI_PPBIOLIMIT(pci_read_config(dev, PCIR_IOLIMITH_1, 2),
106 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
108 sc->iolimit = PCI_PPBIOLIMIT(0, pci_read_config(dev, PCIR_IOLIMITL_1, 1));
113 * Determine current memory decode.
115 if (sc->command & PCIM_CMD_MEMEN) {
116 sc->membase = PCI_PPBMEMBASE(0, pci_read_config(dev, PCIR_MEMBASE_1, 2));
117 sc->memlimit = PCI_PPBMEMLIMIT(0, pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
118 sc->pmembase = PCI_PPBMEMBASE((pci_addr_t)pci_read_config(dev, PCIR_PMBASEH_1, 4),
119 pci_read_config(dev, PCIR_PMBASEL_1, 2));
120 sc->pmemlimit = PCI_PPBMEMLIMIT((pci_addr_t)pci_read_config(dev, PCIR_PMLIMITH_1, 4),
121 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
127 switch (pci_get_devid(dev)) {
128 case 0x12258086: /* Intel 82454KX/GX (Orion) */
132 supbus = pci_read_config(dev, 0x41, 1);
133 if (supbus != 0xff) {
134 sc->secbus = supbus + 1;
135 sc->subbus = supbus + 1;
141 * The i82380FB mobile docking controller is a PCI-PCI bridge,
142 * and it is a subtractive bridge. However, the ProgIf is wrong
143 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
144 * happen. There's also a Toshiba bridge that behaves this
147 case 0x124b8086: /* Intel 82380FB Mobile */
148 case 0x060513d7: /* Toshiba ???? */
149 sc->flags |= PCIB_SUBTRACTIVE;
154 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
155 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
156 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
157 * This means they act as if they were subtractively decoding
158 * bridges and pass all transactions. Mark them and real ProgIf 1
159 * parts as subtractive.
161 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
162 pci_read_config(dev, PCIR_PROGIF, 1) == 1)
163 sc->flags |= PCIB_SUBTRACTIVE;
166 device_printf(dev, " secondary bus %d\n", sc->secbus);
167 device_printf(dev, " subordinate bus %d\n", sc->subbus);
168 device_printf(dev, " I/O decode 0x%x-0x%x\n", sc->iobase, sc->iolimit);
169 device_printf(dev, " memory decode 0x%x-0x%x\n", sc->membase, sc->memlimit);
170 device_printf(dev, " prefetched decode 0x%x-0x%x\n", sc->pmembase, sc->pmemlimit);
171 if (sc->flags & PCIB_SUBTRACTIVE)
172 device_printf(dev, " Subtractively decoded bridge.\n");
175 if (pci_is_pcie(dev) && pcie_slot_implemented(dev)) {
181 * Before proper PCI Express hot-plug support is in place,
182 * disable all hot-plug interrupts on the PCI Express root
183 * port or down stream port for now.
185 #define HPINTRS (PCIEM_SLTCTL_HPINTR_MASK | PCIEM_SLTCTL_HPINTR_EN)
187 ptr = pci_get_pciecap_ptr(dev);
188 slot_ctrl = pci_read_config(dev, ptr + PCIER_SLOTCTRL, 2);
189 if (slot_ctrl & HPINTRS) {
190 device_printf(dev, "Disable PCI Express hot-plug "
191 "interrupts(0x%04x)\n", slot_ctrl & HPINTRS);
192 slot_ctrl &= ~HPINTRS;
193 pci_write_config(dev, ptr + PCIER_SLOTCTRL, slot_ctrl, 2);
200 * XXX If the secondary bus number is zero, we should assign a bus number
201 * since the BIOS hasn't, then initialise the bridge.
205 * XXX If the subordinate bus number is less than the secondary bus number,
206 * we should pick a better value. One sensible alternative would be to
207 * pick 255; the only tradeoff here is that configuration transactions
208 * would be more widely routed than absolutely necessary.
213 * Called with the bridge candidate, which is under a PCI slot device.
214 * Note that the ivars are stored in the candidate.
217 pci_match_bridge(device_t dev)
219 switch (pci_get_devid(dev)) {
220 /* Intel -- vendor 0x8086 */
222 return ("Intel 82443LX (440 LX) PCI-PCI (AGP) bridge");
224 return ("Intel 82443BX (440 BX) PCI-PCI (AGP) bridge");
226 return ("Intel 82443GX (440 GX) PCI-PCI (AGP) bridge");
228 return ("Intel 82454NX PCI Expander Bridge");
230 return ("Intel 82801BA/BAM (ICH2) PCI-PCI (AGP) bridge");
232 return ("Intel 82380FB mobile PCI to PCI bridge");
234 return ("Intel 82801AA (ICH) Hub to PCI bridge");
236 return ("Intel 82801AB (ICH0) Hub to PCI bridge");
238 return ("Intel 82801BA/CA/DB/EB/FB (ICH2/3/4/5/6) Hub to PCI bridge");
240 return ("Intel 82845 PCI-PCI (AGP) bridge");
242 /* VLSI -- vendor 0x1004 */
244 return ("VLSI 82C534 Eagle II PCI Bus bridge");
246 return ("VLSI 82C538 Eagle II PCI Docking bridge");
248 /* VIA Technologies -- vendor 0x1106 */
250 return ("VIA 8363 (Apollo KT133) PCI-PCI (AGP) bridge");
252 return ("VIA 82C598MVP (Apollo MVP3) PCI-PCI (AGP) bridge");
253 /* Exclude the ACPI function of VT82Cxxx series */
259 /* AcerLabs -- vendor 0x10b9 */
260 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
261 /* id is '10b9" but the register always shows "10b9". -Foxfair */
263 return ("AcerLabs M5247 PCI-PCI(AGP Supported) bridge");
264 case 0x524310b9:/* 5243 seems like 5247, need more info to divide*/
265 return ("AcerLabs M5243 PCI-PCI bridge");
267 /* AMD -- vendor 0x1022 */
269 return ("AMD-751 PCI-PCI (1x/2x AGP) bridge");
271 return ("AMD-761 PCI-PCI (4x AGP) bridge");
273 /* DEC -- vendor 0x1011 */
275 return ("DEC 21050 PCI-PCI bridge");
277 return ("DEC 21052 PCI-PCI bridge");
279 return ("DEC 21150 PCI-PCI bridge");
281 return ("DEC 21152 PCI-PCI bridge");
283 return ("DEC 21153 PCI-PCI bridge");
285 return ("DEC 21154 PCI-PCI bridge");
287 /* NVIDIA -- vendor 0x10de */
290 return ("NVIDIA nForce2 PCI-PCI bridge");
294 return ("IBM 82351 PCI-PCI bridge");
295 /* UMC United Microelectronics 0x1060 */
297 return ("UMC UM8881 HB4 486 PCI Chipset");
300 if (pci_get_class(dev) == PCIC_BRIDGE
301 && pci_get_subclass(dev) == PCIS_BRIDGE_PCI) {
302 return pci_bridge_type(dev);
309 * bus/pci/i386/pcibus.c added "pcib" devices under "pci" (slot) devices,
310 * causing us to probe and attach here.
312 * Note that the parent "pci" device has stored ivars in our device. We
313 * are both a "pci" device and potentially a "pcib" device.
316 pcib_probe(device_t dev)
320 desc = pci_match_bridge(dev);
322 device_set_desc_copy(dev, desc);
330 * Note that the "pci" device ivars are stored in the ivar data field
331 * for our device. The "pcib" device ivars are stored in the softc
335 pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
337 struct pcib_softc *sc = device_get_softc(dev);
341 *result = sc->secbus;
348 pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
350 struct pcib_softc *sc = device_get_softc(dev);
361 pcib_attach(device_t dev)
363 struct pcib_softc *sc;
365 pcib_attach_common(dev);
366 sc = device_get_softc(dev);
367 /*chipset_attach(dev, device_get_unit(dev));*/
370 * The pcib unit is not really under our control because
371 * we have are not (XXX) using the identify interface to
372 * assign the bridge driver, instead letting subr_bus do
373 * it via the probe mechanism. However, we *do* directly
374 * create the "pci" children and we can control the unit
375 * number we assign for those. We assign the secondary bus
376 * id as the unit number.
378 if (sc->secbus != 0) {
379 if (devclass_find_unit("pci", sc->secbus)) {
380 device_printf(dev, "Duplicate secondary bus %d, "
381 "cannot attach bridge\n",
385 device_add_child(dev, "pci", sc->secbus);
386 bus_generic_attach(dev);
393 * Is the prefetch window open (eg, can we allocate memory in it?)
396 pcib_is_prefetch_open(struct pcib_softc *sc)
398 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
402 * Is the nonprefetch window open (eg, can we allocate memory in it?)
405 pcib_is_nonprefetch_open(struct pcib_softc *sc)
407 return (sc->membase > 0 && sc->membase < sc->memlimit);
411 * Is the io window open (eg, can we allocate ports in it?)
414 pcib_is_io_open(struct pcib_softc *sc)
416 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
420 * We have to trap resource allocation requests and ensure that the bridge
421 * is set up to, or capable of handling them.
424 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
425 u_long start, u_long end, u_long count, u_int flags)
427 struct pcib_softc *sc = device_get_softc(dev);
431 * Fail the allocation for this range if it's not supported.
436 if (!pcib_is_io_open(sc))
438 ok = (start >= sc->iobase && end <= sc->iolimit);
439 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
441 if (start < sc->iobase)
443 if (end > sc->iolimit)
451 if (start < sc->iobase && end > sc->iolimit) {
458 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", end, start);
464 device_printf(dev, "device %s requested unsupported I/O "
465 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
466 device_get_nameunit(child), start, end,
467 sc->iobase, sc->iolimit);
471 device_printf(dev, "device %s requested decoded I/O range 0x%lx-0x%lx\n",
472 device_get_nameunit(child), start, end);
477 if (pcib_is_nonprefetch_open(sc))
478 ok = ok || (start >= sc->membase && end <= sc->memlimit);
479 if (pcib_is_prefetch_open(sc))
480 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
481 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
484 if (flags & RF_PREFETCHABLE) {
485 if (pcib_is_prefetch_open(sc)) {
486 if (start < sc->pmembase)
487 start = sc->pmembase;
488 if (end > sc->pmemlimit)
493 } else { /* non-prefetchable */
494 if (pcib_is_nonprefetch_open(sc)) {
495 if (start < sc->membase)
497 if (end > sc->memlimit)
505 ok = 1; /* subtractive bridge: always ok */
507 if (pcib_is_nonprefetch_open(sc)) {
508 if (start < sc->membase && end > sc->memlimit) {
513 if (pcib_is_prefetch_open(sc)) {
514 if (start < sc->pmembase && end > sc->pmemlimit) {
515 start = sc->pmembase;
522 device_printf(dev, "memory: end (%lx) < start (%lx)\n", end, start);
527 if (!ok && bootverbose)
529 "device %s requested unsupported memory range "
530 "0x%lx-0x%lx (decoding 0x%x-0x%x, 0x%x-0x%x)\n",
531 device_get_nameunit(child), start, end,
532 sc->membase, sc->memlimit, sc->pmembase,
537 device_printf(dev,"device %s requested decoded memory range 0x%lx-0x%lx\n",
538 device_get_nameunit(child), start, end);
545 * Bridge is OK decoding this resource, so pass it up.
547 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags));
551 pcib_maxslots(device_t dev)
557 pcib_read_config(device_t dev, int b, int s, int f,
561 * Pass through to the next ppb up the chain (i.e. our
564 * [pcibX]->[pciX]->[pciX.Y]
567 * getting back to this point.
569 return PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)),
570 b, s, f, reg, width);
574 pcib_write_config(device_t dev, int b, int s, int f,
575 int reg, uint32_t val, int width)
578 * Pass through to the next ppb up the chain (i.e. our
581 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)),
582 b, s, f, reg, val, width);
586 * Route an interrupt across a PCI bridge.
588 * pcib - is the pci bridge device
589 * dev - is the device
592 pcib_route_interrupt(device_t pcib, device_t dev, int pin)
600 * The PCI standard defines a swizzle of the child-side device/intpin
601 * to the parent-side intpin as follows.
603 * device = device on child bus
604 * child_intpin = intpin on child bus slot (0-3)
605 * parent_intpin = intpin on parent bus slot (0-3)
607 * parent_intpin = (device + child_intpin) % 4
609 parent_intpin = (pci_get_slot(pcib) + (pin - 1)) % 4;
612 * Our parent is a PCI bus. Its parent must export the pci interface
613 * which includes the ability to route interrupts.
615 bus = device_get_parent(pcib);
616 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib,
618 device_printf(pcib, "routed slot %d INT%c to irq %d\n",
619 pci_get_slot(dev), 'A' + pin - 1, intnum);
624 * Try to read the bus number of a host-PCI bridge using appropriate config
628 host_pcib_get_busno(pci_read_config_fn read_config, int bus, int slot, int func,
633 id = read_config(bus, slot, func, PCIR_DEVVENDOR, 4);
634 if (id == 0xffffffff)
640 /* XXX This is a guess */
641 /* *busnum = read_config(bus, slot, func, 0x41, 1); */
645 /* Intel 82454KX/GX (Orion) */
646 *busnum = read_config(bus, slot, func, 0x4a, 1);
650 * For the 450nx chipset, there is a whole bundle of
651 * things pretending to be host bridges. The MIOC will
652 * be seen first and isn't really a pci bridge (the
653 * actual busses are attached to the PXB's). We need to
654 * read the registers of the MIOC to figure out the
655 * bus numbers for the PXB channels.
657 * Since the MIOC doesn't have a pci bus attached, we
658 * pretend it wasn't there.
664 /* Intel 82454NX PXB#0, Bus#A */
665 *busnum = read_config(bus, 0x10, func, 0xd0, 1);
668 /* Intel 82454NX PXB#0, Bus#B */
669 *busnum = read_config(bus, 0x10, func, 0xd1, 1) + 1;
672 /* Intel 82454NX PXB#1, Bus#A */
673 *busnum = read_config(bus, 0x10, func, 0xd3, 1);
676 /* Intel 82454NX PXB#1, Bus#B */
677 *busnum = read_config(bus, 0x10, func, 0xd4, 1) + 1;
682 /* ServerWorks -- vendor 0x1166 */
694 *busnum = read_config(bus, slot, func, 0x44, 1);
697 /* Don't know how to read bus number. */
704 static device_method_t pcib_methods[] = {
705 /* Device interface */
706 DEVMETHOD(device_probe, pcib_probe),
707 DEVMETHOD(device_attach, pcib_attach),
708 DEVMETHOD(device_shutdown, bus_generic_shutdown),
709 DEVMETHOD(device_suspend, bus_generic_suspend),
710 DEVMETHOD(device_resume, bus_generic_resume),
713 DEVMETHOD(bus_print_child, bus_generic_print_child),
714 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
715 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
716 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
717 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
718 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
719 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
720 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
721 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
724 DEVMETHOD(pcib_maxslots, pcib_maxslots),
725 DEVMETHOD(pcib_read_config, pcib_read_config),
726 DEVMETHOD(pcib_write_config, pcib_write_config),
727 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
732 static driver_t pcib_driver = {
735 sizeof(struct pcib_softc)
738 DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, 0, 0);