2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $
30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
32 #include <sys/param.h>
33 #include <sys/endian.h>
34 #include <sys/kernel.h>
36 #include <sys/interrupt.h>
37 #include <sys/malloc.h>
40 #include <sys/serialize.h>
41 #include <sys/socket.h>
42 #include <sys/sockio.h>
43 #include <sys/sysctl.h>
45 #include <net/ethernet.h>
48 #include <net/if_arp.h>
49 #include <net/if_dl.h>
50 #include <net/if_llc.h>
51 #include <net/if_media.h>
52 #include <net/ifq_var.h>
53 #include <net/vlan/if_vlan_var.h>
54 #include <net/vlan/if_vlan_ether.h>
56 #include <netinet/ip.h>
58 #include <dev/netif/mii_layer/miivar.h>
59 #include <dev/netif/mii_layer/jmphyreg.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
63 #include <bus/pci/pcidevs.h>
65 #include <dev/netif/ale/if_alereg.h>
66 #include <dev/netif/ale/if_alevar.h>
68 /* "device miibus" required. See GENERIC if you get errors here. */
69 #include "miibus_if.h"
71 /* For more information about Tx checksum offload issues see ale_encap(). */
72 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
74 struct ale_dmamap_ctx {
76 bus_dma_segment_t *segs;
79 static int ale_probe(device_t);
80 static int ale_attach(device_t);
81 static int ale_detach(device_t);
82 static int ale_shutdown(device_t);
83 static int ale_suspend(device_t);
84 static int ale_resume(device_t);
86 static int ale_miibus_readreg(device_t, int, int);
87 static int ale_miibus_writereg(device_t, int, int, int);
88 static void ale_miibus_statchg(device_t);
90 static void ale_init(void *);
91 static void ale_start(struct ifnet *);
92 static int ale_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
93 static void ale_watchdog(struct ifnet *);
94 static int ale_mediachange(struct ifnet *);
95 static void ale_mediastatus(struct ifnet *, struct ifmediareq *);
97 static void ale_intr(void *);
98 static int ale_rxeof(struct ale_softc *sc);
99 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
100 uint32_t, uint32_t *);
101 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
102 static void ale_txeof(struct ale_softc *);
104 static int ale_dma_alloc(struct ale_softc *);
105 static void ale_dma_free(struct ale_softc *);
106 static int ale_check_boundary(struct ale_softc *);
107 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
108 static void ale_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
110 static int ale_encap(struct ale_softc *, struct mbuf **);
111 static void ale_init_rx_pages(struct ale_softc *);
112 static void ale_init_tx_ring(struct ale_softc *);
114 static void ale_stop(struct ale_softc *);
115 static void ale_tick(void *);
116 static void ale_get_macaddr(struct ale_softc *);
117 static void ale_mac_config(struct ale_softc *);
118 static void ale_phy_reset(struct ale_softc *);
119 static void ale_reset(struct ale_softc *);
120 static void ale_rxfilter(struct ale_softc *);
121 static void ale_rxvlan(struct ale_softc *);
122 static void ale_stats_clear(struct ale_softc *);
123 static void ale_stats_update(struct ale_softc *);
124 static void ale_stop_mac(struct ale_softc *);
126 static void ale_setlinkspeed(struct ale_softc *);
127 static void ale_setwol(struct ale_softc *);
130 static void ale_sysctl_node(struct ale_softc *);
131 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
134 * Devices supported by this driver.
136 static struct ale_dev {
137 uint16_t ale_vendorid;
138 uint16_t ale_deviceid;
139 const char *ale_name;
141 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
142 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
145 static device_method_t ale_methods[] = {
146 /* Device interface. */
147 DEVMETHOD(device_probe, ale_probe),
148 DEVMETHOD(device_attach, ale_attach),
149 DEVMETHOD(device_detach, ale_detach),
150 DEVMETHOD(device_shutdown, ale_shutdown),
151 DEVMETHOD(device_suspend, ale_suspend),
152 DEVMETHOD(device_resume, ale_resume),
155 DEVMETHOD(bus_print_child, bus_generic_print_child),
156 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
159 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
160 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
161 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
166 static driver_t ale_driver = {
169 sizeof(struct ale_softc)
172 static devclass_t ale_devclass;
174 DECLARE_DUMMY_MODULE(if_ale);
175 MODULE_DEPEND(if_ale, miibus, 1, 1, 1);
176 DRIVER_MODULE(if_ale, pci, ale_driver, ale_devclass, 0, 0);
177 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0);
180 ale_miibus_readreg(device_t dev, int phy, int reg)
182 struct ale_softc *sc;
186 sc = device_get_softc(dev);
188 if (phy != sc->ale_phyaddr)
191 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
192 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
193 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
195 v = CSR_READ_4(sc, ALE_MDIO);
196 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
201 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
205 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
209 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
211 struct ale_softc *sc;
215 sc = device_get_softc(dev);
217 if (phy != sc->ale_phyaddr)
220 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
221 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
222 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
223 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
225 v = CSR_READ_4(sc, ALE_MDIO);
226 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
231 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
237 ale_miibus_statchg(device_t dev)
239 struct ale_softc *sc = device_get_softc(dev);
240 struct ifnet *ifp = &sc->arpcom.ac_if;
241 struct mii_data *mii;
244 ASSERT_SERIALIZED(ifp->if_serializer);
246 if ((ifp->if_flags & IFF_RUNNING) == 0)
249 mii = device_get_softc(sc->ale_miibus);
251 sc->ale_flags &= ~ALE_FLAG_LINK;
252 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
253 (IFM_ACTIVE | IFM_AVALID)) {
254 switch (IFM_SUBTYPE(mii->mii_media_active)) {
257 sc->ale_flags |= ALE_FLAG_LINK;
261 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
262 sc->ale_flags |= ALE_FLAG_LINK;
270 /* Stop Rx/Tx MACs. */
273 /* Program MACs with resolved speed/duplex/flow-control. */
274 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
276 /* Reenable Tx/Rx MACs. */
277 reg = CSR_READ_4(sc, ALE_MAC_CFG);
278 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
279 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
284 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
286 struct ale_softc *sc = ifp->if_softc;
287 struct mii_data *mii = device_get_softc(sc->ale_miibus);
289 ASSERT_SERIALIZED(ifp->if_serializer);
292 ifmr->ifm_status = mii->mii_media_status;
293 ifmr->ifm_active = mii->mii_media_active;
297 ale_mediachange(struct ifnet *ifp)
299 struct ale_softc *sc = ifp->if_softc;
300 struct mii_data *mii = device_get_softc(sc->ale_miibus);
303 ASSERT_SERIALIZED(ifp->if_serializer);
305 if (mii->mii_instance != 0) {
306 struct mii_softc *miisc;
308 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
309 mii_phy_reset(miisc);
311 error = mii_mediachg(mii);
317 ale_probe(device_t dev)
321 uint16_t vendor, devid;
323 vendor = pci_get_vendor(dev);
324 devid = pci_get_device(dev);
326 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) {
327 if (vendor == sp->ale_vendorid &&
328 devid == sp->ale_deviceid) {
329 device_set_desc(dev, sp->ale_name);
339 ale_get_macaddr(struct ale_softc *sc)
344 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
345 if ((reg & SPI_VPD_ENB) != 0) {
347 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
350 vpdc = pci_get_vpdcap_ptr(sc->ale_dev);
353 * PCI VPD capability found, let TWSI reload EEPROM.
354 * This will set ethernet address of controller.
356 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
357 TWSI_CTRL_SW_LD_START);
358 for (i = 100; i > 0; i--) {
360 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
361 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
365 device_printf(sc->ale_dev,
366 "reloading EEPROM timeout!\n");
369 device_printf(sc->ale_dev,
370 "PCI VPD capability not found!\n");
373 ea[0] = CSR_READ_4(sc, ALE_PAR0);
374 ea[1] = CSR_READ_4(sc, ALE_PAR1);
375 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
376 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
377 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
378 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
379 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
380 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
384 ale_phy_reset(struct ale_softc *sc)
386 /* Reset magic from Linux. */
387 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
388 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
389 GPHY_CTRL_PHY_PLL_ON);
391 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
392 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
393 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
396 #define ATPHY_DBG_ADDR 0x1D
397 #define ATPHY_DBG_DATA 0x1E
399 /* Enable hibernation mode. */
400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
401 ATPHY_DBG_ADDR, 0x0B);
402 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
403 ATPHY_DBG_DATA, 0xBC00);
404 /* Set Class A/B for all modes. */
405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
406 ATPHY_DBG_ADDR, 0x00);
407 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
408 ATPHY_DBG_DATA, 0x02EF);
409 /* Enable 10BT power saving. */
410 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
411 ATPHY_DBG_ADDR, 0x12);
412 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
413 ATPHY_DBG_DATA, 0x4C04);
414 /* Adjust 1000T power. */
415 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
416 ATPHY_DBG_ADDR, 0x04);
417 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
418 ATPHY_DBG_ADDR, 0x8BBB);
419 /* 10BT center tap voltage. */
420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
421 ATPHY_DBG_ADDR, 0x05);
422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
423 ATPHY_DBG_ADDR, 0x2C46);
425 #undef ATPHY_DBG_ADDR
426 #undef ATPHY_DBG_DATA
431 ale_attach(device_t dev)
433 struct ale_softc *sc = device_get_softc(dev);
434 struct ifnet *ifp = &sc->arpcom.ac_if;
436 uint32_t rxf_len, txf_len;
439 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
442 callout_init(&sc->ale_tick_ch);
445 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
448 irq = pci_read_config(dev, PCIR_INTLINE, 4);
449 mem = pci_read_config(dev, ALE_PCIR_BAR, 4);
451 device_printf(dev, "chip is in D%d power mode "
452 "-- setting to D0\n", pci_get_powerstate(dev));
454 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
456 pci_write_config(dev, PCIR_INTLINE, irq, 4);
457 pci_write_config(dev, ALE_PCIR_BAR, mem, 4);
459 #endif /* !BURN_BRIDGE */
461 /* Enable bus mastering */
462 pci_enable_busmaster(dev);
465 * Allocate memory mapped IO
467 sc->ale_mem_rid = ALE_PCIR_BAR;
468 sc->ale_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
469 &sc->ale_mem_rid, RF_ACTIVE);
470 if (sc->ale_mem_res == NULL) {
471 device_printf(dev, "can't allocate IO memory\n");
474 sc->ale_mem_bt = rman_get_bustag(sc->ale_mem_res);
475 sc->ale_mem_bh = rman_get_bushandle(sc->ale_mem_res);
481 sc->ale_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
483 RF_SHAREABLE | RF_ACTIVE);
484 if (sc->ale_irq_res == NULL) {
485 device_printf(dev, "can't allocate irq\n");
490 /* Set PHY address. */
491 sc->ale_phyaddr = ALE_PHY_ADDR;
496 /* Reset the ethernet controller. */
499 /* Get PCI and chip id/revision. */
500 sc->ale_rev = pci_get_revid(dev);
501 if (sc->ale_rev >= 0xF0) {
502 /* L2E Rev. B. AR8114 */
503 sc->ale_flags |= ALE_FLAG_FASTETHER;
505 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
507 sc->ale_flags |= ALE_FLAG_JUMBO;
509 /* L2E Rev. A. AR8113 */
510 sc->ale_flags |= ALE_FLAG_FASTETHER;
515 * All known controllers seems to require 4 bytes alignment
516 * of Tx buffers to make Tx checksum offload with custom
517 * checksum generation method work.
519 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
522 * All known controllers seems to have issues on Rx checksum
523 * offload for fragmented IP datagrams.
525 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
528 * Don't use Tx CMB. It is known to cause RRS update failure
529 * under certain circumstances. Typical phenomenon of the
530 * issue would be unexpected sequence number encountered in
533 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
534 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
535 MASTER_CHIP_REV_SHIFT;
537 device_printf(dev, "PCI device revision : 0x%04x\n",
539 device_printf(dev, "Chip id/revision : 0x%04x\n",
544 * Uninitialized hardware returns an invalid chip id/revision
545 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
547 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
548 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
549 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
550 rxf_len == 0xFFFFFFF) {
551 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
552 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
557 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
559 /* Get DMA parameters from PCIe device control register. */
560 pcie_ptr = pci_get_pciecap_ptr(dev);
564 sc->ale_flags |= ALE_FLAG_PCIE;
565 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
566 /* Max read request size. */
567 sc->ale_dma_rd_burst = ((devctl >> 12) & 0x07) <<
568 DMA_CFG_RD_BURST_SHIFT;
569 /* Max payload size. */
570 sc->ale_dma_wr_burst = ((devctl >> 5) & 0x07) <<
571 DMA_CFG_WR_BURST_SHIFT;
573 device_printf(dev, "Read request size : %d bytes.\n",
574 128 << ((devctl >> 12) & 0x07));
575 device_printf(dev, "TLP payload size : %d bytes.\n",
576 128 << ((devctl >> 5) & 0x07));
579 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
580 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
583 /* Create device sysctl node. */
586 if ((error = ale_dma_alloc(sc) != 0))
589 /* Load station address. */
593 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
594 ifp->if_ioctl = ale_ioctl;
595 ifp->if_start = ale_start;
596 ifp->if_init = ale_init;
597 ifp->if_watchdog = ale_watchdog;
598 ifq_set_maxlen(&ifp->if_snd, ALE_TX_RING_CNT - 1);
599 ifq_set_ready(&ifp->if_snd);
601 ifp->if_capabilities = IFCAP_HWCSUM |
603 IFCAP_VLAN_HWTAGGING;
604 ifp->if_hwassist = ALE_CSUM_FEATURES;
605 ifp->if_capenable = ifp->if_capabilities;
607 /* Set up MII bus. */
608 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange,
609 ale_mediastatus)) != 0) {
610 device_printf(dev, "no PHY found!\n");
614 ether_ifattach(ifp, sc->ale_eaddr, NULL);
616 /* Tell the upper layer(s) we support long frames. */
617 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
619 error = bus_setup_intr(dev, sc->ale_irq_res, INTR_MPSAFE, ale_intr, sc,
620 &sc->ale_irq_handle, ifp->if_serializer);
622 device_printf(dev, "could not set up interrupt handler.\n");
627 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->ale_irq_res));
628 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
636 ale_detach(device_t dev)
638 struct ale_softc *sc = device_get_softc(dev);
640 if (device_is_attached(dev)) {
641 struct ifnet *ifp = &sc->arpcom.ac_if;
643 lwkt_serialize_enter(ifp->if_serializer);
644 sc->ale_flags |= ALE_FLAG_DETACH;
646 bus_teardown_intr(dev, sc->ale_irq_res, sc->ale_irq_handle);
647 lwkt_serialize_exit(ifp->if_serializer);
652 if (sc->ale_sysctl_tree != NULL)
653 sysctl_ctx_free(&sc->ale_sysctl_ctx);
655 if (sc->ale_miibus != NULL)
656 device_delete_child(dev, sc->ale_miibus);
657 bus_generic_detach(dev);
659 if (sc->ale_irq_res != NULL) {
660 bus_release_resource(dev, SYS_RES_IRQ, sc->ale_irq_rid,
663 if (sc->ale_mem_res != NULL) {
664 bus_release_resource(dev, SYS_RES_MEMORY, sc->ale_mem_rid,
673 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
674 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
675 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
676 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
679 ale_sysctl_node(struct ale_softc *sc)
681 struct sysctl_ctx_list *ctx;
682 struct sysctl_oid_list *child, *parent;
683 struct sysctl_oid *tree;
684 struct ale_hw_stats *stats;
687 sysctl_ctx_init(&sc->ale_sysctl_ctx);
688 sc->ale_sysctl_tree = SYSCTL_ADD_NODE(&sc->ale_sysctl_ctx,
689 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
690 device_get_nameunit(sc->ale_dev),
692 if (sc->ale_sysctl_tree == NULL) {
693 device_printf(sc->ale_dev, "can't add sysctl node\n");
697 stats = &sc->ale_stats;
698 ctx = &sc->ale_sysctl_ctx;
699 child = SYSCTL_CHILDREN(sc->ale_sysctl_tree);
701 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
702 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0,
703 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
704 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
705 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0,
706 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
709 * Pull in device tunables.
711 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
712 error = resource_int_value(device_get_name(sc->ale_dev),
713 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
715 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
716 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
717 device_printf(sc->ale_dev, "int_rx_mod value out of "
718 "range; using default: %d\n",
719 ALE_IM_RX_TIMER_DEFAULT);
720 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
724 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
725 error = resource_int_value(device_get_name(sc->ale_dev),
726 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
728 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
729 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
730 device_printf(sc->ale_dev, "int_tx_mod value out of "
731 "range; using default: %d\n",
732 ALE_IM_TX_TIMER_DEFAULT);
733 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
737 /* Misc statistics. */
738 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
739 &stats->reset_brk_seq,
740 "Controller resets due to broken Rx sequnce number");
742 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
743 NULL, "ATE statistics");
744 parent = SYSCTL_CHILDREN(tree);
747 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD,
748 NULL, "Rx MAC statistics");
749 child = SYSCTL_CHILDREN(tree);
750 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
751 &stats->rx_frames, "Good frames");
752 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
753 &stats->rx_bcast_frames, "Good broadcast frames");
754 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
755 &stats->rx_mcast_frames, "Good multicast frames");
756 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
757 &stats->rx_pause_frames, "Pause control frames");
758 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
759 &stats->rx_control_frames, "Control frames");
760 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
761 &stats->rx_crcerrs, "CRC errors");
762 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
763 &stats->rx_lenerrs, "Frames with length mismatched");
764 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
765 &stats->rx_bytes, "Good octets");
766 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
767 &stats->rx_bcast_bytes, "Good broadcast octets");
768 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
769 &stats->rx_mcast_bytes, "Good multicast octets");
770 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
771 &stats->rx_runts, "Too short frames");
772 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
773 &stats->rx_fragments, "Fragmented frames");
774 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
775 &stats->rx_pkts_64, "64 bytes frames");
776 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
777 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
778 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
779 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
780 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
781 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
782 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
783 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
784 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
785 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
786 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
787 &stats->rx_pkts_1519_max, "1519 to max frames");
788 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
789 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
790 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
791 &stats->rx_fifo_oflows, "FIFO overflows");
792 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
793 &stats->rx_rrs_errs, "Return status write-back errors");
794 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
795 &stats->rx_alignerrs, "Alignment errors");
796 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
797 &stats->rx_pkts_filtered,
798 "Frames dropped due to address filtering");
801 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
802 NULL, "Tx MAC statistics");
803 child = SYSCTL_CHILDREN(tree);
804 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
805 &stats->tx_frames, "Good frames");
806 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
807 &stats->tx_bcast_frames, "Good broadcast frames");
808 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
809 &stats->tx_mcast_frames, "Good multicast frames");
810 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
811 &stats->tx_pause_frames, "Pause control frames");
812 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
813 &stats->tx_control_frames, "Control frames");
814 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
815 &stats->tx_excess_defer, "Frames with excessive derferrals");
816 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
817 &stats->tx_excess_defer, "Frames with derferrals");
818 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
819 &stats->tx_bytes, "Good octets");
820 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
821 &stats->tx_bcast_bytes, "Good broadcast octets");
822 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
823 &stats->tx_mcast_bytes, "Good multicast octets");
824 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
825 &stats->tx_pkts_64, "64 bytes frames");
826 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
827 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
828 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
829 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
830 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
831 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
832 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
833 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
834 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
835 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
836 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
837 &stats->tx_pkts_1519_max, "1519 to max frames");
838 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
839 &stats->tx_single_colls, "Single collisions");
840 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
841 &stats->tx_multi_colls, "Multiple collisions");
842 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
843 &stats->tx_late_colls, "Late collisions");
844 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
845 &stats->tx_excess_colls, "Excessive collisions");
846 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort",
847 &stats->tx_abort, "Aborted frames due to Excessive collisions");
848 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
849 &stats->tx_underrun, "FIFO underruns");
850 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
851 &stats->tx_desc_underrun, "Descriptor write-back errors");
852 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
853 &stats->tx_lenerrs, "Frames with length mismatched");
854 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
855 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
858 #undef ALE_SYSCTL_STAT_ADD32
859 #undef ALE_SYSCTL_STAT_ADD64
861 struct ale_dmamap_arg {
862 bus_addr_t ale_busaddr;
866 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
868 struct ale_dmamap_arg *ctx;
873 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
875 ctx = (struct ale_dmamap_arg *)arg;
876 ctx->ale_busaddr = segs[0].ds_addr;
880 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
881 * which specifies high address region of DMA blocks. Therefore these
882 * blocks should have the same high address of given 4GB address
883 * space(i.e. crossing 4GB boundary is not allowed).
886 ale_check_boundary(struct ale_softc *sc)
888 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
889 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
891 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
893 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
895 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
896 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
897 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
898 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
900 if ((ALE_ADDR_HI(tx_ring_end) !=
901 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
902 (ALE_ADDR_HI(rx_page_end[0]) !=
903 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
904 (ALE_ADDR_HI(rx_page_end[1]) !=
905 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
906 (ALE_ADDR_HI(tx_cmb_end) !=
907 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
908 (ALE_ADDR_HI(rx_cmb_end[0]) !=
909 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
910 (ALE_ADDR_HI(rx_cmb_end[1]) !=
911 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
914 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
915 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
916 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
917 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
918 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
925 ale_dma_alloc(struct ale_softc *sc)
927 struct ale_txdesc *txd;
929 struct ale_dmamap_arg ctx;
930 int error, guard_size, i;
932 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
933 guard_size = ALE_JUMBO_FRAMELEN;
935 guard_size = ALE_MAX_FRAMELEN;
936 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
938 lowaddr = BUS_SPACE_MAXADDR;
940 /* Create parent DMA tag. */
941 error = bus_dma_tag_create(
943 1, 0, /* alignment, boundary */
944 lowaddr, /* lowaddr */
945 BUS_SPACE_MAXADDR, /* highaddr */
946 NULL, NULL, /* filter, filterarg */
947 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
949 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
951 &sc->ale_cdata.ale_parent_tag);
953 device_printf(sc->ale_dev,
954 "could not create parent DMA tag.\n");
958 /* Create DMA tag for Tx descriptor ring. */
959 error = bus_dma_tag_create(
960 sc->ale_cdata.ale_parent_tag, /* parent */
961 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
962 BUS_SPACE_MAXADDR, /* lowaddr */
963 BUS_SPACE_MAXADDR, /* highaddr */
964 NULL, NULL, /* filter, filterarg */
965 ALE_TX_RING_SZ, /* maxsize */
967 ALE_TX_RING_SZ, /* maxsegsize */
969 &sc->ale_cdata.ale_tx_ring_tag);
971 device_printf(sc->ale_dev,
972 "could not create Tx ring DMA tag.\n");
976 /* Create DMA tag for Rx pages. */
977 for (i = 0; i < ALE_RX_PAGES; i++) {
978 error = bus_dma_tag_create(
979 sc->ale_cdata.ale_parent_tag, /* parent */
980 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
981 BUS_SPACE_MAXADDR, /* lowaddr */
982 BUS_SPACE_MAXADDR, /* highaddr */
983 NULL, NULL, /* filter, filterarg */
984 sc->ale_pagesize, /* maxsize */
986 sc->ale_pagesize, /* maxsegsize */
988 &sc->ale_cdata.ale_rx_page[i].page_tag);
990 device_printf(sc->ale_dev,
991 "could not create Rx page %d DMA tag.\n", i);
996 /* Create DMA tag for Tx coalescing message block. */
997 error = bus_dma_tag_create(
998 sc->ale_cdata.ale_parent_tag, /* parent */
999 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1000 BUS_SPACE_MAXADDR, /* lowaddr */
1001 BUS_SPACE_MAXADDR, /* highaddr */
1002 NULL, NULL, /* filter, filterarg */
1003 ALE_TX_CMB_SZ, /* maxsize */
1005 ALE_TX_CMB_SZ, /* maxsegsize */
1007 &sc->ale_cdata.ale_tx_cmb_tag);
1009 device_printf(sc->ale_dev,
1010 "could not create Tx CMB DMA tag.\n");
1014 /* Create DMA tag for Rx coalescing message block. */
1015 for (i = 0; i < ALE_RX_PAGES; i++) {
1016 error = bus_dma_tag_create(
1017 sc->ale_cdata.ale_parent_tag, /* parent */
1018 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1019 BUS_SPACE_MAXADDR, /* lowaddr */
1020 BUS_SPACE_MAXADDR, /* highaddr */
1021 NULL, NULL, /* filter, filterarg */
1022 ALE_RX_CMB_SZ, /* maxsize */
1024 ALE_RX_CMB_SZ, /* maxsegsize */
1026 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1028 device_printf(sc->ale_dev,
1029 "could not create Rx page %d CMB DMA tag.\n", i);
1034 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1035 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1036 (void **)&sc->ale_cdata.ale_tx_ring,
1037 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1038 &sc->ale_cdata.ale_tx_ring_map);
1040 device_printf(sc->ale_dev,
1041 "could not allocate DMA'able memory for Tx ring.\n");
1044 ctx.ale_busaddr = 0;
1045 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1046 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1047 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1048 if (error != 0 || ctx.ale_busaddr == 0) {
1049 device_printf(sc->ale_dev,
1050 "could not load DMA'able memory for Tx ring.\n");
1053 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1056 for (i = 0; i < ALE_RX_PAGES; i++) {
1057 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1058 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1059 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1060 &sc->ale_cdata.ale_rx_page[i].page_map);
1062 device_printf(sc->ale_dev,
1063 "could not allocate DMA'able memory for "
1064 "Rx page %d.\n", i);
1067 ctx.ale_busaddr = 0;
1068 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1069 sc->ale_cdata.ale_rx_page[i].page_map,
1070 sc->ale_cdata.ale_rx_page[i].page_addr,
1071 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1072 if (error != 0 || ctx.ale_busaddr == 0) {
1073 device_printf(sc->ale_dev,
1074 "could not load DMA'able memory for "
1075 "Rx page %d.\n", i);
1078 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1082 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1083 (void **)&sc->ale_cdata.ale_tx_cmb,
1084 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1085 &sc->ale_cdata.ale_tx_cmb_map);
1087 device_printf(sc->ale_dev,
1088 "could not allocate DMA'able memory for Tx CMB.\n");
1091 ctx.ale_busaddr = 0;
1092 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1093 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1094 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1095 if (error != 0 || ctx.ale_busaddr == 0) {
1096 device_printf(sc->ale_dev,
1097 "could not load DMA'able memory for Tx CMB.\n");
1100 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1103 for (i = 0; i < ALE_RX_PAGES; i++) {
1104 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1105 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1106 BUS_DMA_WAITOK | BUS_DMA_ZERO,
1107 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1109 device_printf(sc->ale_dev, "could not allocate "
1110 "DMA'able memory for Rx page %d CMB.\n", i);
1113 ctx.ale_busaddr = 0;
1114 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1115 sc->ale_cdata.ale_rx_page[i].cmb_map,
1116 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1117 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1118 if (error != 0 || ctx.ale_busaddr == 0) {
1119 device_printf(sc->ale_dev, "could not load DMA'able "
1120 "memory for Rx page %d CMB.\n", i);
1123 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1127 * Tx descriptors/RXF0/CMB DMA blocks share the same
1128 * high address region of 64bit DMA address space.
1130 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1131 (error = ale_check_boundary(sc)) != 0) {
1132 device_printf(sc->ale_dev, "4GB boundary crossed, "
1133 "switching to 32bit DMA addressing mode.\n");
1136 * Limit max allowable DMA address space to 32bit
1139 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1144 * Create Tx buffer parent tag.
1145 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1146 * needs separate parent DMA tag as parent DMA address space
1147 * could be restricted to be within 32bit address space by
1148 * 4GB boundary crossing.
1150 error = bus_dma_tag_create(
1152 1, 0, /* alignment, boundary */
1153 BUS_SPACE_MAXADDR, /* lowaddr */
1154 BUS_SPACE_MAXADDR, /* highaddr */
1155 NULL, NULL, /* filter, filterarg */
1156 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1158 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1160 &sc->ale_cdata.ale_buffer_tag);
1162 device_printf(sc->ale_dev,
1163 "could not create parent buffer DMA tag.\n");
1167 /* Create DMA tag for Tx buffers. */
1168 error = bus_dma_tag_create(
1169 sc->ale_cdata.ale_buffer_tag, /* parent */
1170 1, 0, /* alignment, boundary */
1171 BUS_SPACE_MAXADDR, /* lowaddr */
1172 BUS_SPACE_MAXADDR, /* highaddr */
1173 NULL, NULL, /* filter, filterarg */
1174 ALE_TSO_MAXSIZE, /* maxsize */
1175 ALE_MAXTXSEGS, /* nsegments */
1176 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1178 &sc->ale_cdata.ale_tx_tag);
1180 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1184 /* Create DMA maps for Tx buffers. */
1185 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1186 txd = &sc->ale_cdata.ale_txdesc[i];
1188 txd->tx_dmamap = NULL;
1189 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1192 device_printf(sc->ale_dev,
1193 "could not create Tx dmamap.\n");
1202 ale_dma_free(struct ale_softc *sc)
1204 struct ale_txdesc *txd;
1208 if (sc->ale_cdata.ale_tx_tag != NULL) {
1209 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1210 txd = &sc->ale_cdata.ale_txdesc[i];
1211 if (txd->tx_dmamap != NULL) {
1212 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1214 txd->tx_dmamap = NULL;
1217 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1218 sc->ale_cdata.ale_tx_tag = NULL;
1220 /* Tx descriptor ring. */
1221 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1222 if (sc->ale_cdata.ale_tx_ring_map != NULL)
1223 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1224 sc->ale_cdata.ale_tx_ring_map);
1225 if (sc->ale_cdata.ale_tx_ring_map != NULL &&
1226 sc->ale_cdata.ale_tx_ring != NULL)
1227 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1228 sc->ale_cdata.ale_tx_ring,
1229 sc->ale_cdata.ale_tx_ring_map);
1230 sc->ale_cdata.ale_tx_ring = NULL;
1231 sc->ale_cdata.ale_tx_ring_map = NULL;
1232 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1233 sc->ale_cdata.ale_tx_ring_tag = NULL;
1235 /* Rx page block. */
1236 for (i = 0; i < ALE_RX_PAGES; i++) {
1237 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1238 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL)
1240 sc->ale_cdata.ale_rx_page[i].page_tag,
1241 sc->ale_cdata.ale_rx_page[i].page_map);
1242 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL &&
1243 sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1245 sc->ale_cdata.ale_rx_page[i].page_tag,
1246 sc->ale_cdata.ale_rx_page[i].page_addr,
1247 sc->ale_cdata.ale_rx_page[i].page_map);
1248 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1249 sc->ale_cdata.ale_rx_page[i].page_map = NULL;
1250 bus_dma_tag_destroy(
1251 sc->ale_cdata.ale_rx_page[i].page_tag);
1252 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1256 for (i = 0; i < ALE_RX_PAGES; i++) {
1257 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1258 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL)
1260 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1261 sc->ale_cdata.ale_rx_page[i].cmb_map);
1262 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL &&
1263 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1265 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1266 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1267 sc->ale_cdata.ale_rx_page[i].cmb_map);
1268 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1269 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL;
1270 bus_dma_tag_destroy(
1271 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1272 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1276 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1277 if (sc->ale_cdata.ale_tx_cmb_map != NULL)
1278 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1279 sc->ale_cdata.ale_tx_cmb_map);
1280 if (sc->ale_cdata.ale_tx_cmb_map != NULL &&
1281 sc->ale_cdata.ale_tx_cmb != NULL)
1282 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1283 sc->ale_cdata.ale_tx_cmb,
1284 sc->ale_cdata.ale_tx_cmb_map);
1285 sc->ale_cdata.ale_tx_cmb = NULL;
1286 sc->ale_cdata.ale_tx_cmb_map = NULL;
1287 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1288 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1290 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1291 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1292 sc->ale_cdata.ale_buffer_tag = NULL;
1294 if (sc->ale_cdata.ale_parent_tag != NULL) {
1295 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1296 sc->ale_cdata.ale_parent_tag = NULL;
1301 ale_shutdown(device_t dev)
1303 return (ale_suspend(dev));
1309 * Note, this driver resets the link speed to 10/100Mbps by
1310 * restarting auto-negotiation in suspend/shutdown phase but we
1311 * don't know whether that auto-negotiation would succeed or not
1312 * as driver has no control after powering off/suspend operation.
1313 * If the renegotiation fail WOL may not work. Running at 1Gbps
1314 * will draw more power than 375mA at 3.3V which is specified in
1315 * PCI specification and that would result in complete
1316 * shutdowning power to ethernet controller.
1319 * Save current negotiated media speed/duplex/flow-control to
1320 * softc and restore the same link again after resuming. PHY
1321 * handling such as power down/resetting to 100Mbps may be better
1322 * handled in suspend method in phy driver.
1325 ale_setlinkspeed(struct ale_softc *sc)
1327 struct mii_data *mii;
1330 mii = device_get_softc(sc->ale_miibus);
1333 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1334 (IFM_ACTIVE | IFM_AVALID)) {
1335 switch IFM_SUBTYPE(mii->mii_media_active) {
1346 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1347 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1348 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1349 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1350 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1354 * Poll link state until ale(4) get a 10/100Mbps link.
1356 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1358 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1359 == (IFM_ACTIVE | IFM_AVALID)) {
1360 switch (IFM_SUBTYPE(
1361 mii->mii_media_active)) {
1371 pause("alelnk", hz);
1374 if (i == MII_ANEGTICKS_GIGE)
1375 device_printf(sc->ale_dev,
1376 "establishing a link failed, WOL may not work!");
1379 * No link, force MAC to have 100Mbps, full-duplex link.
1380 * This is the last resort and may/may not work.
1382 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1383 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1388 ale_setwol(struct ale_softc *sc)
1395 ALE_LOCK_ASSERT(sc);
1397 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1399 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1400 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1401 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1402 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1403 /* Force PHY power down. */
1404 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1405 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1406 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1407 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1408 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1413 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1414 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1415 ale_setlinkspeed(sc);
1419 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1420 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1421 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1422 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1423 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1425 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1426 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1427 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1428 reg |= MAC_CFG_RX_ENB;
1429 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1431 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1432 /* WOL disabled, PHY power down. */
1433 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1434 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1435 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1436 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1437 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1438 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1439 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1440 GPHY_CTRL_PWDOWN_HW);
1443 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1444 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1445 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1446 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1447 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1453 ale_suspend(device_t dev)
1455 struct ale_softc *sc = device_get_softc(dev);
1456 struct ifnet *ifp = &sc->arpcom.ac_if;
1458 lwkt_serialize_enter(ifp->if_serializer);
1463 lwkt_serialize_exit(ifp->if_serializer);
1468 ale_resume(device_t dev)
1470 struct ale_softc *sc = device_get_softc(dev);
1471 struct ifnet *ifp = &sc->arpcom.ac_if;
1474 lwkt_serialize_enter(ifp->if_serializer);
1477 * Clear INTx emulation disable for hardwares that
1478 * is set in resume event. From Linux.
1480 cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2);
1481 if ((cmd & 0x0400) != 0) {
1483 pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2);
1487 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1491 /* Disable PME and clear PME status. */
1492 pmstat = pci_read_config(sc->ale_dev,
1493 pmc + PCIR_POWER_STATUS, 2);
1494 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1495 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1496 pci_write_config(sc->ale_dev,
1497 pmc + PCIR_POWER_STATUS, pmstat, 2);
1504 if ((ifp->if_flags & IFF_UP) != 0)
1507 lwkt_serialize_exit(ifp->if_serializer);
1512 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1514 struct ale_txdesc *txd, *txd_last;
1515 struct tx_desc *desc;
1517 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1518 struct ale_dmamap_ctx ctx;
1520 uint32_t cflags, poff, vtag;
1521 int error, i, nsegs, prod, si;
1523 M_ASSERTPKTHDR((*m_head));
1529 si = prod = sc->ale_cdata.ale_tx_prod;
1530 txd = &sc->ale_cdata.ale_txdesc[prod];
1532 map = txd->tx_dmamap;
1534 ctx.nsegs = ALE_MAXTXSEGS;
1536 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1537 *m_head, ale_dmamap_buf_cb, &ctx,
1539 if (error == EFBIG) {
1540 m = m_defrag(*m_head, MB_DONTWAIT);
1548 ctx.nsegs = ALE_MAXTXSEGS;
1550 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map,
1551 *m_head, ale_dmamap_buf_cb, &ctx,
1558 } else if (error != 0) {
1569 /* Check descriptor overrun. */
1570 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) {
1571 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1574 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1577 /* Configure Tx checksum offload. */
1578 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1580 * AR81xx supports Tx custom checksum offload feature
1581 * that offloads single 16bit checksum computation.
1582 * So you can choose one among IP, TCP and UDP.
1583 * Normally driver sets checksum start/insertion
1584 * position from the information of TCP/UDP frame as
1585 * TCP/UDP checksum takes more time than that of IP.
1586 * However it seems that custom checksum offload
1587 * requires 4 bytes aligned Tx buffers due to hardware
1589 * AR81xx also supports explicit Tx checksum computation
1590 * if it is told that the size of IP header and TCP
1591 * header(for UDP, the header size does not matter
1592 * because it's fixed length). However with this scheme
1593 * TSO does not work so you have to choose one either
1594 * TSO or explicit Tx checksum offload. I chosen TSO
1595 * plus custom checksum offload with work-around which
1596 * will cover most common usage for this consumer
1597 * ethernet controller. The work-around takes a lot of
1598 * CPU cycles if Tx buffer is not aligned on 4 bytes
1601 cflags |= ALE_TD_CXSUM;
1602 /* Set checksum start offset. */
1603 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1604 /* Set checksum insertion position of TCP/UDP. */
1605 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1606 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1609 /* Configure VLAN hardware tag insertion. */
1610 if ((m->m_flags & M_VLANTAG) != 0) {
1611 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag);
1612 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1613 cflags |= ALE_TD_INSERT_VLAN_TAG;
1617 for (i = 0; i < nsegs; i++) {
1618 desc = &sc->ale_cdata.ale_tx_ring[prod];
1619 desc->addr = htole64(txsegs[i].ds_addr);
1620 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1621 desc->flags = htole32(cflags);
1622 sc->ale_cdata.ale_tx_cnt++;
1623 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1625 /* Update producer index. */
1626 sc->ale_cdata.ale_tx_prod = prod;
1628 /* Finally set EOP on the last descriptor. */
1629 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1630 desc = &sc->ale_cdata.ale_tx_ring[prod];
1631 desc->flags |= htole32(ALE_TD_EOP);
1633 /* Swap dmamap of the first and the last. */
1634 txd = &sc->ale_cdata.ale_txdesc[prod];
1635 map = txd_last->tx_dmamap;
1636 txd_last->tx_dmamap = txd->tx_dmamap;
1637 txd->tx_dmamap = map;
1640 /* Sync descriptors. */
1641 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1642 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREWRITE);
1648 ale_start(struct ifnet *ifp)
1650 struct ale_softc *sc = ifp->if_softc;
1651 struct mbuf *m_head;
1654 ASSERT_SERIALIZED(ifp->if_serializer);
1656 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1657 ifq_purge(&ifp->if_snd);
1661 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1664 /* Reclaim transmitted frames. */
1665 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1669 while (!ifq_is_empty(&ifp->if_snd)) {
1670 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1675 * Pack the data into the transmit ring. If we
1676 * don't have room, set the OACTIVE flag and wait
1677 * for the NIC to drain the ring.
1679 if (ale_encap(sc, &m_head)) {
1682 ifq_prepend(&ifp->if_snd, m_head);
1683 ifp->if_flags |= IFF_OACTIVE;
1689 * If there's a BPF listener, bounce a copy of this frame
1692 ETHER_BPF_MTAP(ifp, m_head);
1697 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1698 sc->ale_cdata.ale_tx_prod);
1700 /* Set a timeout in case the chip goes out to lunch. */
1701 ifp->if_timer = ALE_TX_TIMEOUT;
1706 ale_watchdog(struct ifnet *ifp)
1708 struct ale_softc *sc = ifp->if_softc;
1710 ASSERT_SERIALIZED(ifp->if_serializer);
1712 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1713 if_printf(ifp, "watchdog timeout (lost link)\n");
1719 if_printf(ifp, "watchdog timeout -- resetting\n");
1723 if (!ifq_is_empty(&ifp->if_snd))
1728 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1730 struct ale_softc *sc;
1732 struct mii_data *mii;
1735 ASSERT_SERIALIZED(ifp->if_serializer);
1738 ifr = (struct ifreq *)data;
1743 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1744 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1745 ifr->ifr_mtu > ETHERMTU))
1747 else if (ifp->if_mtu != ifr->ifr_mtu) {
1748 ifp->if_mtu = ifr->ifr_mtu;
1749 if ((ifp->if_flags & IFF_RUNNING) != 0)
1755 if ((ifp->if_flags & IFF_UP) != 0) {
1756 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1757 if (((ifp->if_flags ^ sc->ale_if_flags)
1758 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1761 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0)
1765 if ((ifp->if_flags & IFF_RUNNING) != 0)
1768 sc->ale_if_flags = ifp->if_flags;
1773 if ((ifp->if_flags & IFF_RUNNING) != 0)
1779 mii = device_get_softc(sc->ale_miibus);
1780 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1784 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1785 if ((mask & IFCAP_TXCSUM) != 0 &&
1786 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1787 ifp->if_capenable ^= IFCAP_TXCSUM;
1788 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1789 ifp->if_hwassist |= ALE_CSUM_FEATURES;
1791 ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
1793 if ((mask & IFCAP_RXCSUM) != 0 &&
1794 (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
1795 ifp->if_capenable ^= IFCAP_RXCSUM;
1797 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1798 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1799 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1805 error = ether_ioctl(ifp, cmd, data);
1812 ale_mac_config(struct ale_softc *sc)
1814 struct mii_data *mii;
1817 mii = device_get_softc(sc->ale_miibus);
1818 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1819 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
1820 MAC_CFG_SPEED_MASK);
1821 /* Reprogram MAC with resolved speed/duplex. */
1822 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1825 reg |= MAC_CFG_SPEED_10_100;
1828 reg |= MAC_CFG_SPEED_1000;
1831 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1832 reg |= MAC_CFG_FULL_DUPLEX;
1834 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1835 reg |= MAC_CFG_TX_FC;
1836 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1837 reg |= MAC_CFG_RX_FC;
1840 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1844 ale_stats_clear(struct ale_softc *sc)
1850 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1851 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1852 i += sizeof(uint32_t);
1854 /* Read Tx statistics. */
1855 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1856 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1857 i += sizeof(uint32_t);
1862 ale_stats_update(struct ale_softc *sc)
1864 struct ale_hw_stats *stat;
1865 struct smb sb, *smb;
1870 ifp = &sc->arpcom.ac_if;
1871 stat = &sc->ale_stats;
1874 /* Read Rx statistics. */
1875 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
1876 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1877 i += sizeof(uint32_t);
1879 /* Read Tx statistics. */
1880 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
1881 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1882 i += sizeof(uint32_t);
1886 stat->rx_frames += smb->rx_frames;
1887 stat->rx_bcast_frames += smb->rx_bcast_frames;
1888 stat->rx_mcast_frames += smb->rx_mcast_frames;
1889 stat->rx_pause_frames += smb->rx_pause_frames;
1890 stat->rx_control_frames += smb->rx_control_frames;
1891 stat->rx_crcerrs += smb->rx_crcerrs;
1892 stat->rx_lenerrs += smb->rx_lenerrs;
1893 stat->rx_bytes += smb->rx_bytes;
1894 stat->rx_runts += smb->rx_runts;
1895 stat->rx_fragments += smb->rx_fragments;
1896 stat->rx_pkts_64 += smb->rx_pkts_64;
1897 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
1898 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
1899 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
1900 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
1901 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
1902 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
1903 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
1904 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
1905 stat->rx_rrs_errs += smb->rx_rrs_errs;
1906 stat->rx_alignerrs += smb->rx_alignerrs;
1907 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
1908 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
1909 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
1912 stat->tx_frames += smb->tx_frames;
1913 stat->tx_bcast_frames += smb->tx_bcast_frames;
1914 stat->tx_mcast_frames += smb->tx_mcast_frames;
1915 stat->tx_pause_frames += smb->tx_pause_frames;
1916 stat->tx_excess_defer += smb->tx_excess_defer;
1917 stat->tx_control_frames += smb->tx_control_frames;
1918 stat->tx_deferred += smb->tx_deferred;
1919 stat->tx_bytes += smb->tx_bytes;
1920 stat->tx_pkts_64 += smb->tx_pkts_64;
1921 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
1922 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
1923 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
1924 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
1925 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
1926 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
1927 stat->tx_single_colls += smb->tx_single_colls;
1928 stat->tx_multi_colls += smb->tx_multi_colls;
1929 stat->tx_late_colls += smb->tx_late_colls;
1930 stat->tx_excess_colls += smb->tx_excess_colls;
1931 stat->tx_abort += smb->tx_abort;
1932 stat->tx_underrun += smb->tx_underrun;
1933 stat->tx_desc_underrun += smb->tx_desc_underrun;
1934 stat->tx_lenerrs += smb->tx_lenerrs;
1935 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
1936 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
1937 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
1939 /* Update counters in ifnet. */
1940 ifp->if_opackets += smb->tx_frames;
1942 ifp->if_collisions += smb->tx_single_colls +
1943 smb->tx_multi_colls * 2 + smb->tx_late_colls +
1944 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT;
1948 * tx_pkts_truncated counter looks suspicious. It constantly
1949 * increments with no sign of Tx errors. This may indicate
1950 * the counter name is not correct one so I've removed the
1951 * counter in output errors.
1953 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls +
1956 ifp->if_ipackets += smb->rx_frames;
1958 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs +
1959 smb->rx_runts + smb->rx_pkts_truncated +
1960 smb->rx_fifo_oflows + smb->rx_rrs_errs +
1967 struct ale_softc *sc = xsc;
1968 struct ifnet *ifp = &sc->arpcom.ac_if;
1971 ASSERT_SERIALIZED(ifp->if_serializer);
1973 status = CSR_READ_4(sc, ALE_INTR_STATUS);
1974 if ((status & ALE_INTRS) == 0)
1977 /* Acknowledge and disable interrupts. */
1978 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
1980 if ((ifp->if_flags & IFF_RUNNING) != 0) {
1983 error = ale_rxeof(sc);
1985 sc->ale_stats.reset_brk_seq++;
1990 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
1991 if ((status & INTR_DMA_RD_TO_RST) != 0)
1992 device_printf(sc->ale_dev,
1993 "DMA read error! -- resetting\n");
1994 if ((status & INTR_DMA_WR_TO_RST) != 0)
1995 device_printf(sc->ale_dev,
1996 "DMA write error! -- resetting\n");
2002 if (!ifq_is_empty(&ifp->if_snd))
2006 /* Re-enable interrupts. */
2007 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2011 ale_txeof(struct ale_softc *sc)
2013 struct ifnet *ifp = &sc->arpcom.ac_if;
2014 struct ale_txdesc *txd;
2015 uint32_t cons, prod;
2018 if (sc->ale_cdata.ale_tx_cnt == 0)
2021 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2022 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_POSTREAD);
2023 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2024 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2025 sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_POSTREAD);
2026 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2028 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2029 cons = sc->ale_cdata.ale_tx_cons;
2031 * Go through our Tx list and free mbufs for those
2032 * frames which have been transmitted.
2034 for (prog = 0; cons != prod; prog++,
2035 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2036 if (sc->ale_cdata.ale_tx_cnt <= 0)
2039 ifp->if_flags &= ~IFF_OACTIVE;
2040 sc->ale_cdata.ale_tx_cnt--;
2041 txd = &sc->ale_cdata.ale_txdesc[cons];
2042 if (txd->tx_m != NULL) {
2043 /* Reclaim transmitted mbufs. */
2044 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2052 sc->ale_cdata.ale_tx_cons = cons;
2054 * Unarm watchdog timer only when there is no pending
2055 * Tx descriptors in queue.
2057 if (sc->ale_cdata.ale_tx_cnt == 0)
2063 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2064 uint32_t length, uint32_t *prod)
2066 struct ale_rx_page *rx_page;
2069 /* Update consumer position. */
2070 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2072 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2074 * End of Rx page reached, let hardware reuse
2078 *rx_page->cmb_addr = 0;
2079 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2080 BUS_DMASYNC_PREWRITE);
2081 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2083 /* Switch to alternate Rx page. */
2084 sc->ale_cdata.ale_rx_curp ^= 1;
2086 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2087 /* Page flipped, sync CMB and Rx page. */
2088 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2089 BUS_DMASYNC_POSTREAD);
2090 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2091 BUS_DMASYNC_POSTREAD);
2092 /* Sync completed, cache updated producer index. */
2093 *prod = *rx_page->cmb_addr;
2099 * It seems that AR81xx controller can compute partial checksum.
2100 * The partial checksum value can be used to accelerate checksum
2101 * computation for fragmented TCP/UDP packets. Upper network stack
2102 * already takes advantage of the partial checksum value in IP
2103 * reassembly stage. But I'm not sure the correctness of the
2104 * partial hardware checksum assistance due to lack of data sheet.
2105 * In addition, the Rx feature of controller that requires copying
2106 * for every frames effectively nullifies one of most nice offload
2107 * capability of controller.
2110 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2112 struct ifnet *ifp = &sc->arpcom.ac_if;
2116 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2117 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2118 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2120 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2121 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2122 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2123 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2124 m->m_pkthdr.csum_flags |=
2125 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2126 m->m_pkthdr.csum_data = 0xffff;
2129 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2130 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2131 p = mtod(m, char *);
2133 if ((status & ALE_RD_802_3) != 0)
2134 p += LLC_SNAPFRAMELEN;
2135 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2136 (status & ALE_RD_VLAN) != 0)
2138 ip = (struct ip *)p;
2139 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2141 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2143 m->m_pkthdr.csum_data = 0xffff;
2147 * Don't mark bad checksum for TCP/UDP frames
2148 * as fragmented frames may always have set
2149 * bad checksummed bit of frame status.
2153 /* Process received frames. */
2155 ale_rxeof(struct ale_softc *sc)
2157 struct ifnet *ifp = &sc->arpcom.ac_if;
2158 struct ale_rx_page *rx_page;
2161 uint32_t length, prod, seqno, status, vtags;
2164 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2165 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2166 BUS_DMASYNC_POSTREAD);
2167 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2168 BUS_DMASYNC_POSTREAD);
2170 * Don't directly access producer index as hardware may
2171 * update it while Rx handler is in progress. It would
2172 * be even better if there is a way to let hardware
2173 * know how far driver processed its received frames.
2174 * Alternatively, hardware could provide a way to disable
2175 * CMB updates until driver acknowledges the end of CMB
2178 prod = *rx_page->cmb_addr;
2179 for (prog = 0; ; prog++) {
2180 if (rx_page->cons >= prod)
2182 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2183 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2184 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2186 * Normally I believe this should not happen unless
2187 * severe driver bug or corrupted memory. However
2188 * it seems to happen under certain conditions which
2189 * is triggered by abrupt Rx events such as initiation
2190 * of bulk transfer of remote host. It's not easy to
2191 * reproduce this and I doubt it could be related
2192 * with FIFO overflow of hardware or activity of Tx
2193 * CMB updates. I also remember similar behaviour
2194 * seen on RealTek 8139 which uses resembling Rx
2198 device_printf(sc->ale_dev,
2199 "garbled seq: %u, expected: %u -- "
2200 "resetting!\n", seqno,
2201 sc->ale_cdata.ale_rx_seqno);
2204 /* Frame received. */
2205 sc->ale_cdata.ale_rx_seqno++;
2206 length = ALE_RX_BYTES(le32toh(rs->length));
2207 status = le32toh(rs->flags);
2208 if ((status & ALE_RD_ERROR) != 0) {
2210 * We want to pass the following frames to upper
2211 * layer regardless of error status of Rx return
2214 * o IP/TCP/UDP checksum is bad.
2215 * o frame length and protocol specific length
2218 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2219 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2220 ALE_RD_TRUNC)) != 0) {
2221 ale_rx_update_page(sc, &rx_page, length, &prod);
2226 * m_devget(9) is major bottle-neck of ale(4)(It comes
2227 * from hardware limitation). For jumbo frames we could
2228 * get a slightly better performance if driver use
2229 * m_getjcl(9) with proper buffer size argument. However
2230 * that would make code more complicated and I don't
2231 * think users would expect good Rx performance numbers
2232 * on these low-end consumer ethernet controller.
2234 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2235 ETHER_ALIGN, ifp, NULL);
2238 ale_rx_update_page(sc, &rx_page, length, &prod);
2241 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2242 (status & ALE_RD_IPV4) != 0)
2243 ale_rxcsum(sc, m, status);
2244 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2245 (status & ALE_RD_VLAN) != 0) {
2246 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2247 m->m_pkthdr.ether_vlantag = ALE_RX_VLAN_TAG(vtags);
2248 m->m_flags |= M_VLANTAG;
2251 /* Pass it to upper layer. */
2252 ifp->if_input(ifp, m);
2254 ale_rx_update_page(sc, &rx_page, length, &prod);
2262 struct ale_softc *sc = xsc;
2263 struct ifnet *ifp = &sc->arpcom.ac_if;
2264 struct mii_data *mii;
2266 lwkt_serialize_enter(ifp->if_serializer);
2268 mii = device_get_softc(sc->ale_miibus);
2270 ale_stats_update(sc);
2272 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2274 lwkt_serialize_exit(ifp->if_serializer);
2278 ale_reset(struct ale_softc *sc)
2283 /* Initialize PCIe module. From Linux. */
2284 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2286 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2287 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2289 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2293 device_printf(sc->ale_dev, "master reset timeout!\n");
2295 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2296 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2302 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2308 struct ale_softc *sc = xsc;
2309 struct ifnet *ifp = &sc->arpcom.ac_if;
2310 struct mii_data *mii;
2311 uint8_t eaddr[ETHER_ADDR_LEN];
2313 uint32_t reg, rxf_hi, rxf_lo;
2315 ASSERT_SERIALIZED(ifp->if_serializer);
2317 mii = device_get_softc(sc->ale_miibus);
2320 * Cancel any pending I/O.
2325 * Reset the chip to a known state.
2329 /* Initialize Tx descriptors, DMA memory blocks. */
2330 ale_init_rx_pages(sc);
2331 ale_init_tx_ring(sc);
2333 /* Reprogram the station address. */
2334 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2335 CSR_WRITE_4(sc, ALE_PAR0,
2336 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2337 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2340 * Clear WOL status and disable all WOL feature as WOL
2341 * would interfere Rx operation under normal environments.
2343 CSR_READ_4(sc, ALE_WOL_CFG);
2344 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2347 * Set Tx descriptor/RXF0/CMB base addresses. They share
2348 * the same high address part of DMAable region.
2350 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2351 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2352 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2353 CSR_WRITE_4(sc, ALE_TPD_CNT,
2354 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2356 /* Set Rx page base address, note we use single queue. */
2357 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2358 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2359 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2360 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2362 /* Set Tx/Rx CMB addresses. */
2363 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2364 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2365 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2366 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2367 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2368 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2370 /* Mark RXF0 is valid. */
2371 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2372 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2374 * No need to initialize RFX1/RXF2/RXF3. We don't use
2378 /* Set Rx page size, excluding guard frame size. */
2379 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2381 /* Tell hardware that we're ready to load DMA blocks. */
2382 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2384 /* Set Rx/Tx interrupt trigger threshold. */
2385 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2386 (4 << INT_TRIG_TX_THRESH_SHIFT));
2389 * Set interrupt trigger timer, its purpose and relation
2390 * with interrupt moderation mechanism is not clear yet.
2392 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2393 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2394 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2396 /* Configure interrupt moderation timer. */
2397 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2398 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2399 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2400 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2401 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2402 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2403 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2404 reg |= MASTER_IM_RX_TIMER_ENB;
2405 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2406 reg |= MASTER_IM_TX_TIMER_ENB;
2407 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2408 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2410 /* Set Maximum frame size of controller. */
2411 if (ifp->if_mtu < ETHERMTU)
2412 sc->ale_max_frame_size = ETHERMTU;
2414 sc->ale_max_frame_size = ifp->if_mtu;
2415 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN;
2416 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2418 /* Configure IPG/IFG parameters. */
2419 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2420 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2421 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2422 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2423 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2425 /* Set parameters for half-duplex media. */
2426 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2427 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2428 HDPX_CFG_LCOL_MASK) |
2429 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2430 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2431 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2432 HDPX_CFG_ABEBT_MASK) |
2433 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2434 HDPX_CFG_JAMIPG_MASK));
2436 /* Configure Tx jumbo frame parameters. */
2437 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2438 if (ifp->if_mtu < ETHERMTU)
2439 reg = sc->ale_max_frame_size;
2440 else if (ifp->if_mtu < 6 * 1024)
2441 reg = (sc->ale_max_frame_size * 2) / 3;
2443 reg = sc->ale_max_frame_size / 2;
2444 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2445 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2446 TX_JUMBO_THRESH_UNIT_SHIFT);
2449 /* Configure TxQ. */
2450 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2451 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2452 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2453 TXQ_CFG_TPD_BURST_MASK;
2454 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2456 /* Configure Rx jumbo frame & flow control parameters. */
2457 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2458 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2459 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2460 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2461 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2462 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2463 RX_JUMBO_LKAH_MASK));
2464 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2465 rxf_hi = (reg * 7) / 10;
2466 rxf_lo = (reg * 3)/ 10;
2467 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2468 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2469 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2470 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2471 RX_FIFO_PAUSE_THRESH_HI_MASK));
2475 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2476 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2478 /* Configure RxQ. */
2479 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2480 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2482 /* Configure DMA parameters. */
2484 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2485 reg |= DMA_CFG_TXCMB_ENB;
2486 CSR_WRITE_4(sc, ALE_DMA_CFG,
2487 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2488 sc->ale_dma_rd_burst | reg |
2489 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2490 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2491 DMA_CFG_RD_DELAY_CNT_MASK) |
2492 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2493 DMA_CFG_WR_DELAY_CNT_MASK));
2496 * Hardware can be configured to issue SMB interrupt based
2497 * on programmed interval. Since there is a callout that is
2498 * invoked for every hz in driver we use that instead of
2499 * relying on periodic SMB interrupt.
2501 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2503 /* Clear MAC statistics. */
2504 ale_stats_clear(sc);
2507 * Configure Tx/Rx MACs.
2508 * - Auto-padding for short frames.
2509 * - Enable CRC generation.
2510 * Actual reconfiguration of MAC for resolved speed/duplex
2511 * is followed after detection of link establishment.
2512 * AR81xx always does checksum computation regardless of
2513 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2514 * cause Rx handling issue for fragmented IP datagrams due
2517 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2518 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2519 MAC_CFG_PREAMBLE_MASK);
2520 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2521 reg |= MAC_CFG_SPEED_10_100;
2523 reg |= MAC_CFG_SPEED_1000;
2524 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2526 /* Set up the receive filter. */
2530 /* Acknowledge all pending interrupts and clear it. */
2531 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2532 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2533 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2535 sc->ale_flags &= ~ALE_FLAG_LINK;
2537 /* Switch to the current media. */
2540 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2542 ifp->if_flags |= IFF_RUNNING;
2543 ifp->if_flags &= ~IFF_OACTIVE;
2547 ale_stop(struct ale_softc *sc)
2549 struct ifnet *ifp = &sc->arpcom.ac_if;
2550 struct ale_txdesc *txd;
2554 ASSERT_SERIALIZED(ifp->if_serializer);
2557 * Mark the interface down and cancel the watchdog timer.
2559 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2562 callout_stop(&sc->ale_tick_ch);
2563 sc->ale_flags &= ~ALE_FLAG_LINK;
2565 ale_stats_update(sc);
2567 /* Disable interrupts. */
2568 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2569 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2571 /* Disable queue processing and DMA. */
2572 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2573 reg &= ~TXQ_CFG_ENB;
2574 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2575 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2576 reg &= ~RXQ_CFG_ENB;
2577 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2578 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2579 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2580 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2583 /* Stop Rx/Tx MACs. */
2586 /* Disable interrupts again? XXX */
2587 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2590 * Free TX mbufs still in the queues.
2592 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2593 txd = &sc->ale_cdata.ale_txdesc[i];
2594 if (txd->tx_m != NULL) {
2595 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2604 ale_stop_mac(struct ale_softc *sc)
2609 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2610 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2611 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2612 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2615 for (i = ALE_TIMEOUT; i > 0; i--) {
2616 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2622 device_printf(sc->ale_dev,
2623 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2627 ale_init_tx_ring(struct ale_softc *sc)
2629 struct ale_txdesc *txd;
2632 sc->ale_cdata.ale_tx_prod = 0;
2633 sc->ale_cdata.ale_tx_cons = 0;
2634 sc->ale_cdata.ale_tx_cnt = 0;
2636 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2637 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2638 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2639 txd = &sc->ale_cdata.ale_txdesc[i];
2642 *sc->ale_cdata.ale_tx_cmb = 0;
2643 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2644 sc->ale_cdata.ale_tx_cmb_map,
2645 BUS_DMASYNC_PREWRITE);
2646 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2647 sc->ale_cdata.ale_tx_ring_map,
2648 BUS_DMASYNC_PREWRITE);
2652 ale_init_rx_pages(struct ale_softc *sc)
2654 struct ale_rx_page *rx_page;
2657 sc->ale_cdata.ale_rx_seqno = 0;
2658 sc->ale_cdata.ale_rx_curp = 0;
2660 for (i = 0; i < ALE_RX_PAGES; i++) {
2661 rx_page = &sc->ale_cdata.ale_rx_page[i];
2662 bzero(rx_page->page_addr, sc->ale_pagesize);
2663 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2665 *rx_page->cmb_addr = 0;
2666 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2667 BUS_DMASYNC_PREWRITE);
2668 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2669 BUS_DMASYNC_PREWRITE);
2674 ale_rxvlan(struct ale_softc *sc)
2679 ifp = &sc->arpcom.ac_if;
2680 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2681 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2682 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2683 reg |= MAC_CFG_VLAN_TAG_STRIP;
2684 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2688 ale_rxfilter(struct ale_softc *sc)
2691 struct ifmultiaddr *ifma;
2696 ifp = &sc->arpcom.ac_if;
2698 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
2699 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
2700 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2701 rxcfg |= MAC_CFG_BCAST;
2702 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2703 if ((ifp->if_flags & IFF_PROMISC) != 0)
2704 rxcfg |= MAC_CFG_PROMISC;
2705 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2706 rxcfg |= MAC_CFG_ALLMULTI;
2707 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
2708 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
2709 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2713 /* Program new filter. */
2714 bzero(mchash, sizeof(mchash));
2716 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2717 if (ifma->ifma_addr->sa_family != AF_LINK)
2719 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2720 ifma->ifma_addr), ETHER_ADDR_LEN);
2721 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2724 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
2725 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
2726 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
2730 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
2732 return (sysctl_int_range(oidp, arg1, arg2, req,
2733 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
2737 ale_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
2738 bus_size_t mapsz __unused, int error)
2740 struct ale_dmamap_ctx *ctx = xctx;
2746 if (nsegs > ctx->nsegs) {
2752 for (i = 0; i < nsegs; ++i)
2753 ctx->segs[i] = segs[i];