2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/sis/if_sis.c,v 1.10 2004/03/23 22:19:03 hsu Exp $
35 * $FreeBSD: src/sys/pci/if_sis.c,v 1.13.4.24 2003/03/05 18:42:33 njl Exp $
39 * SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
40 * available from http://www.sis.com.tw.
42 * This driver also supports the NatSemi DP83815. Datasheets are
43 * available from http://www.national.com.
45 * Written by Bill Paul <wpaul@ee.columbia.edu>
46 * Electrical Engineering Department
47 * Columbia University, New York City
51 * The SiS 900 is a fairly simple chip. It uses bus master DMA with
52 * simple TX and RX descriptors of 3 longwords in size. The receiver
53 * has a single perfect filter entry for the station address and a
54 * 128-bit multicast hash table. The SiS 900 has a built-in MII-based
55 * transceiver while the 7016 requires an external transceiver chip.
56 * Both chips offer the standard bit-bang MII interface as well as
57 * an enchanced PHY interface which simplifies accessing MII registers.
59 * The only downside to this chipset is that RX descriptors must be
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/sockio.h>
67 #include <sys/malloc.h>
68 #include <sys/kernel.h>
69 #include <sys/socket.h>
70 #include <sys/sysctl.h>
73 #include <net/if_arp.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/vlan/if_vlan_var.h>
82 #include <vm/vm.h> /* for vtophys */
83 #include <vm/pmap.h> /* for vtophys */
84 #include <machine/clock.h> /* for DELAY */
85 #include <machine/bus_pio.h>
86 #include <machine/bus_memio.h>
87 #include <machine/bus.h>
88 #include <machine/resource.h>
92 #include <dev/netif/mii_layer/mii.h>
93 #include <dev/netif/mii_layer/miivar.h>
95 #include <bus/pci/pcireg.h>
96 #include <bus/pci/pcivar.h>
98 #define SIS_USEIOSPACE
100 #include "if_sisreg.h"
102 /* "controller miibus0" required. See GENERIC if you get errors here. */
103 #include "miibus_if.h"
106 * Various supported device vendors/types and their names.
108 static struct sis_type sis_devs[] = {
109 { SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
110 { SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
111 { NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
115 static int sis_probe(device_t);
116 static int sis_attach(device_t);
117 static int sis_detach(device_t);
119 static int sis_newbuf(struct sis_softc *, struct sis_desc *,
121 static int sis_encap(struct sis_softc *, struct mbuf *, uint32_t *);
122 static void sis_rxeof(struct sis_softc *);
123 static void sis_rxeoc(struct sis_softc *);
124 static void sis_txeof(struct sis_softc *);
125 static void sis_intr(void *);
126 static void sis_tick(void *);
127 static void sis_start(struct ifnet *);
128 static int sis_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
129 static void sis_init(void *);
130 static void sis_stop(struct sis_softc *);
131 static void sis_watchdog(struct ifnet *);
132 static void sis_shutdown(device_t);
133 static int sis_ifmedia_upd(struct ifnet *);
134 static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
136 static uint16_t sis_reverse(uint16_t);
137 static void sis_delay(struct sis_softc *);
138 static void sis_eeprom_idle(struct sis_softc *);
139 static void sis_eeprom_putbyte(struct sis_softc *, int);
140 static void sis_eeprom_getword(struct sis_softc *, int, uint16_t *);
141 static void sis_read_eeprom(struct sis_softc *, caddr_t, int, int, int);
143 static void sis_read_cmos(struct sis_softc *, device_t, caddr_t, int, int);
144 static void sis_read_mac(struct sis_softc *, device_t, caddr_t);
145 static device_t sis_find_bridge(device_t);
148 static void sis_mii_sync(struct sis_softc *);
149 static void sis_mii_send(struct sis_softc *, uint32_t, int);
150 static int sis_mii_readreg(struct sis_softc *, struct sis_mii_frame *);
151 static int sis_mii_writereg(struct sis_softc *, struct sis_mii_frame *);
152 static int sis_miibus_readreg(device_t, int, int);
153 static int sis_miibus_writereg(device_t, int, int, int);
154 static void sis_miibus_statchg(device_t);
156 static void sis_setmulti_sis(struct sis_softc *);
157 static void sis_setmulti_ns(struct sis_softc *);
158 static uint32_t sis_mchash(struct sis_softc *, const uint8_t *);
159 static void sis_reset(struct sis_softc *);
160 static int sis_list_rx_init(struct sis_softc *);
161 static int sis_list_tx_init(struct sis_softc *);
162 #ifdef SIS_USEIOSPACE
163 #define SIS_RES SYS_RES_IOPORT
164 #define SIS_RID SIS_PCI_LOIO
166 #define SIS_RES SYS_RES_MEMORY
167 #define SIS_RID SIS_PCI_LOMEM
170 static device_method_t sis_methods[] = {
171 /* Device interface */
172 DEVMETHOD(device_probe, sis_probe),
173 DEVMETHOD(device_attach, sis_attach),
174 DEVMETHOD(device_detach, sis_detach),
175 DEVMETHOD(device_shutdown, sis_shutdown),
178 DEVMETHOD(bus_print_child, bus_generic_print_child),
179 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
182 DEVMETHOD(miibus_readreg, sis_miibus_readreg),
183 DEVMETHOD(miibus_writereg, sis_miibus_writereg),
184 DEVMETHOD(miibus_statchg, sis_miibus_statchg),
189 static driver_t sis_driver = {
192 sizeof(struct sis_softc)
195 static devclass_t sis_devclass;
197 DECLARE_DUMMY_MODULE(if_sis);
198 DRIVER_MODULE(if_sis, pci, sis_driver, sis_devclass, 0, 0);
199 DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
201 #define SIS_SETBIT(sc, reg, x) \
202 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
204 #define SIS_CLRBIT(sc, reg, x) \
205 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
208 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
211 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
214 * Routine to reverse the bits in a word. Stolen almost
215 * verbatim from /usr/games/fortune.
218 sis_reverse(uint16_t n)
220 n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
221 n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
222 n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
223 n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
229 sis_delay(struct sis_softc *sc)
233 for (idx = (300 / 33) + 1; idx > 0; idx--)
234 CSR_READ_4(sc, SIS_CSR);
238 sis_eeprom_idle(struct sis_softc *sc)
242 SIO_SET(SIS_EECTL_CSEL);
244 SIO_SET(SIS_EECTL_CLK);
247 for (i = 0; i < 25; i++) {
248 SIO_CLR(SIS_EECTL_CLK);
250 SIO_SET(SIS_EECTL_CLK);
254 SIO_CLR(SIS_EECTL_CLK);
256 SIO_CLR(SIS_EECTL_CSEL);
258 CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
262 * Send a read command and address to the EEPROM, check for ACK.
265 sis_eeprom_putbyte(struct sis_softc *sc, int addr)
269 d = addr | SIS_EECMD_READ;
272 * Feed in each bit and stobe the clock.
274 for (i = 0x400; i; i >>= 1) {
276 SIO_SET(SIS_EECTL_DIN);
278 SIO_CLR(SIS_EECTL_DIN);
280 SIO_SET(SIS_EECTL_CLK);
282 SIO_CLR(SIS_EECTL_CLK);
288 * Read a word of data stored in the EEPROM at address 'addr.'
291 sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
296 /* Force EEPROM to idle state. */
299 /* Enter EEPROM access mode. */
301 SIO_CLR(SIS_EECTL_CLK);
303 SIO_SET(SIS_EECTL_CSEL);
307 * Send address of word we want to read.
309 sis_eeprom_putbyte(sc, addr);
312 * Start reading bits from EEPROM.
314 for (i = 0x8000; i; i >>= 1) {
315 SIO_SET(SIS_EECTL_CLK);
317 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
320 SIO_CLR(SIS_EECTL_CLK);
324 /* Turn off EEPROM access mode. */
331 * Read a sequence of words from the EEPROM.
334 sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
337 uint16_t word = 0, *ptr;
339 for (i = 0; i < cnt; i++) {
340 sis_eeprom_getword(sc, off + i, &word);
341 ptr = (uint16_t *)(dest + (i * 2));
351 sis_find_bridge(device_t dev)
353 devclass_t pci_devclass;
354 device_t *pci_devices;
356 device_t *pci_children;
357 int pci_childcount = 0;
358 device_t *busp, *childp;
359 device_t child = NULL;
362 if ((pci_devclass = devclass_find("pci")) == NULL)
365 devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
367 for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
369 device_get_children(*busp, &pci_children, &pci_childcount);
370 for (j = 0, childp = pci_children; j < pci_childcount;
372 if (pci_get_vendor(*childp) == SIS_VENDORID &&
373 pci_get_device(*childp) == 0x0008) {
381 free(pci_devices, M_TEMP);
382 free(pci_children, M_TEMP);
387 sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off,
393 bus_space_tag_t btag;
395 bridge = sis_find_bridge(dev);
398 reg = pci_read_config(bridge, 0x48, 1);
399 pci_write_config(bridge, 0x48, reg|0x40, 1);
402 btag = I386_BUS_SPACE_IO;
404 for (i = 0; i < cnt; i++) {
405 bus_space_write_1(btag, 0x0, 0x70, i + off);
406 *(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
409 pci_write_config(bridge, 0x48, reg & ~0x40, 1);
413 sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
415 uint32_t filtsave, csrsave;
417 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
418 csrsave = CSR_READ_4(sc, SIS_CSR);
420 CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
421 CSR_WRITE_4(sc, SIS_CSR, 0);
423 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
425 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
426 ((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
427 CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
428 ((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
429 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
430 ((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
432 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
433 CSR_WRITE_4(sc, SIS_CSR, csrsave);
438 * Sync the PHYs by setting data bit and strobing the clock 32 times.
441 sis_mii_sync(struct sis_softc *sc)
445 SIO_SET(SIS_MII_DIR|SIS_MII_DATA);
447 for (i = 0; i < 32; i++) {
448 SIO_SET(SIS_MII_CLK);
450 SIO_CLR(SIS_MII_CLK);
456 * Clock a series of bits through the MII.
459 sis_mii_send(struct sis_softc *sc, uint32_t bits, int cnt)
463 SIO_CLR(SIS_MII_CLK);
465 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
467 SIO_SET(SIS_MII_DATA);
469 SIO_CLR(SIS_MII_DATA);
471 SIO_CLR(SIS_MII_CLK);
473 SIO_SET(SIS_MII_CLK);
478 * Read an PHY register through the MII.
481 sis_mii_readreg(struct sis_softc *sc, struct sis_mii_frame *frame)
488 * Set up frame for RX.
490 frame->mii_stdelim = SIS_MII_STARTDELIM;
491 frame->mii_opcode = SIS_MII_READOP;
492 frame->mii_turnaround = 0;
498 SIO_SET(SIS_MII_DIR);
503 * Send command/address info.
505 sis_mii_send(sc, frame->mii_stdelim, 2);
506 sis_mii_send(sc, frame->mii_opcode, 2);
507 sis_mii_send(sc, frame->mii_phyaddr, 5);
508 sis_mii_send(sc, frame->mii_regaddr, 5);
511 SIO_CLR((SIS_MII_CLK|SIS_MII_DATA));
513 SIO_SET(SIS_MII_CLK);
517 SIO_CLR(SIS_MII_DIR);
520 SIO_CLR(SIS_MII_CLK);
522 ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;
523 SIO_SET(SIS_MII_CLK);
527 * Now try reading data bits. If the ack failed, we still
528 * need to clock through 16 cycles to keep the PHY(s) in sync.
531 for(i = 0; i < 16; i++) {
532 SIO_CLR(SIS_MII_CLK);
534 SIO_SET(SIS_MII_CLK);
540 for (i = 0x8000; i; i >>= 1) {
541 SIO_CLR(SIS_MII_CLK);
544 if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)
545 frame->mii_data |= i;
548 SIO_SET(SIS_MII_CLK);
554 SIO_CLR(SIS_MII_CLK);
556 SIO_SET(SIS_MII_CLK);
567 * Write to a PHY register through the MII.
570 sis_mii_writereg(struct sis_softc *sc, struct sis_mii_frame *frame)
576 * Set up frame for TX.
579 frame->mii_stdelim = SIS_MII_STARTDELIM;
580 frame->mii_opcode = SIS_MII_WRITEOP;
581 frame->mii_turnaround = SIS_MII_TURNAROUND;
584 * Turn on data output.
586 SIO_SET(SIS_MII_DIR);
590 sis_mii_send(sc, frame->mii_stdelim, 2);
591 sis_mii_send(sc, frame->mii_opcode, 2);
592 sis_mii_send(sc, frame->mii_phyaddr, 5);
593 sis_mii_send(sc, frame->mii_regaddr, 5);
594 sis_mii_send(sc, frame->mii_turnaround, 2);
595 sis_mii_send(sc, frame->mii_data, 16);
598 SIO_SET(SIS_MII_CLK);
600 SIO_CLR(SIS_MII_CLK);
606 SIO_CLR(SIS_MII_DIR);
614 sis_miibus_readreg(device_t dev, int phy, int reg)
616 struct sis_softc *sc;
617 struct sis_mii_frame frame;
619 sc = device_get_softc(dev);
621 if (sc->sis_type == SIS_TYPE_83815) {
625 * The NatSemi chip can take a while after
626 * a reset to come ready, during which the BMSR
627 * returns a value of 0. This is *never* supposed
628 * to happen: some of the BMSR bits are meant to
629 * be hardwired in the on position, and this can
630 * confuse the miibus code a bit during the probe
631 * and attach phase. So we make an effort to check
632 * for this condition and wait for it to clear.
634 if (!CSR_READ_4(sc, NS_BMSR))
636 return CSR_READ_4(sc, NS_BMCR + (reg * 4));
639 * Chipsets < SIS_635 seem not to be able to read/write
640 * through mdio. Use the enhanced PHY access register
643 if (sc->sis_type == SIS_TYPE_900 &&
644 sc->sis_rev < SIS_REV_635) {
650 CSR_WRITE_4(sc, SIS_PHYCTL,
651 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
652 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
654 for (i = 0; i < SIS_TIMEOUT; i++) {
655 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
659 if (i == SIS_TIMEOUT) {
660 printf("sis%d: PHY failed to come ready\n",
665 val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
672 bzero((char *)&frame, sizeof(frame));
674 frame.mii_phyaddr = phy;
675 frame.mii_regaddr = reg;
676 sis_mii_readreg(sc, &frame);
678 return(frame.mii_data);
683 sis_miibus_writereg(device_t dev, int phy, int reg, int data)
685 struct sis_softc *sc;
686 struct sis_mii_frame frame;
688 sc = device_get_softc(dev);
690 if (sc->sis_type == SIS_TYPE_83815) {
693 CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
697 if (sc->sis_type == SIS_TYPE_900 &&
698 sc->sis_rev < SIS_REV_635) {
704 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
705 (reg << 6) | SIS_PHYOP_WRITE);
706 SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
708 for (i = 0; i < SIS_TIMEOUT; i++) {
709 if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
713 if (i == SIS_TIMEOUT)
714 printf("sis%d: PHY failed to come ready\n",
717 bzero((char *)&frame, sizeof(frame));
719 frame.mii_phyaddr = phy;
720 frame.mii_regaddr = reg;
721 frame.mii_data = data;
722 sis_mii_writereg(sc, &frame);
727 static void sis_miibus_statchg(device_t dev)
729 struct sis_softc *sc;
731 sc = device_get_softc(dev);
736 sis_mchash(struct sis_softc *sc, const uint8_t *addr)
742 /* Compute CRC for the address value. */
743 crc = 0xFFFFFFFF; /* initial value */
745 for (i = 0; i < 6; i++) {
747 for (j = 0; j < 8; j++) {
748 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
752 crc = (crc ^ 0x04c11db6) | carry;
757 * return the filter bit position
759 * The NatSemi chip has a 512-bit filter, which is
760 * different than the SiS, so we special-case it.
762 if (sc->sis_type == SIS_TYPE_83815)
764 else if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
771 sis_setmulti_ns(struct sis_softc *sc)
774 struct ifmultiaddr *ifma;
775 uint32_t h = 0, i, filtsave;
778 ifp = &sc->arpcom.ac_if;
780 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
781 SIS_CLRBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
782 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
787 * We have to explicitly enable the multicast hash table
788 * on the NatSemi chip if we want to use it, which we do.
790 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_MCHASH);
791 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLMULTI);
793 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
795 /* first, zot all the existing hash bits */
796 for (i = 0; i < 32; i++) {
797 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + (i*2));
798 CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
801 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
802 if (ifma->ifma_addr->sa_family != AF_LINK)
805 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
808 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO + index);
811 SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
814 CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
818 sis_setmulti_sis(struct sis_softc *sc)
821 struct ifmultiaddr *ifma;
822 uint32_t h, i, n, ctl;
825 ifp = &sc->arpcom.ac_if;
827 /* hash table size */
828 if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
833 ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;
835 if (ifp->if_flags & IFF_BROADCAST)
836 ctl |= SIS_RXFILTCTL_BROAD;
838 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
839 ctl |= SIS_RXFILTCTL_ALLMULTI;
840 if (ifp->if_flags & IFF_PROMISC)
841 ctl |= SIS_RXFILTCTL_BROAD|SIS_RXFILTCTL_ALLPHYS;
842 for (i = 0; i < n; i++)
845 for (i = 0; i < n; i++)
848 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
849 if (ifma->ifma_addr->sa_family != AF_LINK)
852 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
853 hashes[h >> 4] |= 1 << (h & 0xf);
857 ctl |= SIS_RXFILTCTL_ALLMULTI;
858 for (i = 0; i < n; i++)
863 for (i = 0; i < n; i++) {
864 CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
865 CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
868 CSR_WRITE_4(sc, SIS_RXFILT_CTL, ctl);
872 sis_reset(struct sis_softc *sc)
876 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
878 for (i = 0; i < SIS_TIMEOUT; i++) {
879 if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
883 if (i == SIS_TIMEOUT)
884 printf("sis%d: reset never completed\n", sc->sis_unit);
886 /* Wait a little while for the chip to get its brains in order. */
890 * If this is a NetSemi chip, make sure to clear
893 if (sc->sis_type == SIS_TYPE_83815) {
894 CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
895 CSR_WRITE_4(sc, NS_CLKRUN, 0);
900 * Probe for an SiS chip. Check the PCI vendor and device
901 * IDs against our list and return a device name if we find a match.
904 sis_probe(device_t dev)
910 while(t->sis_name != NULL) {
911 if ((pci_get_vendor(dev) == t->sis_vid) &&
912 (pci_get_device(dev) == t->sis_did)) {
913 device_set_desc(dev, t->sis_name);
923 * Attach the interface. Allocate softc structures, do ifmedia
924 * setup and ethernet/BPF attach.
927 sis_attach(device_t dev)
930 uint8_t eaddr[ETHER_ADDR_LEN];
932 struct sis_softc *sc;
934 int unit, error, rid, waittime;
938 error = waittime = 0;
939 sc = device_get_softc(dev);
940 unit = device_get_unit(dev);
941 bzero(sc, sizeof(struct sis_softc));
943 if (pci_get_device(dev) == SIS_DEVICEID_900)
944 sc->sis_type = SIS_TYPE_900;
945 if (pci_get_device(dev) == SIS_DEVICEID_7016)
946 sc->sis_type = SIS_TYPE_7016;
947 if (pci_get_vendor(dev) == NS_VENDORID)
948 sc->sis_type = SIS_TYPE_83815;
950 sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
953 * Handle power management nonsense.
956 command = pci_read_config(dev, SIS_PCI_CAPID, 4) & 0x000000FF;
957 if (command == 0x01) {
959 command = pci_read_config(dev, SIS_PCI_PWRMGMTCTRL, 4);
960 if (command & SIS_PSTATE_MASK) {
961 uint32_t iobase, membase, irq;
963 /* Save important PCI config data. */
964 iobase = pci_read_config(dev, SIS_PCI_LOIO, 4);
965 membase = pci_read_config(dev, SIS_PCI_LOMEM, 4);
966 irq = pci_read_config(dev, SIS_PCI_INTLINE, 4);
968 /* Reset the power state. */
969 printf("sis%d: chip is in D%d power mode "
970 "-- setting to D0\n", unit, command & SIS_PSTATE_MASK);
971 command &= 0xFFFFFFFC;
972 pci_write_config(dev, SIS_PCI_PWRMGMTCTRL, command, 4);
974 /* Restore PCI config data. */
975 pci_write_config(dev, SIS_PCI_LOIO, iobase, 4);
976 pci_write_config(dev, SIS_PCI_LOMEM, membase, 4);
977 pci_write_config(dev, SIS_PCI_INTLINE, irq, 4);
982 * Map control/status registers.
984 command = pci_read_config(dev, PCIR_COMMAND, 4);
985 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
986 pci_write_config(dev, PCIR_COMMAND, command, 4);
987 command = pci_read_config(dev, PCIR_COMMAND, 4);
989 #ifdef SIS_USEIOSPACE
990 if (!(command & PCIM_CMD_PORTEN)) {
991 printf("sis%d: failed to enable I/O ports!\n", unit);
996 if (!(command & PCIM_CMD_MEMEN)) {
997 printf("sis%d: failed to enable memory mapping!\n", unit);
1004 sc->sis_res = bus_alloc_resource(dev, SIS_RES, &rid,
1005 0, ~0, 1, RF_ACTIVE);
1007 if (sc->sis_res == NULL) {
1008 printf("sis%d: couldn't map ports/memory\n", unit);
1013 sc->sis_btag = rman_get_bustag(sc->sis_res);
1014 sc->sis_bhandle = rman_get_bushandle(sc->sis_res);
1016 /* Allocate interrupt */
1018 sc->sis_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1019 RF_SHAREABLE | RF_ACTIVE);
1021 if (sc->sis_irq == NULL) {
1022 printf("sis%d: couldn't map interrupt\n", unit);
1023 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1028 error = bus_setup_intr(dev, sc->sis_irq, INTR_TYPE_NET,
1029 sis_intr, sc, &sc->sis_intrhand);
1032 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1033 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1034 printf("sis%d: couldn't set up irq\n", unit);
1038 /* Reset the adapter. */
1041 if (sc->sis_type == SIS_TYPE_900 &&
1042 (sc->sis_rev == SIS_REV_635 ||
1043 sc->sis_rev == SIS_REV_900B)) {
1044 SIO_SET(SIS_CFG_RND_CNT);
1045 SIO_SET(SIS_CFG_PERR_DETECT);
1049 * Get station address from the EEPROM.
1051 switch (pci_get_vendor(dev)) {
1054 * Reading the MAC address out of the EEPROM on
1055 * the NatSemi chip takes a bit more work than
1056 * you'd expect. The address spans 4 16-bit words,
1057 * with the first word containing only a single bit.
1058 * You have to shift everything over one bit to
1059 * get it aligned properly. Also, the bits are
1060 * stored backwards (the LSB is really the MSB,
1061 * and so on) so you have to reverse them in order
1062 * to get the MAC address into the form we want.
1063 * Why? Who the hell knows.
1068 sis_read_eeprom(sc, (caddr_t)&tmp,
1069 NS_EE_NODEADDR, 4, 0);
1071 /* Shift everything over one bit. */
1072 tmp[3] = tmp[3] >> 1;
1073 tmp[3] |= tmp[2] << 15;
1074 tmp[2] = tmp[2] >> 1;
1075 tmp[2] |= tmp[1] << 15;
1076 tmp[1] = tmp[1] >> 1;
1077 tmp[1] |= tmp[0] << 15;
1079 /* Now reverse all the bits. */
1080 tmp[3] = sis_reverse(tmp[3]);
1081 tmp[2] = sis_reverse(tmp[2]);
1082 tmp[1] = sis_reverse(tmp[1]);
1084 bcopy((char *)&tmp[1], eaddr, ETHER_ADDR_LEN);
1091 * If this is a SiS 630E chipset with an embedded
1092 * SiS 900 controller, we have to read the MAC address
1093 * from the APC CMOS RAM. Our method for doing this
1094 * is very ugly since we have to reach out and grab
1095 * ahold of hardware for which we cannot properly
1096 * allocate resources. This code is only compiled on
1097 * the i386 architecture since the SiS 630E chipset
1098 * is for x86 motherboards only. Note that there are
1099 * a lot of magic numbers in this hack. These are
1100 * taken from SiS's Linux driver. I'd like to replace
1101 * them with proper symbolic definitions, but that
1102 * requires some datasheets that I don't have access
1105 if (sc->sis_rev == SIS_REV_630S ||
1106 sc->sis_rev == SIS_REV_630E ||
1107 sc->sis_rev == SIS_REV_630EA1)
1108 sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
1110 else if (sc->sis_rev == SIS_REV_635 ||
1111 sc->sis_rev == SIS_REV_630ET)
1112 sis_read_mac(sc, dev, (caddr_t)&eaddr);
1113 else if (sc->sis_rev == SIS_REV_96x) {
1115 * Allow to read EEPROM from LAN. It is shared
1116 * between a 1394 controller and the NIC and each
1117 * time we access it, we need to set SIS_EECMD_REQ.
1119 SIO_SET(SIS_EECMD_REQ);
1120 for (waittime = 0; waittime < SIS_TIMEOUT;
1122 /* Force EEPROM to idle state. */
1123 sis_eeprom_idle(sc);
1124 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
1125 sis_read_eeprom(sc, (caddr_t)&eaddr,
1126 SIS_EE_NODEADDR, 3, 0);
1132 * Set SIS_EECTL_CLK to high, so a other master
1133 * can operate on the i2c bus.
1135 SIO_SET(SIS_EECTL_CLK);
1136 /* Refuse EEPROM access by LAN */
1137 SIO_SET(SIS_EECMD_DONE);
1140 sis_read_eeprom(sc, (caddr_t)&eaddr,
1141 SIS_EE_NODEADDR, 3, 0);
1146 * A SiS chip was detected. Inform the world.
1148 printf("sis%d: Ethernet address: %6D\n", unit, eaddr, ":");
1150 sc->sis_unit = unit;
1151 callout_handle_init(&sc->sis_stat_ch);
1153 sc->sis_ldata = contigmalloc(sizeof(struct sis_list_data), M_DEVBUF,
1154 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1156 if (sc->sis_ldata == NULL) {
1157 printf("sis%d: no memory for list buffers!\n", unit);
1158 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1159 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1160 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1164 bzero(sc->sis_ldata, sizeof(struct sis_list_data));
1166 ifp = &sc->arpcom.ac_if;
1168 if_initname(ifp, "sis", unit);
1169 ifp->if_mtu = ETHERMTU;
1170 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1171 ifp->if_ioctl = sis_ioctl;
1172 ifp->if_output = ether_output;
1173 ifp->if_start = sis_start;
1174 ifp->if_watchdog = sis_watchdog;
1175 ifp->if_init = sis_init;
1176 ifp->if_baudrate = 10000000;
1177 ifp->if_snd.ifq_maxlen = SIS_TX_LIST_CNT - 1;
1182 if (mii_phy_probe(dev, &sc->sis_miibus,
1183 sis_ifmedia_upd, sis_ifmedia_sts)) {
1184 printf("sis%d: MII without any PHY!\n", sc->sis_unit);
1185 contigfree(sc->sis_ldata, sizeof(struct sis_list_data),
1187 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1188 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1189 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1195 * Call MI attach routine.
1197 ether_ifattach(ifp, eaddr);
1200 * Tell the upper layer(s) we support long frames.
1202 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1204 callout_handle_init(&sc->sis_stat_ch);
1212 sis_detach(device_t dev)
1214 struct sis_softc *sc;
1220 sc = device_get_softc(dev);
1221 ifp = &sc->arpcom.ac_if;
1225 ether_ifdetach(ifp);
1227 bus_generic_detach(dev);
1228 device_delete_child(dev, sc->sis_miibus);
1230 bus_teardown_intr(dev, sc->sis_irq, sc->sis_intrhand);
1231 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sis_irq);
1232 bus_release_resource(dev, SIS_RES, SIS_RID, sc->sis_res);
1234 contigfree(sc->sis_ldata, sizeof(struct sis_list_data), M_DEVBUF);
1242 * Initialize the transmit descriptors.
1245 sis_list_tx_init(struct sis_softc *sc)
1247 struct sis_list_data *ld;
1248 struct sis_ring_data *cd;
1251 cd = &sc->sis_cdata;
1254 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
1255 nexti = (i == (SIS_TX_LIST_CNT - 1)) ? 0 : i+1;
1256 ld->sis_tx_list[i].sis_nextdesc =
1257 &ld->sis_tx_list[nexti];
1258 ld->sis_tx_list[i].sis_next =
1259 vtophys(&ld->sis_tx_list[nexti]);
1260 ld->sis_tx_list[i].sis_mbuf = NULL;
1261 ld->sis_tx_list[i].sis_ptr = 0;
1262 ld->sis_tx_list[i].sis_ctl = 0;
1265 cd->sis_tx_prod = cd->sis_tx_cons = cd->sis_tx_cnt = 0;
1271 * Initialize the RX descriptors and allocate mbufs for them. Note that
1272 * we arrange the descriptors in a closed ring, so that the last descriptor
1273 * points back to the first.
1276 sis_list_rx_init(struct sis_softc *sc)
1278 struct sis_list_data *ld;
1279 struct sis_ring_data *cd;
1283 cd = &sc->sis_cdata;
1285 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
1286 if (sis_newbuf(sc, &ld->sis_rx_list[i], NULL) == ENOBUFS)
1288 nexti = (i == (SIS_RX_LIST_CNT - 1)) ? 0 : i+1;
1289 ld->sis_rx_list[i].sis_nextdesc =
1290 &ld->sis_rx_list[nexti];
1291 ld->sis_rx_list[i].sis_next =
1292 vtophys(&ld->sis_rx_list[nexti]);
1295 cd->sis_rx_prod = 0;
1301 * Initialize an RX descriptor and attach an MBUF cluster.
1304 sis_newbuf(struct sis_softc *sc, struct sis_desc *c, struct mbuf *m)
1307 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1311 m->m_data = m->m_ext.ext_buf;
1315 c->sis_ptr = vtophys(mtod(m, caddr_t));
1316 c->sis_ctl = SIS_RXLEN;
1322 * A frame has been uploaded: pass the resulting mbuf chain up to
1323 * the higher level protocols.
1326 sis_rxeof(struct sis_softc *sc)
1330 struct sis_desc *cur_rx;
1331 int i, total_len = 0;
1334 ifp = &sc->arpcom.ac_if;
1335 i = sc->sis_cdata.sis_rx_prod;
1337 while(SIS_OWNDESC(&sc->sis_ldata->sis_rx_list[i])) {
1339 #ifdef DEVICE_POLLING
1340 if (ifp->if_ipending & IFF_POLLING) {
1341 if (sc->rxcycles <= 0)
1345 #endif /* DEVICE_POLLING */
1346 cur_rx = &sc->sis_ldata->sis_rx_list[i];
1347 rxstat = cur_rx->sis_rxstat;
1348 m = cur_rx->sis_mbuf;
1349 cur_rx->sis_mbuf = NULL;
1350 total_len = SIS_RXBYTES(cur_rx);
1351 SIS_INC(i, SIS_RX_LIST_CNT);
1354 * If an error occurs, update stats, clear the
1355 * status word and leave the mbuf cluster in place:
1356 * it should simply get re-used next time this descriptor
1357 * comes up in the ring.
1359 if (!(rxstat & SIS_CMDSTS_PKT_OK)) {
1361 if (rxstat & SIS_RXSTAT_COLL)
1362 ifp->if_collisions++;
1363 sis_newbuf(sc, cur_rx, m);
1367 /* No errors; receive the packet. */
1370 * On the x86 we do not have alignment problems, so try to
1371 * allocate a new buffer for the receive ring, and pass up
1372 * the one where the packet is already, saving the expensive
1373 * copy done in m_devget().
1374 * If we are on an architecture with alignment problems, or
1375 * if the allocation fails, then use m_devget and leave the
1376 * existing buffer in the receive ring.
1378 if (sis_newbuf(sc, cur_rx, NULL) == 0)
1379 m->m_pkthdr.len = m->m_len = total_len;
1384 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1385 total_len + ETHER_ALIGN, 0, ifp, NULL);
1386 sis_newbuf(sc, cur_rx, m);
1391 m_adj(m0, ETHER_ALIGN);
1396 ether_input(ifp, NULL, m);
1399 sc->sis_cdata.sis_rx_prod = i;
1403 sis_rxeoc(struct sis_softc *sc)
1410 * A frame was downloaded to the chip. It's safe for us to clean up
1415 sis_txeof(struct sis_softc *sc)
1417 struct sis_desc *cur_tx = NULL;
1421 ifp = &sc->arpcom.ac_if;
1424 * Go through our tx list and free mbufs for those
1425 * frames that have been transmitted.
1427 idx = sc->sis_cdata.sis_tx_cons;
1428 while (idx != sc->sis_cdata.sis_tx_prod) {
1429 cur_tx = &sc->sis_ldata->sis_tx_list[idx];
1431 if (SIS_OWNDESC(cur_tx))
1434 if (cur_tx->sis_ctl & SIS_CMDSTS_MORE) {
1435 sc->sis_cdata.sis_tx_cnt--;
1436 SIS_INC(idx, SIS_TX_LIST_CNT);
1440 if (!(cur_tx->sis_ctl & SIS_CMDSTS_PKT_OK)) {
1442 if (cur_tx->sis_txstat & SIS_TXSTAT_EXCESSCOLLS)
1443 ifp->if_collisions++;
1444 if (cur_tx->sis_txstat & SIS_TXSTAT_OUTOFWINCOLL)
1445 ifp->if_collisions++;
1448 ifp->if_collisions +=
1449 (cur_tx->sis_txstat & SIS_TXSTAT_COLLCNT) >> 16;
1452 if (cur_tx->sis_mbuf != NULL) {
1453 m_freem(cur_tx->sis_mbuf);
1454 cur_tx->sis_mbuf = NULL;
1457 sc->sis_cdata.sis_tx_cnt--;
1458 SIS_INC(idx, SIS_TX_LIST_CNT);
1462 if (idx != sc->sis_cdata.sis_tx_cons) {
1463 sc->sis_cdata.sis_tx_cons = idx;
1464 ifp->if_flags &= ~IFF_OACTIVE;
1467 ifp->if_timer = (sc->sis_cdata.sis_tx_cnt == 0) ? 0 : 5;
1473 struct sis_softc *sc;
1474 struct mii_data *mii;
1481 ifp = &sc->arpcom.ac_if;
1483 mii = device_get_softc(sc->sis_miibus);
1486 if (!sc->sis_link) {
1488 if (mii->mii_media_status & IFM_ACTIVE &&
1489 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1491 if (ifp->if_snd.ifq_head != NULL)
1495 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
1500 #ifdef DEVICE_POLLING
1501 static poll_handler_t sis_poll;
1504 sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1506 struct sis_softc *sc = ifp->if_softc;
1508 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1509 CSR_WRITE_4(sc, SIS_IER, 1);
1514 * On the sis, reading the status register also clears it.
1515 * So before returning to intr mode we must make sure that all
1516 * possible pending sources of interrupts have been served.
1517 * In practice this means run to completion the *eof routines,
1518 * and then call the interrupt routine
1520 sc->rxcycles = count;
1523 if (ifp->if_snd.ifq_head != NULL)
1526 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1529 /* Reading the ISR register clears all interrupts. */
1530 status = CSR_READ_4(sc, SIS_ISR);
1532 if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
1535 if (status & (SIS_ISR_RX_IDLE))
1536 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1538 if (status & SIS_ISR_SYSERR) {
1544 #endif /* DEVICE_POLLING */
1549 struct sis_softc *sc;
1554 ifp = &sc->arpcom.ac_if;
1556 #ifdef DEVICE_POLLING
1557 if (ifp->if_ipending & IFF_POLLING)
1559 if (ether_poll_register(sis_poll, ifp)) { /* ok, disable interrupts */
1560 CSR_WRITE_4(sc, SIS_IER, 0);
1561 sis_poll(ifp, 0, 1);
1564 #endif /* DEVICE_POLLING */
1566 /* Supress unwanted interrupts */
1567 if (!(ifp->if_flags & IFF_UP)) {
1572 /* Disable interrupts. */
1573 CSR_WRITE_4(sc, SIS_IER, 0);
1576 /* Reading the ISR register clears all interrupts. */
1577 status = CSR_READ_4(sc, SIS_ISR);
1579 if ((status & SIS_INTRS) == 0)
1583 (SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR | SIS_ISR_TX_OK |
1588 (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK | SIS_ISR_RX_IDLE))
1591 if (status & (SIS_ISR_RX_ERR | SIS_ISR_RX_OFLOW))
1594 if (status & (SIS_ISR_RX_IDLE))
1595 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1597 if (status & SIS_ISR_SYSERR) {
1603 /* Re-enable interrupts. */
1604 CSR_WRITE_4(sc, SIS_IER, 1);
1606 if (ifp->if_snd.ifq_head != NULL)
1611 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1612 * pointers to the fragment pointers.
1615 sis_encap(struct sis_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1617 struct sis_desc *f = NULL;
1619 int frag, cur, cnt = 0;
1622 * Start packing the mbufs in this chain into
1623 * the fragment pointers. Stop when we run out
1624 * of fragments or hit the end of the mbuf chain.
1627 cur = frag = *txidx;
1629 for (m = m_head; m != NULL; m = m->m_next) {
1630 if (m->m_len != 0) {
1631 if ((SIS_TX_LIST_CNT -
1632 (sc->sis_cdata.sis_tx_cnt + cnt)) < 2)
1634 f = &sc->sis_ldata->sis_tx_list[frag];
1635 f->sis_ctl = SIS_CMDSTS_MORE | m->m_len;
1636 f->sis_ptr = vtophys(mtod(m, vm_offset_t));
1638 f->sis_ctl |= SIS_CMDSTS_OWN;
1640 SIS_INC(frag, SIS_TX_LIST_CNT);
1648 sc->sis_ldata->sis_tx_list[cur].sis_mbuf = m_head;
1649 sc->sis_ldata->sis_tx_list[cur].sis_ctl &= ~SIS_CMDSTS_MORE;
1650 sc->sis_ldata->sis_tx_list[*txidx].sis_ctl |= SIS_CMDSTS_OWN;
1651 sc->sis_cdata.sis_tx_cnt += cnt;
1658 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1659 * to the mbuf data regions directly in the transmit lists. We also save a
1660 * copy of the pointers since the transmit list fragment pointers are
1661 * physical addresses.
1665 sis_start(struct ifnet *ifp)
1667 struct sis_softc *sc;
1668 struct mbuf *m_head = NULL;
1676 idx = sc->sis_cdata.sis_tx_prod;
1678 if (ifp->if_flags & IFF_OACTIVE)
1681 while(sc->sis_ldata->sis_tx_list[idx].sis_mbuf == NULL) {
1682 IF_DEQUEUE(&ifp->if_snd, m_head);
1686 if (sis_encap(sc, m_head, &idx)) {
1687 IF_PREPEND(&ifp->if_snd, m_head);
1688 ifp->if_flags |= IFF_OACTIVE;
1693 * If there's a BPF listener, bounce a copy of this frame
1696 BPF_MTAP(ifp, m_head);
1700 sc->sis_cdata.sis_tx_prod = idx;
1701 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
1704 * Set a timeout in case the chip goes out to lunch.
1712 struct sis_softc *sc = xsc;
1713 struct ifnet *ifp = &sc->arpcom.ac_if;
1714 struct mii_data *mii;
1720 * Cancel pending I/O and free all RX/TX buffers.
1724 mii = device_get_softc(sc->sis_miibus);
1726 /* Set MAC address */
1727 if (sc->sis_type == SIS_TYPE_83815) {
1728 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
1729 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1730 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1731 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
1732 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1733 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1734 CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
1735 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1736 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1738 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
1739 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1740 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1741 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
1742 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1743 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1744 CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
1745 CSR_WRITE_4(sc, SIS_RXFILT_DATA,
1746 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1749 /* Init circular RX list. */
1750 if (sis_list_rx_init(sc) == ENOBUFS) {
1751 printf("sis%d: initialization failed: no "
1752 "memory for rx buffers\n", sc->sis_unit);
1759 * Init tx descriptors.
1761 sis_list_tx_init(sc);
1764 * For the NatSemi chip, we have to explicitly enable the
1765 * reception of ARP frames, as well as turn on the 'perfect
1766 * match' filter where we store the station address, otherwise
1767 * we won't receive unicasts meant for this host.
1769 if (sc->sis_type == SIS_TYPE_83815) {
1770 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_ARP);
1771 SIS_SETBIT(sc, SIS_RXFILT_CTL, NS_RXFILTCTL_PERFECT);
1774 /* If we want promiscuous mode, set the allframes bit. */
1775 if (ifp->if_flags & IFF_PROMISC)
1776 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1778 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ALLPHYS);
1781 * Set the capture broadcast bit to capture broadcast frames.
1783 if (ifp->if_flags & IFF_BROADCAST)
1784 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1786 SIS_CLRBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_BROAD);
1789 * Load the multicast filter.
1791 if (sc->sis_type == SIS_TYPE_83815)
1792 sis_setmulti_ns(sc);
1794 sis_setmulti_sis(sc);
1796 /* Turn the receive filter on */
1797 SIS_SETBIT(sc, SIS_RXFILT_CTL, SIS_RXFILTCTL_ENABLE);
1800 * Load the address of the RX and TX lists.
1802 CSR_WRITE_4(sc, SIS_RX_LISTPTR,
1803 vtophys(&sc->sis_ldata->sis_rx_list[0]));
1804 CSR_WRITE_4(sc, SIS_TX_LISTPTR,
1805 vtophys(&sc->sis_ldata->sis_tx_list[0]));
1807 /* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
1808 * the PCI bus. When this bit is set, the Max DMA Burst Size
1809 * for TX/RX DMA should be no larger than 16 double words.
1811 if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)
1812 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
1814 CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
1816 /* Accept Long Packets for VLAN support */
1817 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
1819 /* Set TX configuration */
1820 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
1821 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
1823 CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
1825 /* Set full/half duplex mode. */
1826 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1827 SIS_SETBIT(sc, SIS_TX_CFG,
1828 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1829 SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1831 SIS_CLRBIT(sc, SIS_TX_CFG,
1832 (SIS_TXCFG_IGN_HBEAT|SIS_TXCFG_IGN_CARR));
1833 SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
1837 * Enable interrupts.
1839 CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
1840 #ifdef DEVICE_POLLING
1842 * ... only enable interrupts if we are not polling, make sure
1843 * they are off otherwise.
1845 if (ifp->if_ipending & IFF_POLLING)
1846 CSR_WRITE_4(sc, SIS_IER, 0);
1848 #endif /* DEVICE_POLLING */
1849 CSR_WRITE_4(sc, SIS_IER, 1);
1851 /* Enable receiver and transmitter. */
1852 SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
1853 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
1860 * Page 75 of the DP83815 manual recommends the
1861 * following register settings "for optimum
1862 * performance." Note however that at least three
1863 * of the registers are listed as "reserved" in
1864 * the register map, so who knows what they do.
1866 if (sc->sis_type == SIS_TYPE_83815) {
1867 CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
1868 CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
1869 CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
1870 CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
1871 CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
1874 ifp->if_flags |= IFF_RUNNING;
1875 ifp->if_flags &= ~IFF_OACTIVE;
1879 sc->sis_stat_ch = timeout(sis_tick, sc, hz);
1883 * Set media options.
1886 sis_ifmedia_upd(struct ifnet *ifp)
1888 struct sis_softc *sc;
1889 struct mii_data *mii;
1893 mii = device_get_softc(sc->sis_miibus);
1895 if (mii->mii_instance) {
1896 struct mii_softc *miisc;
1897 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1898 mii_phy_reset(miisc);
1906 * Report current media status.
1909 sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1911 struct sis_softc *sc;
1912 struct mii_data *mii;
1916 mii = device_get_softc(sc->sis_miibus);
1918 ifmr->ifm_active = mii->mii_media_active;
1919 ifmr->ifm_status = mii->mii_media_status;
1923 sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1925 struct sis_softc *sc = ifp->if_softc;
1926 struct ifreq *ifr = (struct ifreq *) data;
1927 struct mii_data *mii;
1936 error = ether_ioctl(ifp, command, data);
1939 if (ifp->if_flags & IFF_UP) {
1942 if (ifp->if_flags & IFF_RUNNING)
1949 if (sc->sis_type == SIS_TYPE_83815)
1950 sis_setmulti_ns(sc);
1952 sis_setmulti_sis(sc);
1957 mii = device_get_softc(sc->sis_miibus);
1958 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1971 sis_watchdog(struct ifnet *ifp)
1973 struct sis_softc *sc;
1978 printf("sis%d: watchdog timeout\n", sc->sis_unit);
1984 if (ifp->if_snd.ifq_head != NULL)
1989 * Stop the adapter and free any mbufs allocated to the
1993 sis_stop(struct sis_softc *sc)
1998 ifp = &sc->arpcom.ac_if;
2001 untimeout(sis_tick, sc, sc->sis_stat_ch);
2003 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2004 #ifdef DEVICE_POLLING
2005 ether_poll_deregister(ifp);
2007 CSR_WRITE_4(sc, SIS_IER, 0);
2008 CSR_WRITE_4(sc, SIS_IMR, 0);
2009 SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
2011 CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
2012 CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
2017 * Free data in the RX lists.
2019 for (i = 0; i < SIS_RX_LIST_CNT; i++) {
2020 if (sc->sis_ldata->sis_rx_list[i].sis_mbuf != NULL) {
2021 m_freem(sc->sis_ldata->sis_rx_list[i].sis_mbuf);
2022 sc->sis_ldata->sis_rx_list[i].sis_mbuf = NULL;
2025 bzero((char *)&sc->sis_ldata->sis_rx_list,
2026 sizeof(sc->sis_ldata->sis_rx_list));
2029 * Free the TX list buffers.
2031 for (i = 0; i < SIS_TX_LIST_CNT; i++) {
2032 if (sc->sis_ldata->sis_tx_list[i].sis_mbuf != NULL) {
2033 m_freem(sc->sis_ldata->sis_tx_list[i].sis_mbuf);
2034 sc->sis_ldata->sis_tx_list[i].sis_mbuf = NULL;
2038 bzero((char *)&sc->sis_ldata->sis_tx_list,
2039 sizeof(sc->sis_ldata->sis_tx_list));
2043 * Stop all chip I/O so that the kernel's probe routines don't
2044 * get confused by errant DMAs when rebooting.
2047 sis_shutdown(device_t dev)
2049 struct sis_softc *sc;
2051 sc = device_get_softc(dev);