1 /* $FreeBSD: src/sys/dev/ubsec/ubsec.c,v 1.6.2.12 2003/06/04 17:56:59 sam Exp $ */
2 /* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */
5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Jason L. Wright
22 * 4. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
28 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
33 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
34 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
37 * Effort sponsored in part by the Defense Advanced Research Projects
38 * Agency (DARPA) and Air Force Research Laboratory, Air Force
39 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
44 * uBsec 5[56]01, 58xx hardware crypto accelerator
47 #include "opt_ubsec.h"
49 #include <sys/param.h>
50 #include <sys/systm.h>
52 #include <sys/errno.h>
53 #include <sys/malloc.h>
54 #include <sys/kernel.h>
56 #include <sys/sysctl.h>
57 #include <sys/endian.h>
61 #include <sys/random.h>
62 #include <sys/thread2.h>
67 #include <machine/clock.h>
69 #include <crypto/sha1.h>
70 #include <opencrypto/cryptodev.h>
71 #include <opencrypto/cryptosoft.h>
73 #include "cryptodev_if.h"
75 #include <bus/pci/pcivar.h>
76 #include <bus/pci/pcireg.h>
78 /* grr, #defines for gratuitous incompatibility in queue.h */
79 #define SIMPLEQ_HEAD STAILQ_HEAD
80 #define SIMPLEQ_ENTRY STAILQ_ENTRY
81 #define SIMPLEQ_INIT STAILQ_INIT
82 #define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL
83 #define SIMPLEQ_EMPTY STAILQ_EMPTY
84 #define SIMPLEQ_FIRST STAILQ_FIRST
85 #define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD
86 #define SIMPLEQ_FOREACH STAILQ_FOREACH
87 /* ditto for endian.h */
88 #define letoh16(x) le16toh(x)
89 #define letoh32(x) le32toh(x)
92 #include "../rndtest/rndtest.h"
98 * Prototypes and count for the pci_device structure
100 static int ubsec_probe(device_t);
101 static int ubsec_attach(device_t);
102 static int ubsec_detach(device_t);
103 static int ubsec_suspend(device_t);
104 static int ubsec_resume(device_t);
105 static void ubsec_shutdown(device_t);
106 static void ubsec_intr(void *);
107 static int ubsec_newsession(void *, u_int32_t *, struct cryptoini *);
108 static int ubsec_freesession(void *, u_int64_t);
109 static int ubsec_process(void *, struct cryptop *, int);
110 static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
111 static void ubsec_feed(struct ubsec_softc *);
112 static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
113 static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
114 static int ubsec_feed2(struct ubsec_softc *);
115 static void ubsec_rng(void *);
116 static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
117 struct ubsec_dma_alloc *, int);
118 #define ubsec_dma_sync(_dma, _flags) \
119 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags))
120 static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
121 static int ubsec_dmamap_aligned(struct ubsec_operand *op);
123 static void ubsec_reset_board(struct ubsec_softc *sc);
124 static void ubsec_init_board(struct ubsec_softc *sc);
125 static void ubsec_init_pciregs(device_t dev);
126 static void ubsec_totalreset(struct ubsec_softc *sc);
128 static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q);
130 static int ubsec_kprocess(void*, struct cryptkop *, int);
131 static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int);
132 static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int);
133 static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int);
134 static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
135 static int ubsec_ksigbits(struct crparam *);
136 static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
137 static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
140 static device_method_t ubsec_methods[] = {
141 /* Device interface */
142 DEVMETHOD(device_probe, ubsec_probe),
143 DEVMETHOD(device_attach, ubsec_attach),
144 DEVMETHOD(device_detach, ubsec_detach),
145 DEVMETHOD(device_suspend, ubsec_suspend),
146 DEVMETHOD(device_resume, ubsec_resume),
147 DEVMETHOD(device_shutdown, ubsec_shutdown),
150 DEVMETHOD(bus_print_child, bus_generic_print_child),
151 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
153 /* crypto device methods */
154 DEVMETHOD(cryptodev_newsession, ubsec_newsession),
155 DEVMETHOD(cryptodev_freesession,ubsec_freesession),
156 DEVMETHOD(cryptodev_process, ubsec_process),
157 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess),
161 static driver_t ubsec_driver = {
164 sizeof (struct ubsec_softc)
166 static devclass_t ubsec_devclass;
168 DECLARE_DUMMY_MODULE(ubsec);
169 DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0);
170 MODULE_DEPEND(ubsec, crypto, 1, 1, 1);
172 MODULE_DEPEND(ubsec, rndtest, 1, 1, 1);
175 SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, "Broadcom driver parameters");
178 static void ubsec_dump_pb(volatile struct ubsec_pktbuf *);
179 static void ubsec_dump_mcr(struct ubsec_mcr *);
180 static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
182 static int ubsec_debug = 0;
183 SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug,
184 0, "control debugging msgs");
187 #define READ_REG(sc,r) \
188 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
190 #define WRITE_REG(sc,reg,val) \
191 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
193 #define SWAP32(x) (x) = htole32(ntohl((x)))
194 #define HTOLE32(x) (x) = htole32(x)
197 struct ubsec_stats ubsecstats;
198 SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats,
199 ubsec_stats, "driver statistics");
202 ubsec_probe(device_t dev)
204 if (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
205 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 ||
206 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K))
208 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
209 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 ||
210 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601))
212 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
213 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 ||
214 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
215 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 ||
216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 ||
217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823
226 ubsec_partname(struct ubsec_softc *sc)
228 /* XXX sprintf numbers when not decoded */
229 switch (pci_get_vendor(sc->sc_dev)) {
230 case PCI_VENDOR_BROADCOM:
231 switch (pci_get_device(sc->sc_dev)) {
232 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801";
233 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802";
234 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805";
235 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820";
236 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821";
237 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822";
238 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823";
240 return "Broadcom unknown-part";
241 case PCI_VENDOR_BLUESTEEL:
242 switch (pci_get_device(sc->sc_dev)) {
243 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601";
245 return "Bluesteel unknown-part";
247 switch (pci_get_device(sc->sc_dev)) {
248 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821";
249 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K";
251 return "Sun unknown-part";
253 return "Unknown-vendor unknown-part";
257 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
259 u_int32_t *p = (u_int32_t *)buf;
260 for (count /= sizeof (u_int32_t); count; count--)
261 add_true_randomness(*p++);
265 ubsec_attach(device_t dev)
267 struct ubsec_softc *sc = device_get_softc(dev);
268 struct ubsec_dma *dmap;
272 KASSERT(sc != NULL, ("ubsec_attach: null software carrier!"));
273 bzero(sc, sizeof (*sc));
276 SIMPLEQ_INIT(&sc->sc_queue);
277 SIMPLEQ_INIT(&sc->sc_qchip);
278 SIMPLEQ_INIT(&sc->sc_queue2);
279 SIMPLEQ_INIT(&sc->sc_qchip2);
280 SIMPLEQ_INIT(&sc->sc_q2free);
282 /* XXX handle power management */
284 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
286 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL &&
287 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)
288 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
290 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
291 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 ||
292 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805))
293 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
295 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
296 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820)
297 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
298 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
300 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM &&
301 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 ||
302 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 ||
303 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823)) ||
304 (pci_get_vendor(dev) == PCI_VENDOR_SUN &&
305 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K ||
306 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) {
307 /* NB: the 5821/5822 defines some additional status bits */
308 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
309 BS_STAT_MCR2_ALLEMPTY;
310 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
311 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
314 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
315 cmd |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
316 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
317 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
319 if (!(cmd & PCIM_CMD_MEMEN)) {
320 device_printf(dev, "failed to enable memory mapping\n");
324 if (!(cmd & PCIM_CMD_BUSMASTEREN)) {
325 device_printf(dev, "failed to enable bus mastering\n");
330 * Setup memory-mapping of PCI registers.
333 sc->sc_sr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
334 0, ~0, 1, RF_ACTIVE);
335 if (sc->sc_sr == NULL) {
336 device_printf(dev, "cannot map register space\n");
339 sc->sc_st = rman_get_bustag(sc->sc_sr);
340 sc->sc_sh = rman_get_bushandle(sc->sc_sr);
343 * Arrange interrupt line.
346 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
347 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
348 if (sc->sc_irq == NULL) {
349 device_printf(dev, "could not map interrupt\n");
353 * NB: Network code assumes we are blocked with splimp()
354 * so make sure the IRQ is mapped appropriately.
356 if (bus_setup_intr(dev, sc->sc_irq, 0,
359 device_printf(dev, "could not establish interrupt\n");
363 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
364 if (sc->sc_cid < 0) {
365 device_printf(dev, "could not get crypto driver id\n");
370 * Setup DMA descriptor area.
372 if (bus_dma_tag_create(NULL, /* parent */
373 1, 0, /* alignment, bounds */
374 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
375 BUS_SPACE_MAXADDR, /* highaddr */
376 NULL, NULL, /* filter, filterarg */
377 0x3ffff, /* maxsize */
378 UBS_MAX_SCATTER, /* nsegments */
379 0xffff, /* maxsegsize */
380 BUS_DMA_ALLOCNOW, /* flags */
382 device_printf(dev, "cannot allocate DMA tag\n");
385 SIMPLEQ_INIT(&sc->sc_freequeue);
387 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
390 q = kmalloc(sizeof(struct ubsec_q), M_DEVBUF, M_WAITOK);
391 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
392 &dmap->d_alloc, 0)) {
393 device_printf(dev, "cannot allocate dma buffers\n");
397 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
400 sc->sc_queuea[i] = q;
402 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
405 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc));
407 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
408 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
409 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
410 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
413 * Reset Broadcom chip
415 ubsec_reset_board(sc);
418 * Init Broadcom specific PCI settings
420 ubsec_init_pciregs(dev);
425 ubsec_init_board(sc);
428 if (sc->sc_flags & UBS_FLAGS_RNG) {
429 sc->sc_statmask |= BS_STAT_MCR2_DONE;
431 sc->sc_rndtest = rndtest_attach(dev);
433 sc->sc_harvest = rndtest_harvest;
435 sc->sc_harvest = default_harvest;
437 sc->sc_harvest = default_harvest;
440 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
441 &sc->sc_rng.rng_q.q_mcr, 0))
444 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
445 &sc->sc_rng.rng_q.q_ctx, 0)) {
446 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
450 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
451 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
452 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
453 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
458 sc->sc_rnghz = hz / 100;
461 callout_init(&sc->sc_rngto);
462 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
466 #endif /* UBSEC_NO_RNG */
468 if (sc->sc_flags & UBS_FLAGS_KEY) {
469 sc->sc_statmask |= BS_STAT_MCR2_DONE;
471 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0);
473 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0);
478 crypto_unregister_all(sc->sc_cid);
480 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
482 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
484 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
490 * Detach a device that successfully probed.
493 ubsec_detach(device_t dev)
495 struct ubsec_softc *sc = device_get_softc(dev);
497 KASSERT(sc != NULL, ("ubsec_detach: null software carrier"));
499 /* XXX wait/abort active ops */
503 callout_stop(&sc->sc_rngto);
505 crypto_unregister_all(sc->sc_cid);
509 rndtest_detach(sc->sc_rndtest);
512 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
515 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
516 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
517 ubsec_dma_free(sc, &q->q_dma->d_alloc);
521 if (sc->sc_flags & UBS_FLAGS_RNG) {
522 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
523 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
524 ubsec_dma_free(sc, &sc->sc_rng.rng_buf);
526 #endif /* UBSEC_NO_RNG */
528 bus_generic_detach(dev);
529 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih);
530 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
532 bus_dma_tag_destroy(sc->sc_dmat);
533 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr);
541 * Stop all chip i/o so that the kernel's probe routines don't
542 * get confused by errant DMAs when rebooting.
545 ubsec_shutdown(device_t dev)
548 ubsec_stop(device_get_softc(dev));
553 * Device suspend routine.
556 ubsec_suspend(device_t dev)
558 struct ubsec_softc *sc = device_get_softc(dev);
560 KASSERT(sc != NULL, ("ubsec_suspend: null software carrier"));
562 /* XXX stop the device and save PCI settings */
564 sc->sc_suspended = 1;
570 ubsec_resume(device_t dev)
572 struct ubsec_softc *sc = device_get_softc(dev);
574 KASSERT(sc != NULL, ("ubsec_resume: null software carrier"));
576 /* XXX retore PCI settings and start the device */
578 sc->sc_suspended = 0;
583 * UBSEC Interrupt routine
586 ubsec_intr(void *arg)
588 struct ubsec_softc *sc = arg;
589 volatile u_int32_t stat;
591 struct ubsec_dma *dmap;
594 stat = READ_REG(sc, BS_STAT);
595 stat &= sc->sc_statmask;
600 WRITE_REG(sc, BS_STAT, stat); /* IACK */
603 * Check to see if we have any packets waiting for us
605 if ((stat & BS_STAT_MCR1_DONE)) {
606 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
607 q = SIMPLEQ_FIRST(&sc->sc_qchip);
610 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
613 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
615 npkts = q->q_nstacked_mcrs;
616 sc->sc_nqchip -= 1+npkts;
618 * search for further sc_qchip ubsec_q's that share
619 * the same MCR, and complete them too, they must be
622 for (i = 0; i < npkts; i++) {
623 if(q->q_stacked_mcr[i]) {
624 ubsec_callback(sc, q->q_stacked_mcr[i]);
629 ubsec_callback(sc, q);
633 * Don't send any more packet to chip if there has been
636 if (!(stat & BS_STAT_DMAERR))
641 * Check to see if we have any key setups/rng's waiting for us
643 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
644 (stat & BS_STAT_MCR2_DONE)) {
646 struct ubsec_mcr *mcr;
648 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
649 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
651 ubsec_dma_sync(&q2->q_mcr,
652 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
654 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
655 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
656 ubsec_dma_sync(&q2->q_mcr,
657 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
660 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
661 ubsec_callback2(sc, q2);
663 * Don't send any more packet to chip if there has been
666 if (!(stat & BS_STAT_DMAERR))
672 * Check to see if we got any DMA Error
674 if (stat & BS_STAT_DMAERR) {
677 volatile u_int32_t a = READ_REG(sc, BS_ERR);
679 kprintf("dmaerr %s@%08x\n",
680 (a & BS_ERR_READ) ? "read" : "write",
683 #endif /* UBSEC_DEBUG */
684 ubsecstats.hst_dmaerr++;
685 ubsec_totalreset(sc);
689 if (sc->sc_needwakeup) { /* XXX check high watermark */
690 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
693 device_printf(sc->sc_dev, "wakeup crypto (%x)\n",
695 #endif /* UBSEC_DEBUG */
696 sc->sc_needwakeup &= ~wakeup;
697 crypto_unblock(sc->sc_cid, wakeup);
702 * ubsec_feed() - aggregate and post requests to chip
705 ubsec_feed(struct ubsec_softc *sc)
707 struct ubsec_q *q, *q2;
713 * Decide how many ops to combine in a single MCR. We cannot
714 * aggregate more than UBS_MAX_AGGR because this is the number
715 * of slots defined in the data structure. Note that
716 * aggregation only happens if ops are marked batch'able.
717 * Aggregating ops reduces the number of interrupts to the host
718 * but also (potentially) increases the latency for processing
719 * completed ops as we only get an interrupt when all aggregated
720 * ops have completed.
722 if (sc->sc_nqueue == 0)
724 if (sc->sc_nqueue > 1) {
726 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) {
728 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0)
734 * Check device status before going any further.
736 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
737 if (stat & BS_STAT_DMAERR) {
738 ubsec_totalreset(sc);
739 ubsecstats.hst_dmaerr++;
741 ubsecstats.hst_mcr1full++;
744 if (sc->sc_nqueue > ubsecstats.hst_maxqueue)
745 ubsecstats.hst_maxqueue = sc->sc_nqueue;
746 if (npkts > UBS_MAX_AGGR)
747 npkts = UBS_MAX_AGGR;
748 if (npkts < 2) /* special case 1 op */
751 ubsecstats.hst_totbatch += npkts-1;
754 kprintf("merging %d records\n", npkts);
755 #endif /* UBSEC_DEBUG */
757 q = SIMPLEQ_FIRST(&sc->sc_queue);
758 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
761 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
762 if (q->q_dst_map != NULL)
763 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
765 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
767 for (i = 0; i < q->q_nstacked_mcrs; i++) {
768 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
769 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
770 BUS_DMASYNC_PREWRITE);
771 if (q2->q_dst_map != NULL)
772 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
773 BUS_DMASYNC_PREREAD);
774 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
777 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
778 sizeof(struct ubsec_mcr_add));
779 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
780 q->q_stacked_mcr[i] = q2;
782 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
783 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
784 sc->sc_nqchip += npkts;
785 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
786 ubsecstats.hst_maxqchip = sc->sc_nqchip;
787 ubsec_dma_sync(&q->q_dma->d_alloc,
788 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
789 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
790 offsetof(struct ubsec_dmachunk, d_mcr));
794 q = SIMPLEQ_FIRST(&sc->sc_queue);
796 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE);
797 if (q->q_dst_map != NULL)
798 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD);
799 ubsec_dma_sync(&q->q_dma->d_alloc,
800 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
802 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
803 offsetof(struct ubsec_dmachunk, d_mcr));
806 kprintf("feed1: q->chip %p %08x stat %08x\n",
807 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr),
809 #endif /* UBSEC_DEBUG */
810 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
812 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
814 if (sc->sc_nqchip > ubsecstats.hst_maxqchip)
815 ubsecstats.hst_maxqchip = sc->sc_nqchip;
820 ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key)
823 /* Go ahead and compute key in ubsec's byte order */
824 if (algo == CRYPTO_DES_CBC) {
825 bcopy(key, &ses->ses_deskey[0], 8);
826 bcopy(key, &ses->ses_deskey[2], 8);
827 bcopy(key, &ses->ses_deskey[4], 8);
829 bcopy(key, ses->ses_deskey, 24);
831 SWAP32(ses->ses_deskey[0]);
832 SWAP32(ses->ses_deskey[1]);
833 SWAP32(ses->ses_deskey[2]);
834 SWAP32(ses->ses_deskey[3]);
835 SWAP32(ses->ses_deskey[4]);
836 SWAP32(ses->ses_deskey[5]);
840 ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen)
846 for (i = 0; i < klen; i++)
847 key[i] ^= HMAC_IPAD_VAL;
849 if (algo == CRYPTO_MD5_HMAC) {
851 MD5Update(&md5ctx, key, klen);
852 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_HMAC_BLOCK_LEN - klen);
853 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state));
856 SHA1Update(&sha1ctx, key, klen);
857 SHA1Update(&sha1ctx, hmac_ipad_buffer,
858 SHA1_HMAC_BLOCK_LEN - klen);
859 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32));
862 for (i = 0; i < klen; i++)
863 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
865 if (algo == CRYPTO_MD5_HMAC) {
867 MD5Update(&md5ctx, key, klen);
868 MD5Update(&md5ctx, hmac_opad_buffer, MD5_HMAC_BLOCK_LEN - klen);
869 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state));
872 SHA1Update(&sha1ctx, key, klen);
873 SHA1Update(&sha1ctx, hmac_opad_buffer,
874 SHA1_HMAC_BLOCK_LEN - klen);
875 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32));
878 for (i = 0; i < klen; i++)
879 key[i] ^= HMAC_OPAD_VAL;
883 * Allocate a new 'session' and return an encoded session id. 'sidp'
884 * contains our registration id, and should contain an encoded session
885 * id on successful allocation.
888 ubsec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
890 struct cryptoini *c, *encini = NULL, *macini = NULL;
891 struct ubsec_softc *sc = arg;
892 struct ubsec_session *ses = NULL;
900 KASSERT(sc != NULL, ("ubsec_newsession: null softc"));
901 if (sidp == NULL || cri == NULL || sc == NULL)
904 for (c = cri; c != NULL; c = c->cri_next) {
905 if (c->cri_alg == CRYPTO_MD5_HMAC ||
906 c->cri_alg == CRYPTO_SHA1_HMAC) {
910 } else if (c->cri_alg == CRYPTO_DES_CBC ||
911 c->cri_alg == CRYPTO_3DES_CBC) {
918 if (encini == NULL && macini == NULL)
921 if (sc->sc_sessions == NULL) {
922 ses = sc->sc_sessions = kmalloc(sizeof(struct ubsec_session),
923 M_DEVBUF, M_INTWAIT);
925 sc->sc_nsessions = 1;
927 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
928 if (sc->sc_sessions[sesn].ses_used == 0) {
929 ses = &sc->sc_sessions[sesn];
935 sesn = sc->sc_nsessions;
936 ses = kmalloc((sesn + 1) * sizeof(struct ubsec_session),
937 M_DEVBUF, M_INTWAIT);
938 bcopy(sc->sc_sessions, ses, sesn *
939 sizeof(struct ubsec_session));
940 bzero(sc->sc_sessions, sesn *
941 sizeof(struct ubsec_session));
942 kfree(sc->sc_sessions, M_DEVBUF);
943 sc->sc_sessions = ses;
944 ses = &sc->sc_sessions[sesn];
949 bzero(ses, sizeof(struct ubsec_session));
952 read_random(ses->ses_iv, sizeof(ses->ses_iv));
953 if (encini->cri_key != NULL) {
954 ubsec_setup_enckey(ses, encini->cri_alg,
958 /* get an IV, network byte order */
959 /* XXX may read fewer than requested */
960 read_random(ses->ses_iv, sizeof(ses->ses_iv));
962 /* Go ahead and compute key in ubsec's byte order */
963 if (encini->cri_alg == CRYPTO_DES_CBC) {
964 bcopy(encini->cri_key, &ses->ses_deskey[0], 8);
965 bcopy(encini->cri_key, &ses->ses_deskey[2], 8);
966 bcopy(encini->cri_key, &ses->ses_deskey[4], 8);
968 bcopy(encini->cri_key, ses->ses_deskey, 24);
970 SWAP32(ses->ses_deskey[0]);
971 SWAP32(ses->ses_deskey[1]);
972 SWAP32(ses->ses_deskey[2]);
973 SWAP32(ses->ses_deskey[3]);
974 SWAP32(ses->ses_deskey[4]);
975 SWAP32(ses->ses_deskey[5]);
980 ses->ses_mlen = macini->cri_mlen;
981 if (ses->ses_mlen == 0) {
982 if (macini->cri_alg == CRYPTO_MD5_HMAC)
983 ses->ses_mlen = MD5_HASH_LEN;
985 ses->ses_mlen = SHA1_HASH_LEN;
988 if (macini->cri_key != NULL) {
989 ubsec_setup_mackey(ses, macini->cri_alg,
990 macini->cri_key, macini->cri_klen/8);
993 for (i = 0; i < macini->cri_klen / 8; i++)
994 macini->cri_key[i] ^= HMAC_IPAD_VAL;
996 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
998 MD5Update(&md5ctx, macini->cri_key,
999 macini->cri_klen / 8);
1000 MD5Update(&md5ctx, hmac_ipad_buffer,
1001 MD5_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1002 bcopy(md5ctx.state, ses->ses_hminner,
1003 sizeof(md5ctx.state));
1006 SHA1Update(&sha1ctx, macini->cri_key,
1007 macini->cri_klen / 8);
1008 SHA1Update(&sha1ctx, hmac_ipad_buffer,
1009 SHA1_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1010 bcopy(sha1ctx.h.b32, ses->ses_hminner,
1011 sizeof(sha1ctx.h.b32));
1014 for (i = 0; i < macini->cri_klen / 8; i++)
1015 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
1017 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
1019 MD5Update(&md5ctx, macini->cri_key,
1020 macini->cri_klen / 8);
1021 MD5Update(&md5ctx, hmac_opad_buffer,
1022 MD5_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1023 bcopy(md5ctx.state, ses->ses_hmouter,
1024 sizeof(md5ctx.state));
1027 SHA1Update(&sha1ctx, macini->cri_key,
1028 macini->cri_klen / 8);
1029 SHA1Update(&sha1ctx, hmac_opad_buffer,
1030 SHA1_HMAC_BLOCK_LEN - (macini->cri_klen / 8));
1031 bcopy(sha1ctx.h.b32, ses->ses_hmouter,
1032 sizeof(sha1ctx.h.b32));
1035 for (i = 0; i < macini->cri_klen / 8; i++)
1036 macini->cri_key[i] ^= HMAC_OPAD_VAL;
1040 *sidp = UBSEC_SID(device_get_unit(sc->sc_dev), sesn);
1045 * Deallocate a session.
1048 ubsec_freesession(void *arg, u_int64_t tid)
1050 struct ubsec_softc *sc = arg;
1052 u_int32_t sid = ((u_int32_t) tid) & 0xffffffff;
1054 KASSERT(sc != NULL, ("ubsec_freesession: null softc"));
1058 session = UBSEC_SESSION(sid);
1059 if (session >= sc->sc_nsessions)
1062 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
1067 ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1069 struct ubsec_operand *op = arg;
1071 KASSERT(nsegs <= UBS_MAX_SCATTER,
1072 ("Too many DMA segments returned when mapping operand"));
1075 kprintf("ubsec_op_cb: mapsize %u nsegs %d\n",
1076 (u_int) mapsize, nsegs);
1078 op->mapsize = mapsize;
1080 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1084 ubsec_process(void *arg, struct cryptop *crp, int hint)
1086 struct ubsec_q *q = NULL;
1087 int err = 0, i, j, nicealign;
1088 struct ubsec_softc *sc = arg;
1089 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
1090 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
1091 int sskip, dskip, stheend, dtheend;
1093 struct ubsec_session *ses;
1094 struct ubsec_pktctx ctx;
1095 struct ubsec_dma *dmap = NULL;
1097 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) {
1098 ubsecstats.hst_invalid++;
1101 if (UBSEC_SESSION(crp->crp_sid) >= sc->sc_nsessions) {
1102 ubsecstats.hst_badsession++;
1108 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
1109 ubsecstats.hst_queuefull++;
1110 sc->sc_needwakeup |= CRYPTO_SYMQ;
1114 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
1115 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
1118 dmap = q->q_dma; /* Save dma pointer */
1119 bzero(q, sizeof(struct ubsec_q));
1120 bzero(&ctx, sizeof(ctx));
1122 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
1124 ses = &sc->sc_sessions[q->q_sesn];
1126 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1127 q->q_src_m = (struct mbuf *)crp->crp_buf;
1128 q->q_dst_m = (struct mbuf *)crp->crp_buf;
1129 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1130 q->q_src_io = (struct uio *)crp->crp_buf;
1131 q->q_dst_io = (struct uio *)crp->crp_buf;
1133 ubsecstats.hst_badflags++;
1135 goto errout; /* XXX we don't handle contiguous blocks! */
1138 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
1140 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
1141 dmap->d_dma->d_mcr.mcr_flags = 0;
1144 crd1 = crp->crp_desc;
1146 ubsecstats.hst_nodesc++;
1150 crd2 = crd1->crd_next;
1153 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
1154 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
1157 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
1158 crd1->crd_alg == CRYPTO_3DES_CBC) {
1162 ubsecstats.hst_badalg++;
1167 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
1168 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
1169 (crd2->crd_alg == CRYPTO_DES_CBC ||
1170 crd2->crd_alg == CRYPTO_3DES_CBC) &&
1171 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
1174 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
1175 crd1->crd_alg == CRYPTO_3DES_CBC) &&
1176 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
1177 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
1178 (crd1->crd_flags & CRD_F_ENCRYPT)) {
1183 * We cannot order the ubsec as requested
1185 ubsecstats.hst_badalg++;
1192 encoffset = enccrd->crd_skip;
1193 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
1195 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
1196 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
1198 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1199 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1201 ctx.pc_iv[0] = ses->ses_iv[0];
1202 ctx.pc_iv[1] = ses->ses_iv[1];
1205 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
1206 if (crp->crp_flags & CRYPTO_F_IMBUF)
1207 m_copyback(q->q_src_m,
1209 8, (caddr_t)ctx.pc_iv);
1210 else if (crp->crp_flags & CRYPTO_F_IOV)
1211 cuio_copyback(q->q_src_io,
1213 8, (caddr_t)ctx.pc_iv);
1216 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
1218 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
1219 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
1220 else if (crp->crp_flags & CRYPTO_F_IMBUF)
1221 m_copydata(q->q_src_m, enccrd->crd_inject,
1222 8, (caddr_t)ctx.pc_iv);
1223 else if (crp->crp_flags & CRYPTO_F_IOV)
1224 cuio_copydata(q->q_src_io,
1225 enccrd->crd_inject, 8,
1226 (caddr_t)ctx.pc_iv);
1229 ctx.pc_deskey[0] = ses->ses_deskey[0];
1230 ctx.pc_deskey[1] = ses->ses_deskey[1];
1231 ctx.pc_deskey[2] = ses->ses_deskey[2];
1232 ctx.pc_deskey[3] = ses->ses_deskey[3];
1233 ctx.pc_deskey[4] = ses->ses_deskey[4];
1234 ctx.pc_deskey[5] = ses->ses_deskey[5];
1235 SWAP32(ctx.pc_iv[0]);
1236 SWAP32(ctx.pc_iv[1]);
1240 macoffset = maccrd->crd_skip;
1242 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
1243 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
1245 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
1247 for (i = 0; i < 5; i++) {
1248 ctx.pc_hminner[i] = ses->ses_hminner[i];
1249 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
1251 HTOLE32(ctx.pc_hminner[i]);
1252 HTOLE32(ctx.pc_hmouter[i]);
1256 if (enccrd && maccrd) {
1258 * ubsec cannot handle packets where the end of encryption
1259 * and authentication are not the same, or where the
1260 * encrypted part begins before the authenticated part.
1262 if ((encoffset + enccrd->crd_len) !=
1263 (macoffset + maccrd->crd_len)) {
1264 ubsecstats.hst_lenmismatch++;
1268 if (enccrd->crd_skip < maccrd->crd_skip) {
1269 ubsecstats.hst_skipmismatch++;
1273 sskip = maccrd->crd_skip;
1274 cpskip = dskip = enccrd->crd_skip;
1275 stheend = maccrd->crd_len;
1276 dtheend = enccrd->crd_len;
1277 coffset = enccrd->crd_skip - maccrd->crd_skip;
1278 cpoffset = cpskip + dtheend;
1281 kprintf("mac: skip %d, len %d, inject %d\n",
1282 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
1283 kprintf("enc: skip %d, len %d, inject %d\n",
1284 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
1285 kprintf("src: skip %d, len %d\n", sskip, stheend);
1286 kprintf("dst: skip %d, len %d\n", dskip, dtheend);
1287 kprintf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
1288 coffset, stheend, cpskip, cpoffset);
1292 cpskip = dskip = sskip = macoffset + encoffset;
1293 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
1294 cpoffset = cpskip + dtheend;
1297 ctx.pc_offset = htole16(coffset >> 2);
1299 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) {
1300 ubsecstats.hst_nomap++;
1304 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1305 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
1306 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1307 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1308 q->q_src_map = NULL;
1309 ubsecstats.hst_noload++;
1313 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1314 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
1315 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) {
1316 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1317 q->q_src_map = NULL;
1318 ubsecstats.hst_noload++;
1323 nicealign = ubsec_dmamap_aligned(&q->q_src);
1325 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
1329 kprintf("src skip: %d nicealign: %u\n", sskip, nicealign);
1331 for (i = j = 0; i < q->q_src_nsegs; i++) {
1332 struct ubsec_pktbuf *pb;
1333 bus_size_t packl = q->q_src_segs[i].ds_len;
1334 bus_addr_t packp = q->q_src_segs[i].ds_addr;
1336 if (sskip >= packl) {
1345 if (packl > 0xfffc) {
1351 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
1353 pb = &dmap->d_dma->d_sbuf[j - 1];
1355 pb->pb_addr = htole32(packp);
1358 if (packl > stheend) {
1359 pb->pb_len = htole32(stheend);
1362 pb->pb_len = htole32(packl);
1366 pb->pb_len = htole32(packl);
1368 if ((i + 1) == q->q_src_nsegs)
1371 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1372 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1376 if (enccrd == NULL && maccrd != NULL) {
1377 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1378 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1379 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr +
1380 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1383 kprintf("opkt: %x %x %x\n",
1384 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1385 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1386 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1389 if (crp->crp_flags & CRYPTO_F_IOV) {
1391 ubsecstats.hst_iovmisaligned++;
1395 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
1397 ubsecstats.hst_nomap++;
1401 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1402 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) {
1403 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1404 q->q_dst_map = NULL;
1405 ubsecstats.hst_noload++;
1409 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1411 q->q_dst = q->q_src;
1414 struct mbuf *m, *top, **mp;
1416 ubsecstats.hst_unaligned++;
1417 totlen = q->q_src_mapsize;
1418 if (q->q_src_m->m_flags & M_PKTHDR) {
1420 MGETHDR(m, MB_DONTWAIT, MT_DATA);
1421 if (m && !m_dup_pkthdr(m, q->q_src_m, MB_DONTWAIT)) {
1427 MGET(m, MB_DONTWAIT, MT_DATA);
1430 ubsecstats.hst_nombuf++;
1431 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1434 if (totlen >= MINCLSIZE) {
1435 MCLGET(m, MB_DONTWAIT);
1436 if ((m->m_flags & M_EXT) == 0) {
1438 ubsecstats.hst_nomcl++;
1439 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1448 while (totlen > 0) {
1450 MGET(m, MB_DONTWAIT, MT_DATA);
1453 ubsecstats.hst_nombuf++;
1454 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1459 if (top && totlen >= MINCLSIZE) {
1460 MCLGET(m, MB_DONTWAIT);
1461 if ((m->m_flags & M_EXT) == 0) {
1464 ubsecstats.hst_nomcl++;
1465 err = sc->sc_nqueue ? ERESTART : ENOMEM;
1470 m->m_len = len = min(totlen, len);
1476 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1478 if (bus_dmamap_create(sc->sc_dmat,
1479 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) {
1480 ubsecstats.hst_nomap++;
1484 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1485 q->q_dst_map, q->q_dst_m,
1486 ubsec_op_cb, &q->q_dst,
1487 BUS_DMA_NOWAIT) != 0) {
1488 bus_dmamap_destroy(sc->sc_dmat,
1490 q->q_dst_map = NULL;
1491 ubsecstats.hst_noload++;
1497 ubsecstats.hst_badflags++;
1504 kprintf("dst skip: %d\n", dskip);
1506 for (i = j = 0; i < q->q_dst_nsegs; i++) {
1507 struct ubsec_pktbuf *pb;
1508 bus_size_t packl = q->q_dst_segs[i].ds_len;
1509 bus_addr_t packp = q->q_dst_segs[i].ds_addr;
1511 if (dskip >= packl) {
1520 if (packl > 0xfffc) {
1526 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1528 pb = &dmap->d_dma->d_dbuf[j - 1];
1530 pb->pb_addr = htole32(packp);
1533 if (packl > dtheend) {
1534 pb->pb_len = htole32(dtheend);
1537 pb->pb_len = htole32(packl);
1541 pb->pb_len = htole32(packl);
1543 if ((i + 1) == q->q_dst_nsegs) {
1545 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1546 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1550 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1551 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1556 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1557 offsetof(struct ubsec_dmachunk, d_ctx));
1559 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1560 struct ubsec_pktctx_long *ctxl;
1562 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1563 offsetof(struct ubsec_dmachunk, d_ctx));
1565 /* transform small context into long context */
1566 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1567 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1568 ctxl->pc_flags = ctx.pc_flags;
1569 ctxl->pc_offset = ctx.pc_offset;
1570 for (i = 0; i < 6; i++)
1571 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1572 for (i = 0; i < 5; i++)
1573 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1574 for (i = 0; i < 5; i++)
1575 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1576 ctxl->pc_iv[0] = ctx.pc_iv[0];
1577 ctxl->pc_iv[1] = ctx.pc_iv[1];
1579 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1580 offsetof(struct ubsec_dmachunk, d_ctx),
1581 sizeof(struct ubsec_pktctx));
1584 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1586 ubsecstats.hst_ipackets++;
1587 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size;
1588 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR)
1595 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1596 m_freem(q->q_dst_m);
1598 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1599 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1600 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1602 if (q->q_src_map != NULL) {
1603 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1604 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1608 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1611 if (err != ERESTART) {
1612 crp->crp_etype = err;
1615 sc->sc_needwakeup |= CRYPTO_SYMQ;
1621 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1623 struct cryptop *crp = (struct cryptop *)q->q_crp;
1624 struct cryptodesc *crd;
1625 struct ubsec_dma *dmap = q->q_dma;
1627 ubsecstats.hst_opackets++;
1628 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1630 ubsec_dma_sync(&dmap->d_alloc,
1631 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1632 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1633 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1634 BUS_DMASYNC_POSTREAD);
1635 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1636 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1638 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE);
1639 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1640 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1642 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1643 m_freem(q->q_src_m);
1644 crp->crp_buf = (caddr_t)q->q_dst_m;
1646 ubsecstats.hst_obytes += ((struct mbuf *)crp->crp_buf)->m_len;
1648 /* copy out IV for future use */
1649 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1650 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1651 if (crd->crd_alg != CRYPTO_DES_CBC &&
1652 crd->crd_alg != CRYPTO_3DES_CBC)
1654 if (crp->crp_flags & CRYPTO_F_IMBUF)
1655 m_copydata((struct mbuf *)crp->crp_buf,
1656 crd->crd_skip + crd->crd_len - 8, 8,
1657 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1658 else if (crp->crp_flags & CRYPTO_F_IOV) {
1659 cuio_copydata((struct uio *)crp->crp_buf,
1660 crd->crd_skip + crd->crd_len - 8, 8,
1661 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1667 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1668 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1669 crd->crd_alg != CRYPTO_SHA1_HMAC)
1671 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject,
1672 sc->sc_sessions[q->q_sesn].ses_mlen,
1673 (caddr_t)dmap->d_dma->d_macbuf);
1675 if (crp->crp_flags & CRYPTO_F_IMBUF)
1676 m_copyback((struct mbuf *)crp->crp_buf,
1677 crd->crd_inject, 12,
1678 (caddr_t)dmap->d_dma->d_macbuf);
1679 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1680 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1685 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1690 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1692 int i, j, dlen, slen;
1696 sptr = srcm->m_data;
1698 dptr = dstm->m_data;
1702 for (i = 0; i < min(slen, dlen); i++) {
1703 if (j < hoffset || j >= toffset)
1710 srcm = srcm->m_next;
1713 sptr = srcm->m_data;
1717 dstm = dstm->m_next;
1720 dptr = dstm->m_data;
1727 * feed the key generator, must be called at splimp() or higher.
1730 ubsec_feed2(struct ubsec_softc *sc)
1734 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1735 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1737 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1739 ubsec_dma_sync(&q->q_mcr,
1740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1741 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE);
1743 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1744 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1746 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1752 * Callback for handling random numbers
1755 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1757 struct cryptkop *krp;
1758 struct ubsec_ctx_keyop *ctx;
1760 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1761 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE);
1763 switch (q->q_type) {
1764 #ifndef UBSEC_NO_RNG
1765 case UBS_CTXOP_RNGBYPASS: {
1766 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1768 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD);
1769 (*sc->sc_harvest)(sc->sc_rndtest,
1770 rng->rng_buf.dma_vaddr,
1771 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t));
1773 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1777 case UBS_CTXOP_MODEXP: {
1778 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1782 rlen = (me->me_modbits + 7) / 8;
1783 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1785 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE);
1786 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE);
1787 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD);
1788 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE);
1791 krp->krp_status = E2BIG;
1793 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1794 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1795 (krp->krp_param[krp->krp_iparams].crp_nbits
1797 bcopy(me->me_C.dma_vaddr,
1798 krp->krp_param[krp->krp_iparams].crp_p,
1799 (me->me_modbits + 7) / 8);
1801 ubsec_kshift_l(me->me_shiftbits,
1802 me->me_C.dma_vaddr, me->me_normbits,
1803 krp->krp_param[krp->krp_iparams].crp_p,
1804 krp->krp_param[krp->krp_iparams].crp_nbits);
1809 /* bzero all potentially sensitive data */
1810 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1811 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1812 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1813 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1815 /* Can't free here, so put us on the free list. */
1816 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1819 case UBS_CTXOP_RSAPRIV: {
1820 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1824 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE);
1825 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD);
1827 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1828 bcopy(rp->rpr_msgout.dma_vaddr,
1829 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1833 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1834 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1835 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1837 /* Can't free here, so put us on the free list. */
1838 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1842 device_printf(sc->sc_dev, "unknown ctx op: %x\n",
1843 letoh16(ctx->ctx_op));
1848 #ifndef UBSEC_NO_RNG
1850 ubsec_rng(void *vsc)
1852 struct ubsec_softc *sc = vsc;
1853 struct ubsec_q2_rng *rng = &sc->sc_rng;
1854 struct ubsec_mcr *mcr;
1855 struct ubsec_ctx_rngbypass *ctx;
1858 if (rng->rng_used) {
1863 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1866 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1867 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1869 mcr->mcr_pkts = htole16(1);
1871 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1872 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1873 mcr->mcr_ipktbuf.pb_len = 0;
1874 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1875 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1876 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1878 mcr->mcr_opktbuf.pb_next = 0;
1880 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1881 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS);
1882 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS;
1884 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD);
1886 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1889 ubsecstats.hst_rng++;
1896 * Something weird happened, generate our own call back.
1900 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc);
1902 #endif /* UBSEC_NO_RNG */
1905 ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1907 bus_addr_t *paddr = (bus_addr_t*) arg;
1908 *paddr = segs->ds_addr;
1913 struct ubsec_softc *sc,
1915 struct ubsec_dma_alloc *dma,
1921 /* XXX could specify sc_dmat as parent but that just adds overhead */
1922 r = bus_dma_tag_create(NULL, /* parent */
1923 1, 0, /* alignment, bounds */
1924 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1925 BUS_SPACE_MAXADDR, /* highaddr */
1926 NULL, NULL, /* filter, filterarg */
1929 size, /* maxsegsize */
1930 BUS_DMA_ALLOCNOW, /* flags */
1933 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1934 "bus_dma_tag_create failed; error %u\n", r);
1938 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
1940 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1941 "bus_dmamap_create failed; error %u\n", r);
1945 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr,
1946 BUS_DMA_NOWAIT, &dma->dma_map);
1948 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1949 "bus_dmammem_alloc failed; size %ju, error %u\n",
1954 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr,
1958 mapflags | BUS_DMA_NOWAIT);
1960 device_printf(sc->sc_dev, "ubsec_dma_malloc: "
1961 "bus_dmamap_load failed; error %u\n", r);
1965 dma->dma_size = size;
1969 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1971 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1973 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1974 bus_dma_tag_destroy(dma->dma_tag);
1976 dma->dma_map = NULL;
1977 dma->dma_tag = NULL;
1982 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1984 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
1985 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
1986 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
1987 bus_dma_tag_destroy(dma->dma_tag);
1991 * Resets the board. Values in the regesters are left as is
1992 * from the reset (i.e. initial values are assigned elsewhere).
1995 ubsec_reset_board(struct ubsec_softc *sc)
1997 volatile u_int32_t ctrl;
1999 ctrl = READ_REG(sc, BS_CTRL);
2000 ctrl |= BS_CTRL_RESET;
2001 WRITE_REG(sc, BS_CTRL, ctrl);
2004 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
2010 * Init Broadcom registers
2013 ubsec_init_board(struct ubsec_softc *sc)
2017 ctrl = READ_REG(sc, BS_CTRL);
2018 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
2019 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
2021 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG))
2022 ctrl |= BS_CTRL_MCR2INT;
2024 ctrl &= ~BS_CTRL_MCR2INT;
2026 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2027 ctrl &= ~BS_CTRL_SWNORM;
2029 WRITE_REG(sc, BS_CTRL, ctrl);
2033 * Init Broadcom PCI registers
2036 ubsec_init_pciregs(device_t dev)
2041 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT);
2042 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT))
2043 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT);
2044 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT))
2045 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT);
2046 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc);
2050 * This will set the cache line size to 1, this will
2051 * force the BCM58xx chip just to do burst read/writes.
2052 * Cache line read/writes are to slow
2054 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1);
2058 * Clean up after a chip crash.
2059 * It is assumed that the caller in splimp()
2062 ubsec_cleanchip(struct ubsec_softc *sc)
2066 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
2067 q = SIMPLEQ_FIRST(&sc->sc_qchip);
2068 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
2069 ubsec_free_q(sc, q);
2076 * It is assumed that the caller is within spimp()
2079 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
2082 struct cryptop *crp;
2086 npkts = q->q_nstacked_mcrs;
2088 for (i = 0; i < npkts; i++) {
2089 if(q->q_stacked_mcr[i]) {
2090 q2 = q->q_stacked_mcr[i];
2092 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
2093 m_freem(q2->q_dst_m);
2095 crp = (struct cryptop *)q2->q_crp;
2097 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
2099 crp->crp_etype = EFAULT;
2109 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
2110 m_freem(q->q_dst_m);
2112 crp = (struct cryptop *)q->q_crp;
2114 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
2116 crp->crp_etype = EFAULT;
2122 * Routine to reset the chip and clean up.
2123 * It is assumed that the caller is in splimp()
2126 ubsec_totalreset(struct ubsec_softc *sc)
2128 ubsec_reset_board(sc);
2129 ubsec_init_board(sc);
2130 ubsec_cleanchip(sc);
2134 ubsec_dmamap_aligned(struct ubsec_operand *op)
2138 for (i = 0; i < op->nsegs; i++) {
2139 if (op->segs[i].ds_addr & 3)
2141 if ((i != (op->nsegs - 1)) &&
2142 (op->segs[i].ds_len & 3))
2149 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
2151 switch (q->q_type) {
2152 case UBS_CTXOP_MODEXP: {
2153 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
2155 ubsec_dma_free(sc, &me->me_q.q_mcr);
2156 ubsec_dma_free(sc, &me->me_q.q_ctx);
2157 ubsec_dma_free(sc, &me->me_M);
2158 ubsec_dma_free(sc, &me->me_E);
2159 ubsec_dma_free(sc, &me->me_C);
2160 ubsec_dma_free(sc, &me->me_epb);
2161 kfree(me, M_DEVBUF);
2164 case UBS_CTXOP_RSAPRIV: {
2165 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
2167 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2168 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
2169 ubsec_dma_free(sc, &rp->rpr_msgin);
2170 ubsec_dma_free(sc, &rp->rpr_msgout);
2171 kfree(rp, M_DEVBUF);
2175 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type);
2181 ubsec_kprocess(void *arg, struct cryptkop *krp, int hint)
2183 struct ubsec_softc *sc = arg;
2186 if (krp == NULL || krp->krp_callback == NULL)
2189 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
2192 q = SIMPLEQ_FIRST(&sc->sc_q2free);
2193 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
2197 switch (krp->krp_op) {
2199 if (sc->sc_flags & UBS_FLAGS_HWNORM)
2200 r = ubsec_kprocess_modexp_hw(sc, krp, hint);
2202 r = ubsec_kprocess_modexp_sw(sc, krp, hint);
2204 case CRK_MOD_EXP_CRT:
2205 return (ubsec_kprocess_rsapriv(sc, krp, hint));
2207 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n",
2209 krp->krp_status = EOPNOTSUPP;
2213 return (0); /* silence compiler */
2217 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
2220 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2222 struct ubsec_q2_modexp *me;
2223 struct ubsec_mcr *mcr;
2224 struct ubsec_ctx_modexp *ctx;
2225 struct ubsec_pktbuf *epb;
2227 u_int nbits, normbits, mbits, shiftbits, ebits;
2229 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2231 me->me_q.q_type = UBS_CTXOP_MODEXP;
2233 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2236 else if (nbits <= 768)
2238 else if (nbits <= 1024)
2240 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2242 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2249 shiftbits = normbits - nbits;
2251 me->me_modbits = nbits;
2252 me->me_shiftbits = shiftbits;
2253 me->me_normbits = normbits;
2255 /* Sanity check: result bits must be >= true modulus bits. */
2256 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2261 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2262 &me->me_q.q_mcr, 0)) {
2266 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2268 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2269 &me->me_q.q_ctx, 0)) {
2274 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2275 if (mbits > nbits) {
2279 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2283 ubsec_kshift_r(shiftbits,
2284 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
2285 me->me_M.dma_vaddr, normbits);
2287 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2291 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2293 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2294 if (ebits > nbits) {
2298 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2302 ubsec_kshift_r(shiftbits,
2303 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
2304 me->me_E.dma_vaddr, normbits);
2306 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2311 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2312 epb->pb_addr = htole32(me->me_E.dma_paddr);
2314 epb->pb_len = htole32(normbits / 8);
2323 mcr->mcr_pkts = htole16(1);
2325 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2326 mcr->mcr_reserved = 0;
2327 mcr->mcr_pktlen = 0;
2329 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2330 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2331 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2333 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2334 mcr->mcr_opktbuf.pb_next = 0;
2335 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2338 /* Misaligned output buffer will hang the chip. */
2339 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2340 panic("%s: modexp invalid addr 0x%x\n",
2341 device_get_nameunit(sc->sc_dev),
2342 letoh32(mcr->mcr_opktbuf.pb_addr));
2343 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2344 panic("%s: modexp invalid len 0x%x\n",
2345 device_get_nameunit(sc->sc_dev),
2346 letoh32(mcr->mcr_opktbuf.pb_len));
2349 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2350 bzero(ctx, sizeof(*ctx));
2351 ubsec_kshift_r(shiftbits,
2352 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
2353 ctx->me_N, normbits);
2354 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2355 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2356 ctx->me_E_len = htole16(nbits);
2357 ctx->me_N_len = htole16(nbits);
2361 ubsec_dump_mcr(mcr);
2362 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2367 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2370 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2371 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2372 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2373 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2375 /* Enqueue and we're done... */
2377 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2379 ubsecstats.hst_modexp++;
2386 if (me->me_q.q_mcr.dma_map != NULL)
2387 ubsec_dma_free(sc, &me->me_q.q_mcr);
2388 if (me->me_q.q_ctx.dma_map != NULL) {
2389 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2390 ubsec_dma_free(sc, &me->me_q.q_ctx);
2392 if (me->me_M.dma_map != NULL) {
2393 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2394 ubsec_dma_free(sc, &me->me_M);
2396 if (me->me_E.dma_map != NULL) {
2397 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2398 ubsec_dma_free(sc, &me->me_E);
2400 if (me->me_C.dma_map != NULL) {
2401 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2402 ubsec_dma_free(sc, &me->me_C);
2404 if (me->me_epb.dma_map != NULL)
2405 ubsec_dma_free(sc, &me->me_epb);
2406 kfree(me, M_DEVBUF);
2408 krp->krp_status = err;
2414 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2417 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2419 struct ubsec_q2_modexp *me;
2420 struct ubsec_mcr *mcr;
2421 struct ubsec_ctx_modexp *ctx;
2422 struct ubsec_pktbuf *epb;
2424 u_int nbits, normbits, mbits, shiftbits, ebits;
2426 me = kmalloc(sizeof *me, M_DEVBUF, M_INTWAIT | M_ZERO);
2428 me->me_q.q_type = UBS_CTXOP_MODEXP;
2430 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2433 else if (nbits <= 768)
2435 else if (nbits <= 1024)
2437 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2439 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2446 shiftbits = normbits - nbits;
2449 me->me_modbits = nbits;
2450 me->me_shiftbits = shiftbits;
2451 me->me_normbits = normbits;
2453 /* Sanity check: result bits must be >= true modulus bits. */
2454 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2459 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2460 &me->me_q.q_mcr, 0)) {
2464 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2466 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2467 &me->me_q.q_ctx, 0)) {
2472 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2473 if (mbits > nbits) {
2477 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2481 bzero(me->me_M.dma_vaddr, normbits / 8);
2482 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2483 me->me_M.dma_vaddr, (mbits + 7) / 8);
2485 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2489 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2491 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2492 if (ebits > nbits) {
2496 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2500 bzero(me->me_E.dma_vaddr, normbits / 8);
2501 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2502 me->me_E.dma_vaddr, (ebits + 7) / 8);
2504 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2509 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2510 epb->pb_addr = htole32(me->me_E.dma_paddr);
2512 epb->pb_len = htole32((ebits + 7) / 8);
2521 mcr->mcr_pkts = htole16(1);
2523 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2524 mcr->mcr_reserved = 0;
2525 mcr->mcr_pktlen = 0;
2527 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2528 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2529 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2531 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2532 mcr->mcr_opktbuf.pb_next = 0;
2533 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2536 /* Misaligned output buffer will hang the chip. */
2537 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2538 panic("%s: modexp invalid addr 0x%x\n",
2539 device_get_nameunit(sc->sc_dev),
2540 letoh32(mcr->mcr_opktbuf.pb_addr));
2541 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2542 panic("%s: modexp invalid len 0x%x\n",
2543 device_get_nameunit(sc->sc_dev),
2544 letoh32(mcr->mcr_opktbuf.pb_len));
2547 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2548 bzero(ctx, sizeof(*ctx));
2549 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2551 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2552 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2553 ctx->me_E_len = htole16(ebits);
2554 ctx->me_N_len = htole16(nbits);
2558 ubsec_dump_mcr(mcr);
2559 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2564 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2567 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE);
2568 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE);
2569 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD);
2570 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE);
2572 /* Enqueue and we're done... */
2574 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2582 if (me->me_q.q_mcr.dma_map != NULL)
2583 ubsec_dma_free(sc, &me->me_q.q_mcr);
2584 if (me->me_q.q_ctx.dma_map != NULL) {
2585 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2586 ubsec_dma_free(sc, &me->me_q.q_ctx);
2588 if (me->me_M.dma_map != NULL) {
2589 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2590 ubsec_dma_free(sc, &me->me_M);
2592 if (me->me_E.dma_map != NULL) {
2593 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2594 ubsec_dma_free(sc, &me->me_E);
2596 if (me->me_C.dma_map != NULL) {
2597 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2598 ubsec_dma_free(sc, &me->me_C);
2600 if (me->me_epb.dma_map != NULL)
2601 ubsec_dma_free(sc, &me->me_epb);
2602 kfree(me, M_DEVBUF);
2604 krp->krp_status = err;
2610 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint)
2612 struct ubsec_q2_rsapriv *rp = NULL;
2613 struct ubsec_mcr *mcr;
2614 struct ubsec_ctx_rsapriv *ctx;
2616 u_int padlen, msglen;
2618 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2619 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2620 if (msglen > padlen)
2625 else if (padlen <= 384)
2627 else if (padlen <= 512)
2629 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2631 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2638 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2643 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2648 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2653 rp = kmalloc(sizeof *rp, M_DEVBUF, M_INTWAIT | M_ZERO);
2655 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2657 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2658 &rp->rpr_q.q_mcr, 0)) {
2662 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2664 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2665 &rp->rpr_q.q_ctx, 0)) {
2669 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2670 bzero(ctx, sizeof *ctx);
2673 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2674 &ctx->rpr_buf[0 * (padlen / 8)],
2675 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2678 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2679 &ctx->rpr_buf[1 * (padlen / 8)],
2680 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2683 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2684 &ctx->rpr_buf[2 * (padlen / 8)],
2685 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2688 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2689 &ctx->rpr_buf[3 * (padlen / 8)],
2690 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2693 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2694 &ctx->rpr_buf[4 * (padlen / 8)],
2695 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2697 msglen = padlen * 2;
2699 /* Copy in input message (aligned buffer/length). */
2700 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2701 /* Is this likely? */
2705 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2709 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2710 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2711 rp->rpr_msgin.dma_vaddr,
2712 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2714 /* Prepare space for output message (aligned buffer/length). */
2715 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2716 /* Is this likely? */
2720 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2724 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2726 mcr->mcr_pkts = htole16(1);
2728 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2729 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2730 mcr->mcr_ipktbuf.pb_next = 0;
2731 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2732 mcr->mcr_reserved = 0;
2733 mcr->mcr_pktlen = htole16(msglen);
2734 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2735 mcr->mcr_opktbuf.pb_next = 0;
2736 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2739 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2740 panic("%s: rsapriv: invalid msgin %x(0x%jx)",
2741 device_get_nameunit(sc->sc_dev),
2742 rp->rpr_msgin.dma_paddr,
2743 (uintmax_t)rp->rpr_msgin.dma_size);
2745 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2746 panic("%s: rsapriv: invalid msgout %x(0x%jx)",
2747 device_get_nameunit(sc->sc_dev),
2748 rp->rpr_msgout.dma_paddr,
2749 (uintmax_t)rp->rpr_msgout.dma_size);
2753 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2754 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2755 ctx->rpr_q_len = htole16(padlen);
2756 ctx->rpr_p_len = htole16(padlen);
2759 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2762 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE);
2763 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD);
2765 /* Enqueue and we're done... */
2767 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2769 ubsecstats.hst_modexpcrt++;
2775 if (rp->rpr_q.q_mcr.dma_map != NULL)
2776 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2777 if (rp->rpr_msgin.dma_map != NULL) {
2778 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2779 ubsec_dma_free(sc, &rp->rpr_msgin);
2781 if (rp->rpr_msgout.dma_map != NULL) {
2782 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2783 ubsec_dma_free(sc, &rp->rpr_msgout);
2785 kfree(rp, M_DEVBUF);
2787 krp->krp_status = err;
2794 ubsec_dump_pb(volatile struct ubsec_pktbuf *pb)
2796 kprintf("addr 0x%x (0x%x) next 0x%x\n",
2797 pb->pb_addr, pb->pb_len, pb->pb_next);
2801 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2803 kprintf("CTX (0x%x):\n", c->ctx_len);
2804 switch (letoh16(c->ctx_op)) {
2805 case UBS_CTXOP_RNGBYPASS:
2806 case UBS_CTXOP_RNGSHA1:
2808 case UBS_CTXOP_MODEXP:
2810 struct ubsec_ctx_modexp *cx = (void *)c;
2813 kprintf(" Elen %u, Nlen %u\n",
2814 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2815 len = (cx->me_N_len + 7)/8;
2816 for (i = 0; i < len; i++)
2817 kprintf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2822 kprintf("unknown context: %x\n", c->ctx_op);
2824 kprintf("END CTX\n");
2828 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2830 volatile struct ubsec_mcr_add *ma;
2834 kprintf(" pkts: %u, flags 0x%x\n",
2835 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2836 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2837 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2838 kprintf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2839 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2840 letoh16(ma->mcr_reserved));
2841 kprintf(" %d: ipkt ", i);
2842 ubsec_dump_pb(&ma->mcr_ipktbuf);
2843 kprintf(" %d: opkt ", i);
2844 ubsec_dump_pb(&ma->mcr_opktbuf);
2847 kprintf("END MCR\n");
2849 #endif /* UBSEC_DEBUG */
2852 * Return the number of significant bits of a big number.
2855 ubsec_ksigbits(struct crparam *cr)
2857 u_int plen = (cr->crp_nbits + 7) / 8;
2858 int i, sig = plen * 8;
2859 u_int8_t c, *p = cr->crp_p;
2861 for (i = plen - 1; i >= 0; i--) {
2864 while ((c & 0x80) == 0) {
2878 u_int8_t *src, u_int srcbits,
2879 u_int8_t *dst, u_int dstbits)
2884 slen = (srcbits + 7) / 8;
2885 dlen = (dstbits + 7) / 8;
2887 for (i = 0; i < slen; i++)
2889 for (i = 0; i < dlen - slen; i++)
2897 dst[di--] = dst[si--];
2904 for (i = dlen - 1; i > 0; i--)
2905 dst[i] = (dst[i] << n) |
2906 (dst[i - 1] >> (8 - n));
2907 dst[0] = dst[0] << n;
2914 u_int8_t *src, u_int srcbits,
2915 u_int8_t *dst, u_int dstbits)
2917 int slen, dlen, i, n;
2919 slen = (srcbits + 7) / 8;
2920 dlen = (dstbits + 7) / 8;
2923 for (i = 0; i < slen; i++)
2924 dst[i] = src[i + n];
2925 for (i = 0; i < dlen - slen; i++)
2930 for (i = 0; i < (dlen - 1); i++)
2931 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2932 dst[dlen - 1] = dst[dlen - 1] >> n;