2 * Copyright (c) 2001 Gary Jennejohn. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * i4b_ifpi2_pci.c: AVM Fritz!Card PCI hardware driver
34 * --------------------------------------------------
38 * $FreeBSD: src/sys/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.6.2.2 2002/05/15 08:12:42 gj Exp $
39 * $DragonFly: src/sys/net/i4b/layer1/ifpi2/i4b_ifpi2_pci.c,v 1.14 2006/12/22 23:44:56 swildner Exp $
41 * last edit-date: [Fri Jan 12 17:01:26 2001]
43 *---------------------------------------------------------------------------*/
45 #include "use_ifpi2.h"
49 #if (NIFPI2 > 0) && (NPCI > 0)
51 #include <sys/param.h>
52 #include <sys/kernel.h>
53 #include <sys/systm.h>
57 #include <sys/socket.h>
58 #include <sys/thread2.h>
60 #include <bus/pci/pcireg.h>
61 #include <bus/pci/pcivar.h>
64 #include <net/i4b/include/machine/i4b_debug.h>
65 #include <net/i4b/include/machine/i4b_ioctl.h>
66 #include <net/i4b/include/machine/i4b_trace.h>
68 #include "../../include/i4b_global.h"
69 #include "../../include/i4b_mbuf.h"
71 #include "../i4b_l1.h"
72 #include "../isic/i4b_isic.h"
73 /*#include "../isic/i4b_isac.h"*/
74 #include "../isic/i4b_hscx.h"
76 #include "i4b_ifpi2_ext.h"
77 #include "i4b_ifpi2_isacsx.h"
79 #define PCI_AVMA1_VID 0x1244
80 #define PCI_AVMA1_V2_DID 0x0e00
83 static void avma1pp2_disable(device_t);
85 static void avma1pp2_intr(void *);
86 static void hscx_write_reg(int, u_int, struct l1_softc *);
87 static u_char hscx_read_reg(int, struct l1_softc *);
88 static u_int hscx_read_reg_int(int, struct l1_softc *);
89 static void hscx_read_fifo(int, void *, size_t, struct l1_softc *);
90 static void hscx_write_fifo(int, void *, size_t, struct l1_softc *);
91 static void avma1pp2_hscx_int_handler(struct l1_softc *);
92 static void avma1pp2_hscx_intr(int, u_int, struct l1_softc *);
93 static void avma1pp2_init_linktab(struct l1_softc *);
94 static void avma1pp2_bchannel_setup(int, int, int, int);
95 static void avma1pp2_bchannel_start(int, int);
96 static void avma1pp2_hscx_init(struct l1_softc *, int, int);
97 static void avma1pp2_bchannel_stat(int, int, bchan_statistics_t *);
98 static void avma1pp2_set_linktab(int, int, drvr_link_t *);
99 static isdn_link_t * avma1pp2_ret_linktab(int, int);
100 static int avma1pp2_pci_probe(device_t);
101 static int avma1pp2_hscx_fifo(l1_bchan_state_t *, struct l1_softc *);
102 int avma1pp2_attach_avma1pp(device_t);
103 static void ifpi2_isacsx_intr(struct l1_softc *sc);
105 static device_method_t avma1pp2_pci_methods[] = {
106 /* Device interface */
107 DEVMETHOD(device_probe, avma1pp2_pci_probe),
108 DEVMETHOD(device_attach, avma1pp2_attach_avma1pp),
109 DEVMETHOD(device_shutdown, avma1pp2_disable),
112 DEVMETHOD(bus_print_child, bus_generic_print_child),
113 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
118 static driver_t avma1pp2_pci_driver = {
120 avma1pp2_pci_methods,
121 sizeof(struct l1_softc)
124 static devclass_t avma1pp2_pci_devclass;
126 DRIVER_MODULE(avma1pp2, pci, avma1pp2_pci_driver, avma1pp2_pci_devclass, 0, 0);
128 /* jump table for multiplex routines */
130 struct i4b_l1mux_func avma1pp2_l1mux_func = {
131 avma1pp2_ret_linktab,
132 avma1pp2_set_linktab,
133 ifpi2_mph_command_req,
135 ifpi2_ph_activate_req,
138 struct l1_softc *ifpi2_scp[IFPI2_MAXUNIT];
140 /*---------------------------------------------------------------------------*
141 * AVM PCI Fritz!Card V. 2 special registers
142 *---------------------------------------------------------------------------*/
145 * AVM PCI Status Latch 0 read only bits
147 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active high */
148 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active high */
149 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active high */
150 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
151 /* actually active high */
152 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
155 * AVM PCI Status Latch 0 read only bits
157 #define ASL_TIMERRESET 0x04
158 #define ASL_ENABLE_INT 0x08
163 #define HSCX_STAT_RME 0x01
164 #define HSCX_STAT_RDO 0x10
165 #define HSCX_STAT_CRCVFRRAB 0x0E
166 #define HSCX_STAT_CRCVFR 0x06
167 #define HSCX_STAT_RML_MASK 0x3f00
170 * "HSCX" interrupt bits
172 #define HSCX_INT_XPR 0x80
173 #define HSCX_INT_XDU 0x40
174 #define HSCX_INT_RPR 0x20
175 #define HSCX_INT_MASK 0xE0
178 * "HSCX" command bits
180 #define HSCX_CMD_XRS 0x80
181 #define HSCX_CMD_XME 0x01
182 #define HSCX_CMD_RRS 0x20
183 #define HSCX_CMD_XML_MASK 0x3f00
185 /* "HSCX" mode bits */
186 #define HSCX_MODE_ITF_FLG 0x01
187 #define HSCX_MODE_TRANS 0x02
189 /* offsets to various registers in the ASIC, evidently */
190 #define STAT0_OFFSET 0x02
192 #define HSCX_FIFO1 0x10
193 #define HSCX_FIFO2 0x18
195 #define HSCX_STAT1 0x14
196 #define HSCX_STAT2 0x1c
198 #define ISACSX_INDEX 0x04
199 #define ISACSX_DATA 0x08
202 * Commands and parameters are sent to the "HSCX" as a long, but the
203 * fields are handled as bytes.
206 * (prot << 16)|(txl << 8)|cmd
209 * prot = protocol to use
210 * txl = transmit length
211 * cmd = the command to be executed
213 * The fields are defined as u_char in struct l1_softc.
215 * Macro to coalesce the byte fields into a u_int
217 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
218 | (sc->avma1pp_prot << 16))
221 * to prevent deactivating the "HSCX" when both channels are active we
222 * define an HSCX_ACTIVE flag which is or'd into the channel's state
223 * flag in avma1pp2_bchannel_setup upon active and cleared upon deactivation.
224 * It is set high to allow room for new flags.
226 #define HSCX_AVMA1PP_ACTIVE 0x1000
228 /*---------------------------------------------------------------------------*
229 * AVM read fifo routines
230 *---------------------------------------------------------------------------*/
233 avma1pp2_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
235 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
236 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
241 bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
242 /* evidently each byte must be read as a long */
243 for (i = 0; i < size; i++)
244 ((u_int8_t *)buf)[i] = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
246 case ISIC_WHAT_HSCXA:
247 hscx_read_fifo(0, buf, size, sc);
249 case ISIC_WHAT_HSCXB:
250 hscx_read_fifo(1, buf, size, sc);
256 hscx_read_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
261 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
262 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
264 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
266 ip = (u_int32_t *)buf;
268 /* what if len isn't a multiple of sizeof(int) and buf is */
272 *ip++ = bus_space_read_4(btag, bhandle, dataoff);
277 /*---------------------------------------------------------------------------*
278 * AVM write fifo routines
279 *---------------------------------------------------------------------------*/
281 avma1pp2_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
283 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
284 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
289 bus_space_write_4(btag, bhandle, ISACSX_INDEX, 0);
290 /* evidently each byte must written as a long */
291 for (i = 0; i < size; i++)
292 bus_space_write_4(btag, bhandle, ISACSX_DATA, ((unsigned char *)buf)[i]);
294 case ISIC_WHAT_HSCXA:
295 hscx_write_fifo(0, buf, size, sc);
297 case ISIC_WHAT_HSCXB:
298 hscx_write_fifo(1, buf, size, sc);
304 hscx_write_fifo(int chan, void *buf, size_t len, struct l1_softc *sc)
309 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
310 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
311 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
313 dataoff = chan ? HSCX_FIFO2 : HSCX_FIFO1;
315 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
317 if (Bchan->out_mbuf_cur == NULL)
319 if (Bchan->bprot != BPROT_NONE)
320 sc->avma1pp_cmd |= HSCX_CMD_XME;
322 if (len != sc->sc_bfifolen)
323 sc->avma1pp_txl = len;
325 cnt = 0; /* borrow cnt */
326 AVMA1PPSETCMDLONG(cnt);
327 hscx_write_reg(chan, cnt, sc);
329 ip = (u_int32_t *)buf;
333 bus_space_write_4(btag, bhandle, dataoff, *ip);
339 /*---------------------------------------------------------------------------*
340 * AVM write register routines
341 *---------------------------------------------------------------------------*/
344 avma1pp2_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
346 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
347 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
351 bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
352 bus_space_write_4(btag, bhandle, ISACSX_DATA, data);
354 case ISIC_WHAT_HSCXA:
355 hscx_write_reg(0, data, sc);
357 case ISIC_WHAT_HSCXB:
358 hscx_write_reg(1, data, sc);
364 hscx_write_reg(int chan, u_int val, struct l1_softc *sc)
366 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
367 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
370 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
372 bus_space_write_4(btag, bhandle, off, val);
375 /*---------------------------------------------------------------------------*
376 * AVM read register routines
377 *---------------------------------------------------------------------------*/
379 avma1pp2_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
381 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
382 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
387 bus_space_write_4(btag, bhandle, ISACSX_INDEX, offs);
388 val = (u_int8_t)bus_space_read_4(btag, bhandle, ISACSX_DATA);
390 case ISIC_WHAT_HSCXA:
391 return hscx_read_reg(0, sc);
392 case ISIC_WHAT_HSCXB:
393 return hscx_read_reg(1, sc);
399 hscx_read_reg(int chan, struct l1_softc *sc)
401 return(hscx_read_reg_int(chan, sc) & 0xff);
405 * need to be able to return an int because the RBCH is in the 2nd
409 hscx_read_reg_int(int chan, struct l1_softc *sc)
411 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
412 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
415 off = (chan == 0 ? HSCX_STAT1 : HSCX_STAT2);
416 return(bus_space_read_4(btag, bhandle, off));
419 /*---------------------------------------------------------------------------*
420 * avma1pp2_probe - probe for a card
421 *---------------------------------------------------------------------------*/
423 avma1pp2_pci_probe(device_t dev)
427 vid = pci_get_vendor(dev);
428 did = pci_get_device(dev);
430 if ((vid == PCI_AVMA1_VID) && (did == PCI_AVMA1_V2_DID)) {
431 device_set_desc(dev, "AVM Fritz!Card PCI Version 2");
438 /*---------------------------------------------------------------------------*
439 * avma1pp2_attach_avma1pp - attach Fritz!Card PCI
440 *---------------------------------------------------------------------------*/
442 avma1pp2_attach_avma1pp(device_t dev)
449 bus_space_handle_t bhandle;
450 bus_space_tag_t btag;
454 vid = pci_get_vendor(dev);
455 did = pci_get_device(dev);
456 sc = device_get_softc(dev);
457 unit = device_get_unit(dev);
458 bzero(sc, sizeof(struct l1_softc));
460 /* probably not really required */
461 if(unit > IFPI2_MAXUNIT) {
462 kprintf("ifpi2-%d: Error, unit > IFPI_MAXUNIT!\n", unit);
467 if ((vid != PCI_AVMA1_VID) && (did != PCI_AVMA1_V2_DID)) {
468 kprintf("ifpi2-%d: unknown device!?\n", unit);
472 ifpi2_scp[unit] = sc;
474 sc->sc_resources.io_rid[0] = PCIR_MAPS+4;
475 sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
476 &sc->sc_resources.io_rid[0],
477 0, ~0, 1, RF_ACTIVE);
479 if (sc->sc_resources.io_base[0] == NULL) {
480 kprintf("ifpi2-%d: couldn't map IO port\n", unit);
485 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
486 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
488 /* Allocate interrupt */
489 sc->sc_resources.irq_rid = 0;
490 sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
491 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
493 if (sc->sc_resources.irq == NULL) {
494 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
495 kprintf("ifpi2-%d: couldn't map interrupt\n", unit);
500 error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
501 avma1pp2_intr, sc, &ih, NULL);
504 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
505 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+4, sc->sc_resources.io_base[0]);
506 kprintf("ifpi2-%d: couldn't set up irq\n", unit);
512 /* end of new-bus stuff */
514 ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
516 HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
517 HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
519 /* setup access routines */
522 sc->readreg = avma1pp2_read_reg;
523 sc->writereg = avma1pp2_write_reg;
525 sc->readfifo = avma1pp2_read_fifo;
526 sc->writefifo = avma1pp2_write_fifo;
528 /* setup card type */
530 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI_V2;
532 /* setup IOM bus type */
534 sc->sc_bustyp = BUS_TYPE_IOM2;
536 /* set up some other miscellaneous things */
538 sc->sc_bfifolen = HSCX_FIFO_LEN;
541 /* the Linux driver does this to clear any pending ISAC interrupts */
543 v = ISAC_READ(I_RMODED);
544 #ifdef AVMA1PCI_V2_DEBUG
545 kprintf("avma1pp2_attach: I_MODED %x...", v);
547 v = ISAC_READ(I_ISTAD);
548 #ifdef AVMA1PCI_V2_DEBUG
549 kprintf("avma1pp2_attach: I_ISTAD %x...", v);
551 v = ISAC_READ(I_ISTA);
552 #ifdef AVMA1PCI_V2_DEBUG
553 kprintf("avma1pp2_attach: I_ISTA %x...", v);
555 ISAC_WRITE(I_MASKD, 0xff);
556 ISAC_WRITE(I_MASK, 0xff);
557 /* the Linux driver does this to clear any pending HSCX interrupts */
558 v = hscx_read_reg_int(0, sc);
559 #ifdef AVMA1PCI_V2_DEBUG
560 kprintf("avma1pp2_attach: 0 HSCX_STAT %x...", v);
562 v = hscx_read_reg_int(1, sc);
563 #ifdef AVMA1PCI_V2_DEBUG
564 kprintf("avma1pp2_attach: 1 HSCX_STAT %x\n", v);
567 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_TIMERRESET);
568 DELAY(SEC_DELAY/100); /* 10 ms */
569 bus_space_write_1(btag, bhandle, STAT0_OFFSET, ASL_ENABLE_INT);
570 DELAY(SEC_DELAY/100); /* 10 ms */
572 /* from here to the end would normally be done in isic_pciattach */
574 kprintf("ifpi2-%d: ISACSX %s\n", unit, "PSB3186");
577 ifpi2_isacsx_init(sc);
579 /* init the "HSCX" */
580 avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
582 avma1pp2_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
584 /* can't use the normal B-Channel stuff */
585 avma1pp2_init_linktab(sc);
587 /* set trace level */
589 sc->sc_trace = TRACE_OFF;
591 sc->sc_state = ISAC_IDLE;
603 sc->sc_freeflag2 = 0;
605 callout_init(&sc->sc_T3_timeout);
606 callout_init(&sc->sc_T4_timeout);
608 /* init higher protocol layers */
610 i4b_l1_mph_status_ind(L0IFPI2UNIT(sc->sc_unit), STI_ATTACH, sc->sc_cardtyp, &avma1pp2_l1mux_func);
618 * this is the real interrupt routine
621 avma1pp2_hscx_intr(int h_chan, u_int stat, struct l1_softc *sc)
623 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
627 NDBGL1(L1_H_IRQ, "%#x", stat);
629 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
632 NDBGL1(L1_H_XFRERR, "xmit data underrun");
633 /* abort the transmission */
635 sc->avma1pp_cmd |= HSCX_CMD_XRS;
636 AVMA1PPSETCMDLONG(param);
637 hscx_write_reg(h_chan, param, sc);
638 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
639 AVMA1PPSETCMDLONG(param);
640 hscx_write_reg(h_chan, param, sc);
642 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
644 i4b_Bfreembuf(chan->out_mbuf_head);
645 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
650 * The following is based on examination of the Linux driver.
652 * The logic here is different than with a "real" HSCX; all kinds
653 * of information (interrupt/status bits) are in stat.
654 * HSCX_INT_RPR indicates a receive interrupt
655 * HSCX_STAT_RDO indicates an overrun condition, abort -
656 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
657 * HSCX_STAT_RME indicates end-of-frame and apparently any
658 * CRC/framing errors are only reported in this state.
659 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
663 if(stat & HSCX_INT_RPR)
667 /* always have to read the FIFO, so use a scratch buffer */
668 u_char scrbuf[HSCX_FIFO_LEN];
670 if(stat & HSCX_STAT_RDO)
673 NDBGL1(L1_H_XFRERR, "receive data overflow");
678 * check whether we're receiving data for an inactive B-channel
679 * and discard it. This appears to happen for telephony when
680 * both B-channels are active and one is deactivated. Since
681 * it is not really possible to deactivate the channel in that
682 * case (the ASIC seems to deactivate _both_ channels), the
683 * "deactivated" channel keeps receiving data which can lead
684 * to exhaustion of mbufs and a kernel panic.
686 * This is a hack, but it's the only solution I can think of
687 * without having the documentation for the ASIC.
690 if (chan->state == HSCX_IDLE)
692 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
696 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
698 if(fifo_data_len == 0)
699 fifo_data_len = sc->sc_bfifolen;
701 /* ALWAYS read data from HSCX fifo */
703 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
704 chan->rxcount += fifo_data_len;
706 /* all error conditions checked, now decide and take action */
710 if(chan->in_mbuf == NULL)
712 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
713 panic("L1 avma1pp2_hscx_intr: RME, cannot allocate mbuf!\n");
714 chan->in_cbptr = chan->in_mbuf->m_data;
718 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
720 /* OK to copy the data */
721 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
722 chan->in_cbptr += fifo_data_len;
723 chan->in_len += fifo_data_len;
725 /* setup mbuf data length */
727 chan->in_mbuf->m_len = chan->in_len;
728 chan->in_mbuf->m_pkthdr.len = chan->in_len;
730 if(sc->sc_trace & TRACE_B_RX)
733 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
734 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
736 hdr.count = ++sc->sc_trace_bcount;
738 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
741 if (stat & HSCX_STAT_RME)
743 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
745 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
748 /* mark buffer ptr as unused */
750 chan->in_mbuf = NULL;
751 chan->in_cbptr = NULL;
757 NDBGL1(L1_H_XFRERR, "CRC/RAB");
758 if (chan->in_mbuf != NULL)
760 i4b_Bfreembuf(chan->in_mbuf);
761 chan->in_mbuf = NULL;
762 chan->in_cbptr = NULL;
767 } /* END enough space in mbuf */
770 if(chan->bprot == BPROT_NONE)
772 /* setup mbuf data length */
774 chan->in_mbuf->m_len = chan->in_len;
775 chan->in_mbuf->m_pkthdr.len = chan->in_len;
777 if(sc->sc_trace & TRACE_B_RX)
780 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
781 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
783 hdr.count = ++sc->sc_trace_bcount;
785 i4b_l1_trace_ind(&hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
788 if(!(i4b_l1_bchan_tel_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
791 /* move rx'd data to rx queue */
793 if(!(IF_QFULL(&chan->rx_queue)))
795 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
799 i4b_Bfreembuf(chan->in_mbuf);
801 /* signal upper layer that data are available */
802 (*chan->isic_drvr_linktab->bch_rx_data_ready)(chan->isic_drvr_linktab->unit);
804 /* alloc new buffer */
806 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
807 panic("L1 avma1pp2_hscx_intr: RPF, cannot allocate new mbuf!\n");
809 /* setup new data ptr */
811 chan->in_cbptr = chan->in_mbuf->m_data;
813 /* OK to copy the data */
814 bcopy(scrbuf, chan->in_cbptr, fifo_data_len);
816 chan->in_cbptr += fifo_data_len;
817 chan->in_len = fifo_data_len;
819 chan->rxcount += fifo_data_len;
823 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
824 chan->in_cbptr = chan->in_mbuf->m_data;
828 } /* if(error == 0) */
831 /* land here for RDO */
832 if (chan->in_mbuf != NULL)
834 i4b_Bfreembuf(chan->in_mbuf);
835 chan->in_mbuf = NULL;
836 chan->in_cbptr = NULL;
840 sc->avma1pp_cmd |= HSCX_CMD_RRS;
841 AVMA1PPSETCMDLONG(param);
842 hscx_write_reg(h_chan, param, sc);
843 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
844 AVMA1PPSETCMDLONG(param);
845 hscx_write_reg(h_chan, param, sc);
850 /* transmit fifo empty, new data can be written to fifo */
852 if(stat & HSCX_INT_XPR)
855 * for a description what is going on here, please have
856 * a look at isic_bchannel_start() in i4b_bchan.c !
859 NDBGL1(L1_H_IRQ, "unit %d, chan %d - XPR, Tx Fifo Empty!", sc->sc_unit, h_chan);
861 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
863 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
865 if(chan->out_mbuf_head == NULL)
867 chan->state &= ~HSCX_TX_ACTIVE;
868 (*chan->isic_drvr_linktab->bch_tx_queue_empty)(chan->isic_drvr_linktab->unit);
872 chan->state |= HSCX_TX_ACTIVE;
873 chan->out_mbuf_cur = chan->out_mbuf_head;
874 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
875 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
877 if(sc->sc_trace & TRACE_B_TX)
880 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
881 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
883 hdr.count = ++sc->sc_trace_bcount;
885 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
888 if(chan->bprot == BPROT_NONE)
890 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
900 avma1pp2_hscx_fifo(chan, sc);
903 /* call timeout handling routine */
905 if(activity == ACT_RX || activity == ACT_TX)
906 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
910 * this is the main routine which checks each channel and then calls
911 * the real interrupt routine as appropriate
914 avma1pp2_hscx_int_handler(struct l1_softc *sc)
918 /* has to be a u_int because the byte count is in the 2nd byte */
919 stat = hscx_read_reg_int(0, sc);
920 if (stat & HSCX_INT_MASK)
921 avma1pp2_hscx_intr(0, stat, sc);
922 stat = hscx_read_reg_int(1, sc);
923 if (stat & HSCX_INT_MASK)
924 avma1pp2_hscx_intr(1, stat, sc);
928 avma1pp2_disable(device_t dev)
930 struct l1_softc *sc = device_get_softc(dev);
931 bus_space_handle_t bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
932 bus_space_tag_t btag = rman_get_bustag(sc->sc_resources.io_base[0]);
934 /* could still be wrong, but it seems to help */
935 bus_space_write_1(btag, bhandle, STAT0_OFFSET, 0x00);
939 avma1pp2_intr(void *xsc)
943 bus_space_handle_t bhandle;
944 bus_space_tag_t btag;
947 bhandle = rman_get_bushandle(sc->sc_resources.io_base[0]);
948 btag = rman_get_bustag(sc->sc_resources.io_base[0]);
950 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
951 NDBGL1(L1_H_IRQ, "stat %x", stat);
952 /* was there an interrupt from this card ? */
953 if ((stat & ASL_IRQ_Pending) == 0)
955 /* For slow machines loop as long as an interrupt is active */
956 for (; ((stat & ASL_IRQ_Pending) != 0) ;)
958 /* interrupts are high active */
959 if (stat & ASL_IRQ_TIMER)
960 NDBGL1(L1_H_IRQ, "timer interrupt ???");
961 if (stat & ASL_IRQ_HSCX)
963 NDBGL1(L1_H_IRQ, "HSCX");
964 avma1pp2_hscx_int_handler(sc);
966 if (stat & ASL_IRQ_ISAC)
968 NDBGL1(L1_H_IRQ, "ISAC");
969 ifpi2_isacsx_intr(sc);
971 stat = bus_space_read_1(btag, bhandle, STAT0_OFFSET);
972 NDBGL1(L1_H_IRQ, "stat %x", stat);
978 avma1pp2_hscx_init(struct l1_softc *sc, int h_chan, int activate)
980 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
983 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
984 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
986 sc->avma1pp_cmd = sc->avma1pp_prot = sc->avma1pp_txl = 0;
990 /* only deactivate if both channels are idle */
991 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
992 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
996 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
997 sc->avma1pp_prot = HSCX_MODE_TRANS;
998 AVMA1PPSETCMDLONG(param);
999 hscx_write_reg(h_chan, param, sc);
1002 if(chan->bprot == BPROT_RHDLC)
1004 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1006 /* HDLC Frames, transparent mode 0 */
1007 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1008 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1009 AVMA1PPSETCMDLONG(param);
1010 hscx_write_reg(h_chan, param, sc);
1011 sc->avma1pp_cmd = HSCX_CMD_XRS;
1012 AVMA1PPSETCMDLONG(param);
1013 hscx_write_reg(h_chan, param, sc);
1014 sc->avma1pp_cmd = 0;
1018 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1020 /* Raw Telephony, extended transparent mode 1 */
1021 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1022 sc->avma1pp_prot = HSCX_MODE_TRANS;
1023 AVMA1PPSETCMDLONG(param);
1024 hscx_write_reg(h_chan, param, sc);
1025 sc->avma1pp_cmd = HSCX_CMD_XRS;
1026 AVMA1PPSETCMDLONG(param);
1027 hscx_write_reg(h_chan, param, sc);
1028 sc->avma1pp_cmd = 0;
1033 avma1pp2_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1035 struct l1_softc *sc = ifpi2_scp[unit];
1036 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1043 chan->state = HSCX_IDLE;
1044 avma1pp2_hscx_init(sc, h_chan, activate);
1047 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1048 sc->sc_unit, h_chan, activate ? "activate" : "deactivate");
1052 chan->unit = sc->sc_unit; /* unit number */
1053 chan->channel = h_chan; /* B channel */
1054 chan->bprot = bprot; /* B channel protocol */
1055 chan->state = HSCX_IDLE; /* B channel state */
1059 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1061 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1063 chan->rxcount = 0; /* reset rx counter */
1065 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1067 chan->in_mbuf = NULL; /* reset mbuf ptr */
1068 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1069 chan->in_len = 0; /* reset mbuf data len */
1071 /* transmitter part */
1073 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1075 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1077 chan->txcount = 0; /* reset tx counter */
1079 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1081 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1082 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1083 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1084 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1089 avma1pp2_hscx_init(sc, h_chan, activate);
1090 chan->state |= HSCX_AVMA1PP_ACTIVE;
1097 avma1pp2_bchannel_start(int unit, int h_chan)
1099 struct l1_softc *sc = ifpi2_scp[unit];
1100 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1104 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1107 return; /* yes, leave */
1110 /* get next mbuf from queue */
1112 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1114 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1117 return; /* yes, exit */
1120 /* init current mbuf values */
1122 chan->out_mbuf_cur = chan->out_mbuf_head;
1123 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1124 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1126 /* activity indicator for timeout handling */
1128 if(chan->bprot == BPROT_NONE)
1130 if(!(i4b_l1_bchan_tel_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1138 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1140 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1142 i4b_trace_hdr_t hdr;
1143 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1144 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1146 hdr.count = ++sc->sc_trace_bcount;
1147 MICROTIME(hdr.time);
1148 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1151 avma1pp2_hscx_fifo(chan, sc);
1153 /* call timeout handling routine */
1155 if(activity == ACT_RX || activity == ACT_TX)
1156 (*chan->isic_drvr_linktab->bch_activity)(chan->isic_drvr_linktab->unit, activity);
1161 /*---------------------------------------------------------------------------*
1162 * return the address of isic drivers linktab
1163 *---------------------------------------------------------------------------*/
1164 static isdn_link_t *
1165 avma1pp2_ret_linktab(int unit, int channel)
1167 struct l1_softc *sc = ifpi2_scp[unit];
1168 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1170 return(&chan->isic_isdn_linktab);
1173 /*---------------------------------------------------------------------------*
1174 * set the driver linktab in the b channel softc
1175 *---------------------------------------------------------------------------*/
1177 avma1pp2_set_linktab(int unit, int channel, drvr_link_t *dlt)
1179 struct l1_softc *sc = ifpi2_scp[unit];
1180 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1182 chan->isic_drvr_linktab = dlt;
1186 /*---------------------------------------------------------------------------*
1187 * initialize our local linktab
1188 *---------------------------------------------------------------------------*/
1190 avma1pp2_init_linktab(struct l1_softc *sc)
1192 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1193 isdn_link_t *lt = &chan->isic_isdn_linktab;
1195 /* make sure the hardware driver is known to layer 4 */
1196 /* avoid overwriting if already set */
1197 if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
1199 ctrl_types[CTRL_PASSIVE].set_linktab = i4b_l1_set_linktab;
1200 ctrl_types[CTRL_PASSIVE].get_linktab = i4b_l1_ret_linktab;
1204 lt->unit = sc->sc_unit;
1205 lt->channel = HSCX_CH_A;
1206 lt->bch_config = avma1pp2_bchannel_setup;
1207 lt->bch_tx_start = avma1pp2_bchannel_start;
1208 lt->bch_stat = avma1pp2_bchannel_stat;
1209 lt->tx_queue = &chan->tx_queue;
1211 /* used by non-HDLC data transfers, i.e. telephony drivers */
1212 lt->rx_queue = &chan->rx_queue;
1214 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1215 lt->rx_mbuf = &chan->in_mbuf;
1217 chan = &sc->sc_chan[HSCX_CH_B];
1218 lt = &chan->isic_isdn_linktab;
1220 lt->unit = sc->sc_unit;
1221 lt->channel = HSCX_CH_B;
1222 lt->bch_config = avma1pp2_bchannel_setup;
1223 lt->bch_tx_start = avma1pp2_bchannel_start;
1224 lt->bch_stat = avma1pp2_bchannel_stat;
1225 lt->tx_queue = &chan->tx_queue;
1227 /* used by non-HDLC data transfers, i.e. telephony drivers */
1228 lt->rx_queue = &chan->rx_queue;
1230 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1231 lt->rx_mbuf = &chan->in_mbuf;
1235 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1238 avma1pp2_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
1240 struct l1_softc *sc = ifpi2_scp[unit];
1241 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1245 bsp->outbytes = chan->txcount;
1246 bsp->inbytes = chan->rxcount;
1254 /*---------------------------------------------------------------------------*
1255 * fill HSCX fifo with data from the current mbuf
1256 * Put this here until it can go into i4b_hscx.c
1257 *---------------------------------------------------------------------------*/
1259 avma1pp2_hscx_fifo(l1_bchan_state_t *chan, struct l1_softc *sc)
1265 /* using a scratch buffer simplifies writing to the FIFO */
1266 u_char scrbuf[HSCX_FIFO_LEN];
1271 * fill the HSCX tx fifo with data from the current mbuf. if
1272 * current mbuf holds less data than HSCX fifo length, try to
1273 * get the next mbuf from (a possible) mbuf chain. if there is
1274 * not enough data in a single mbuf or in a chain, then this
1275 * is the last mbuf and we tell the HSCX that it has to send
1276 * CRC and closing flag
1279 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1281 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1284 kprintf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1285 chan->out_mbuf_head,
1287 chan->out_mbuf_cur_ptr,
1288 chan->out_mbuf_cur_len,
1293 cmd |= HSCX_CMDR_XTF;
1294 /* collect the data in the scratch buffer */
1295 for (i = 0; i < nextlen; i++)
1296 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1299 chan->txcount += nextlen;
1301 chan->out_mbuf_cur_ptr += nextlen;
1302 chan->out_mbuf_cur_len -= nextlen;
1304 if(chan->out_mbuf_cur_len == 0)
1306 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1308 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1309 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1311 if(sc->sc_trace & TRACE_B_TX)
1313 i4b_trace_hdr_t hdr;
1314 hdr.unit = L0IFPI2UNIT(sc->sc_unit);
1315 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1317 hdr.count = ++sc->sc_trace_bcount;
1318 MICROTIME(hdr.time);
1319 i4b_l1_trace_ind(&hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1324 if (chan->bprot != BPROT_NONE)
1325 cmd |= HSCX_CMDR_XME;
1326 i4b_Bfreembuf(chan->out_mbuf_head);
1327 chan->out_mbuf_head = NULL;
1331 /* write what we have from the scratch buf to the HSCX fifo */
1333 HSCX_WRFIFO(chan->channel, scrbuf, len);
1337 /*---------------------------------------------------------------------------*
1338 * ifpi2 - ISAC interrupt routine
1339 *---------------------------------------------------------------------------*/
1341 ifpi2_isacsx_intr(struct l1_softc *sc)
1343 u_char isacsx_irq_stat;
1347 /* get isac irq status */
1348 /* ISTA tells us whether it was a C/I or HDLC int. */
1349 isacsx_irq_stat = ISAC_READ(I_ISTA);
1352 ifpi2_isacsx_irq(sc, isacsx_irq_stat); /* isac handler */
1357 ISAC_WRITE(I_MASKD, 0xff);
1358 ISAC_WRITE(I_MASK, 0xff);
1362 ISAC_WRITE(I_MASKD, isacsx_imaskd);
1363 ISAC_WRITE(I_MASK, isacsx_imask);
1366 /*---------------------------------------------------------------------------*
1367 * ifpi2_recover - try to recover from irq lockup
1368 *---------------------------------------------------------------------------*/
1370 ifpi2_recover(struct l1_softc *sc)
1372 kprintf("ifpi2_recover %d\n", sc->sc_unit);
1373 #if 0 /* fix me later */
1376 /* get isac irq status */
1378 byte = ISAC_READ(I_ISTA);
1380 NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
1382 if(byte & ISACSX_ISTA_EXI)
1383 NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
1385 if(byte & ISACSX_ISTA_CISQ)
1387 byte = ISAC_READ(I_CIRR);
1389 NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
1391 if(byte & ISACSX_CIRR_SQC)
1392 NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
1395 NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISACSX_IMASK);
1397 ISAC_WRITE(I_MASKD, 0xff);
1398 ISAC_WRITE(I_MASK, 0xff);
1400 ISAC_WRITE(I_MASKD, isacsx_imaskd);
1401 ISAC_WRITE(I_MASK, isacsx_imask);
1406 #endif /* NIFPI2 > 0 */