1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
348 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
349 union { rtx r; int i; enum machine_mode m; } old_contents;
350 union { rtx *r; int *i; } where;
353 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
354 num_undo says how many are currently recorded.
356 other_insn is nonzero if we have modified some other insn in the process
357 of working on subst_insn. It must be verified too. */
366 static struct undobuf undobuf;
368 /* Number of times the pseudo being substituted for
369 was found and replaced. */
371 static int n_occurrences;
373 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
375 unsigned HOST_WIDE_INT,
376 unsigned HOST_WIDE_INT *);
377 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
379 unsigned int, unsigned int *);
380 static void do_SUBST (rtx *, rtx);
381 static void do_SUBST_INT (int *, int);
382 static void init_reg_last (void);
383 static void setup_incoming_promotions (rtx);
384 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
385 static int cant_combine_insn_p (rtx);
386 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
387 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
388 static int contains_muldiv (rtx);
389 static rtx try_combine (rtx, rtx, rtx, int *);
390 static void undo_all (void);
391 static void undo_commit (void);
392 static rtx *find_split_point (rtx *, rtx);
393 static rtx subst (rtx, rtx, rtx, int, int);
394 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
395 static rtx simplify_if_then_else (rtx);
396 static rtx simplify_set (rtx);
397 static rtx simplify_logical (rtx);
398 static rtx expand_compound_operation (rtx);
399 static const_rtx expand_field_assignment (const_rtx);
400 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
401 rtx, unsigned HOST_WIDE_INT, int, int, int);
402 static rtx extract_left_shift (rtx, int);
403 static rtx make_compound_operation (rtx, enum rtx_code);
404 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
405 unsigned HOST_WIDE_INT *);
406 static rtx canon_reg_for_combine (rtx, rtx);
407 static rtx force_to_mode (rtx, enum machine_mode,
408 unsigned HOST_WIDE_INT, int);
409 static rtx if_then_else_cond (rtx, rtx *, rtx *);
410 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
411 static int rtx_equal_for_field_assignment_p (rtx, rtx);
412 static rtx make_field_assignment (rtx);
413 static rtx apply_distributive_law (rtx);
414 static rtx distribute_and_simplify_rtx (rtx, int);
415 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
416 unsigned HOST_WIDE_INT);
417 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
420 HOST_WIDE_INT, enum machine_mode, int *);
421 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
422 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
424 static int recog_for_combine (rtx *, rtx, rtx *);
425 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
426 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
427 static void update_table_tick (rtx);
428 static void record_value_for_reg (rtx, rtx, rtx);
429 static void check_promoted_subreg (rtx, rtx);
430 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
431 static void record_dead_and_set_regs (rtx);
432 static int get_last_value_validate (rtx *, rtx, int, int);
433 static rtx get_last_value (const_rtx);
434 static int use_crosses_set_p (const_rtx, int);
435 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
436 static int reg_dead_at_p (rtx, rtx);
437 static void move_deaths (rtx, rtx, int, rtx, rtx *);
438 static int reg_bitfield_target_p (rtx, rtx);
439 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
440 static void distribute_links (rtx);
441 static void mark_used_regs_combine (rtx);
442 static void record_promoted_value (rtx, rtx);
443 static int unmentioned_reg_p_1 (rtx *, void *);
444 static bool unmentioned_reg_p (rtx, rtx);
445 static int record_truncated_value (rtx *, void *);
446 static void record_truncated_values (rtx *, void *);
447 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
448 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
451 /* It is not safe to use ordinary gen_lowpart in combine.
452 See comments in gen_lowpart_for_combine. */
453 #undef RTL_HOOKS_GEN_LOWPART
454 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
456 /* Our implementation of gen_lowpart never emits a new pseudo. */
457 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
458 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
460 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
461 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
463 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
464 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
466 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
467 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
469 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
472 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
473 PATTERN can not be split. Otherwise, it returns an insn sequence.
474 This is a wrapper around split_insns which ensures that the
475 reg_stat vector is made larger if the splitter creates a new
479 combine_split_insns (rtx pattern, rtx insn)
484 ret = split_insns (pattern, insn);
485 nregs = max_reg_num ();
486 if (nregs > VEC_length (reg_stat_type, reg_stat))
487 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
491 /* This is used by find_single_use to locate an rtx in LOC that
492 contains exactly one use of DEST, which is typically either a REG
493 or CC0. It returns a pointer to the innermost rtx expression
494 containing DEST. Appearances of DEST that are being used to
495 totally replace it are not counted. */
498 find_single_use_1 (rtx dest, rtx *loc)
501 enum rtx_code code = GET_CODE (x);
519 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
520 of a REG that occupies all of the REG, the insn uses DEST if
521 it is mentioned in the destination or the source. Otherwise, we
522 need just check the source. */
523 if (GET_CODE (SET_DEST (x)) != CC0
524 && GET_CODE (SET_DEST (x)) != PC
525 && !REG_P (SET_DEST (x))
526 && ! (GET_CODE (SET_DEST (x)) == SUBREG
527 && REG_P (SUBREG_REG (SET_DEST (x)))
528 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
529 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
530 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
534 return find_single_use_1 (dest, &SET_SRC (x));
538 return find_single_use_1 (dest, &XEXP (x, 0));
544 /* If it wasn't one of the common cases above, check each expression and
545 vector of this code. Look for a unique usage of DEST. */
547 fmt = GET_RTX_FORMAT (code);
548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
552 if (dest == XEXP (x, i)
553 || (REG_P (dest) && REG_P (XEXP (x, i))
554 && REGNO (dest) == REGNO (XEXP (x, i))))
557 this_result = find_single_use_1 (dest, &XEXP (x, i));
560 result = this_result;
561 else if (this_result)
562 /* Duplicate usage. */
565 else if (fmt[i] == 'E')
569 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
571 if (XVECEXP (x, i, j) == dest
573 && REG_P (XVECEXP (x, i, j))
574 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
577 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
580 result = this_result;
581 else if (this_result)
591 /* See if DEST, produced in INSN, is used only a single time in the
592 sequel. If so, return a pointer to the innermost rtx expression in which
595 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
597 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
598 care about REG_DEAD notes or LOG_LINKS.
600 Otherwise, we find the single use by finding an insn that has a
601 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
602 only referenced once in that insn, we know that it must be the first
603 and last insn referencing DEST. */
606 find_single_use (rtx dest, rtx insn, rtx *ploc)
615 next = NEXT_INSN (insn);
617 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
620 result = find_single_use_1 (dest, &PATTERN (next));
630 for (next = next_nonnote_insn (insn);
631 next != 0 && !LABEL_P (next);
632 next = next_nonnote_insn (next))
633 if (INSN_P (next) && dead_or_set_p (next, dest))
635 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
636 if (XEXP (link, 0) == insn)
641 result = find_single_use_1 (dest, &PATTERN (next));
651 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
652 insn. The substitution can be undone by undo_all. If INTO is already
653 set to NEWVAL, do not record this change. Because computing NEWVAL might
654 also call SUBST, we have to compute it before we put anything into
658 do_SUBST (rtx *into, rtx newval)
663 if (oldval == newval)
666 /* We'd like to catch as many invalid transformations here as
667 possible. Unfortunately, there are way too many mode changes
668 that are perfectly valid, so we'd waste too much effort for
669 little gain doing the checks here. Focus on catching invalid
670 transformations involving integer constants. */
671 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
672 && GET_CODE (newval) == CONST_INT)
674 /* Sanity check that we're replacing oldval with a CONST_INT
675 that is a valid sign-extension for the original mode. */
676 gcc_assert (INTVAL (newval)
677 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
679 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
680 CONST_INT is not valid, because after the replacement, the
681 original mode would be gone. Unfortunately, we can't tell
682 when do_SUBST is called to replace the operand thereof, so we
683 perform this test on oldval instead, checking whether an
684 invalid replacement took place before we got here. */
685 gcc_assert (!(GET_CODE (oldval) == SUBREG
686 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
687 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
688 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
692 buf = undobuf.frees, undobuf.frees = buf->next;
694 buf = XNEW (struct undo);
696 buf->kind = UNDO_RTX;
698 buf->old_contents.r = oldval;
701 buf->next = undobuf.undos, undobuf.undos = buf;
704 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
706 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
707 for the value of a HOST_WIDE_INT value (including CONST_INT) is
711 do_SUBST_INT (int *into, int newval)
716 if (oldval == newval)
720 buf = undobuf.frees, undobuf.frees = buf->next;
722 buf = XNEW (struct undo);
724 buf->kind = UNDO_INT;
726 buf->old_contents.i = oldval;
729 buf->next = undobuf.undos, undobuf.undos = buf;
732 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
734 /* Similar to SUBST, but just substitute the mode. This is used when
735 changing the mode of a pseudo-register, so that any other
736 references to the entry in the regno_reg_rtx array will change as
740 do_SUBST_MODE (rtx *into, enum machine_mode newval)
743 enum machine_mode oldval = GET_MODE (*into);
745 if (oldval == newval)
749 buf = undobuf.frees, undobuf.frees = buf->next;
751 buf = XNEW (struct undo);
753 buf->kind = UNDO_MODE;
755 buf->old_contents.m = oldval;
756 adjust_reg_mode (*into, newval);
758 buf->next = undobuf.undos, undobuf.undos = buf;
761 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
763 /* Subroutine of try_combine. Determine whether the combine replacement
764 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
765 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
766 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
767 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
768 function returns false, if the costs of all instructions can be
769 estimated, and the replacements are more expensive than the original
773 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
776 int i1_cost, i2_cost, i3_cost;
777 int new_i2_cost, new_i3_cost;
778 int old_cost, new_cost;
780 /* Lookup the original insn_rtx_costs. */
781 i2_cost = INSN_COST (i2);
782 i3_cost = INSN_COST (i3);
786 i1_cost = INSN_COST (i1);
787 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
788 ? i1_cost + i2_cost + i3_cost : 0;
792 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
796 /* Calculate the replacement insn_rtx_costs. */
797 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
800 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
801 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
802 ? new_i2_cost + new_i3_cost : 0;
806 new_cost = new_i3_cost;
810 if (undobuf.other_insn)
812 int old_other_cost, new_other_cost;
814 old_other_cost = INSN_COST (undobuf.other_insn);
815 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
816 if (old_other_cost > 0 && new_other_cost > 0)
818 old_cost += old_other_cost;
819 new_cost += new_other_cost;
825 /* Disallow this recombination if both new_cost and old_cost are
826 greater than zero, and new_cost is greater than old cost. */
828 && new_cost > old_cost)
835 "rejecting combination of insns %d, %d and %d\n",
836 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
837 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
838 i1_cost, i2_cost, i3_cost, old_cost);
843 "rejecting combination of insns %d and %d\n",
844 INSN_UID (i2), INSN_UID (i3));
845 fprintf (dump_file, "original costs %d + %d = %d\n",
846 i2_cost, i3_cost, old_cost);
851 fprintf (dump_file, "replacement costs %d + %d = %d\n",
852 new_i2_cost, new_i3_cost, new_cost);
855 fprintf (dump_file, "replacement cost %d\n", new_cost);
861 /* Update the uid_insn_cost array with the replacement costs. */
862 INSN_COST (i2) = new_i2_cost;
863 INSN_COST (i3) = new_i3_cost;
871 /* Delete any insns that copy a register to itself. */
874 delete_noop_moves (void)
881 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
883 next = NEXT_INSN (insn);
884 if (INSN_P (insn) && noop_move_p (insn))
887 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
889 delete_insn_and_edges (insn);
896 /* Fill in log links field for all insns. */
899 create_log_links (void)
903 df_ref *def_vec, *use_vec;
905 next_use = XCNEWVEC (rtx, max_reg_num ());
907 /* Pass through each block from the end, recording the uses of each
908 register and establishing log links when def is encountered.
909 Note that we do not clear next_use array in order to save time,
910 so we have to test whether the use is in the same basic block as def.
912 There are a few cases below when we do not consider the definition or
913 usage -- these are taken from original flow.c did. Don't ask me why it is
914 done this way; I don't know and if it works, I don't want to know. */
918 FOR_BB_INSNS_REVERSE (bb, insn)
923 /* Log links are created only once. */
924 gcc_assert (!LOG_LINKS (insn));
926 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
928 df_ref def = *def_vec;
929 int regno = DF_REF_REGNO (def);
932 if (!next_use[regno])
935 /* Do not consider if it is pre/post modification in MEM. */
936 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
939 /* Do not make the log link for frame pointer. */
940 if ((regno == FRAME_POINTER_REGNUM
941 && (! reload_completed || frame_pointer_needed))
942 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
943 || (regno == HARD_FRAME_POINTER_REGNUM
944 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
947 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
952 use_insn = next_use[regno];
953 if (BLOCK_FOR_INSN (use_insn) == bb)
957 We don't build a LOG_LINK for hard registers contained
958 in ASM_OPERANDs. If these registers get replaced,
959 we might wind up changing the semantics of the insn,
960 even if reload can make what appear to be valid
961 assignments later. */
962 if (regno >= FIRST_PSEUDO_REGISTER
963 || asm_noperands (PATTERN (use_insn)) < 0)
965 /* Don't add duplicate links between instructions. */
967 for (links = LOG_LINKS (use_insn); links;
968 links = XEXP (links, 1))
969 if (insn == XEXP (links, 0))
973 LOG_LINKS (use_insn) =
974 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
977 next_use[regno] = NULL_RTX;
980 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
982 df_ref use = *use_vec;
983 int regno = DF_REF_REGNO (use);
985 /* Do not consider the usage of the stack pointer
987 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
990 next_use[regno] = insn;
998 /* Clear LOG_LINKS fields of insns. */
1001 clear_log_links (void)
1005 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1007 free_INSN_LIST_list (&LOG_LINKS (insn));
1013 /* Main entry point for combiner. F is the first insn of the function.
1014 NREGS is the first unused pseudo-reg number.
1016 Return nonzero if the combiner has turned an indirect jump
1017 instruction into a direct jump. */
1019 combine_instructions (rtx f, unsigned int nregs)
1025 rtx links, nextlinks;
1028 int new_direct_jump_p = 0;
1030 for (first = f; first && !INSN_P (first); )
1031 first = NEXT_INSN (first);
1035 combine_attempts = 0;
1038 combine_successes = 0;
1040 rtl_hooks = combine_rtl_hooks;
1042 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1044 init_recog_no_volatile ();
1046 /* Allocate array for insn info. */
1047 max_uid_known = get_max_uid ();
1048 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1049 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1051 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1053 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1054 problems when, for example, we have j <<= 1 in a loop. */
1056 nonzero_sign_valid = 0;
1058 /* Scan all SETs and see if we can deduce anything about what
1059 bits are known to be zero for some registers and how many copies
1060 of the sign bit are known to exist for those registers.
1062 Also set any known values so that we can use it while searching
1063 for what bits are known to be set. */
1065 label_tick = label_tick_ebb_start = 1;
1067 setup_incoming_promotions (first);
1069 create_log_links ();
1070 FOR_EACH_BB (this_basic_block)
1072 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1076 FOR_BB_INSNS (this_basic_block, insn)
1077 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1079 subst_low_luid = DF_INSN_LUID (insn);
1082 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1084 record_dead_and_set_regs (insn);
1087 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1088 if (REG_NOTE_KIND (links) == REG_INC)
1089 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1093 /* Record the current insn_rtx_cost of this instruction. */
1094 if (NONJUMP_INSN_P (insn))
1095 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1096 optimize_this_for_speed_p);
1098 fprintf(dump_file, "insn_cost %d: %d\n",
1099 INSN_UID (insn), INSN_COST (insn));
1101 else if (LABEL_P (insn))
1102 label_tick_ebb_start = label_tick;
1105 nonzero_sign_valid = 1;
1107 /* Now scan all the insns in forward order. */
1109 label_tick = label_tick_ebb_start = 1;
1111 setup_incoming_promotions (first);
1113 FOR_EACH_BB (this_basic_block)
1115 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1119 rtl_profile_for_bb (this_basic_block);
1120 for (insn = BB_HEAD (this_basic_block);
1121 insn != NEXT_INSN (BB_END (this_basic_block));
1122 insn = next ? next : NEXT_INSN (insn))
1127 /* See if we know about function return values before this
1128 insn based upon SUBREG flags. */
1129 check_promoted_subreg (insn, PATTERN (insn));
1131 /* See if we can find hardregs and subreg of pseudos in
1132 narrower modes. This could help turning TRUNCATEs
1134 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1136 /* Try this insn with each insn it links back to. */
1138 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1139 if ((next = try_combine (insn, XEXP (links, 0),
1140 NULL_RTX, &new_direct_jump_p)) != 0)
1143 /* Try each sequence of three linked insns ending with this one. */
1145 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1147 rtx link = XEXP (links, 0);
1149 /* If the linked insn has been replaced by a note, then there
1150 is no point in pursuing this chain any further. */
1154 for (nextlinks = LOG_LINKS (link);
1156 nextlinks = XEXP (nextlinks, 1))
1157 if ((next = try_combine (insn, link,
1158 XEXP (nextlinks, 0),
1159 &new_direct_jump_p)) != 0)
1164 /* Try to combine a jump insn that uses CC0
1165 with a preceding insn that sets CC0, and maybe with its
1166 logical predecessor as well.
1167 This is how we make decrement-and-branch insns.
1168 We need this special code because data flow connections
1169 via CC0 do not get entered in LOG_LINKS. */
1172 && (prev = prev_nonnote_insn (insn)) != 0
1173 && NONJUMP_INSN_P (prev)
1174 && sets_cc0_p (PATTERN (prev)))
1176 if ((next = try_combine (insn, prev,
1177 NULL_RTX, &new_direct_jump_p)) != 0)
1180 for (nextlinks = LOG_LINKS (prev); nextlinks;
1181 nextlinks = XEXP (nextlinks, 1))
1182 if ((next = try_combine (insn, prev,
1183 XEXP (nextlinks, 0),
1184 &new_direct_jump_p)) != 0)
1188 /* Do the same for an insn that explicitly references CC0. */
1189 if (NONJUMP_INSN_P (insn)
1190 && (prev = prev_nonnote_insn (insn)) != 0
1191 && NONJUMP_INSN_P (prev)
1192 && sets_cc0_p (PATTERN (prev))
1193 && GET_CODE (PATTERN (insn)) == SET
1194 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1196 if ((next = try_combine (insn, prev,
1197 NULL_RTX, &new_direct_jump_p)) != 0)
1200 for (nextlinks = LOG_LINKS (prev); nextlinks;
1201 nextlinks = XEXP (nextlinks, 1))
1202 if ((next = try_combine (insn, prev,
1203 XEXP (nextlinks, 0),
1204 &new_direct_jump_p)) != 0)
1208 /* Finally, see if any of the insns that this insn links to
1209 explicitly references CC0. If so, try this insn, that insn,
1210 and its predecessor if it sets CC0. */
1211 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1212 if (NONJUMP_INSN_P (XEXP (links, 0))
1213 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1214 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1215 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1216 && NONJUMP_INSN_P (prev)
1217 && sets_cc0_p (PATTERN (prev))
1218 && (next = try_combine (insn, XEXP (links, 0),
1219 prev, &new_direct_jump_p)) != 0)
1223 /* Try combining an insn with two different insns whose results it
1225 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1226 for (nextlinks = XEXP (links, 1); nextlinks;
1227 nextlinks = XEXP (nextlinks, 1))
1228 if ((next = try_combine (insn, XEXP (links, 0),
1229 XEXP (nextlinks, 0),
1230 &new_direct_jump_p)) != 0)
1233 /* Try this insn with each REG_EQUAL note it links back to. */
1234 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1237 rtx temp = XEXP (links, 0);
1238 if ((set = single_set (temp)) != 0
1239 && (note = find_reg_equal_equiv_note (temp)) != 0
1240 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1241 /* Avoid using a register that may already been marked
1242 dead by an earlier instruction. */
1243 && ! unmentioned_reg_p (note, SET_SRC (set))
1244 && (GET_MODE (note) == VOIDmode
1245 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1246 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1248 /* Temporarily replace the set's source with the
1249 contents of the REG_EQUAL note. The insn will
1250 be deleted or recognized by try_combine. */
1251 rtx orig = SET_SRC (set);
1252 SET_SRC (set) = note;
1254 i2mod_old_rhs = copy_rtx (orig);
1255 i2mod_new_rhs = copy_rtx (note);
1256 next = try_combine (insn, i2mod, NULL_RTX,
1257 &new_direct_jump_p);
1261 SET_SRC (set) = orig;
1266 record_dead_and_set_regs (insn);
1271 else if (LABEL_P (insn))
1272 label_tick_ebb_start = label_tick;
1276 default_rtl_profile ();
1279 new_direct_jump_p |= purge_all_dead_edges ();
1280 delete_noop_moves ();
1283 free (uid_log_links);
1284 free (uid_insn_cost);
1285 VEC_free (reg_stat_type, heap, reg_stat);
1288 struct undo *undo, *next;
1289 for (undo = undobuf.frees; undo; undo = next)
1297 total_attempts += combine_attempts;
1298 total_merges += combine_merges;
1299 total_extras += combine_extras;
1300 total_successes += combine_successes;
1302 nonzero_sign_valid = 0;
1303 rtl_hooks = general_rtl_hooks;
1305 /* Make recognizer allow volatile MEMs again. */
1308 return new_direct_jump_p;
1311 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1314 init_reg_last (void)
1319 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1320 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1323 /* Set up any promoted values for incoming argument registers. */
1326 setup_incoming_promotions (rtx first)
1329 bool strictly_local = false;
1331 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1334 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1335 arg = TREE_CHAIN (arg))
1337 rtx reg = DECL_INCOMING_RTL (arg);
1339 enum machine_mode mode1, mode2, mode3, mode4;
1341 /* Only continue if the incoming argument is in a register. */
1345 /* Determine, if possible, whether all call sites of the current
1346 function lie within the current compilation unit. (This does
1347 take into account the exporting of a function via taking its
1348 address, and so forth.) */
1349 strictly_local = cgraph_local_info (current_function_decl)->local;
1351 /* The mode and signedness of the argument before any promotions happen
1352 (equal to the mode of the pseudo holding it at that stage). */
1353 mode1 = TYPE_MODE (TREE_TYPE (arg));
1354 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1356 /* The mode and signedness of the argument after any source language and
1357 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1358 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1359 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1361 /* The mode and signedness of the argument as it is actually passed,
1362 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1363 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1365 /* The mode of the register in which the argument is being passed. */
1366 mode4 = GET_MODE (reg);
1368 /* Eliminate sign extensions in the callee when possible. Only
1370 (a) a mode promotion has occurred;
1371 (b) the mode of the register is the same as the mode of
1372 the argument as it is passed; and
1373 (c) the signedness does not change across any of the promotions; and
1374 (d) when no language-level promotions (which we cannot guarantee
1375 will have been done by an external caller) are necessary,
1376 unless we know that this function is only ever called from
1377 the current compilation unit -- all of whose call sites will
1378 do the mode1 --> mode2 promotion. */
1382 && (mode1 == mode2 || strictly_local))
1384 /* Record that the value was promoted from mode1 to mode3,
1385 so that any sign extension at the head of the current
1386 function may be eliminated. */
1388 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1389 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1390 record_value_for_reg (reg, first, x);
1395 /* Called via note_stores. If X is a pseudo that is narrower than
1396 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1398 If we are setting only a portion of X and we can't figure out what
1399 portion, assume all bits will be used since we don't know what will
1402 Similarly, set how many bits of X are known to be copies of the sign bit
1403 at all locations in the function. This is the smallest number implied
1407 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1409 rtx insn = (rtx) data;
1413 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1414 /* If this register is undefined at the start of the file, we can't
1415 say what its contents were. */
1416 && ! REGNO_REG_SET_P
1417 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1418 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1420 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1422 if (set == 0 || GET_CODE (set) == CLOBBER)
1424 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1425 rsp->sign_bit_copies = 1;
1429 /* If this register is being initialized using itself, and the
1430 register is uninitialized in this basic block, and there are
1431 no LOG_LINKS which set the register, then part of the
1432 register is uninitialized. In that case we can't assume
1433 anything about the number of nonzero bits.
1435 ??? We could do better if we checked this in
1436 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1437 could avoid making assumptions about the insn which initially
1438 sets the register, while still using the information in other
1439 insns. We would have to be careful to check every insn
1440 involved in the combination. */
1443 && reg_referenced_p (x, PATTERN (insn))
1444 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1449 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1451 if (dead_or_set_p (XEXP (link, 0), x))
1456 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1457 rsp->sign_bit_copies = 1;
1462 /* If this is a complex assignment, see if we can convert it into a
1463 simple assignment. */
1464 set = expand_field_assignment (set);
1466 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1467 set what we know about X. */
1469 if (SET_DEST (set) == x
1470 || (GET_CODE (SET_DEST (set)) == SUBREG
1471 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1472 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1473 && SUBREG_REG (SET_DEST (set)) == x))
1475 rtx src = SET_SRC (set);
1477 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1478 /* If X is narrower than a word and SRC is a non-negative
1479 constant that would appear negative in the mode of X,
1480 sign-extend it for use in reg_stat[].nonzero_bits because some
1481 machines (maybe most) will actually do the sign-extension
1482 and this is the conservative approach.
1484 ??? For 2.5, try to tighten up the MD files in this regard
1485 instead of this kludge. */
1487 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1488 && GET_CODE (src) == CONST_INT
1490 && 0 != (INTVAL (src)
1491 & ((HOST_WIDE_INT) 1
1492 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1493 src = GEN_INT (INTVAL (src)
1494 | ((HOST_WIDE_INT) (-1)
1495 << GET_MODE_BITSIZE (GET_MODE (x))));
1498 /* Don't call nonzero_bits if it cannot change anything. */
1499 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1500 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1501 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1502 if (rsp->sign_bit_copies == 0
1503 || rsp->sign_bit_copies > num)
1504 rsp->sign_bit_copies = num;
1508 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1509 rsp->sign_bit_copies = 1;
1514 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1515 insns that were previously combined into I3 or that will be combined
1516 into the merger of INSN and I3.
1518 Return 0 if the combination is not allowed for any reason.
1520 If the combination is allowed, *PDEST will be set to the single
1521 destination of INSN and *PSRC to the single source, and this function
1525 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1526 rtx *pdest, rtx *psrc)
1535 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1536 && next_active_insn (succ) == i3)
1537 : next_active_insn (insn) == i3);
1539 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1540 or a PARALLEL consisting of such a SET and CLOBBERs.
1542 If INSN has CLOBBER parallel parts, ignore them for our processing.
1543 By definition, these happen during the execution of the insn. When it
1544 is merged with another insn, all bets are off. If they are, in fact,
1545 needed and aren't also supplied in I3, they may be added by
1546 recog_for_combine. Otherwise, it won't match.
1548 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1551 Get the source and destination of INSN. If more than one, can't
1554 if (GET_CODE (PATTERN (insn)) == SET)
1555 set = PATTERN (insn);
1556 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1557 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1559 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1561 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1564 switch (GET_CODE (elt))
1566 /* This is important to combine floating point insns
1567 for the SH4 port. */
1569 /* Combining an isolated USE doesn't make sense.
1570 We depend here on combinable_i3pat to reject them. */
1571 /* The code below this loop only verifies that the inputs of
1572 the SET in INSN do not change. We call reg_set_between_p
1573 to verify that the REG in the USE does not change between
1575 If the USE in INSN was for a pseudo register, the matching
1576 insn pattern will likely match any register; combining this
1577 with any other USE would only be safe if we knew that the
1578 used registers have identical values, or if there was
1579 something to tell them apart, e.g. different modes. For
1580 now, we forgo such complicated tests and simply disallow
1581 combining of USES of pseudo registers with any other USE. */
1582 if (REG_P (XEXP (elt, 0))
1583 && GET_CODE (PATTERN (i3)) == PARALLEL)
1585 rtx i3pat = PATTERN (i3);
1586 int i = XVECLEN (i3pat, 0) - 1;
1587 unsigned int regno = REGNO (XEXP (elt, 0));
1591 rtx i3elt = XVECEXP (i3pat, 0, i);
1593 if (GET_CODE (i3elt) == USE
1594 && REG_P (XEXP (i3elt, 0))
1595 && (REGNO (XEXP (i3elt, 0)) == regno
1596 ? reg_set_between_p (XEXP (elt, 0),
1597 PREV_INSN (insn), i3)
1598 : regno >= FIRST_PSEUDO_REGISTER))
1605 /* We can ignore CLOBBERs. */
1610 /* Ignore SETs whose result isn't used but not those that
1611 have side-effects. */
1612 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1613 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1614 || INTVAL (XEXP (note, 0)) <= 0)
1615 && ! side_effects_p (elt))
1618 /* If we have already found a SET, this is a second one and
1619 so we cannot combine with this insn. */
1627 /* Anything else means we can't combine. */
1633 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1634 so don't do anything with it. */
1635 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1644 set = expand_field_assignment (set);
1645 src = SET_SRC (set), dest = SET_DEST (set);
1647 /* Don't eliminate a store in the stack pointer. */
1648 if (dest == stack_pointer_rtx
1649 /* Don't combine with an insn that sets a register to itself if it has
1650 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1651 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1652 /* Can't merge an ASM_OPERANDS. */
1653 || GET_CODE (src) == ASM_OPERANDS
1654 /* Can't merge a function call. */
1655 || GET_CODE (src) == CALL
1656 /* Don't eliminate a function call argument. */
1658 && (find_reg_fusage (i3, USE, dest)
1660 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1661 && global_regs[REGNO (dest)])))
1662 /* Don't substitute into an incremented register. */
1663 || FIND_REG_INC_NOTE (i3, dest)
1664 || (succ && FIND_REG_INC_NOTE (succ, dest))
1665 /* Don't substitute into a non-local goto, this confuses CFG. */
1666 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1667 /* Make sure that DEST is not used after SUCC but before I3. */
1668 || (succ && ! all_adjacent
1669 && reg_used_between_p (dest, succ, i3))
1670 /* Make sure that the value that is to be substituted for the register
1671 does not use any registers whose values alter in between. However,
1672 If the insns are adjacent, a use can't cross a set even though we
1673 think it might (this can happen for a sequence of insns each setting
1674 the same destination; last_set of that register might point to
1675 a NOTE). If INSN has a REG_EQUIV note, the register is always
1676 equivalent to the memory so the substitution is valid even if there
1677 are intervening stores. Also, don't move a volatile asm or
1678 UNSPEC_VOLATILE across any other insns. */
1681 || ! find_reg_note (insn, REG_EQUIV, src))
1682 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1683 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1684 || GET_CODE (src) == UNSPEC_VOLATILE))
1685 /* Don't combine across a CALL_INSN, because that would possibly
1686 change whether the life span of some REGs crosses calls or not,
1687 and it is a pain to update that information.
1688 Exception: if source is a constant, moving it later can't hurt.
1689 Accept that as a special case. */
1690 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1693 /* DEST must either be a REG or CC0. */
1696 /* If register alignment is being enforced for multi-word items in all
1697 cases except for parameters, it is possible to have a register copy
1698 insn referencing a hard register that is not allowed to contain the
1699 mode being copied and which would not be valid as an operand of most
1700 insns. Eliminate this problem by not combining with such an insn.
1702 Also, on some machines we don't want to extend the life of a hard
1706 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1707 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1708 /* Don't extend the life of a hard register unless it is
1709 user variable (if we have few registers) or it can't
1710 fit into the desired register (meaning something special
1712 Also avoid substituting a return register into I3, because
1713 reload can't handle a conflict with constraints of other
1715 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1716 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1719 else if (GET_CODE (dest) != CC0)
1723 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1724 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1725 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1727 /* Don't substitute for a register intended as a clobberable
1729 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1730 if (rtx_equal_p (reg, dest))
1733 /* If the clobber represents an earlyclobber operand, we must not
1734 substitute an expression containing the clobbered register.
1735 As we do not analyze the constraint strings here, we have to
1736 make the conservative assumption. However, if the register is
1737 a fixed hard reg, the clobber cannot represent any operand;
1738 we leave it up to the machine description to either accept or
1739 reject use-and-clobber patterns. */
1741 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1742 || !fixed_regs[REGNO (reg)])
1743 if (reg_overlap_mentioned_p (reg, src))
1747 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1748 or not), reject, unless nothing volatile comes between it and I3 */
1750 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1752 /* Make sure succ doesn't contain a volatile reference. */
1753 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1756 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1757 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1761 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1762 to be an explicit register variable, and was chosen for a reason. */
1764 if (GET_CODE (src) == ASM_OPERANDS
1765 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1768 /* If there are any volatile insns between INSN and I3, reject, because
1769 they might affect machine state. */
1771 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1772 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1775 /* If INSN contains an autoincrement or autodecrement, make sure that
1776 register is not used between there and I3, and not already used in
1777 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1778 Also insist that I3 not be a jump; if it were one
1779 and the incremented register were spilled, we would lose. */
1782 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1783 if (REG_NOTE_KIND (link) == REG_INC
1785 || reg_used_between_p (XEXP (link, 0), insn, i3)
1786 || (pred != NULL_RTX
1787 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1788 || (succ != NULL_RTX
1789 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1790 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1795 /* Don't combine an insn that follows a CC0-setting insn.
1796 An insn that uses CC0 must not be separated from the one that sets it.
1797 We do, however, allow I2 to follow a CC0-setting insn if that insn
1798 is passed as I1; in that case it will be deleted also.
1799 We also allow combining in this case if all the insns are adjacent
1800 because that would leave the two CC0 insns adjacent as well.
1801 It would be more logical to test whether CC0 occurs inside I1 or I2,
1802 but that would be much slower, and this ought to be equivalent. */
1804 p = prev_nonnote_insn (insn);
1805 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1810 /* If we get here, we have passed all the tests and the combination is
1819 /* LOC is the location within I3 that contains its pattern or the component
1820 of a PARALLEL of the pattern. We validate that it is valid for combining.
1822 One problem is if I3 modifies its output, as opposed to replacing it
1823 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1824 so would produce an insn that is not equivalent to the original insns.
1828 (set (reg:DI 101) (reg:DI 100))
1829 (set (subreg:SI (reg:DI 101) 0) <foo>)
1831 This is NOT equivalent to:
1833 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1834 (set (reg:DI 101) (reg:DI 100))])
1836 Not only does this modify 100 (in which case it might still be valid
1837 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1839 We can also run into a problem if I2 sets a register that I1
1840 uses and I1 gets directly substituted into I3 (not via I2). In that
1841 case, we would be getting the wrong value of I2DEST into I3, so we
1842 must reject the combination. This case occurs when I2 and I1 both
1843 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1844 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1845 of a SET must prevent combination from occurring.
1847 Before doing the above check, we first try to expand a field assignment
1848 into a set of logical operations.
1850 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1851 we place a register that is both set and used within I3. If more than one
1852 such register is detected, we fail.
1854 Return 1 if the combination is valid, zero otherwise. */
1857 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1858 int i1_not_in_src, rtx *pi3dest_killed)
1862 if (GET_CODE (x) == SET)
1865 rtx dest = SET_DEST (set);
1866 rtx src = SET_SRC (set);
1867 rtx inner_dest = dest;
1870 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1871 || GET_CODE (inner_dest) == SUBREG
1872 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1873 inner_dest = XEXP (inner_dest, 0);
1875 /* Check for the case where I3 modifies its output, as discussed
1876 above. We don't want to prevent pseudos from being combined
1877 into the address of a MEM, so only prevent the combination if
1878 i1 or i2 set the same MEM. */
1879 if ((inner_dest != dest &&
1880 (!MEM_P (inner_dest)
1881 || rtx_equal_p (i2dest, inner_dest)
1882 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1883 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1884 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1886 /* This is the same test done in can_combine_p except we can't test
1887 all_adjacent; we don't have to, since this instruction will stay
1888 in place, thus we are not considering increasing the lifetime of
1891 Also, if this insn sets a function argument, combining it with
1892 something that might need a spill could clobber a previous
1893 function argument; the all_adjacent test in can_combine_p also
1894 checks this; here, we do a more specific test for this case. */
1896 || (REG_P (inner_dest)
1897 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1898 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1899 GET_MODE (inner_dest))))
1900 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1903 /* If DEST is used in I3, it is being killed in this insn, so
1904 record that for later. We have to consider paradoxical
1905 subregs here, since they kill the whole register, but we
1906 ignore partial subregs, STRICT_LOW_PART, etc.
1907 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1908 STACK_POINTER_REGNUM, since these are always considered to be
1909 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1911 if (GET_CODE (subdest) == SUBREG
1912 && (GET_MODE_SIZE (GET_MODE (subdest))
1913 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1914 subdest = SUBREG_REG (subdest);
1917 && reg_referenced_p (subdest, PATTERN (i3))
1918 && REGNO (subdest) != FRAME_POINTER_REGNUM
1919 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1920 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1922 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1923 && (REGNO (subdest) != ARG_POINTER_REGNUM
1924 || ! fixed_regs [REGNO (subdest)])
1926 && REGNO (subdest) != STACK_POINTER_REGNUM)
1928 if (*pi3dest_killed)
1931 *pi3dest_killed = subdest;
1935 else if (GET_CODE (x) == PARALLEL)
1939 for (i = 0; i < XVECLEN (x, 0); i++)
1940 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1941 i1_not_in_src, pi3dest_killed))
1948 /* Return 1 if X is an arithmetic expression that contains a multiplication
1949 and division. We don't count multiplications by powers of two here. */
1952 contains_muldiv (rtx x)
1954 switch (GET_CODE (x))
1956 case MOD: case DIV: case UMOD: case UDIV:
1960 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1961 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1964 return contains_muldiv (XEXP (x, 0))
1965 || contains_muldiv (XEXP (x, 1));
1968 return contains_muldiv (XEXP (x, 0));
1974 /* Determine whether INSN can be used in a combination. Return nonzero if
1975 not. This is used in try_combine to detect early some cases where we
1976 can't perform combinations. */
1979 cant_combine_insn_p (rtx insn)
1984 /* If this isn't really an insn, we can't do anything.
1985 This can occur when flow deletes an insn that it has merged into an
1986 auto-increment address. */
1987 if (! INSN_P (insn))
1990 /* Never combine loads and stores involving hard regs that are likely
1991 to be spilled. The register allocator can usually handle such
1992 reg-reg moves by tying. If we allow the combiner to make
1993 substitutions of likely-spilled regs, reload might die.
1994 As an exception, we allow combinations involving fixed regs; these are
1995 not available to the register allocator so there's no risk involved. */
1997 set = single_set (insn);
2000 src = SET_SRC (set);
2001 dest = SET_DEST (set);
2002 if (GET_CODE (src) == SUBREG)
2003 src = SUBREG_REG (src);
2004 if (GET_CODE (dest) == SUBREG)
2005 dest = SUBREG_REG (dest);
2006 if (REG_P (src) && REG_P (dest)
2007 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2008 && ! fixed_regs[REGNO (src)]
2009 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2010 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2011 && ! fixed_regs[REGNO (dest)]
2012 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2018 struct likely_spilled_retval_info
2020 unsigned regno, nregs;
2024 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2025 hard registers that are known to be written to / clobbered in full. */
2027 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2029 struct likely_spilled_retval_info *const info =
2030 (struct likely_spilled_retval_info *) data;
2031 unsigned regno, nregs;
2034 if (!REG_P (XEXP (set, 0)))
2037 if (regno >= info->regno + info->nregs)
2039 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2040 if (regno + nregs <= info->regno)
2042 new_mask = (2U << (nregs - 1)) - 1;
2043 if (regno < info->regno)
2044 new_mask >>= info->regno - regno;
2046 new_mask <<= regno - info->regno;
2047 info->mask &= ~new_mask;
2050 /* Return nonzero iff part of the return value is live during INSN, and
2051 it is likely spilled. This can happen when more than one insn is needed
2052 to copy the return value, e.g. when we consider to combine into the
2053 second copy insn for a complex value. */
2056 likely_spilled_retval_p (rtx insn)
2058 rtx use = BB_END (this_basic_block);
2060 unsigned regno, nregs;
2061 /* We assume here that no machine mode needs more than
2062 32 hard registers when the value overlaps with a register
2063 for which FUNCTION_VALUE_REGNO_P is true. */
2065 struct likely_spilled_retval_info info;
2067 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2069 reg = XEXP (PATTERN (use), 0);
2070 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2072 regno = REGNO (reg);
2073 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2076 mask = (2U << (nregs - 1)) - 1;
2078 /* Disregard parts of the return value that are set later. */
2082 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2084 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2087 /* Check if any of the (probably) live return value registers is
2092 if ((mask & 1 << nregs)
2093 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2099 /* Adjust INSN after we made a change to its destination.
2101 Changing the destination can invalidate notes that say something about
2102 the results of the insn and a LOG_LINK pointing to the insn. */
2105 adjust_for_new_dest (rtx insn)
2107 /* For notes, be conservative and simply remove them. */
2108 remove_reg_equal_equiv_notes (insn);
2110 /* The new insn will have a destination that was previously the destination
2111 of an insn just above it. Call distribute_links to make a LOG_LINK from
2112 the next use of that destination. */
2113 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2115 df_insn_rescan (insn);
2118 /* Return TRUE if combine can reuse reg X in mode MODE.
2119 ADDED_SETS is nonzero if the original set is still required. */
2121 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2129 /* Allow hard registers if the new mode is legal, and occupies no more
2130 registers than the old mode. */
2131 if (regno < FIRST_PSEUDO_REGISTER)
2132 return (HARD_REGNO_MODE_OK (regno, mode)
2133 && (hard_regno_nregs[regno][GET_MODE (x)]
2134 >= hard_regno_nregs[regno][mode]));
2136 /* Or a pseudo that is only used once. */
2137 return (REG_N_SETS (regno) == 1 && !added_sets
2138 && !REG_USERVAR_P (x));
2142 /* Check whether X, the destination of a set, refers to part of
2143 the register specified by REG. */
2146 reg_subword_p (rtx x, rtx reg)
2148 /* Check that reg is an integer mode register. */
2149 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2152 if (GET_CODE (x) == STRICT_LOW_PART
2153 || GET_CODE (x) == ZERO_EXTRACT)
2156 return GET_CODE (x) == SUBREG
2157 && SUBREG_REG (x) == reg
2158 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2162 /* Try to combine the insns I1 and I2 into I3.
2163 Here I1 and I2 appear earlier than I3.
2164 I1 can be zero; then we combine just I2 into I3.
2166 If we are combining three insns and the resulting insn is not recognized,
2167 try splitting it into two insns. If that happens, I2 and I3 are retained
2168 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2171 Return 0 if the combination does not work. Then nothing is changed.
2172 If we did the combination, return the insn at which combine should
2175 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2176 new direct jump instruction. */
2179 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2181 /* New patterns for I3 and I2, respectively. */
2182 rtx newpat, newi2pat = 0;
2183 rtvec newpat_vec_with_clobbers = 0;
2184 int substed_i2 = 0, substed_i1 = 0;
2185 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2186 int added_sets_1, added_sets_2;
2187 /* Total number of SETs to put into I3. */
2189 /* Nonzero if I2's body now appears in I3. */
2191 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2192 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2193 /* Contains I3 if the destination of I3 is used in its source, which means
2194 that the old life of I3 is being killed. If that usage is placed into
2195 I2 and not in I3, a REG_DEAD note must be made. */
2196 rtx i3dest_killed = 0;
2197 /* SET_DEST and SET_SRC of I2 and I1. */
2198 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2199 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2200 rtx i1pat = 0, i2pat = 0;
2201 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2202 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2203 int i2dest_killed = 0, i1dest_killed = 0;
2204 int i1_feeds_i3 = 0;
2205 /* Notes that must be added to REG_NOTES in I3 and I2. */
2206 rtx new_i3_notes, new_i2_notes;
2207 /* Notes that we substituted I3 into I2 instead of the normal case. */
2208 int i3_subst_into_i2 = 0;
2209 /* Notes that I1, I2 or I3 is a MULT operation. */
2212 int changed_i3_dest = 0;
2218 rtx new_other_notes;
2221 /* Exit early if one of the insns involved can't be used for
2223 if (cant_combine_insn_p (i3)
2224 || cant_combine_insn_p (i2)
2225 || (i1 && cant_combine_insn_p (i1))
2226 || likely_spilled_retval_p (i3))
2230 undobuf.other_insn = 0;
2232 /* Reset the hard register usage information. */
2233 CLEAR_HARD_REG_SET (newpat_used_regs);
2235 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2236 code below, set I1 to be the earlier of the two insns. */
2237 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2238 temp = i1, i1 = i2, i2 = temp;
2240 added_links_insn = 0;
2242 /* First check for one important special-case that the code below will
2243 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2244 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2245 we may be able to replace that destination with the destination of I3.
2246 This occurs in the common code where we compute both a quotient and
2247 remainder into a structure, in which case we want to do the computation
2248 directly into the structure to avoid register-register copies.
2250 Note that this case handles both multiple sets in I2 and also
2251 cases where I2 has a number of CLOBBER or PARALLELs.
2253 We make very conservative checks below and only try to handle the
2254 most common cases of this. For example, we only handle the case
2255 where I2 and I3 are adjacent to avoid making difficult register
2258 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2259 && REG_P (SET_SRC (PATTERN (i3)))
2260 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2261 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2262 && GET_CODE (PATTERN (i2)) == PARALLEL
2263 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2264 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2265 below would need to check what is inside (and reg_overlap_mentioned_p
2266 doesn't support those codes anyway). Don't allow those destinations;
2267 the resulting insn isn't likely to be recognized anyway. */
2268 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2269 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2270 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2271 SET_DEST (PATTERN (i3)))
2272 && next_real_insn (i2) == i3)
2274 rtx p2 = PATTERN (i2);
2276 /* Make sure that the destination of I3,
2277 which we are going to substitute into one output of I2,
2278 is not used within another output of I2. We must avoid making this:
2279 (parallel [(set (mem (reg 69)) ...)
2280 (set (reg 69) ...)])
2281 which is not well-defined as to order of actions.
2282 (Besides, reload can't handle output reloads for this.)
2284 The problem can also happen if the dest of I3 is a memory ref,
2285 if another dest in I2 is an indirect memory ref. */
2286 for (i = 0; i < XVECLEN (p2, 0); i++)
2287 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2288 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2289 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2290 SET_DEST (XVECEXP (p2, 0, i))))
2293 if (i == XVECLEN (p2, 0))
2294 for (i = 0; i < XVECLEN (p2, 0); i++)
2295 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2296 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2297 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2302 subst_low_luid = DF_INSN_LUID (i2);
2304 added_sets_2 = added_sets_1 = 0;
2305 i2dest = SET_SRC (PATTERN (i3));
2306 i2dest_killed = dead_or_set_p (i2, i2dest);
2308 /* Replace the dest in I2 with our dest and make the resulting
2309 insn the new pattern for I3. Then skip to where we
2310 validate the pattern. Everything was set up above. */
2311 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2312 SET_DEST (PATTERN (i3)));
2315 i3_subst_into_i2 = 1;
2316 goto validate_replacement;
2320 /* If I2 is setting a pseudo to a constant and I3 is setting some
2321 sub-part of it to another constant, merge them by making a new
2324 && (temp = single_set (i2)) != 0
2325 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2326 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2327 && GET_CODE (PATTERN (i3)) == SET
2328 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2329 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2330 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2332 rtx dest = SET_DEST (PATTERN (i3));
2336 if (GET_CODE (dest) == ZERO_EXTRACT)
2338 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2339 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2341 width = INTVAL (XEXP (dest, 1));
2342 offset = INTVAL (XEXP (dest, 2));
2343 dest = XEXP (dest, 0);
2344 if (BITS_BIG_ENDIAN)
2345 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2350 if (GET_CODE (dest) == STRICT_LOW_PART)
2351 dest = XEXP (dest, 0);
2352 width = GET_MODE_BITSIZE (GET_MODE (dest));
2358 /* If this is the low part, we're done. */
2359 if (subreg_lowpart_p (dest))
2361 /* Handle the case where inner is twice the size of outer. */
2362 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2363 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2364 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2365 /* Otherwise give up for now. */
2371 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2372 <= HOST_BITS_PER_WIDE_INT * 2))
2374 HOST_WIDE_INT mhi, ohi, ihi;
2375 HOST_WIDE_INT mlo, olo, ilo;
2376 rtx inner = SET_SRC (PATTERN (i3));
2377 rtx outer = SET_SRC (temp);
2379 if (GET_CODE (outer) == CONST_INT)
2381 olo = INTVAL (outer);
2382 ohi = olo < 0 ? -1 : 0;
2386 olo = CONST_DOUBLE_LOW (outer);
2387 ohi = CONST_DOUBLE_HIGH (outer);
2390 if (GET_CODE (inner) == CONST_INT)
2392 ilo = INTVAL (inner);
2393 ihi = ilo < 0 ? -1 : 0;
2397 ilo = CONST_DOUBLE_LOW (inner);
2398 ihi = CONST_DOUBLE_HIGH (inner);
2401 if (width < HOST_BITS_PER_WIDE_INT)
2403 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2406 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2408 mhi = ((unsigned HOST_WIDE_INT) 1
2409 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2421 if (offset >= HOST_BITS_PER_WIDE_INT)
2423 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2425 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2428 else if (offset > 0)
2430 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2431 >> (HOST_BITS_PER_WIDE_INT - offset));
2432 mlo = mlo << offset;
2433 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2434 >> (HOST_BITS_PER_WIDE_INT - offset));
2435 ilo = ilo << offset;
2438 olo = (olo & ~mlo) | ilo;
2439 ohi = (ohi & ~mhi) | ihi;
2443 subst_low_luid = DF_INSN_LUID (i2);
2444 added_sets_2 = added_sets_1 = 0;
2445 i2dest = SET_DEST (temp);
2446 i2dest_killed = dead_or_set_p (i2, i2dest);
2448 /* Replace the source in I2 with the new constant and make the
2449 resulting insn the new pattern for I3. Then skip to
2450 where we validate the pattern. Everything was set up above. */
2451 SUBST (SET_SRC (temp),
2452 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2454 newpat = PATTERN (i2);
2456 /* The dest of I3 has been replaced with the dest of I2. */
2457 changed_i3_dest = 1;
2458 goto validate_replacement;
2463 /* If we have no I1 and I2 looks like:
2464 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2466 make up a dummy I1 that is
2469 (set (reg:CC X) (compare:CC Y (const_int 0)))
2471 (We can ignore any trailing CLOBBERs.)
2473 This undoes a previous combination and allows us to match a branch-and-
2476 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2477 && XVECLEN (PATTERN (i2), 0) >= 2
2478 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2479 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2481 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2482 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2483 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2484 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2485 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2486 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2488 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2489 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2494 /* We make I1 with the same INSN_UID as I2. This gives it
2495 the same DF_INSN_LUID for value tracking. Our fake I1 will
2496 never appear in the insn stream so giving it the same INSN_UID
2497 as I2 will not cause a problem. */
2499 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2500 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2501 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2503 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2504 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2505 SET_DEST (PATTERN (i1)));
2510 /* Verify that I2 and I1 are valid for combining. */
2511 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2512 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2518 /* Record whether I2DEST is used in I2SRC and similarly for the other
2519 cases. Knowing this will help in register status updating below. */
2520 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2521 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2522 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2523 i2dest_killed = dead_or_set_p (i2, i2dest);
2524 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2526 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2528 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2530 /* Ensure that I3's pattern can be the destination of combines. */
2531 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2532 i1 && i2dest_in_i1src && i1_feeds_i3,
2539 /* See if any of the insns is a MULT operation. Unless one is, we will
2540 reject a combination that is, since it must be slower. Be conservative
2542 if (GET_CODE (i2src) == MULT
2543 || (i1 != 0 && GET_CODE (i1src) == MULT)
2544 || (GET_CODE (PATTERN (i3)) == SET
2545 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2548 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2549 We used to do this EXCEPT in one case: I3 has a post-inc in an
2550 output operand. However, that exception can give rise to insns like
2552 which is a famous insn on the PDP-11 where the value of r3 used as the
2553 source was model-dependent. Avoid this sort of thing. */
2556 if (!(GET_CODE (PATTERN (i3)) == SET
2557 && REG_P (SET_SRC (PATTERN (i3)))
2558 && MEM_P (SET_DEST (PATTERN (i3)))
2559 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2560 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2561 /* It's not the exception. */
2564 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2565 if (REG_NOTE_KIND (link) == REG_INC
2566 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2568 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2575 /* See if the SETs in I1 or I2 need to be kept around in the merged
2576 instruction: whenever the value set there is still needed past I3.
2577 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2579 For the SET in I1, we have two cases: If I1 and I2 independently
2580 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2581 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2582 in I1 needs to be kept around unless I1DEST dies or is set in either
2583 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2584 I1DEST. If so, we know I1 feeds into I2. */
2586 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2589 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2590 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2592 /* If the set in I2 needs to be kept around, we must make a copy of
2593 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2594 PATTERN (I2), we are only substituting for the original I1DEST, not into
2595 an already-substituted copy. This also prevents making self-referential
2596 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2601 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2602 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2604 i2pat = copy_rtx (PATTERN (i2));
2609 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2610 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2612 i1pat = copy_rtx (PATTERN (i1));
2617 /* Substitute in the latest insn for the regs set by the earlier ones. */
2619 maxreg = max_reg_num ();
2624 /* Many machines that don't use CC0 have insns that can both perform an
2625 arithmetic operation and set the condition code. These operations will
2626 be represented as a PARALLEL with the first element of the vector
2627 being a COMPARE of an arithmetic operation with the constant zero.
2628 The second element of the vector will set some pseudo to the result
2629 of the same arithmetic operation. If we simplify the COMPARE, we won't
2630 match such a pattern and so will generate an extra insn. Here we test
2631 for this case, where both the comparison and the operation result are
2632 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2633 I2SRC. Later we will make the PARALLEL that contains I2. */
2635 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2636 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2637 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2638 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2640 #ifdef SELECT_CC_MODE
2642 enum machine_mode compare_mode;
2645 newpat = PATTERN (i3);
2646 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2650 #ifdef SELECT_CC_MODE
2651 /* See if a COMPARE with the operand we substituted in should be done
2652 with the mode that is currently being used. If not, do the same
2653 processing we do in `subst' for a SET; namely, if the destination
2654 is used only once, try to replace it with a register of the proper
2655 mode and also replace the COMPARE. */
2656 if (undobuf.other_insn == 0
2657 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2658 &undobuf.other_insn))
2659 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2661 != GET_MODE (SET_DEST (newpat))))
2663 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2666 unsigned int regno = REGNO (SET_DEST (newpat));
2669 if (regno < FIRST_PSEUDO_REGISTER)
2670 new_dest = gen_rtx_REG (compare_mode, regno);
2673 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2674 new_dest = regno_reg_rtx[regno];
2677 SUBST (SET_DEST (newpat), new_dest);
2678 SUBST (XEXP (*cc_use, 0), new_dest);
2679 SUBST (SET_SRC (newpat),
2680 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2683 undobuf.other_insn = 0;
2690 /* It is possible that the source of I2 or I1 may be performing
2691 an unneeded operation, such as a ZERO_EXTEND of something
2692 that is known to have the high part zero. Handle that case
2693 by letting subst look at the innermost one of them.
2695 Another way to do this would be to have a function that tries
2696 to simplify a single insn instead of merging two or more
2697 insns. We don't do this because of the potential of infinite
2698 loops and because of the potential extra memory required.
2699 However, doing it the way we are is a bit of a kludge and
2700 doesn't catch all cases.
2702 But only do this if -fexpensive-optimizations since it slows
2703 things down and doesn't usually win.
2705 This is not done in the COMPARE case above because the
2706 unmodified I2PAT is used in the PARALLEL and so a pattern
2707 with a modified I2SRC would not match. */
2709 if (flag_expensive_optimizations)
2711 /* Pass pc_rtx so no substitutions are done, just
2715 subst_low_luid = DF_INSN_LUID (i1);
2716 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2720 subst_low_luid = DF_INSN_LUID (i2);
2721 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2725 n_occurrences = 0; /* `subst' counts here */
2727 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2728 need to make a unique copy of I2SRC each time we substitute it
2729 to avoid self-referential rtl. */
2731 subst_low_luid = DF_INSN_LUID (i2);
2732 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2733 ! i1_feeds_i3 && i1dest_in_i1src);
2736 /* Record whether i2's body now appears within i3's body. */
2737 i2_is_used = n_occurrences;
2740 /* If we already got a failure, don't try to do more. Otherwise,
2741 try to substitute in I1 if we have it. */
2743 if (i1 && GET_CODE (newpat) != CLOBBER)
2745 /* Check that an autoincrement side-effect on I1 has not been lost.
2746 This happens if I1DEST is mentioned in I2 and dies there, and
2747 has disappeared from the new pattern. */
2748 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2750 && dead_or_set_p (i2, i1dest)
2751 && !reg_overlap_mentioned_p (i1dest, newpat))
2752 /* Before we can do this substitution, we must redo the test done
2753 above (see detailed comments there) that ensures that I1DEST
2754 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2755 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2762 subst_low_luid = DF_INSN_LUID (i1);
2763 newpat = subst (newpat, i1dest, i1src, 0, 0);
2767 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2768 to count all the ways that I2SRC and I1SRC can be used. */
2769 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2770 && i2_is_used + added_sets_2 > 1)
2771 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2772 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2774 /* Fail if we tried to make a new register. */
2775 || max_reg_num () != maxreg
2776 /* Fail if we couldn't do something and have a CLOBBER. */
2777 || GET_CODE (newpat) == CLOBBER
2778 /* Fail if this new pattern is a MULT and we didn't have one before
2779 at the outer level. */
2780 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2787 /* If the actions of the earlier insns must be kept
2788 in addition to substituting them into the latest one,
2789 we must make a new PARALLEL for the latest insn
2790 to hold additional the SETs. */
2792 if (added_sets_1 || added_sets_2)
2796 if (GET_CODE (newpat) == PARALLEL)
2798 rtvec old = XVEC (newpat, 0);
2799 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2800 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2801 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2802 sizeof (old->elem[0]) * old->num_elem);
2807 total_sets = 1 + added_sets_1 + added_sets_2;
2808 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2809 XVECEXP (newpat, 0, 0) = old;
2813 XVECEXP (newpat, 0, --total_sets) = i1pat;
2817 /* If there is no I1, use I2's body as is. We used to also not do
2818 the subst call below if I2 was substituted into I3,
2819 but that could lose a simplification. */
2821 XVECEXP (newpat, 0, --total_sets) = i2pat;
2823 /* See comment where i2pat is assigned. */
2824 XVECEXP (newpat, 0, --total_sets)
2825 = subst (i2pat, i1dest, i1src, 0, 0);
2829 validate_replacement:
2831 /* Note which hard regs this insn has as inputs. */
2832 mark_used_regs_combine (newpat);
2834 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2835 consider splitting this pattern, we might need these clobbers. */
2836 if (i1 && GET_CODE (newpat) == PARALLEL
2837 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2839 int len = XVECLEN (newpat, 0);
2841 newpat_vec_with_clobbers = rtvec_alloc (len);
2842 for (i = 0; i < len; i++)
2843 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2846 /* Is the result of combination a valid instruction? */
2847 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2849 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2850 the second SET's destination is a register that is unused and isn't
2851 marked as an instruction that might trap in an EH region. In that case,
2852 we just need the first SET. This can occur when simplifying a divmod
2853 insn. We *must* test for this case here because the code below that
2854 splits two independent SETs doesn't handle this case correctly when it
2855 updates the register status.
2857 It's pointless doing this if we originally had two sets, one from
2858 i3, and one from i2. Combining then splitting the parallel results
2859 in the original i2 again plus an invalid insn (which we delete).
2860 The net effect is only to move instructions around, which makes
2861 debug info less accurate.
2863 Also check the case where the first SET's destination is unused.
2864 That would not cause incorrect code, but does cause an unneeded
2867 if (insn_code_number < 0
2868 && !(added_sets_2 && i1 == 0)
2869 && GET_CODE (newpat) == PARALLEL
2870 && XVECLEN (newpat, 0) == 2
2871 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2872 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2873 && asm_noperands (newpat) < 0)
2875 rtx set0 = XVECEXP (newpat, 0, 0);
2876 rtx set1 = XVECEXP (newpat, 0, 1);
2879 if (((REG_P (SET_DEST (set1))
2880 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2881 || (GET_CODE (SET_DEST (set1)) == SUBREG
2882 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2883 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2884 || INTVAL (XEXP (note, 0)) <= 0)
2885 && ! side_effects_p (SET_SRC (set1)))
2888 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2891 else if (((REG_P (SET_DEST (set0))
2892 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2893 || (GET_CODE (SET_DEST (set0)) == SUBREG
2894 && find_reg_note (i3, REG_UNUSED,
2895 SUBREG_REG (SET_DEST (set0)))))
2896 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2897 || INTVAL (XEXP (note, 0)) <= 0)
2898 && ! side_effects_p (SET_SRC (set0)))
2901 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2903 if (insn_code_number >= 0)
2904 changed_i3_dest = 1;
2908 /* If we were combining three insns and the result is a simple SET
2909 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2910 insns. There are two ways to do this. It can be split using a
2911 machine-specific method (like when you have an addition of a large
2912 constant) or by combine in the function find_split_point. */
2914 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2915 && asm_noperands (newpat) < 0)
2917 rtx parallel, m_split, *split;
2919 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2920 use I2DEST as a scratch register will help. In the latter case,
2921 convert I2DEST to the mode of the source of NEWPAT if we can. */
2923 m_split = combine_split_insns (newpat, i3);
2925 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2926 inputs of NEWPAT. */
2928 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2929 possible to try that as a scratch reg. This would require adding
2930 more code to make it work though. */
2932 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2934 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2936 /* First try to split using the original register as a
2937 scratch register. */
2938 parallel = gen_rtx_PARALLEL (VOIDmode,
2939 gen_rtvec (2, newpat,
2940 gen_rtx_CLOBBER (VOIDmode,
2942 m_split = combine_split_insns (parallel, i3);
2944 /* If that didn't work, try changing the mode of I2DEST if
2947 && new_mode != GET_MODE (i2dest)
2948 && new_mode != VOIDmode
2949 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2951 enum machine_mode old_mode = GET_MODE (i2dest);
2954 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2955 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2958 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2959 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2962 parallel = (gen_rtx_PARALLEL
2964 gen_rtvec (2, newpat,
2965 gen_rtx_CLOBBER (VOIDmode,
2967 m_split = combine_split_insns (parallel, i3);
2970 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2974 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
2975 buf = undobuf.undos;
2976 undobuf.undos = buf->next;
2977 buf->next = undobuf.frees;
2978 undobuf.frees = buf;
2983 /* If recog_for_combine has discarded clobbers, try to use them
2984 again for the split. */
2985 if (m_split == 0 && newpat_vec_with_clobbers)
2987 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
2988 m_split = combine_split_insns (parallel, i3);
2991 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2993 m_split = PATTERN (m_split);
2994 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2995 if (insn_code_number >= 0)
2998 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2999 && (next_real_insn (i2) == i3
3000 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3003 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3004 newi2pat = PATTERN (m_split);
3006 i3set = single_set (NEXT_INSN (m_split));
3007 i2set = single_set (m_split);
3009 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3011 /* If I2 or I3 has multiple SETs, we won't know how to track
3012 register status, so don't use these insns. If I2's destination
3013 is used between I2 and I3, we also can't use these insns. */
3015 if (i2_code_number >= 0 && i2set && i3set
3016 && (next_real_insn (i2) == i3
3017 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3018 insn_code_number = recog_for_combine (&newi3pat, i3,
3020 if (insn_code_number >= 0)
3023 /* It is possible that both insns now set the destination of I3.
3024 If so, we must show an extra use of it. */
3026 if (insn_code_number >= 0)
3028 rtx new_i3_dest = SET_DEST (i3set);
3029 rtx new_i2_dest = SET_DEST (i2set);
3031 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3032 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3033 || GET_CODE (new_i3_dest) == SUBREG)
3034 new_i3_dest = XEXP (new_i3_dest, 0);
3036 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3037 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3038 || GET_CODE (new_i2_dest) == SUBREG)
3039 new_i2_dest = XEXP (new_i2_dest, 0);
3041 if (REG_P (new_i3_dest)
3042 && REG_P (new_i2_dest)
3043 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3044 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3048 /* If we can split it and use I2DEST, go ahead and see if that
3049 helps things be recognized. Verify that none of the registers
3050 are set between I2 and I3. */
3051 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3055 /* We need I2DEST in the proper mode. If it is a hard register
3056 or the only use of a pseudo, we can change its mode.
3057 Make sure we don't change a hard register to have a mode that
3058 isn't valid for it, or change the number of registers. */
3059 && (GET_MODE (*split) == GET_MODE (i2dest)
3060 || GET_MODE (*split) == VOIDmode
3061 || can_change_dest_mode (i2dest, added_sets_2,
3063 && (next_real_insn (i2) == i3
3064 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3065 /* We can't overwrite I2DEST if its value is still used by
3067 && ! reg_referenced_p (i2dest, newpat))
3069 rtx newdest = i2dest;
3070 enum rtx_code split_code = GET_CODE (*split);
3071 enum machine_mode split_mode = GET_MODE (*split);
3072 bool subst_done = false;
3073 newi2pat = NULL_RTX;
3075 /* Get NEWDEST as a register in the proper mode. We have already
3076 validated that we can do this. */
3077 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3079 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3080 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3083 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3084 newdest = regno_reg_rtx[REGNO (i2dest)];
3088 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3089 an ASHIFT. This can occur if it was inside a PLUS and hence
3090 appeared to be a memory address. This is a kludge. */
3091 if (split_code == MULT
3092 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3093 && INTVAL (XEXP (*split, 1)) > 0
3094 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3096 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3097 XEXP (*split, 0), GEN_INT (i)));
3098 /* Update split_code because we may not have a multiply
3100 split_code = GET_CODE (*split);
3103 #ifdef INSN_SCHEDULING
3104 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3105 be written as a ZERO_EXTEND. */
3106 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3108 #ifdef LOAD_EXTEND_OP
3109 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3110 what it really is. */
3111 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3113 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3114 SUBREG_REG (*split)));
3117 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3118 SUBREG_REG (*split)));
3122 /* Attempt to split binary operators using arithmetic identities. */
3123 if (BINARY_P (SET_SRC (newpat))
3124 && split_mode == GET_MODE (SET_SRC (newpat))
3125 && ! side_effects_p (SET_SRC (newpat)))
3127 rtx setsrc = SET_SRC (newpat);
3128 enum machine_mode mode = GET_MODE (setsrc);
3129 enum rtx_code code = GET_CODE (setsrc);
3130 rtx src_op0 = XEXP (setsrc, 0);
3131 rtx src_op1 = XEXP (setsrc, 1);
3133 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3134 if (rtx_equal_p (src_op0, src_op1))
3136 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3137 SUBST (XEXP (setsrc, 0), newdest);
3138 SUBST (XEXP (setsrc, 1), newdest);
3141 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3142 else if ((code == PLUS || code == MULT)
3143 && GET_CODE (src_op0) == code
3144 && GET_CODE (XEXP (src_op0, 0)) == code
3145 && (INTEGRAL_MODE_P (mode)
3146 || (FLOAT_MODE_P (mode)
3147 && flag_unsafe_math_optimizations)))
3149 rtx p = XEXP (XEXP (src_op0, 0), 0);
3150 rtx q = XEXP (XEXP (src_op0, 0), 1);
3151 rtx r = XEXP (src_op0, 1);
3154 /* Split both "((X op Y) op X) op Y" and
3155 "((X op Y) op Y) op X" as "T op T" where T is
3157 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3158 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3160 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3162 SUBST (XEXP (setsrc, 0), newdest);
3163 SUBST (XEXP (setsrc, 1), newdest);
3166 /* Split "((X op X) op Y) op Y)" as "T op T" where
3168 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3170 rtx tmp = simplify_gen_binary (code, mode, p, r);
3171 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3172 SUBST (XEXP (setsrc, 0), newdest);
3173 SUBST (XEXP (setsrc, 1), newdest);
3181 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3182 SUBST (*split, newdest);
3185 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3187 /* recog_for_combine might have added CLOBBERs to newi2pat.
3188 Make sure NEWPAT does not depend on the clobbered regs. */
3189 if (GET_CODE (newi2pat) == PARALLEL)
3190 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3191 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3193 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3194 if (reg_overlap_mentioned_p (reg, newpat))
3201 /* If the split point was a MULT and we didn't have one before,
3202 don't use one now. */
3203 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3204 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3208 /* Check for a case where we loaded from memory in a narrow mode and
3209 then sign extended it, but we need both registers. In that case,
3210 we have a PARALLEL with both loads from the same memory location.
3211 We can split this into a load from memory followed by a register-register
3212 copy. This saves at least one insn, more if register allocation can
3215 We cannot do this if the destination of the first assignment is a
3216 condition code register or cc0. We eliminate this case by making sure
3217 the SET_DEST and SET_SRC have the same mode.
3219 We cannot do this if the destination of the second assignment is
3220 a register that we have already assumed is zero-extended. Similarly
3221 for a SUBREG of such a register. */
3223 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3224 && GET_CODE (newpat) == PARALLEL
3225 && XVECLEN (newpat, 0) == 2
3226 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3227 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3228 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3229 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3230 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3231 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3232 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3233 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3235 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3236 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3237 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3239 && VEC_index (reg_stat_type, reg_stat,
3240 REGNO (temp))->nonzero_bits != 0
3241 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3242 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3243 && (VEC_index (reg_stat_type, reg_stat,
3244 REGNO (temp))->nonzero_bits
3245 != GET_MODE_MASK (word_mode))))
3246 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3247 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3249 && VEC_index (reg_stat_type, reg_stat,
3250 REGNO (temp))->nonzero_bits != 0
3251 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3252 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3253 && (VEC_index (reg_stat_type, reg_stat,
3254 REGNO (temp))->nonzero_bits
3255 != GET_MODE_MASK (word_mode)))))
3256 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3257 SET_SRC (XVECEXP (newpat, 0, 1)))
3258 && ! find_reg_note (i3, REG_UNUSED,
3259 SET_DEST (XVECEXP (newpat, 0, 0))))
3263 newi2pat = XVECEXP (newpat, 0, 0);
3264 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3265 newpat = XVECEXP (newpat, 0, 1);
3266 SUBST (SET_SRC (newpat),
3267 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3268 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3270 if (i2_code_number >= 0)
3271 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3273 if (insn_code_number >= 0)
3277 /* Similarly, check for a case where we have a PARALLEL of two independent
3278 SETs but we started with three insns. In this case, we can do the sets
3279 as two separate insns. This case occurs when some SET allows two
3280 other insns to combine, but the destination of that SET is still live. */
3282 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3283 && GET_CODE (newpat) == PARALLEL
3284 && XVECLEN (newpat, 0) == 2
3285 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3286 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3287 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3288 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3289 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3290 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3291 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3293 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3294 XVECEXP (newpat, 0, 0))
3295 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3296 XVECEXP (newpat, 0, 1))
3297 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3298 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3300 /* We cannot split the parallel into two sets if both sets
3302 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3303 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3307 /* Normally, it doesn't matter which of the two is done first,
3308 but it does if one references cc0. In that case, it has to
3311 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3313 newi2pat = XVECEXP (newpat, 0, 0);
3314 newpat = XVECEXP (newpat, 0, 1);
3319 newi2pat = XVECEXP (newpat, 0, 1);
3320 newpat = XVECEXP (newpat, 0, 0);
3323 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3325 if (i2_code_number >= 0)
3326 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3329 /* If it still isn't recognized, fail and change things back the way they
3331 if ((insn_code_number < 0
3332 /* Is the result a reasonable ASM_OPERANDS? */
3333 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3339 /* If we had to change another insn, make sure it is valid also. */
3340 if (undobuf.other_insn)
3342 CLEAR_HARD_REG_SET (newpat_used_regs);
3344 other_pat = PATTERN (undobuf.other_insn);
3345 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3348 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3356 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3357 they are adjacent to each other or not. */
3359 rtx p = prev_nonnote_insn (i3);
3360 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3361 && sets_cc0_p (newi2pat))
3369 /* Only allow this combination if insn_rtx_costs reports that the
3370 replacement instructions are cheaper than the originals. */
3371 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3377 /* If we will be able to accept this, we have made a
3378 change to the destination of I3. This requires us to
3379 do a few adjustments. */
3381 if (changed_i3_dest)
3383 PATTERN (i3) = newpat;
3384 adjust_for_new_dest (i3);
3387 /* We now know that we can do this combination. Merge the insns and
3388 update the status of registers and LOG_LINKS. */
3390 if (undobuf.other_insn)
3394 PATTERN (undobuf.other_insn) = other_pat;
3396 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3397 are still valid. Then add any non-duplicate notes added by
3398 recog_for_combine. */
3399 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3401 next = XEXP (note, 1);
3403 if (REG_NOTE_KIND (note) == REG_UNUSED
3404 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3405 remove_note (undobuf.other_insn, note);
3408 distribute_notes (new_other_notes, undobuf.other_insn,
3409 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3418 /* I3 now uses what used to be its destination and which is now
3419 I2's destination. This requires us to do a few adjustments. */
3420 PATTERN (i3) = newpat;
3421 adjust_for_new_dest (i3);
3423 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3426 However, some later insn might be using I2's dest and have
3427 a LOG_LINK pointing at I3. We must remove this link.
3428 The simplest way to remove the link is to point it at I1,
3429 which we know will be a NOTE. */
3431 /* newi2pat is usually a SET here; however, recog_for_combine might
3432 have added some clobbers. */
3433 if (GET_CODE (newi2pat) == PARALLEL)
3434 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3436 ni2dest = SET_DEST (newi2pat);
3438 for (insn = NEXT_INSN (i3);
3439 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3440 || insn != BB_HEAD (this_basic_block->next_bb));
3441 insn = NEXT_INSN (insn))
3443 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3445 for (link = LOG_LINKS (insn); link;
3446 link = XEXP (link, 1))
3447 if (XEXP (link, 0) == i3)
3448 XEXP (link, 0) = i1;
3456 rtx i3notes, i2notes, i1notes = 0;
3457 rtx i3links, i2links, i1links = 0;
3460 /* Compute which registers we expect to eliminate. newi2pat may be setting
3461 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3462 same as i3dest, in which case newi2pat may be setting i1dest. */
3463 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3464 || i2dest_in_i2src || i2dest_in_i1src
3467 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3468 || (newi2pat && reg_set_p (i1dest, newi2pat))
3472 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3474 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3475 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3477 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3479 /* Ensure that we do not have something that should not be shared but
3480 occurs multiple times in the new insns. Check this by first
3481 resetting all the `used' flags and then copying anything is shared. */
3483 reset_used_flags (i3notes);
3484 reset_used_flags (i2notes);
3485 reset_used_flags (i1notes);
3486 reset_used_flags (newpat);
3487 reset_used_flags (newi2pat);
3488 if (undobuf.other_insn)
3489 reset_used_flags (PATTERN (undobuf.other_insn));
3491 i3notes = copy_rtx_if_shared (i3notes);
3492 i2notes = copy_rtx_if_shared (i2notes);
3493 i1notes = copy_rtx_if_shared (i1notes);
3494 newpat = copy_rtx_if_shared (newpat);
3495 newi2pat = copy_rtx_if_shared (newi2pat);
3496 if (undobuf.other_insn)
3497 reset_used_flags (PATTERN (undobuf.other_insn));
3499 INSN_CODE (i3) = insn_code_number;
3500 PATTERN (i3) = newpat;
3502 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3504 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3506 reset_used_flags (call_usage);
3507 call_usage = copy_rtx (call_usage);
3510 replace_rtx (call_usage, i2dest, i2src);
3513 replace_rtx (call_usage, i1dest, i1src);
3515 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3518 if (undobuf.other_insn)
3519 INSN_CODE (undobuf.other_insn) = other_code_number;
3521 /* We had one special case above where I2 had more than one set and
3522 we replaced a destination of one of those sets with the destination
3523 of I3. In that case, we have to update LOG_LINKS of insns later
3524 in this basic block. Note that this (expensive) case is rare.
3526 Also, in this case, we must pretend that all REG_NOTEs for I2
3527 actually came from I3, so that REG_UNUSED notes from I2 will be
3528 properly handled. */
3530 if (i3_subst_into_i2)
3532 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3533 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3534 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3535 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3536 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3537 && ! find_reg_note (i2, REG_UNUSED,
3538 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3539 for (temp = NEXT_INSN (i2);
3540 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3541 || BB_HEAD (this_basic_block) != temp);
3542 temp = NEXT_INSN (temp))
3543 if (temp != i3 && INSN_P (temp))
3544 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3545 if (XEXP (link, 0) == i2)
3546 XEXP (link, 0) = i3;
3551 while (XEXP (link, 1))
3552 link = XEXP (link, 1);
3553 XEXP (link, 1) = i2notes;
3567 INSN_CODE (i2) = i2_code_number;
3568 PATTERN (i2) = newi2pat;
3571 SET_INSN_DELETED (i2);
3577 SET_INSN_DELETED (i1);
3580 /* Get death notes for everything that is now used in either I3 or
3581 I2 and used to die in a previous insn. If we built two new
3582 patterns, move from I1 to I2 then I2 to I3 so that we get the
3583 proper movement on registers that I2 modifies. */
3587 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3588 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3591 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3594 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3596 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3599 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3602 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3605 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3608 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3609 know these are REG_UNUSED and want them to go to the desired insn,
3610 so we always pass it as i3. */
3612 if (newi2pat && new_i2_notes)
3613 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3616 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3618 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3619 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3620 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3621 in that case, it might delete I2. Similarly for I2 and I1.
3622 Show an additional death due to the REG_DEAD note we make here. If
3623 we discard it in distribute_notes, we will decrement it again. */
3627 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3628 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3630 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3632 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3634 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3638 if (i2dest_in_i2src)
3640 if (newi2pat && reg_set_p (i2dest, newi2pat))
3641 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3642 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3644 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3645 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3646 NULL_RTX, NULL_RTX);
3649 if (i1dest_in_i1src)
3651 if (newi2pat && reg_set_p (i1dest, newi2pat))
3652 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3653 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3655 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3656 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3657 NULL_RTX, NULL_RTX);
3660 distribute_links (i3links);
3661 distribute_links (i2links);
3662 distribute_links (i1links);
3667 rtx i2_insn = 0, i2_val = 0, set;
3669 /* The insn that used to set this register doesn't exist, and
3670 this life of the register may not exist either. See if one of
3671 I3's links points to an insn that sets I2DEST. If it does,
3672 that is now the last known value for I2DEST. If we don't update
3673 this and I2 set the register to a value that depended on its old
3674 contents, we will get confused. If this insn is used, thing
3675 will be set correctly in combine_instructions. */
3677 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3678 if ((set = single_set (XEXP (link, 0))) != 0
3679 && rtx_equal_p (i2dest, SET_DEST (set)))
3680 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3682 record_value_for_reg (i2dest, i2_insn, i2_val);
3684 /* If the reg formerly set in I2 died only once and that was in I3,
3685 zero its use count so it won't make `reload' do any work. */
3687 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3688 && ! i2dest_in_i2src)
3690 regno = REGNO (i2dest);
3691 INC_REG_N_SETS (regno, -1);
3695 if (i1 && REG_P (i1dest))
3698 rtx i1_insn = 0, i1_val = 0, set;
3700 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3701 if ((set = single_set (XEXP (link, 0))) != 0
3702 && rtx_equal_p (i1dest, SET_DEST (set)))
3703 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3705 record_value_for_reg (i1dest, i1_insn, i1_val);
3707 regno = REGNO (i1dest);
3708 if (! added_sets_1 && ! i1dest_in_i1src)
3709 INC_REG_N_SETS (regno, -1);
3712 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3713 been made to this insn. The order of
3714 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3715 can affect nonzero_bits of newpat */
3717 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3718 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3720 /* Set new_direct_jump_p if a new return or simple jump instruction
3723 If I3 is now an unconditional jump, ensure that it has a
3724 BARRIER following it since it may have initially been a
3725 conditional jump. It may also be the last nonnote insn. */
3727 if (returnjump_p (i3) || any_uncondjump_p (i3))
3729 *new_direct_jump_p = 1;
3730 mark_jump_label (PATTERN (i3), i3, 0);
3732 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3733 || !BARRIER_P (temp))
3734 emit_barrier_after (i3);
3737 if (undobuf.other_insn != NULL_RTX
3738 && (returnjump_p (undobuf.other_insn)
3739 || any_uncondjump_p (undobuf.other_insn)))
3741 *new_direct_jump_p = 1;
3743 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3744 || !BARRIER_P (temp))
3745 emit_barrier_after (undobuf.other_insn);
3748 /* An NOOP jump does not need barrier, but it does need cleaning up
3750 if (GET_CODE (newpat) == SET
3751 && SET_SRC (newpat) == pc_rtx
3752 && SET_DEST (newpat) == pc_rtx)
3753 *new_direct_jump_p = 1;
3756 if (undobuf.other_insn != NULL_RTX)
3760 fprintf (dump_file, "modifying other_insn ");
3761 dump_insn_slim (dump_file, undobuf.other_insn);
3763 df_insn_rescan (undobuf.other_insn);
3766 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3770 fprintf (dump_file, "modifying insn i1 ");
3771 dump_insn_slim (dump_file, i1);
3773 df_insn_rescan (i1);
3776 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3780 fprintf (dump_file, "modifying insn i2 ");
3781 dump_insn_slim (dump_file, i2);
3783 df_insn_rescan (i2);
3786 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3790 fprintf (dump_file, "modifying insn i3 ");
3791 dump_insn_slim (dump_file, i3);
3793 df_insn_rescan (i3);
3796 combine_successes++;
3799 if (added_links_insn
3800 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3801 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3802 return added_links_insn;
3804 return newi2pat ? i2 : i3;
3807 /* Undo all the modifications recorded in undobuf. */
3812 struct undo *undo, *next;
3814 for (undo = undobuf.undos; undo; undo = next)
3820 *undo->where.r = undo->old_contents.r;
3823 *undo->where.i = undo->old_contents.i;
3826 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3832 undo->next = undobuf.frees;
3833 undobuf.frees = undo;
3839 /* We've committed to accepting the changes we made. Move all
3840 of the undos to the free list. */
3845 struct undo *undo, *next;
3847 for (undo = undobuf.undos; undo; undo = next)
3850 undo->next = undobuf.frees;
3851 undobuf.frees = undo;
3856 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3857 where we have an arithmetic expression and return that point. LOC will
3860 try_combine will call this function to see if an insn can be split into
3864 find_split_point (rtx *loc, rtx insn)
3867 enum rtx_code code = GET_CODE (x);
3869 unsigned HOST_WIDE_INT len = 0;
3870 HOST_WIDE_INT pos = 0;
3872 rtx inner = NULL_RTX;
3874 /* First special-case some codes. */
3878 #ifdef INSN_SCHEDULING
3879 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3881 if (MEM_P (SUBREG_REG (x)))
3884 return find_split_point (&SUBREG_REG (x), insn);
3888 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3889 using LO_SUM and HIGH. */
3890 if (GET_CODE (XEXP (x, 0)) == CONST
3891 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3894 gen_rtx_LO_SUM (Pmode,
3895 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3897 return &XEXP (XEXP (x, 0), 0);
3901 /* If we have a PLUS whose second operand is a constant and the
3902 address is not valid, perhaps will can split it up using
3903 the machine-specific way to split large constants. We use
3904 the first pseudo-reg (one of the virtual regs) as a placeholder;
3905 it will not remain in the result. */
3906 if (GET_CODE (XEXP (x, 0)) == PLUS
3907 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3908 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3910 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3911 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3915 /* This should have produced two insns, each of which sets our
3916 placeholder. If the source of the second is a valid address,
3917 we can make put both sources together and make a split point
3921 && NEXT_INSN (seq) != NULL_RTX
3922 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3923 && NONJUMP_INSN_P (seq)
3924 && GET_CODE (PATTERN (seq)) == SET
3925 && SET_DEST (PATTERN (seq)) == reg
3926 && ! reg_mentioned_p (reg,
3927 SET_SRC (PATTERN (seq)))
3928 && NONJUMP_INSN_P (NEXT_INSN (seq))
3929 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3930 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3931 && memory_address_p (GET_MODE (x),
3932 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3934 rtx src1 = SET_SRC (PATTERN (seq));
3935 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3937 /* Replace the placeholder in SRC2 with SRC1. If we can
3938 find where in SRC2 it was placed, that can become our
3939 split point and we can replace this address with SRC2.
3940 Just try two obvious places. */
3942 src2 = replace_rtx (src2, reg, src1);
3944 if (XEXP (src2, 0) == src1)
3945 split = &XEXP (src2, 0);
3946 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3947 && XEXP (XEXP (src2, 0), 0) == src1)
3948 split = &XEXP (XEXP (src2, 0), 0);
3952 SUBST (XEXP (x, 0), src2);
3957 /* If that didn't work, perhaps the first operand is complex and
3958 needs to be computed separately, so make a split point there.
3959 This will occur on machines that just support REG + CONST
3960 and have a constant moved through some previous computation. */
3962 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3963 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3964 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3965 return &XEXP (XEXP (x, 0), 0);
3968 /* If we have a PLUS whose first operand is complex, try computing it
3969 separately by making a split there. */
3970 if (GET_CODE (XEXP (x, 0)) == PLUS
3971 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3972 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3973 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3974 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3975 return &XEXP (XEXP (x, 0), 0);
3980 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3981 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3982 we need to put the operand into a register. So split at that
3985 if (SET_DEST (x) == cc0_rtx
3986 && GET_CODE (SET_SRC (x)) != COMPARE
3987 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3988 && !OBJECT_P (SET_SRC (x))
3989 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3990 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3991 return &SET_SRC (x);
3994 /* See if we can split SET_SRC as it stands. */
3995 split = find_split_point (&SET_SRC (x), insn);
3996 if (split && split != &SET_SRC (x))
3999 /* See if we can split SET_DEST as it stands. */
4000 split = find_split_point (&SET_DEST (x), insn);
4001 if (split && split != &SET_DEST (x))
4004 /* See if this is a bitfield assignment with everything constant. If
4005 so, this is an IOR of an AND, so split it into that. */
4006 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4007 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4008 <= HOST_BITS_PER_WIDE_INT)
4009 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
4010 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
4011 && GET_CODE (SET_SRC (x)) == CONST_INT
4012 && ((INTVAL (XEXP (SET_DEST (x), 1))
4013 + INTVAL (XEXP (SET_DEST (x), 2)))
4014 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4015 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4017 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4018 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4019 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4020 rtx dest = XEXP (SET_DEST (x), 0);
4021 enum machine_mode mode = GET_MODE (dest);
4022 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4025 if (BITS_BIG_ENDIAN)
4026 pos = GET_MODE_BITSIZE (mode) - len - pos;
4028 or_mask = gen_int_mode (src << pos, mode);
4031 simplify_gen_binary (IOR, mode, dest, or_mask));
4034 rtx negmask = gen_int_mode (~(mask << pos), mode);
4036 simplify_gen_binary (IOR, mode,
4037 simplify_gen_binary (AND, mode,
4042 SUBST (SET_DEST (x), dest);
4044 split = find_split_point (&SET_SRC (x), insn);
4045 if (split && split != &SET_SRC (x))
4049 /* Otherwise, see if this is an operation that we can split into two.
4050 If so, try to split that. */
4051 code = GET_CODE (SET_SRC (x));
4056 /* If we are AND'ing with a large constant that is only a single
4057 bit and the result is only being used in a context where we
4058 need to know if it is zero or nonzero, replace it with a bit
4059 extraction. This will avoid the large constant, which might
4060 have taken more than one insn to make. If the constant were
4061 not a valid argument to the AND but took only one insn to make,
4062 this is no worse, but if it took more than one insn, it will
4065 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4066 && REG_P (XEXP (SET_SRC (x), 0))
4067 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4068 && REG_P (SET_DEST (x))
4069 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4070 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4071 && XEXP (*split, 0) == SET_DEST (x)
4072 && XEXP (*split, 1) == const0_rtx)
4074 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4075 XEXP (SET_SRC (x), 0),
4076 pos, NULL_RTX, 1, 1, 0, 0);
4077 if (extraction != 0)
4079 SUBST (SET_SRC (x), extraction);
4080 return find_split_point (loc, insn);
4086 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4087 is known to be on, this can be converted into a NEG of a shift. */
4088 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4089 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4090 && 1 <= (pos = exact_log2
4091 (nonzero_bits (XEXP (SET_SRC (x), 0),
4092 GET_MODE (XEXP (SET_SRC (x), 0))))))
4094 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4098 gen_rtx_LSHIFTRT (mode,
4099 XEXP (SET_SRC (x), 0),
4102 split = find_split_point (&SET_SRC (x), insn);
4103 if (split && split != &SET_SRC (x))
4109 inner = XEXP (SET_SRC (x), 0);
4111 /* We can't optimize if either mode is a partial integer
4112 mode as we don't know how many bits are significant
4114 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4115 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4119 len = GET_MODE_BITSIZE (GET_MODE (inner));
4125 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4126 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4128 inner = XEXP (SET_SRC (x), 0);
4129 len = INTVAL (XEXP (SET_SRC (x), 1));
4130 pos = INTVAL (XEXP (SET_SRC (x), 2));
4132 if (BITS_BIG_ENDIAN)
4133 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4134 unsignedp = (code == ZERO_EXTRACT);
4142 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4144 enum machine_mode mode = GET_MODE (SET_SRC (x));
4146 /* For unsigned, we have a choice of a shift followed by an
4147 AND or two shifts. Use two shifts for field sizes where the
4148 constant might be too large. We assume here that we can
4149 always at least get 8-bit constants in an AND insn, which is
4150 true for every current RISC. */
4152 if (unsignedp && len <= 8)
4157 (mode, gen_lowpart (mode, inner),
4159 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4161 split = find_split_point (&SET_SRC (x), insn);
4162 if (split && split != &SET_SRC (x))
4169 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4170 gen_rtx_ASHIFT (mode,
4171 gen_lowpart (mode, inner),
4172 GEN_INT (GET_MODE_BITSIZE (mode)
4174 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4176 split = find_split_point (&SET_SRC (x), insn);
4177 if (split && split != &SET_SRC (x))
4182 /* See if this is a simple operation with a constant as the second
4183 operand. It might be that this constant is out of range and hence
4184 could be used as a split point. */
4185 if (BINARY_P (SET_SRC (x))
4186 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4187 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4188 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4189 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4190 return &XEXP (SET_SRC (x), 1);
4192 /* Finally, see if this is a simple operation with its first operand
4193 not in a register. The operation might require this operand in a
4194 register, so return it as a split point. We can always do this
4195 because if the first operand were another operation, we would have
4196 already found it as a split point. */
4197 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4198 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4199 return &XEXP (SET_SRC (x), 0);
4205 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4206 it is better to write this as (not (ior A B)) so we can split it.
4207 Similarly for IOR. */
4208 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4211 gen_rtx_NOT (GET_MODE (x),
4212 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4214 XEXP (XEXP (x, 0), 0),
4215 XEXP (XEXP (x, 1), 0))));
4216 return find_split_point (loc, insn);
4219 /* Many RISC machines have a large set of logical insns. If the
4220 second operand is a NOT, put it first so we will try to split the
4221 other operand first. */
4222 if (GET_CODE (XEXP (x, 1)) == NOT)
4224 rtx tem = XEXP (x, 0);
4225 SUBST (XEXP (x, 0), XEXP (x, 1));
4226 SUBST (XEXP (x, 1), tem);
4234 /* Otherwise, select our actions depending on our rtx class. */
4235 switch (GET_RTX_CLASS (code))
4237 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4239 split = find_split_point (&XEXP (x, 2), insn);
4242 /* ... fall through ... */
4244 case RTX_COMM_ARITH:
4246 case RTX_COMM_COMPARE:
4247 split = find_split_point (&XEXP (x, 1), insn);
4250 /* ... fall through ... */
4252 /* Some machines have (and (shift ...) ...) insns. If X is not
4253 an AND, but XEXP (X, 0) is, use it as our split point. */
4254 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4255 return &XEXP (x, 0);
4257 split = find_split_point (&XEXP (x, 0), insn);
4263 /* Otherwise, we don't have a split point. */
4268 /* Throughout X, replace FROM with TO, and return the result.
4269 The result is TO if X is FROM;
4270 otherwise the result is X, but its contents may have been modified.
4271 If they were modified, a record was made in undobuf so that
4272 undo_all will (among other things) return X to its original state.
4274 If the number of changes necessary is too much to record to undo,
4275 the excess changes are not made, so the result is invalid.
4276 The changes already made can still be undone.
4277 undobuf.num_undo is incremented for such changes, so by testing that
4278 the caller can tell whether the result is valid.
4280 `n_occurrences' is incremented each time FROM is replaced.
4282 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4284 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4285 by copying if `n_occurrences' is nonzero. */
4288 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4290 enum rtx_code code = GET_CODE (x);
4291 enum machine_mode op0_mode = VOIDmode;
4296 /* Two expressions are equal if they are identical copies of a shared
4297 RTX or if they are both registers with the same register number
4300 #define COMBINE_RTX_EQUAL_P(X,Y) \
4302 || (REG_P (X) && REG_P (Y) \
4303 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4305 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4308 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4311 /* If X and FROM are the same register but different modes, they
4312 will not have been seen as equal above. However, the log links code
4313 will make a LOG_LINKS entry for that case. If we do nothing, we
4314 will try to rerecognize our original insn and, when it succeeds,
4315 we will delete the feeding insn, which is incorrect.
4317 So force this insn not to match in this (rare) case. */
4318 if (! in_dest && code == REG && REG_P (from)
4319 && reg_overlap_mentioned_p (x, from))
4320 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4322 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4323 of which may contain things that can be combined. */
4324 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4327 /* It is possible to have a subexpression appear twice in the insn.
4328 Suppose that FROM is a register that appears within TO.
4329 Then, after that subexpression has been scanned once by `subst',
4330 the second time it is scanned, TO may be found. If we were
4331 to scan TO here, we would find FROM within it and create a
4332 self-referent rtl structure which is completely wrong. */
4333 if (COMBINE_RTX_EQUAL_P (x, to))
4336 /* Parallel asm_operands need special attention because all of the
4337 inputs are shared across the arms. Furthermore, unsharing the
4338 rtl results in recognition failures. Failure to handle this case
4339 specially can result in circular rtl.
4341 Solve this by doing a normal pass across the first entry of the
4342 parallel, and only processing the SET_DESTs of the subsequent
4345 if (code == PARALLEL
4346 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4347 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4349 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4351 /* If this substitution failed, this whole thing fails. */
4352 if (GET_CODE (new_rtx) == CLOBBER
4353 && XEXP (new_rtx, 0) == const0_rtx)
4356 SUBST (XVECEXP (x, 0, 0), new_rtx);
4358 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4360 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4363 && GET_CODE (dest) != CC0
4364 && GET_CODE (dest) != PC)
4366 new_rtx = subst (dest, from, to, 0, unique_copy);
4368 /* If this substitution failed, this whole thing fails. */
4369 if (GET_CODE (new_rtx) == CLOBBER
4370 && XEXP (new_rtx, 0) == const0_rtx)
4373 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4379 len = GET_RTX_LENGTH (code);
4380 fmt = GET_RTX_FORMAT (code);
4382 /* We don't need to process a SET_DEST that is a register, CC0,
4383 or PC, so set up to skip this common case. All other cases
4384 where we want to suppress replacing something inside a
4385 SET_SRC are handled via the IN_DEST operand. */
4387 && (REG_P (SET_DEST (x))
4388 || GET_CODE (SET_DEST (x)) == CC0
4389 || GET_CODE (SET_DEST (x)) == PC))
4392 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4395 op0_mode = GET_MODE (XEXP (x, 0));
4397 for (i = 0; i < len; i++)
4402 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4404 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4406 new_rtx = (unique_copy && n_occurrences
4407 ? copy_rtx (to) : to);
4412 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4415 /* If this substitution failed, this whole thing
4417 if (GET_CODE (new_rtx) == CLOBBER
4418 && XEXP (new_rtx, 0) == const0_rtx)
4422 SUBST (XVECEXP (x, i, j), new_rtx);
4425 else if (fmt[i] == 'e')
4427 /* If this is a register being set, ignore it. */
4428 new_rtx = XEXP (x, i);
4431 && (((code == SUBREG || code == ZERO_EXTRACT)
4433 || code == STRICT_LOW_PART))
4436 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4438 /* In general, don't install a subreg involving two
4439 modes not tieable. It can worsen register
4440 allocation, and can even make invalid reload
4441 insns, since the reg inside may need to be copied
4442 from in the outside mode, and that may be invalid
4443 if it is an fp reg copied in integer mode.
4445 We allow two exceptions to this: It is valid if
4446 it is inside another SUBREG and the mode of that
4447 SUBREG and the mode of the inside of TO is
4448 tieable and it is valid if X is a SET that copies
4451 if (GET_CODE (to) == SUBREG
4452 && ! MODES_TIEABLE_P (GET_MODE (to),
4453 GET_MODE (SUBREG_REG (to)))
4454 && ! (code == SUBREG
4455 && MODES_TIEABLE_P (GET_MODE (x),
4456 GET_MODE (SUBREG_REG (to))))
4458 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4461 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4463 #ifdef CANNOT_CHANGE_MODE_CLASS
4466 && REGNO (to) < FIRST_PSEUDO_REGISTER
4467 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4470 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4473 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4477 /* If we are in a SET_DEST, suppress most cases unless we
4478 have gone inside a MEM, in which case we want to
4479 simplify the address. We assume here that things that
4480 are actually part of the destination have their inner
4481 parts in the first expression. This is true for SUBREG,
4482 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4483 things aside from REG and MEM that should appear in a
4485 new_rtx = subst (XEXP (x, i), from, to,
4487 && (code == SUBREG || code == STRICT_LOW_PART
4488 || code == ZERO_EXTRACT))
4490 && i == 0), unique_copy);
4492 /* If we found that we will have to reject this combination,
4493 indicate that by returning the CLOBBER ourselves, rather than
4494 an expression containing it. This will speed things up as
4495 well as prevent accidents where two CLOBBERs are considered
4496 to be equal, thus producing an incorrect simplification. */
4498 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4501 if (GET_CODE (x) == SUBREG
4502 && (GET_CODE (new_rtx) == CONST_INT
4503 || GET_CODE (new_rtx) == CONST_DOUBLE))
4505 enum machine_mode mode = GET_MODE (x);
4507 x = simplify_subreg (GET_MODE (x), new_rtx,
4508 GET_MODE (SUBREG_REG (x)),
4511 x = gen_rtx_CLOBBER (mode, const0_rtx);
4513 else if (GET_CODE (new_rtx) == CONST_INT
4514 && GET_CODE (x) == ZERO_EXTEND)
4516 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4517 new_rtx, GET_MODE (XEXP (x, 0)));
4521 SUBST (XEXP (x, i), new_rtx);
4526 /* Check if we are loading something from the constant pool via float
4527 extension; in this case we would undo compress_float_constant
4528 optimization and degenerate constant load to an immediate value. */
4529 if (GET_CODE (x) == FLOAT_EXTEND
4530 && MEM_P (XEXP (x, 0))
4531 && MEM_READONLY_P (XEXP (x, 0)))
4533 rtx tmp = avoid_constant_pool_reference (x);
4538 /* Try to simplify X. If the simplification changed the code, it is likely
4539 that further simplification will help, so loop, but limit the number
4540 of repetitions that will be performed. */
4542 for (i = 0; i < 4; i++)
4544 /* If X is sufficiently simple, don't bother trying to do anything
4546 if (code != CONST_INT && code != REG && code != CLOBBER)
4547 x = combine_simplify_rtx (x, op0_mode, in_dest);
4549 if (GET_CODE (x) == code)
4552 code = GET_CODE (x);
4554 /* We no longer know the original mode of operand 0 since we
4555 have changed the form of X) */
4556 op0_mode = VOIDmode;
4562 /* Simplify X, a piece of RTL. We just operate on the expression at the
4563 outer level; call `subst' to simplify recursively. Return the new
4566 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4567 if we are inside a SET_DEST. */
4570 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4572 enum rtx_code code = GET_CODE (x);
4573 enum machine_mode mode = GET_MODE (x);
4577 /* If this is a commutative operation, put a constant last and a complex
4578 expression first. We don't need to do this for comparisons here. */
4579 if (COMMUTATIVE_ARITH_P (x)
4580 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4583 SUBST (XEXP (x, 0), XEXP (x, 1));
4584 SUBST (XEXP (x, 1), temp);
4587 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4588 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4589 things. Check for cases where both arms are testing the same
4592 Don't do anything if all operands are very simple. */
4595 && ((!OBJECT_P (XEXP (x, 0))
4596 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4597 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4598 || (!OBJECT_P (XEXP (x, 1))
4599 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4600 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4602 && (!OBJECT_P (XEXP (x, 0))
4603 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4604 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4606 rtx cond, true_rtx, false_rtx;
4608 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4610 /* If everything is a comparison, what we have is highly unlikely
4611 to be simpler, so don't use it. */
4612 && ! (COMPARISON_P (x)
4613 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4615 rtx cop1 = const0_rtx;
4616 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4618 if (cond_code == NE && COMPARISON_P (cond))
4621 /* Simplify the alternative arms; this may collapse the true and
4622 false arms to store-flag values. Be careful to use copy_rtx
4623 here since true_rtx or false_rtx might share RTL with x as a
4624 result of the if_then_else_cond call above. */
4625 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4626 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4628 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4629 is unlikely to be simpler. */
4630 if (general_operand (true_rtx, VOIDmode)
4631 && general_operand (false_rtx, VOIDmode))
4633 enum rtx_code reversed;
4635 /* Restarting if we generate a store-flag expression will cause
4636 us to loop. Just drop through in this case. */
4638 /* If the result values are STORE_FLAG_VALUE and zero, we can
4639 just make the comparison operation. */
4640 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4641 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4643 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4644 && ((reversed = reversed_comparison_code_parts
4645 (cond_code, cond, cop1, NULL))
4647 x = simplify_gen_relational (reversed, mode, VOIDmode,
4650 /* Likewise, we can make the negate of a comparison operation
4651 if the result values are - STORE_FLAG_VALUE and zero. */
4652 else if (GET_CODE (true_rtx) == CONST_INT
4653 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4654 && false_rtx == const0_rtx)
4655 x = simplify_gen_unary (NEG, mode,
4656 simplify_gen_relational (cond_code,
4660 else if (GET_CODE (false_rtx) == CONST_INT
4661 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4662 && true_rtx == const0_rtx
4663 && ((reversed = reversed_comparison_code_parts
4664 (cond_code, cond, cop1, NULL))
4666 x = simplify_gen_unary (NEG, mode,
4667 simplify_gen_relational (reversed,
4672 return gen_rtx_IF_THEN_ELSE (mode,
4673 simplify_gen_relational (cond_code,
4678 true_rtx, false_rtx);
4680 code = GET_CODE (x);
4681 op0_mode = VOIDmode;
4686 /* Try to fold this expression in case we have constants that weren't
4689 switch (GET_RTX_CLASS (code))
4692 if (op0_mode == VOIDmode)
4693 op0_mode = GET_MODE (XEXP (x, 0));
4694 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4697 case RTX_COMM_COMPARE:
4699 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4700 if (cmp_mode == VOIDmode)
4702 cmp_mode = GET_MODE (XEXP (x, 1));
4703 if (cmp_mode == VOIDmode)
4704 cmp_mode = op0_mode;
4706 temp = simplify_relational_operation (code, mode, cmp_mode,
4707 XEXP (x, 0), XEXP (x, 1));
4710 case RTX_COMM_ARITH:
4712 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4714 case RTX_BITFIELD_OPS:
4716 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4717 XEXP (x, 1), XEXP (x, 2));
4726 code = GET_CODE (temp);
4727 op0_mode = VOIDmode;
4728 mode = GET_MODE (temp);
4731 /* First see if we can apply the inverse distributive law. */
4732 if (code == PLUS || code == MINUS
4733 || code == AND || code == IOR || code == XOR)
4735 x = apply_distributive_law (x);
4736 code = GET_CODE (x);
4737 op0_mode = VOIDmode;
4740 /* If CODE is an associative operation not otherwise handled, see if we
4741 can associate some operands. This can win if they are constants or
4742 if they are logically related (i.e. (a & b) & a). */
4743 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4744 || code == AND || code == IOR || code == XOR
4745 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4746 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4747 || (flag_associative_math && FLOAT_MODE_P (mode))))
4749 if (GET_CODE (XEXP (x, 0)) == code)
4751 rtx other = XEXP (XEXP (x, 0), 0);
4752 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4753 rtx inner_op1 = XEXP (x, 1);
4756 /* Make sure we pass the constant operand if any as the second
4757 one if this is a commutative operation. */
4758 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4760 rtx tem = inner_op0;
4761 inner_op0 = inner_op1;
4764 inner = simplify_binary_operation (code == MINUS ? PLUS
4765 : code == DIV ? MULT
4767 mode, inner_op0, inner_op1);
4769 /* For commutative operations, try the other pair if that one
4771 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4773 other = XEXP (XEXP (x, 0), 1);
4774 inner = simplify_binary_operation (code, mode,
4775 XEXP (XEXP (x, 0), 0),
4780 return simplify_gen_binary (code, mode, other, inner);
4784 /* A little bit of algebraic simplification here. */
4788 /* Ensure that our address has any ASHIFTs converted to MULT in case
4789 address-recognizing predicates are called later. */
4790 temp = make_compound_operation (XEXP (x, 0), MEM);
4791 SUBST (XEXP (x, 0), temp);
4795 if (op0_mode == VOIDmode)
4796 op0_mode = GET_MODE (SUBREG_REG (x));
4798 /* See if this can be moved to simplify_subreg. */
4799 if (CONSTANT_P (SUBREG_REG (x))
4800 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4801 /* Don't call gen_lowpart if the inner mode
4802 is VOIDmode and we cannot simplify it, as SUBREG without
4803 inner mode is invalid. */
4804 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4805 || gen_lowpart_common (mode, SUBREG_REG (x))))
4806 return gen_lowpart (mode, SUBREG_REG (x));
4808 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4812 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4818 /* Don't change the mode of the MEM if that would change the meaning
4820 if (MEM_P (SUBREG_REG (x))
4821 && (MEM_VOLATILE_P (SUBREG_REG (x))
4822 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4823 return gen_rtx_CLOBBER (mode, const0_rtx);
4825 /* Note that we cannot do any narrowing for non-constants since
4826 we might have been counting on using the fact that some bits were
4827 zero. We now do this in the SET. */
4832 temp = expand_compound_operation (XEXP (x, 0));
4834 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4835 replaced by (lshiftrt X C). This will convert
4836 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4838 if (GET_CODE (temp) == ASHIFTRT
4839 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4840 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4841 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4842 INTVAL (XEXP (temp, 1)));
4844 /* If X has only a single bit that might be nonzero, say, bit I, convert
4845 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4846 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4847 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4848 or a SUBREG of one since we'd be making the expression more
4849 complex if it was just a register. */
4852 && ! (GET_CODE (temp) == SUBREG
4853 && REG_P (SUBREG_REG (temp)))
4854 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4856 rtx temp1 = simplify_shift_const
4857 (NULL_RTX, ASHIFTRT, mode,
4858 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4859 GET_MODE_BITSIZE (mode) - 1 - i),
4860 GET_MODE_BITSIZE (mode) - 1 - i);
4862 /* If all we did was surround TEMP with the two shifts, we
4863 haven't improved anything, so don't use it. Otherwise,
4864 we are better off with TEMP1. */
4865 if (GET_CODE (temp1) != ASHIFTRT
4866 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4867 || XEXP (XEXP (temp1, 0), 0) != temp)
4873 /* We can't handle truncation to a partial integer mode here
4874 because we don't know the real bitsize of the partial
4876 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4879 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4880 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4881 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4883 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4884 GET_MODE_MASK (mode), 0));
4886 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4887 whose value is a comparison can be replaced with a subreg if
4888 STORE_FLAG_VALUE permits. */
4889 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4890 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4891 && (temp = get_last_value (XEXP (x, 0)))
4892 && COMPARISON_P (temp))
4893 return gen_lowpart (mode, XEXP (x, 0));
4898 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4899 using cc0, in which case we want to leave it as a COMPARE
4900 so we can distinguish it from a register-register-copy. */
4901 if (XEXP (x, 1) == const0_rtx)
4904 /* x - 0 is the same as x unless x's mode has signed zeros and
4905 allows rounding towards -infinity. Under those conditions,
4907 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4908 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4909 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4915 /* (const (const X)) can become (const X). Do it this way rather than
4916 returning the inner CONST since CONST can be shared with a
4918 if (GET_CODE (XEXP (x, 0)) == CONST)
4919 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4924 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4925 can add in an offset. find_split_point will split this address up
4926 again if it doesn't match. */
4927 if (GET_CODE (XEXP (x, 0)) == HIGH
4928 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4934 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4935 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4936 bit-field and can be replaced by either a sign_extend or a
4937 sign_extract. The `and' may be a zero_extend and the two
4938 <c>, -<c> constants may be reversed. */
4939 if (GET_CODE (XEXP (x, 0)) == XOR
4940 && GET_CODE (XEXP (x, 1)) == CONST_INT
4941 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4942 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4943 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4944 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4945 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4946 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4947 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4948 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4949 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4950 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4951 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4952 == (unsigned int) i + 1))))
4953 return simplify_shift_const
4954 (NULL_RTX, ASHIFTRT, mode,
4955 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4956 XEXP (XEXP (XEXP (x, 0), 0), 0),
4957 GET_MODE_BITSIZE (mode) - (i + 1)),
4958 GET_MODE_BITSIZE (mode) - (i + 1));
4960 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4961 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4962 the bitsize of the mode - 1. This allows simplification of
4963 "a = (b & 8) == 0;" */
4964 if (XEXP (x, 1) == constm1_rtx
4965 && !REG_P (XEXP (x, 0))
4966 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4967 && REG_P (SUBREG_REG (XEXP (x, 0))))
4968 && nonzero_bits (XEXP (x, 0), mode) == 1)
4969 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4970 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4971 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4972 GET_MODE_BITSIZE (mode) - 1),
4973 GET_MODE_BITSIZE (mode) - 1);
4975 /* If we are adding two things that have no bits in common, convert
4976 the addition into an IOR. This will often be further simplified,
4977 for example in cases like ((a & 1) + (a & 2)), which can
4980 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4981 && (nonzero_bits (XEXP (x, 0), mode)
4982 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4984 /* Try to simplify the expression further. */
4985 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4986 temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
4988 /* If we could, great. If not, do not go ahead with the IOR
4989 replacement, since PLUS appears in many special purpose
4990 address arithmetic instructions. */
4991 if (GET_CODE (temp) != CLOBBER && temp != tor)
4997 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4998 (and <foo> (const_int pow2-1)) */
4999 if (GET_CODE (XEXP (x, 1)) == AND
5000 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5001 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5002 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5003 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5004 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5008 /* If we have (mult (plus A B) C), apply the distributive law and then
5009 the inverse distributive law to see if things simplify. This
5010 occurs mostly in addresses, often when unrolling loops. */
5012 if (GET_CODE (XEXP (x, 0)) == PLUS)
5014 rtx result = distribute_and_simplify_rtx (x, 0);
5019 /* Try simplify a*(b/c) as (a*b)/c. */
5020 if (FLOAT_MODE_P (mode) && flag_associative_math
5021 && GET_CODE (XEXP (x, 0)) == DIV)
5023 rtx tem = simplify_binary_operation (MULT, mode,
5024 XEXP (XEXP (x, 0), 0),
5027 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5032 /* If this is a divide by a power of two, treat it as a shift if
5033 its first operand is a shift. */
5034 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5035 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5036 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5037 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5038 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5039 || GET_CODE (XEXP (x, 0)) == ROTATE
5040 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5041 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5045 case GT: case GTU: case GE: case GEU:
5046 case LT: case LTU: case LE: case LEU:
5047 case UNEQ: case LTGT:
5048 case UNGT: case UNGE:
5049 case UNLT: case UNLE:
5050 case UNORDERED: case ORDERED:
5051 /* If the first operand is a condition code, we can't do anything
5053 if (GET_CODE (XEXP (x, 0)) == COMPARE
5054 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5055 && ! CC0_P (XEXP (x, 0))))
5057 rtx op0 = XEXP (x, 0);
5058 rtx op1 = XEXP (x, 1);
5059 enum rtx_code new_code;
5061 if (GET_CODE (op0) == COMPARE)
5062 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5064 /* Simplify our comparison, if possible. */
5065 new_code = simplify_comparison (code, &op0, &op1);
5067 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5068 if only the low-order bit is possibly nonzero in X (such as when
5069 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5070 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5071 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5074 Remove any ZERO_EXTRACT we made when thinking this was a
5075 comparison. It may now be simpler to use, e.g., an AND. If a
5076 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5077 the call to make_compound_operation in the SET case. */
5079 if (STORE_FLAG_VALUE == 1
5080 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5081 && op1 == const0_rtx
5082 && mode == GET_MODE (op0)
5083 && nonzero_bits (op0, mode) == 1)
5084 return gen_lowpart (mode,
5085 expand_compound_operation (op0));
5087 else if (STORE_FLAG_VALUE == 1
5088 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5089 && op1 == const0_rtx
5090 && mode == GET_MODE (op0)
5091 && (num_sign_bit_copies (op0, mode)
5092 == GET_MODE_BITSIZE (mode)))
5094 op0 = expand_compound_operation (op0);
5095 return simplify_gen_unary (NEG, mode,
5096 gen_lowpart (mode, op0),
5100 else if (STORE_FLAG_VALUE == 1
5101 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5102 && op1 == const0_rtx
5103 && mode == GET_MODE (op0)
5104 && nonzero_bits (op0, mode) == 1)
5106 op0 = expand_compound_operation (op0);
5107 return simplify_gen_binary (XOR, mode,
5108 gen_lowpart (mode, op0),
5112 else if (STORE_FLAG_VALUE == 1
5113 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5114 && op1 == const0_rtx
5115 && mode == GET_MODE (op0)
5116 && (num_sign_bit_copies (op0, mode)
5117 == GET_MODE_BITSIZE (mode)))
5119 op0 = expand_compound_operation (op0);
5120 return plus_constant (gen_lowpart (mode, op0), 1);
5123 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5125 if (STORE_FLAG_VALUE == -1
5126 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5127 && op1 == const0_rtx
5128 && (num_sign_bit_copies (op0, mode)
5129 == GET_MODE_BITSIZE (mode)))
5130 return gen_lowpart (mode,
5131 expand_compound_operation (op0));
5133 else if (STORE_FLAG_VALUE == -1
5134 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5135 && op1 == const0_rtx
5136 && mode == GET_MODE (op0)
5137 && nonzero_bits (op0, mode) == 1)
5139 op0 = expand_compound_operation (op0);
5140 return simplify_gen_unary (NEG, mode,
5141 gen_lowpart (mode, op0),
5145 else if (STORE_FLAG_VALUE == -1
5146 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5147 && op1 == const0_rtx
5148 && mode == GET_MODE (op0)
5149 && (num_sign_bit_copies (op0, mode)
5150 == GET_MODE_BITSIZE (mode)))
5152 op0 = expand_compound_operation (op0);
5153 return simplify_gen_unary (NOT, mode,
5154 gen_lowpart (mode, op0),
5158 /* If X is 0/1, (eq X 0) is X-1. */
5159 else if (STORE_FLAG_VALUE == -1
5160 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5161 && op1 == const0_rtx
5162 && mode == GET_MODE (op0)
5163 && nonzero_bits (op0, mode) == 1)
5165 op0 = expand_compound_operation (op0);
5166 return plus_constant (gen_lowpart (mode, op0), -1);
5169 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5170 one bit that might be nonzero, we can convert (ne x 0) to
5171 (ashift x c) where C puts the bit in the sign bit. Remove any
5172 AND with STORE_FLAG_VALUE when we are done, since we are only
5173 going to test the sign bit. */
5174 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5175 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5176 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5177 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5178 && op1 == const0_rtx
5179 && mode == GET_MODE (op0)
5180 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5182 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5183 expand_compound_operation (op0),
5184 GET_MODE_BITSIZE (mode) - 1 - i);
5185 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5191 /* If the code changed, return a whole new comparison. */
5192 if (new_code != code)
5193 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5195 /* Otherwise, keep this operation, but maybe change its operands.
5196 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5197 SUBST (XEXP (x, 0), op0);
5198 SUBST (XEXP (x, 1), op1);
5203 return simplify_if_then_else (x);
5209 /* If we are processing SET_DEST, we are done. */
5213 return expand_compound_operation (x);
5216 return simplify_set (x);
5220 return simplify_logical (x);
5227 /* If this is a shift by a constant amount, simplify it. */
5228 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5229 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5230 INTVAL (XEXP (x, 1)));
5232 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5234 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5236 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5248 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5251 simplify_if_then_else (rtx x)
5253 enum machine_mode mode = GET_MODE (x);
5254 rtx cond = XEXP (x, 0);
5255 rtx true_rtx = XEXP (x, 1);
5256 rtx false_rtx = XEXP (x, 2);
5257 enum rtx_code true_code = GET_CODE (cond);
5258 int comparison_p = COMPARISON_P (cond);
5261 enum rtx_code false_code;
5264 /* Simplify storing of the truth value. */
5265 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5266 return simplify_gen_relational (true_code, mode, VOIDmode,
5267 XEXP (cond, 0), XEXP (cond, 1));
5269 /* Also when the truth value has to be reversed. */
5271 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5272 && (reversed = reversed_comparison (cond, mode)))
5275 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5276 in it is being compared against certain values. Get the true and false
5277 comparisons and see if that says anything about the value of each arm. */
5280 && ((false_code = reversed_comparison_code (cond, NULL))
5282 && REG_P (XEXP (cond, 0)))
5285 rtx from = XEXP (cond, 0);
5286 rtx true_val = XEXP (cond, 1);
5287 rtx false_val = true_val;
5290 /* If FALSE_CODE is EQ, swap the codes and arms. */
5292 if (false_code == EQ)
5294 swapped = 1, true_code = EQ, false_code = NE;
5295 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5298 /* If we are comparing against zero and the expression being tested has
5299 only a single bit that might be nonzero, that is its value when it is
5300 not equal to zero. Similarly if it is known to be -1 or 0. */
5302 if (true_code == EQ && true_val == const0_rtx
5303 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5306 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5308 else if (true_code == EQ && true_val == const0_rtx
5309 && (num_sign_bit_copies (from, GET_MODE (from))
5310 == GET_MODE_BITSIZE (GET_MODE (from))))
5313 false_val = constm1_rtx;
5316 /* Now simplify an arm if we know the value of the register in the
5317 branch and it is used in the arm. Be careful due to the potential
5318 of locally-shared RTL. */
5320 if (reg_mentioned_p (from, true_rtx))
5321 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5323 pc_rtx, pc_rtx, 0, 0);
5324 if (reg_mentioned_p (from, false_rtx))
5325 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5327 pc_rtx, pc_rtx, 0, 0);
5329 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5330 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5332 true_rtx = XEXP (x, 1);
5333 false_rtx = XEXP (x, 2);
5334 true_code = GET_CODE (cond);
5337 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5338 reversed, do so to avoid needing two sets of patterns for
5339 subtract-and-branch insns. Similarly if we have a constant in the true
5340 arm, the false arm is the same as the first operand of the comparison, or
5341 the false arm is more complicated than the true arm. */
5344 && reversed_comparison_code (cond, NULL) != UNKNOWN
5345 && (true_rtx == pc_rtx
5346 || (CONSTANT_P (true_rtx)
5347 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5348 || true_rtx == const0_rtx
5349 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5350 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5351 && !OBJECT_P (false_rtx))
5352 || reg_mentioned_p (true_rtx, false_rtx)
5353 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5355 true_code = reversed_comparison_code (cond, NULL);
5356 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5357 SUBST (XEXP (x, 1), false_rtx);
5358 SUBST (XEXP (x, 2), true_rtx);
5360 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5363 /* It is possible that the conditional has been simplified out. */
5364 true_code = GET_CODE (cond);
5365 comparison_p = COMPARISON_P (cond);
5368 /* If the two arms are identical, we don't need the comparison. */
5370 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5373 /* Convert a == b ? b : a to "a". */
5374 if (true_code == EQ && ! side_effects_p (cond)
5375 && !HONOR_NANS (mode)
5376 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5377 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5379 else if (true_code == NE && ! side_effects_p (cond)
5380 && !HONOR_NANS (mode)
5381 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5382 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5385 /* Look for cases where we have (abs x) or (neg (abs X)). */
5387 if (GET_MODE_CLASS (mode) == MODE_INT
5389 && XEXP (cond, 1) == const0_rtx
5390 && GET_CODE (false_rtx) == NEG
5391 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5392 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5393 && ! side_effects_p (true_rtx))
5398 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5402 simplify_gen_unary (NEG, mode,
5403 simplify_gen_unary (ABS, mode, true_rtx, mode),
5409 /* Look for MIN or MAX. */
5411 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5413 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5414 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5415 && ! side_effects_p (cond))
5420 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5423 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5426 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5429 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5434 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5435 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5436 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5437 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5438 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5439 neither 1 or -1, but it isn't worth checking for. */
5441 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5443 && GET_MODE_CLASS (mode) == MODE_INT
5444 && ! side_effects_p (x))
5446 rtx t = make_compound_operation (true_rtx, SET);
5447 rtx f = make_compound_operation (false_rtx, SET);
5448 rtx cond_op0 = XEXP (cond, 0);
5449 rtx cond_op1 = XEXP (cond, 1);
5450 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5451 enum machine_mode m = mode;
5452 rtx z = 0, c1 = NULL_RTX;
5454 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5455 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5456 || GET_CODE (t) == ASHIFT
5457 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5458 && rtx_equal_p (XEXP (t, 0), f))
5459 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5461 /* If an identity-zero op is commutative, check whether there
5462 would be a match if we swapped the operands. */
5463 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5464 || GET_CODE (t) == XOR)
5465 && rtx_equal_p (XEXP (t, 1), f))
5466 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5467 else if (GET_CODE (t) == SIGN_EXTEND
5468 && (GET_CODE (XEXP (t, 0)) == PLUS
5469 || GET_CODE (XEXP (t, 0)) == MINUS
5470 || GET_CODE (XEXP (t, 0)) == IOR
5471 || GET_CODE (XEXP (t, 0)) == XOR
5472 || GET_CODE (XEXP (t, 0)) == ASHIFT
5473 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5474 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5475 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5476 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5477 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5478 && (num_sign_bit_copies (f, GET_MODE (f))
5480 (GET_MODE_BITSIZE (mode)
5481 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5483 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5484 extend_op = SIGN_EXTEND;
5485 m = GET_MODE (XEXP (t, 0));
5487 else if (GET_CODE (t) == SIGN_EXTEND
5488 && (GET_CODE (XEXP (t, 0)) == PLUS
5489 || GET_CODE (XEXP (t, 0)) == IOR
5490 || GET_CODE (XEXP (t, 0)) == XOR)
5491 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5492 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5493 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5494 && (num_sign_bit_copies (f, GET_MODE (f))
5496 (GET_MODE_BITSIZE (mode)
5497 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5499 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5500 extend_op = SIGN_EXTEND;
5501 m = GET_MODE (XEXP (t, 0));
5503 else if (GET_CODE (t) == ZERO_EXTEND
5504 && (GET_CODE (XEXP (t, 0)) == PLUS
5505 || GET_CODE (XEXP (t, 0)) == MINUS
5506 || GET_CODE (XEXP (t, 0)) == IOR
5507 || GET_CODE (XEXP (t, 0)) == XOR
5508 || GET_CODE (XEXP (t, 0)) == ASHIFT
5509 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5510 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5511 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5512 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5513 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5514 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5515 && ((nonzero_bits (f, GET_MODE (f))
5516 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5519 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5520 extend_op = ZERO_EXTEND;
5521 m = GET_MODE (XEXP (t, 0));
5523 else if (GET_CODE (t) == ZERO_EXTEND
5524 && (GET_CODE (XEXP (t, 0)) == PLUS
5525 || GET_CODE (XEXP (t, 0)) == IOR
5526 || GET_CODE (XEXP (t, 0)) == XOR)
5527 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5528 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5529 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5530 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5531 && ((nonzero_bits (f, GET_MODE (f))
5532 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5535 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5536 extend_op = ZERO_EXTEND;
5537 m = GET_MODE (XEXP (t, 0));
5542 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5543 cond_op0, cond_op1),
5544 pc_rtx, pc_rtx, 0, 0);
5545 temp = simplify_gen_binary (MULT, m, temp,
5546 simplify_gen_binary (MULT, m, c1,
5548 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5549 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5551 if (extend_op != UNKNOWN)
5552 temp = simplify_gen_unary (extend_op, mode, temp, m);
5558 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5559 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5560 negation of a single bit, we can convert this operation to a shift. We
5561 can actually do this more generally, but it doesn't seem worth it. */
5563 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5564 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5565 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5566 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5567 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5568 == GET_MODE_BITSIZE (mode))
5569 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5571 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5572 gen_lowpart (mode, XEXP (cond, 0)), i);
5574 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5575 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5576 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5577 && GET_MODE (XEXP (cond, 0)) == mode
5578 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5579 == nonzero_bits (XEXP (cond, 0), mode)
5580 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5581 return XEXP (cond, 0);
5586 /* Simplify X, a SET expression. Return the new expression. */
5589 simplify_set (rtx x)
5591 rtx src = SET_SRC (x);
5592 rtx dest = SET_DEST (x);
5593 enum machine_mode mode
5594 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5598 /* (set (pc) (return)) gets written as (return). */
5599 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5602 /* Now that we know for sure which bits of SRC we are using, see if we can
5603 simplify the expression for the object knowing that we only need the
5606 if (GET_MODE_CLASS (mode) == MODE_INT
5607 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5609 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5610 SUBST (SET_SRC (x), src);
5613 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5614 the comparison result and try to simplify it unless we already have used
5615 undobuf.other_insn. */
5616 if ((GET_MODE_CLASS (mode) == MODE_CC
5617 || GET_CODE (src) == COMPARE
5619 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5620 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5621 && COMPARISON_P (*cc_use)
5622 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5624 enum rtx_code old_code = GET_CODE (*cc_use);
5625 enum rtx_code new_code;
5627 int other_changed = 0;
5628 enum machine_mode compare_mode = GET_MODE (dest);
5630 if (GET_CODE (src) == COMPARE)
5631 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5633 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5635 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5638 new_code = old_code;
5639 else if (!CONSTANT_P (tmp))
5641 new_code = GET_CODE (tmp);
5642 op0 = XEXP (tmp, 0);
5643 op1 = XEXP (tmp, 1);
5647 rtx pat = PATTERN (other_insn);
5648 undobuf.other_insn = other_insn;
5649 SUBST (*cc_use, tmp);
5651 /* Attempt to simplify CC user. */
5652 if (GET_CODE (pat) == SET)
5654 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5655 if (new_rtx != NULL_RTX)
5656 SUBST (SET_SRC (pat), new_rtx);
5659 /* Convert X into a no-op move. */
5660 SUBST (SET_DEST (x), pc_rtx);
5661 SUBST (SET_SRC (x), pc_rtx);
5665 /* Simplify our comparison, if possible. */
5666 new_code = simplify_comparison (new_code, &op0, &op1);
5668 #ifdef SELECT_CC_MODE
5669 /* If this machine has CC modes other than CCmode, check to see if we
5670 need to use a different CC mode here. */
5671 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5672 compare_mode = GET_MODE (op0);
5674 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5677 /* If the mode changed, we have to change SET_DEST, the mode in the
5678 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5679 a hard register, just build new versions with the proper mode. If it
5680 is a pseudo, we lose unless it is only time we set the pseudo, in
5681 which case we can safely change its mode. */
5682 if (compare_mode != GET_MODE (dest))
5684 if (can_change_dest_mode (dest, 0, compare_mode))
5686 unsigned int regno = REGNO (dest);
5689 if (regno < FIRST_PSEUDO_REGISTER)
5690 new_dest = gen_rtx_REG (compare_mode, regno);
5693 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5694 new_dest = regno_reg_rtx[regno];
5697 SUBST (SET_DEST (x), new_dest);
5698 SUBST (XEXP (*cc_use, 0), new_dest);
5705 #endif /* SELECT_CC_MODE */
5707 /* If the code changed, we have to build a new comparison in
5708 undobuf.other_insn. */
5709 if (new_code != old_code)
5711 int other_changed_previously = other_changed;
5712 unsigned HOST_WIDE_INT mask;
5713 rtx old_cc_use = *cc_use;
5715 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5719 /* If the only change we made was to change an EQ into an NE or
5720 vice versa, OP0 has only one bit that might be nonzero, and OP1
5721 is zero, check if changing the user of the condition code will
5722 produce a valid insn. If it won't, we can keep the original code
5723 in that insn by surrounding our operation with an XOR. */
5725 if (((old_code == NE && new_code == EQ)
5726 || (old_code == EQ && new_code == NE))
5727 && ! other_changed_previously && op1 == const0_rtx
5728 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5729 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5731 rtx pat = PATTERN (other_insn), note = 0;
5733 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5734 && ! check_asm_operands (pat)))
5736 *cc_use = old_cc_use;
5739 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5740 op0, GEN_INT (mask));
5746 undobuf.other_insn = other_insn;
5749 /* If we are now comparing against zero, change our source if
5750 needed. If we do not use cc0, we always have a COMPARE. */
5751 if (op1 == const0_rtx && dest == cc0_rtx)
5753 SUBST (SET_SRC (x), op0);
5759 /* Otherwise, if we didn't previously have a COMPARE in the
5760 correct mode, we need one. */
5761 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5763 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5766 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5768 SUBST (SET_SRC (x), op0);
5771 /* Otherwise, update the COMPARE if needed. */
5772 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5774 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5780 /* Get SET_SRC in a form where we have placed back any
5781 compound expressions. Then do the checks below. */
5782 src = make_compound_operation (src, SET);
5783 SUBST (SET_SRC (x), src);
5786 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5787 and X being a REG or (subreg (reg)), we may be able to convert this to
5788 (set (subreg:m2 x) (op)).
5790 We can always do this if M1 is narrower than M2 because that means that
5791 we only care about the low bits of the result.
5793 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5794 perform a narrower operation than requested since the high-order bits will
5795 be undefined. On machine where it is defined, this transformation is safe
5796 as long as M1 and M2 have the same number of words. */
5798 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5799 && !OBJECT_P (SUBREG_REG (src))
5800 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5802 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5803 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5804 #ifndef WORD_REGISTER_OPERATIONS
5805 && (GET_MODE_SIZE (GET_MODE (src))
5806 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5808 #ifdef CANNOT_CHANGE_MODE_CLASS
5809 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5810 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5811 GET_MODE (SUBREG_REG (src)),
5815 || (GET_CODE (dest) == SUBREG
5816 && REG_P (SUBREG_REG (dest)))))
5818 SUBST (SET_DEST (x),
5819 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5821 SUBST (SET_SRC (x), SUBREG_REG (src));
5823 src = SET_SRC (x), dest = SET_DEST (x);
5827 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5830 && GET_CODE (src) == SUBREG
5831 && subreg_lowpart_p (src)
5832 && (GET_MODE_BITSIZE (GET_MODE (src))
5833 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5835 rtx inner = SUBREG_REG (src);
5836 enum machine_mode inner_mode = GET_MODE (inner);
5838 /* Here we make sure that we don't have a sign bit on. */
5839 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5840 && (nonzero_bits (inner, inner_mode)
5841 < ((unsigned HOST_WIDE_INT) 1
5842 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5844 SUBST (SET_SRC (x), inner);
5850 #ifdef LOAD_EXTEND_OP
5851 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5852 would require a paradoxical subreg. Replace the subreg with a
5853 zero_extend to avoid the reload that would otherwise be required. */
5855 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5856 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
5857 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5858 && SUBREG_BYTE (src) == 0
5859 && (GET_MODE_SIZE (GET_MODE (src))
5860 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5861 && MEM_P (SUBREG_REG (src)))
5864 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5865 GET_MODE (src), SUBREG_REG (src)));
5871 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5872 are comparing an item known to be 0 or -1 against 0, use a logical
5873 operation instead. Check for one of the arms being an IOR of the other
5874 arm with some value. We compute three terms to be IOR'ed together. In
5875 practice, at most two will be nonzero. Then we do the IOR's. */
5877 if (GET_CODE (dest) != PC
5878 && GET_CODE (src) == IF_THEN_ELSE
5879 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5880 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5881 && XEXP (XEXP (src, 0), 1) == const0_rtx
5882 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5883 #ifdef HAVE_conditional_move
5884 && ! can_conditionally_move_p (GET_MODE (src))
5886 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5887 GET_MODE (XEXP (XEXP (src, 0), 0)))
5888 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5889 && ! side_effects_p (src))
5891 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5892 ? XEXP (src, 1) : XEXP (src, 2));
5893 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5894 ? XEXP (src, 2) : XEXP (src, 1));
5895 rtx term1 = const0_rtx, term2, term3;
5897 if (GET_CODE (true_rtx) == IOR
5898 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5899 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5900 else if (GET_CODE (true_rtx) == IOR
5901 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5902 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5903 else if (GET_CODE (false_rtx) == IOR
5904 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5905 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5906 else if (GET_CODE (false_rtx) == IOR
5907 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5908 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5910 term2 = simplify_gen_binary (AND, GET_MODE (src),
5911 XEXP (XEXP (src, 0), 0), true_rtx);
5912 term3 = simplify_gen_binary (AND, GET_MODE (src),
5913 simplify_gen_unary (NOT, GET_MODE (src),
5914 XEXP (XEXP (src, 0), 0),
5919 simplify_gen_binary (IOR, GET_MODE (src),
5920 simplify_gen_binary (IOR, GET_MODE (src),
5927 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5928 whole thing fail. */
5929 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5931 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5934 /* Convert this into a field assignment operation, if possible. */
5935 return make_field_assignment (x);
5938 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5942 simplify_logical (rtx x)
5944 enum machine_mode mode = GET_MODE (x);
5945 rtx op0 = XEXP (x, 0);
5946 rtx op1 = XEXP (x, 1);
5948 switch (GET_CODE (x))
5951 /* We can call simplify_and_const_int only if we don't lose
5952 any (sign) bits when converting INTVAL (op1) to
5953 "unsigned HOST_WIDE_INT". */
5954 if (GET_CODE (op1) == CONST_INT
5955 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5956 || INTVAL (op1) > 0))
5958 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5959 if (GET_CODE (x) != AND)
5966 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5967 apply the distributive law and then the inverse distributive
5968 law to see if things simplify. */
5969 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5971 rtx result = distribute_and_simplify_rtx (x, 0);
5975 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5977 rtx result = distribute_and_simplify_rtx (x, 1);
5984 /* If we have (ior (and A B) C), apply the distributive law and then
5985 the inverse distributive law to see if things simplify. */
5987 if (GET_CODE (op0) == AND)
5989 rtx result = distribute_and_simplify_rtx (x, 0);
5994 if (GET_CODE (op1) == AND)
5996 rtx result = distribute_and_simplify_rtx (x, 1);
6009 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6010 operations" because they can be replaced with two more basic operations.
6011 ZERO_EXTEND is also considered "compound" because it can be replaced with
6012 an AND operation, which is simpler, though only one operation.
6014 The function expand_compound_operation is called with an rtx expression
6015 and will convert it to the appropriate shifts and AND operations,
6016 simplifying at each stage.
6018 The function make_compound_operation is called to convert an expression
6019 consisting of shifts and ANDs into the equivalent compound expression.
6020 It is the inverse of this function, loosely speaking. */
6023 expand_compound_operation (rtx x)
6025 unsigned HOST_WIDE_INT pos = 0, len;
6027 unsigned int modewidth;
6030 switch (GET_CODE (x))
6035 /* We can't necessarily use a const_int for a multiword mode;
6036 it depends on implicitly extending the value.
6037 Since we don't know the right way to extend it,
6038 we can't tell whether the implicit way is right.
6040 Even for a mode that is no wider than a const_int,
6041 we can't win, because we need to sign extend one of its bits through
6042 the rest of it, and we don't know which bit. */
6043 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6046 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6047 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6048 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6049 reloaded. If not for that, MEM's would very rarely be safe.
6051 Reject MODEs bigger than a word, because we might not be able
6052 to reference a two-register group starting with an arbitrary register
6053 (and currently gen_lowpart might crash for a SUBREG). */
6055 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6058 /* Reject MODEs that aren't scalar integers because turning vector
6059 or complex modes into shifts causes problems. */
6061 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6064 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6065 /* If the inner object has VOIDmode (the only way this can happen
6066 is if it is an ASM_OPERANDS), we can't do anything since we don't
6067 know how much masking to do. */
6076 /* ... fall through ... */
6079 /* If the operand is a CLOBBER, just return it. */
6080 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6083 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6084 || GET_CODE (XEXP (x, 2)) != CONST_INT
6085 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6088 /* Reject MODEs that aren't scalar integers because turning vector
6089 or complex modes into shifts causes problems. */
6091 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6094 len = INTVAL (XEXP (x, 1));
6095 pos = INTVAL (XEXP (x, 2));
6097 /* This should stay within the object being extracted, fail otherwise. */
6098 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6101 if (BITS_BIG_ENDIAN)
6102 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6109 /* Convert sign extension to zero extension, if we know that the high
6110 bit is not set, as this is easier to optimize. It will be converted
6111 back to cheaper alternative in make_extraction. */
6112 if (GET_CODE (x) == SIGN_EXTEND
6113 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6114 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6115 & ~(((unsigned HOST_WIDE_INT)
6116 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6120 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6121 rtx temp2 = expand_compound_operation (temp);
6123 /* Make sure this is a profitable operation. */
6124 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6125 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6127 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6128 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6134 /* We can optimize some special cases of ZERO_EXTEND. */
6135 if (GET_CODE (x) == ZERO_EXTEND)
6137 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6138 know that the last value didn't have any inappropriate bits
6140 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6141 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6142 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6143 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6144 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6145 return XEXP (XEXP (x, 0), 0);
6147 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6148 if (GET_CODE (XEXP (x, 0)) == SUBREG
6149 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6150 && subreg_lowpart_p (XEXP (x, 0))
6151 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6152 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6153 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6154 return SUBREG_REG (XEXP (x, 0));
6156 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6157 is a comparison and STORE_FLAG_VALUE permits. This is like
6158 the first case, but it works even when GET_MODE (x) is larger
6159 than HOST_WIDE_INT. */
6160 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6161 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6162 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6163 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6164 <= HOST_BITS_PER_WIDE_INT)
6165 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6166 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6167 return XEXP (XEXP (x, 0), 0);
6169 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6170 if (GET_CODE (XEXP (x, 0)) == SUBREG
6171 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6172 && subreg_lowpart_p (XEXP (x, 0))
6173 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6174 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6175 <= HOST_BITS_PER_WIDE_INT)
6176 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6177 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6178 return SUBREG_REG (XEXP (x, 0));
6182 /* If we reach here, we want to return a pair of shifts. The inner
6183 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6184 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6185 logical depending on the value of UNSIGNEDP.
6187 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6188 converted into an AND of a shift.
6190 We must check for the case where the left shift would have a negative
6191 count. This can happen in a case like (x >> 31) & 255 on machines
6192 that can't shift by a constant. On those machines, we would first
6193 combine the shift with the AND to produce a variable-position
6194 extraction. Then the constant of 31 would be substituted in to produce
6195 a such a position. */
6197 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6198 if (modewidth + len >= pos)
6200 enum machine_mode mode = GET_MODE (x);
6201 tem = gen_lowpart (mode, XEXP (x, 0));
6202 if (!tem || GET_CODE (tem) == CLOBBER)
6204 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6205 tem, modewidth - pos - len);
6206 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6207 mode, tem, modewidth - len);
6209 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6210 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6211 simplify_shift_const (NULL_RTX, LSHIFTRT,
6214 ((HOST_WIDE_INT) 1 << len) - 1);
6216 /* Any other cases we can't handle. */
6219 /* If we couldn't do this for some reason, return the original
6221 if (GET_CODE (tem) == CLOBBER)
6227 /* X is a SET which contains an assignment of one object into
6228 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6229 or certain SUBREGS). If possible, convert it into a series of
6232 We half-heartedly support variable positions, but do not at all
6233 support variable lengths. */
6236 expand_field_assignment (const_rtx x)
6239 rtx pos; /* Always counts from low bit. */
6241 rtx mask, cleared, masked;
6242 enum machine_mode compute_mode;
6244 /* Loop until we find something we can't simplify. */
6247 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6248 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6250 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6251 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6252 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6254 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6255 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6257 inner = XEXP (SET_DEST (x), 0);
6258 len = INTVAL (XEXP (SET_DEST (x), 1));
6259 pos = XEXP (SET_DEST (x), 2);
6261 /* A constant position should stay within the width of INNER. */
6262 if (GET_CODE (pos) == CONST_INT
6263 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6266 if (BITS_BIG_ENDIAN)
6268 if (GET_CODE (pos) == CONST_INT)
6269 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6271 else if (GET_CODE (pos) == MINUS
6272 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6273 && (INTVAL (XEXP (pos, 1))
6274 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6275 /* If position is ADJUST - X, new position is X. */
6276 pos = XEXP (pos, 0);
6278 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6279 GEN_INT (GET_MODE_BITSIZE (
6286 /* A SUBREG between two modes that occupy the same numbers of words
6287 can be done by moving the SUBREG to the source. */
6288 else if (GET_CODE (SET_DEST (x)) == SUBREG
6289 /* We need SUBREGs to compute nonzero_bits properly. */
6290 && nonzero_sign_valid
6291 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6292 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6293 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6294 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6296 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6298 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6305 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6306 inner = SUBREG_REG (inner);
6308 compute_mode = GET_MODE (inner);
6310 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6311 if (! SCALAR_INT_MODE_P (compute_mode))
6313 enum machine_mode imode;
6315 /* Don't do anything for vector or complex integral types. */
6316 if (! FLOAT_MODE_P (compute_mode))
6319 /* Try to find an integral mode to pun with. */
6320 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6321 if (imode == BLKmode)
6324 compute_mode = imode;
6325 inner = gen_lowpart (imode, inner);
6328 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6329 if (len >= HOST_BITS_PER_WIDE_INT)
6332 /* Now compute the equivalent expression. Make a copy of INNER
6333 for the SET_DEST in case it is a MEM into which we will substitute;
6334 we don't want shared RTL in that case. */
6335 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6336 cleared = simplify_gen_binary (AND, compute_mode,
6337 simplify_gen_unary (NOT, compute_mode,
6338 simplify_gen_binary (ASHIFT,
6343 masked = simplify_gen_binary (ASHIFT, compute_mode,
6344 simplify_gen_binary (
6346 gen_lowpart (compute_mode, SET_SRC (x)),
6350 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6351 simplify_gen_binary (IOR, compute_mode,
6358 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6359 it is an RTX that represents a variable starting position; otherwise,
6360 POS is the (constant) starting bit position (counted from the LSB).
6362 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6365 IN_DEST is nonzero if this is a reference in the destination of a
6366 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6367 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6370 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6371 ZERO_EXTRACT should be built even for bits starting at bit 0.
6373 MODE is the desired mode of the result (if IN_DEST == 0).
6375 The result is an RTX for the extraction or NULL_RTX if the target
6379 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6380 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6381 int in_dest, int in_compare)
6383 /* This mode describes the size of the storage area
6384 to fetch the overall value from. Within that, we
6385 ignore the POS lowest bits, etc. */
6386 enum machine_mode is_mode = GET_MODE (inner);
6387 enum machine_mode inner_mode;
6388 enum machine_mode wanted_inner_mode;
6389 enum machine_mode wanted_inner_reg_mode = word_mode;
6390 enum machine_mode pos_mode = word_mode;
6391 enum machine_mode extraction_mode = word_mode;
6392 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6394 rtx orig_pos_rtx = pos_rtx;
6395 HOST_WIDE_INT orig_pos;
6397 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6399 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6400 consider just the QI as the memory to extract from.
6401 The subreg adds or removes high bits; its mode is
6402 irrelevant to the meaning of this extraction,
6403 since POS and LEN count from the lsb. */
6404 if (MEM_P (SUBREG_REG (inner)))
6405 is_mode = GET_MODE (SUBREG_REG (inner));
6406 inner = SUBREG_REG (inner);
6408 else if (GET_CODE (inner) == ASHIFT
6409 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6410 && pos_rtx == 0 && pos == 0
6411 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6413 /* We're extracting the least significant bits of an rtx
6414 (ashift X (const_int C)), where LEN > C. Extract the
6415 least significant (LEN - C) bits of X, giving an rtx
6416 whose mode is MODE, then shift it left C times. */
6417 new_rtx = make_extraction (mode, XEXP (inner, 0),
6418 0, 0, len - INTVAL (XEXP (inner, 1)),
6419 unsignedp, in_dest, in_compare);
6421 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6424 inner_mode = GET_MODE (inner);
6426 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6427 pos = INTVAL (pos_rtx), pos_rtx = 0;
6429 /* See if this can be done without an extraction. We never can if the
6430 width of the field is not the same as that of some integer mode. For
6431 registers, we can only avoid the extraction if the position is at the
6432 low-order bit and this is either not in the destination or we have the
6433 appropriate STRICT_LOW_PART operation available.
6435 For MEM, we can avoid an extract if the field starts on an appropriate
6436 boundary and we can change the mode of the memory reference. */
6438 if (tmode != BLKmode
6439 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6441 && (inner_mode == tmode
6443 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6444 GET_MODE_BITSIZE (inner_mode))
6445 || reg_truncated_to_mode (tmode, inner))
6448 && have_insn_for (STRICT_LOW_PART, tmode))))
6449 || (MEM_P (inner) && pos_rtx == 0
6451 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6452 : BITS_PER_UNIT)) == 0
6453 /* We can't do this if we are widening INNER_MODE (it
6454 may not be aligned, for one thing). */
6455 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6456 && (inner_mode == tmode
6457 || (! mode_dependent_address_p (XEXP (inner, 0))
6458 && ! MEM_VOLATILE_P (inner))))))
6460 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6461 field. If the original and current mode are the same, we need not
6462 adjust the offset. Otherwise, we do if bytes big endian.
6464 If INNER is not a MEM, get a piece consisting of just the field
6465 of interest (in this case POS % BITS_PER_WORD must be 0). */
6469 HOST_WIDE_INT offset;
6471 /* POS counts from lsb, but make OFFSET count in memory order. */
6472 if (BYTES_BIG_ENDIAN)
6473 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6475 offset = pos / BITS_PER_UNIT;
6477 new_rtx = adjust_address_nv (inner, tmode, offset);
6479 else if (REG_P (inner))
6481 if (tmode != inner_mode)
6483 /* We can't call gen_lowpart in a DEST since we
6484 always want a SUBREG (see below) and it would sometimes
6485 return a new hard register. */
6488 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6490 if (WORDS_BIG_ENDIAN
6491 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6492 final_word = ((GET_MODE_SIZE (inner_mode)
6493 - GET_MODE_SIZE (tmode))
6494 / UNITS_PER_WORD) - final_word;
6496 final_word *= UNITS_PER_WORD;
6497 if (BYTES_BIG_ENDIAN &&
6498 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6499 final_word += (GET_MODE_SIZE (inner_mode)
6500 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6502 /* Avoid creating invalid subregs, for example when
6503 simplifying (x>>32)&255. */
6504 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6507 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6510 new_rtx = gen_lowpart (tmode, inner);
6516 new_rtx = force_to_mode (inner, tmode,
6517 len >= HOST_BITS_PER_WIDE_INT
6518 ? ~(unsigned HOST_WIDE_INT) 0
6519 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6522 /* If this extraction is going into the destination of a SET,
6523 make a STRICT_LOW_PART unless we made a MEM. */
6526 return (MEM_P (new_rtx) ? new_rtx
6527 : (GET_CODE (new_rtx) != SUBREG
6528 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6529 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6534 if (CONST_INT_P (new_rtx)
6535 || GET_CODE (new_rtx) == CONST_DOUBLE)
6536 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6537 mode, new_rtx, tmode);
6539 /* If we know that no extraneous bits are set, and that the high
6540 bit is not set, convert the extraction to the cheaper of
6541 sign and zero extension, that are equivalent in these cases. */
6542 if (flag_expensive_optimizations
6543 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6544 && ((nonzero_bits (new_rtx, tmode)
6545 & ~(((unsigned HOST_WIDE_INT)
6546 GET_MODE_MASK (tmode))
6550 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6551 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6553 /* Prefer ZERO_EXTENSION, since it gives more information to
6555 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6556 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6561 /* Otherwise, sign- or zero-extend unless we already are in the
6564 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6568 /* Unless this is a COMPARE or we have a funny memory reference,
6569 don't do anything with zero-extending field extracts starting at
6570 the low-order bit since they are simple AND operations. */
6571 if (pos_rtx == 0 && pos == 0 && ! in_dest
6572 && ! in_compare && unsignedp)
6575 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6576 if the position is not a constant and the length is not 1. In all
6577 other cases, we would only be going outside our object in cases when
6578 an original shift would have been undefined. */
6580 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6581 || (pos_rtx != 0 && len != 1)))
6584 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6585 and the mode for the result. */
6586 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6588 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6589 pos_mode = mode_for_extraction (EP_insv, 2);
6590 extraction_mode = mode_for_extraction (EP_insv, 3);
6593 if (! in_dest && unsignedp
6594 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6596 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6597 pos_mode = mode_for_extraction (EP_extzv, 3);
6598 extraction_mode = mode_for_extraction (EP_extzv, 0);
6601 if (! in_dest && ! unsignedp
6602 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6604 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6605 pos_mode = mode_for_extraction (EP_extv, 3);
6606 extraction_mode = mode_for_extraction (EP_extv, 0);
6609 /* Never narrow an object, since that might not be safe. */
6611 if (mode != VOIDmode
6612 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6613 extraction_mode = mode;
6615 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6616 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6617 pos_mode = GET_MODE (pos_rtx);
6619 /* If this is not from memory, the desired mode is the preferred mode
6620 for an extraction pattern's first input operand, or word_mode if there
6623 wanted_inner_mode = wanted_inner_reg_mode;
6626 /* Be careful not to go beyond the extracted object and maintain the
6627 natural alignment of the memory. */
6628 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6629 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6630 > GET_MODE_BITSIZE (wanted_inner_mode))
6632 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6633 gcc_assert (wanted_inner_mode != VOIDmode);
6636 /* If we have to change the mode of memory and cannot, the desired mode
6637 is EXTRACTION_MODE. */
6638 if (inner_mode != wanted_inner_mode
6639 && (mode_dependent_address_p (XEXP (inner, 0))
6640 || MEM_VOLATILE_P (inner)
6642 wanted_inner_mode = extraction_mode;
6647 if (BITS_BIG_ENDIAN)
6649 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6650 BITS_BIG_ENDIAN style. If position is constant, compute new
6651 position. Otherwise, build subtraction.
6652 Note that POS is relative to the mode of the original argument.
6653 If it's a MEM we need to recompute POS relative to that.
6654 However, if we're extracting from (or inserting into) a register,
6655 we want to recompute POS relative to wanted_inner_mode. */
6656 int width = (MEM_P (inner)
6657 ? GET_MODE_BITSIZE (is_mode)
6658 : GET_MODE_BITSIZE (wanted_inner_mode));
6661 pos = width - len - pos;
6664 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6665 /* POS may be less than 0 now, but we check for that below.
6666 Note that it can only be less than 0 if !MEM_P (inner). */
6669 /* If INNER has a wider mode, and this is a constant extraction, try to
6670 make it smaller and adjust the byte to point to the byte containing
6672 if (wanted_inner_mode != VOIDmode
6673 && inner_mode != wanted_inner_mode
6675 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6677 && ! mode_dependent_address_p (XEXP (inner, 0))
6678 && ! MEM_VOLATILE_P (inner))
6682 /* The computations below will be correct if the machine is big
6683 endian in both bits and bytes or little endian in bits and bytes.
6684 If it is mixed, we must adjust. */
6686 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6687 adjust OFFSET to compensate. */
6688 if (BYTES_BIG_ENDIAN
6689 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6690 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6692 /* We can now move to the desired byte. */
6693 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6694 * GET_MODE_SIZE (wanted_inner_mode);
6695 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6697 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6698 && is_mode != wanted_inner_mode)
6699 offset = (GET_MODE_SIZE (is_mode)
6700 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6702 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6705 /* If INNER is not memory, we can always get it into the proper mode. If we
6706 are changing its mode, POS must be a constant and smaller than the size
6708 else if (!MEM_P (inner))
6710 if (GET_MODE (inner) != wanted_inner_mode
6712 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6718 inner = force_to_mode (inner, wanted_inner_mode,
6720 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6721 ? ~(unsigned HOST_WIDE_INT) 0
6722 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6727 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6728 have to zero extend. Otherwise, we can just use a SUBREG. */
6730 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6732 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6734 /* If we know that no extraneous bits are set, and that the high
6735 bit is not set, convert extraction to cheaper one - either
6736 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6738 if (flag_expensive_optimizations
6739 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6740 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6741 & ~(((unsigned HOST_WIDE_INT)
6742 GET_MODE_MASK (GET_MODE (pos_rtx)))
6746 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6748 /* Prefer ZERO_EXTENSION, since it gives more information to
6750 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6751 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6756 else if (pos_rtx != 0
6757 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6758 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6760 /* Make POS_RTX unless we already have it and it is correct. If we don't
6761 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6763 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6764 pos_rtx = orig_pos_rtx;
6766 else if (pos_rtx == 0)
6767 pos_rtx = GEN_INT (pos);
6769 /* Make the required operation. See if we can use existing rtx. */
6770 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6771 extraction_mode, inner, GEN_INT (len), pos_rtx);
6773 new_rtx = gen_lowpart (mode, new_rtx);
6778 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6779 with any other operations in X. Return X without that shift if so. */
6782 extract_left_shift (rtx x, int count)
6784 enum rtx_code code = GET_CODE (x);
6785 enum machine_mode mode = GET_MODE (x);
6791 /* This is the shift itself. If it is wide enough, we will return
6792 either the value being shifted if the shift count is equal to
6793 COUNT or a shift for the difference. */
6794 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6795 && INTVAL (XEXP (x, 1)) >= count)
6796 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6797 INTVAL (XEXP (x, 1)) - count);
6801 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6802 return simplify_gen_unary (code, mode, tem, mode);
6806 case PLUS: case IOR: case XOR: case AND:
6807 /* If we can safely shift this constant and we find the inner shift,
6808 make a new operation. */
6809 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6810 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6811 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6812 return simplify_gen_binary (code, mode, tem,
6813 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6824 /* Look at the expression rooted at X. Look for expressions
6825 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6826 Form these expressions.
6828 Return the new rtx, usually just X.
6830 Also, for machines like the VAX that don't have logical shift insns,
6831 try to convert logical to arithmetic shift operations in cases where
6832 they are equivalent. This undoes the canonicalizations to logical
6833 shifts done elsewhere.
6835 We try, as much as possible, to re-use rtl expressions to save memory.
6837 IN_CODE says what kind of expression we are processing. Normally, it is
6838 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6839 being kludges), it is MEM. When processing the arguments of a comparison
6840 or a COMPARE against zero, it is COMPARE. */
6843 make_compound_operation (rtx x, enum rtx_code in_code)
6845 enum rtx_code code = GET_CODE (x);
6846 enum machine_mode mode = GET_MODE (x);
6847 int mode_width = GET_MODE_BITSIZE (mode);
6849 enum rtx_code next_code;
6855 /* Select the code to be used in recursive calls. Once we are inside an
6856 address, we stay there. If we have a comparison, set to COMPARE,
6857 but once inside, go back to our default of SET. */
6859 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6860 : ((code == COMPARE || COMPARISON_P (x))
6861 && XEXP (x, 1) == const0_rtx) ? COMPARE
6862 : in_code == COMPARE ? SET : in_code);
6864 /* Process depending on the code of this operation. If NEW is set
6865 nonzero, it will be returned. */
6870 /* Convert shifts by constants into multiplications if inside
6872 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6873 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6874 && INTVAL (XEXP (x, 1)) >= 0)
6876 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6877 new_rtx = gen_rtx_MULT (mode, new_rtx,
6878 GEN_INT ((HOST_WIDE_INT) 1
6879 << INTVAL (XEXP (x, 1))));
6884 /* If the second operand is not a constant, we can't do anything
6886 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6889 /* If the constant is a power of two minus one and the first operand
6890 is a logical right shift, make an extraction. */
6891 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6892 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6894 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6895 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6896 0, in_code == COMPARE);
6899 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6900 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6901 && subreg_lowpart_p (XEXP (x, 0))
6902 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6903 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6905 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6907 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6908 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6909 0, in_code == COMPARE);
6911 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6912 else if ((GET_CODE (XEXP (x, 0)) == XOR
6913 || GET_CODE (XEXP (x, 0)) == IOR)
6914 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6915 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6916 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6918 /* Apply the distributive law, and then try to make extractions. */
6919 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6920 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6922 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6924 new_rtx = make_compound_operation (new_rtx, in_code);
6927 /* If we are have (and (rotate X C) M) and C is larger than the number
6928 of bits in M, this is an extraction. */
6930 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6931 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6932 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6933 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6935 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6936 new_rtx = make_extraction (mode, new_rtx,
6937 (GET_MODE_BITSIZE (mode)
6938 - INTVAL (XEXP (XEXP (x, 0), 1))),
6939 NULL_RTX, i, 1, 0, in_code == COMPARE);
6942 /* On machines without logical shifts, if the operand of the AND is
6943 a logical shift and our mask turns off all the propagated sign
6944 bits, we can replace the logical shift with an arithmetic shift. */
6945 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6946 && !have_insn_for (LSHIFTRT, mode)
6947 && have_insn_for (ASHIFTRT, mode)
6948 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6949 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6950 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6951 && mode_width <= HOST_BITS_PER_WIDE_INT)
6953 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6955 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6956 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6958 gen_rtx_ASHIFTRT (mode,
6959 make_compound_operation
6960 (XEXP (XEXP (x, 0), 0), next_code),
6961 XEXP (XEXP (x, 0), 1)));
6964 /* If the constant is one less than a power of two, this might be
6965 representable by an extraction even if no shift is present.
6966 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6967 we are in a COMPARE. */
6968 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6969 new_rtx = make_extraction (mode,
6970 make_compound_operation (XEXP (x, 0),
6972 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6974 /* If we are in a comparison and this is an AND with a power of two,
6975 convert this into the appropriate bit extract. */
6976 else if (in_code == COMPARE
6977 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6978 new_rtx = make_extraction (mode,
6979 make_compound_operation (XEXP (x, 0),
6981 i, NULL_RTX, 1, 1, 0, 1);
6986 /* If the sign bit is known to be zero, replace this with an
6987 arithmetic shift. */
6988 if (have_insn_for (ASHIFTRT, mode)
6989 && ! have_insn_for (LSHIFTRT, mode)
6990 && mode_width <= HOST_BITS_PER_WIDE_INT
6991 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6993 new_rtx = gen_rtx_ASHIFTRT (mode,
6994 make_compound_operation (XEXP (x, 0),
7000 /* ... fall through ... */
7006 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7007 this is a SIGN_EXTRACT. */
7008 if (GET_CODE (rhs) == CONST_INT
7009 && GET_CODE (lhs) == ASHIFT
7010 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7011 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7012 && INTVAL (rhs) < mode_width)
7014 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7015 new_rtx = make_extraction (mode, new_rtx,
7016 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7017 NULL_RTX, mode_width - INTVAL (rhs),
7018 code == LSHIFTRT, 0, in_code == COMPARE);
7022 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7023 If so, try to merge the shifts into a SIGN_EXTEND. We could
7024 also do this for some cases of SIGN_EXTRACT, but it doesn't
7025 seem worth the effort; the case checked for occurs on Alpha. */
7028 && ! (GET_CODE (lhs) == SUBREG
7029 && (OBJECT_P (SUBREG_REG (lhs))))
7030 && GET_CODE (rhs) == CONST_INT
7031 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7032 && INTVAL (rhs) < mode_width
7033 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7034 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7035 0, NULL_RTX, mode_width - INTVAL (rhs),
7036 code == LSHIFTRT, 0, in_code == COMPARE);
7041 /* Call ourselves recursively on the inner expression. If we are
7042 narrowing the object and it has a different RTL code from
7043 what it originally did, do this SUBREG as a force_to_mode. */
7045 tem = make_compound_operation (SUBREG_REG (x), in_code);
7048 rtx simplified = simplify_subreg (mode, tem, GET_MODE (SUBREG_REG (x)),
7054 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7055 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7056 && subreg_lowpart_p (x))
7058 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7061 /* If we have something other than a SUBREG, we might have
7062 done an expansion, so rerun ourselves. */
7063 if (GET_CODE (newer) != SUBREG)
7064 newer = make_compound_operation (newer, in_code);
7080 x = gen_lowpart (mode, new_rtx);
7081 code = GET_CODE (x);
7084 /* Now recursively process each operand of this operation. */
7085 fmt = GET_RTX_FORMAT (code);
7086 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7089 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7090 SUBST (XEXP (x, i), new_rtx);
7092 else if (fmt[i] == 'E')
7093 for (j = 0; j < XVECLEN (x, i); j++)
7095 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7096 SUBST (XVECEXP (x, i, j), new_rtx);
7099 /* If this is a commutative operation, the changes to the operands
7100 may have made it noncanonical. */
7101 if (COMMUTATIVE_ARITH_P (x)
7102 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7105 SUBST (XEXP (x, 0), XEXP (x, 1));
7106 SUBST (XEXP (x, 1), tem);
7112 /* Given M see if it is a value that would select a field of bits
7113 within an item, but not the entire word. Return -1 if not.
7114 Otherwise, return the starting position of the field, where 0 is the
7117 *PLEN is set to the length of the field. */
7120 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7122 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7123 int pos = exact_log2 (m & -m);
7127 /* Now shift off the low-order zero bits and see if we have a
7128 power of two minus 1. */
7129 len = exact_log2 ((m >> pos) + 1);
7138 /* If X refers to a register that equals REG in value, replace these
7139 references with REG. */
7141 canon_reg_for_combine (rtx x, rtx reg)
7148 enum rtx_code code = GET_CODE (x);
7149 switch (GET_RTX_CLASS (code))
7152 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7153 if (op0 != XEXP (x, 0))
7154 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7159 case RTX_COMM_ARITH:
7160 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7161 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7162 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7163 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7167 case RTX_COMM_COMPARE:
7168 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7169 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7170 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7171 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7172 GET_MODE (op0), op0, op1);
7176 case RTX_BITFIELD_OPS:
7177 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7178 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7179 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7180 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7181 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7182 GET_MODE (op0), op0, op1, op2);
7187 if (rtx_equal_p (get_last_value (reg), x)
7188 || rtx_equal_p (reg, get_last_value (x)))
7197 fmt = GET_RTX_FORMAT (code);
7199 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7202 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7203 if (op != XEXP (x, i))
7213 else if (fmt[i] == 'E')
7216 for (j = 0; j < XVECLEN (x, i); j++)
7218 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7219 if (op != XVECEXP (x, i, j))
7226 XVECEXP (x, i, j) = op;
7237 /* Return X converted to MODE. If the value is already truncated to
7238 MODE we can just return a subreg even though in the general case we
7239 would need an explicit truncation. */
7242 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7244 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7245 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7246 GET_MODE_BITSIZE (GET_MODE (x)))
7247 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7248 return gen_lowpart (mode, x);
7250 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7253 /* See if X can be simplified knowing that we will only refer to it in
7254 MODE and will only refer to those bits that are nonzero in MASK.
7255 If other bits are being computed or if masking operations are done
7256 that select a superset of the bits in MASK, they can sometimes be
7259 Return a possibly simplified expression, but always convert X to
7260 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7262 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7263 are all off in X. This is used when X will be complemented, by either
7264 NOT, NEG, or XOR. */
7267 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7270 enum rtx_code code = GET_CODE (x);
7271 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7272 enum machine_mode op_mode;
7273 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7276 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7277 code below will do the wrong thing since the mode of such an
7278 expression is VOIDmode.
7280 Also do nothing if X is a CLOBBER; this can happen if X was
7281 the return value from a call to gen_lowpart. */
7282 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7285 /* We want to perform the operation is its present mode unless we know
7286 that the operation is valid in MODE, in which case we do the operation
7288 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7289 && have_insn_for (code, mode))
7290 ? mode : GET_MODE (x));
7292 /* It is not valid to do a right-shift in a narrower mode
7293 than the one it came in with. */
7294 if ((code == LSHIFTRT || code == ASHIFTRT)
7295 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7296 op_mode = GET_MODE (x);
7298 /* Truncate MASK to fit OP_MODE. */
7300 mask &= GET_MODE_MASK (op_mode);
7302 /* When we have an arithmetic operation, or a shift whose count we
7303 do not know, we need to assume that all bits up to the highest-order
7304 bit in MASK will be needed. This is how we form such a mask. */
7305 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7306 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7308 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7311 /* Determine what bits of X are guaranteed to be (non)zero. */
7312 nonzero = nonzero_bits (x, mode);
7314 /* If none of the bits in X are needed, return a zero. */
7315 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7318 /* If X is a CONST_INT, return a new one. Do this here since the
7319 test below will fail. */
7320 if (GET_CODE (x) == CONST_INT)
7322 if (SCALAR_INT_MODE_P (mode))
7323 return gen_int_mode (INTVAL (x) & mask, mode);
7326 x = GEN_INT (INTVAL (x) & mask);
7327 return gen_lowpart_common (mode, x);
7331 /* If X is narrower than MODE and we want all the bits in X's mode, just
7332 get X in the proper mode. */
7333 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7334 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7335 return gen_lowpart (mode, x);
7337 /* The arithmetic simplifications here do the wrong thing on vector modes. */
7338 if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x)))
7339 return gen_lowpart (mode, x);
7344 /* If X is a (clobber (const_int)), return it since we know we are
7345 generating something that won't match. */
7352 x = expand_compound_operation (x);
7353 if (GET_CODE (x) != code)
7354 return force_to_mode (x, mode, mask, next_select);
7358 if (subreg_lowpart_p (x)
7359 /* We can ignore the effect of this SUBREG if it narrows the mode or
7360 if the constant masks to zero all the bits the mode doesn't
7362 && ((GET_MODE_SIZE (GET_MODE (x))
7363 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7365 & GET_MODE_MASK (GET_MODE (x))
7366 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7367 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7371 /* If this is an AND with a constant, convert it into an AND
7372 whose constant is the AND of that constant with MASK. If it
7373 remains an AND of MASK, delete it since it is redundant. */
7375 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7377 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7378 mask & INTVAL (XEXP (x, 1)));
7380 /* If X is still an AND, see if it is an AND with a mask that
7381 is just some low-order bits. If so, and it is MASK, we don't
7384 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7385 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7389 /* If it remains an AND, try making another AND with the bits
7390 in the mode mask that aren't in MASK turned on. If the
7391 constant in the AND is wide enough, this might make a
7392 cheaper constant. */
7394 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7395 && GET_MODE_MASK (GET_MODE (x)) != mask
7396 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7398 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7399 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7400 int width = GET_MODE_BITSIZE (GET_MODE (x));
7403 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7404 number, sign extend it. */
7405 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7406 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7407 cval |= (HOST_WIDE_INT) -1 << width;
7409 y = simplify_gen_binary (AND, GET_MODE (x),
7410 XEXP (x, 0), GEN_INT (cval));
7411 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7412 < rtx_cost (x, SET, optimize_this_for_speed_p))
7422 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7423 low-order bits (as in an alignment operation) and FOO is already
7424 aligned to that boundary, mask C1 to that boundary as well.
7425 This may eliminate that PLUS and, later, the AND. */
7428 unsigned int width = GET_MODE_BITSIZE (mode);
7429 unsigned HOST_WIDE_INT smask = mask;
7431 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7432 number, sign extend it. */
7434 if (width < HOST_BITS_PER_WIDE_INT
7435 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7436 smask |= (HOST_WIDE_INT) -1 << width;
7438 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7439 && exact_log2 (- smask) >= 0
7440 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7441 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7442 return force_to_mode (plus_constant (XEXP (x, 0),
7443 (INTVAL (XEXP (x, 1)) & smask)),
7444 mode, smask, next_select);
7447 /* ... fall through ... */
7450 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7451 most significant bit in MASK since carries from those bits will
7452 affect the bits we are interested in. */
7457 /* If X is (minus C Y) where C's least set bit is larger than any bit
7458 in the mask, then we may replace with (neg Y). */
7459 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7460 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7461 & -INTVAL (XEXP (x, 0))))
7464 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7466 return force_to_mode (x, mode, mask, next_select);
7469 /* Similarly, if C contains every bit in the fuller_mask, then we may
7470 replace with (not Y). */
7471 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7472 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7473 == INTVAL (XEXP (x, 0))))
7475 x = simplify_gen_unary (NOT, GET_MODE (x),
7476 XEXP (x, 1), GET_MODE (x));
7477 return force_to_mode (x, mode, mask, next_select);
7485 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7486 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7487 operation which may be a bitfield extraction. Ensure that the
7488 constant we form is not wider than the mode of X. */
7490 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7491 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7492 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7493 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7494 && GET_CODE (XEXP (x, 1)) == CONST_INT
7495 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7496 + floor_log2 (INTVAL (XEXP (x, 1))))
7497 < GET_MODE_BITSIZE (GET_MODE (x)))
7498 && (INTVAL (XEXP (x, 1))
7499 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7501 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7502 << INTVAL (XEXP (XEXP (x, 0), 1)));
7503 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7504 XEXP (XEXP (x, 0), 0), temp);
7505 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7506 XEXP (XEXP (x, 0), 1));
7507 return force_to_mode (x, mode, mask, next_select);
7511 /* For most binary operations, just propagate into the operation and
7512 change the mode if we have an operation of that mode. */
7514 op0 = gen_lowpart_or_truncate (op_mode,
7515 force_to_mode (XEXP (x, 0), mode, mask,
7517 op1 = gen_lowpart_or_truncate (op_mode,
7518 force_to_mode (XEXP (x, 1), mode, mask,
7521 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7522 x = simplify_gen_binary (code, op_mode, op0, op1);
7526 /* For left shifts, do the same, but just for the first operand.
7527 However, we cannot do anything with shifts where we cannot
7528 guarantee that the counts are smaller than the size of the mode
7529 because such a count will have a different meaning in a
7532 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7533 && INTVAL (XEXP (x, 1)) >= 0
7534 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7535 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7536 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7537 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7540 /* If the shift count is a constant and we can do arithmetic in
7541 the mode of the shift, refine which bits we need. Otherwise, use the
7542 conservative form of the mask. */
7543 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7544 && INTVAL (XEXP (x, 1)) >= 0
7545 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7546 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7547 mask >>= INTVAL (XEXP (x, 1));
7551 op0 = gen_lowpart_or_truncate (op_mode,
7552 force_to_mode (XEXP (x, 0), op_mode,
7553 mask, next_select));
7555 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7556 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7560 /* Here we can only do something if the shift count is a constant,
7561 this shift constant is valid for the host, and we can do arithmetic
7564 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7565 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7566 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7568 rtx inner = XEXP (x, 0);
7569 unsigned HOST_WIDE_INT inner_mask;
7571 /* Select the mask of the bits we need for the shift operand. */
7572 inner_mask = mask << INTVAL (XEXP (x, 1));
7574 /* We can only change the mode of the shift if we can do arithmetic
7575 in the mode of the shift and INNER_MASK is no wider than the
7576 width of X's mode. */
7577 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7578 op_mode = GET_MODE (x);
7580 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7582 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7583 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7586 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7587 shift and AND produces only copies of the sign bit (C2 is one less
7588 than a power of two), we can do this with just a shift. */
7590 if (GET_CODE (x) == LSHIFTRT
7591 && GET_CODE (XEXP (x, 1)) == CONST_INT
7592 /* The shift puts one of the sign bit copies in the least significant
7594 && ((INTVAL (XEXP (x, 1))
7595 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7596 >= GET_MODE_BITSIZE (GET_MODE (x)))
7597 && exact_log2 (mask + 1) >= 0
7598 /* Number of bits left after the shift must be more than the mask
7600 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7601 <= GET_MODE_BITSIZE (GET_MODE (x)))
7602 /* Must be more sign bit copies than the mask needs. */
7603 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7604 >= exact_log2 (mask + 1)))
7605 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7606 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7607 - exact_log2 (mask + 1)));
7612 /* If we are just looking for the sign bit, we don't need this shift at
7613 all, even if it has a variable count. */
7614 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7615 && (mask == ((unsigned HOST_WIDE_INT) 1
7616 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7617 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7619 /* If this is a shift by a constant, get a mask that contains those bits
7620 that are not copies of the sign bit. We then have two cases: If
7621 MASK only includes those bits, this can be a logical shift, which may
7622 allow simplifications. If MASK is a single-bit field not within
7623 those bits, we are requesting a copy of the sign bit and hence can
7624 shift the sign bit to the appropriate location. */
7626 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7627 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7631 /* If the considered data is wider than HOST_WIDE_INT, we can't
7632 represent a mask for all its bits in a single scalar.
7633 But we only care about the lower bits, so calculate these. */
7635 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7637 nonzero = ~(HOST_WIDE_INT) 0;
7639 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7640 is the number of bits a full-width mask would have set.
7641 We need only shift if these are fewer than nonzero can
7642 hold. If not, we must keep all bits set in nonzero. */
7644 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7645 < HOST_BITS_PER_WIDE_INT)
7646 nonzero >>= INTVAL (XEXP (x, 1))
7647 + HOST_BITS_PER_WIDE_INT
7648 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7652 nonzero = GET_MODE_MASK (GET_MODE (x));
7653 nonzero >>= INTVAL (XEXP (x, 1));
7656 if ((mask & ~nonzero) == 0)
7658 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7659 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7660 if (GET_CODE (x) != ASHIFTRT)
7661 return force_to_mode (x, mode, mask, next_select);
7664 else if ((i = exact_log2 (mask)) >= 0)
7666 x = simplify_shift_const
7667 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7668 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7670 if (GET_CODE (x) != ASHIFTRT)
7671 return force_to_mode (x, mode, mask, next_select);
7675 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7676 even if the shift count isn't a constant. */
7678 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7679 XEXP (x, 0), XEXP (x, 1));
7683 /* If this is a zero- or sign-extension operation that just affects bits
7684 we don't care about, remove it. Be sure the call above returned
7685 something that is still a shift. */
7687 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7688 && GET_CODE (XEXP (x, 1)) == CONST_INT
7689 && INTVAL (XEXP (x, 1)) >= 0
7690 && (INTVAL (XEXP (x, 1))
7691 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7692 && GET_CODE (XEXP (x, 0)) == ASHIFT
7693 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7694 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7701 /* If the shift count is constant and we can do computations
7702 in the mode of X, compute where the bits we care about are.
7703 Otherwise, we can't do anything. Don't change the mode of
7704 the shift or propagate MODE into the shift, though. */
7705 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7706 && INTVAL (XEXP (x, 1)) >= 0)
7708 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7709 GET_MODE (x), GEN_INT (mask),
7711 if (temp && GET_CODE (temp) == CONST_INT)
7713 force_to_mode (XEXP (x, 0), GET_MODE (x),
7714 INTVAL (temp), next_select));
7719 /* If we just want the low-order bit, the NEG isn't needed since it
7720 won't change the low-order bit. */
7722 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7724 /* We need any bits less significant than the most significant bit in
7725 MASK since carries from those bits will affect the bits we are
7731 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7732 same as the XOR case above. Ensure that the constant we form is not
7733 wider than the mode of X. */
7735 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7736 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7737 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7738 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7739 < GET_MODE_BITSIZE (GET_MODE (x)))
7740 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7742 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7744 temp = simplify_gen_binary (XOR, GET_MODE (x),
7745 XEXP (XEXP (x, 0), 0), temp);
7746 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7747 temp, XEXP (XEXP (x, 0), 1));
7749 return force_to_mode (x, mode, mask, next_select);
7752 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7753 use the full mask inside the NOT. */
7757 op0 = gen_lowpart_or_truncate (op_mode,
7758 force_to_mode (XEXP (x, 0), mode, mask,
7760 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7761 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7765 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7766 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7767 which is equal to STORE_FLAG_VALUE. */
7768 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7769 && GET_MODE (XEXP (x, 0)) == mode
7770 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7771 && (nonzero_bits (XEXP (x, 0), mode)
7772 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7773 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7778 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7779 written in a narrower mode. We play it safe and do not do so. */
7782 gen_lowpart_or_truncate (GET_MODE (x),
7783 force_to_mode (XEXP (x, 1), mode,
7784 mask, next_select)));
7786 gen_lowpart_or_truncate (GET_MODE (x),
7787 force_to_mode (XEXP (x, 2), mode,
7788 mask, next_select)));
7795 /* Ensure we return a value of the proper mode. */
7796 return gen_lowpart_or_truncate (mode, x);
7799 /* Return nonzero if X is an expression that has one of two values depending on
7800 whether some other value is zero or nonzero. In that case, we return the
7801 value that is being tested, *PTRUE is set to the value if the rtx being
7802 returned has a nonzero value, and *PFALSE is set to the other alternative.
7804 If we return zero, we set *PTRUE and *PFALSE to X. */
7807 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7809 enum machine_mode mode = GET_MODE (x);
7810 enum rtx_code code = GET_CODE (x);
7811 rtx cond0, cond1, true0, true1, false0, false1;
7812 unsigned HOST_WIDE_INT nz;
7814 /* If we are comparing a value against zero, we are done. */
7815 if ((code == NE || code == EQ)
7816 && XEXP (x, 1) == const0_rtx)
7818 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7819 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7823 /* If this is a unary operation whose operand has one of two values, apply
7824 our opcode to compute those values. */
7825 else if (UNARY_P (x)
7826 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7828 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7829 *pfalse = simplify_gen_unary (code, mode, false0,
7830 GET_MODE (XEXP (x, 0)));
7834 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7835 make can't possibly match and would suppress other optimizations. */
7836 else if (code == COMPARE)
7839 /* If this is a binary operation, see if either side has only one of two
7840 values. If either one does or if both do and they are conditional on
7841 the same value, compute the new true and false values. */
7842 else if (BINARY_P (x))
7844 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7845 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7847 if ((cond0 != 0 || cond1 != 0)
7848 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7850 /* If if_then_else_cond returned zero, then true/false are the
7851 same rtl. We must copy one of them to prevent invalid rtl
7854 true0 = copy_rtx (true0);
7855 else if (cond1 == 0)
7856 true1 = copy_rtx (true1);
7858 if (COMPARISON_P (x))
7860 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7862 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7867 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7868 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7871 return cond0 ? cond0 : cond1;
7874 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7875 operands is zero when the other is nonzero, and vice-versa,
7876 and STORE_FLAG_VALUE is 1 or -1. */
7878 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7879 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7881 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7883 rtx op0 = XEXP (XEXP (x, 0), 1);
7884 rtx op1 = XEXP (XEXP (x, 1), 1);
7886 cond0 = XEXP (XEXP (x, 0), 0);
7887 cond1 = XEXP (XEXP (x, 1), 0);
7889 if (COMPARISON_P (cond0)
7890 && COMPARISON_P (cond1)
7891 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7892 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7893 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7894 || ((swap_condition (GET_CODE (cond0))
7895 == reversed_comparison_code (cond1, NULL))
7896 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7897 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7898 && ! side_effects_p (x))
7900 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7901 *pfalse = simplify_gen_binary (MULT, mode,
7903 ? simplify_gen_unary (NEG, mode,
7911 /* Similarly for MULT, AND and UMIN, except that for these the result
7913 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7914 && (code == MULT || code == AND || code == UMIN)
7915 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7917 cond0 = XEXP (XEXP (x, 0), 0);
7918 cond1 = XEXP (XEXP (x, 1), 0);
7920 if (COMPARISON_P (cond0)
7921 && COMPARISON_P (cond1)
7922 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7923 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7924 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7925 || ((swap_condition (GET_CODE (cond0))
7926 == reversed_comparison_code (cond1, NULL))
7927 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7928 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7929 && ! side_effects_p (x))
7931 *ptrue = *pfalse = const0_rtx;
7937 else if (code == IF_THEN_ELSE)
7939 /* If we have IF_THEN_ELSE already, extract the condition and
7940 canonicalize it if it is NE or EQ. */
7941 cond0 = XEXP (x, 0);
7942 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7943 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7944 return XEXP (cond0, 0);
7945 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7947 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7948 return XEXP (cond0, 0);
7954 /* If X is a SUBREG, we can narrow both the true and false values
7955 if the inner expression, if there is a condition. */
7956 else if (code == SUBREG
7957 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7960 true0 = simplify_gen_subreg (mode, true0,
7961 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7962 false0 = simplify_gen_subreg (mode, false0,
7963 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7964 if (true0 && false0)
7972 /* If X is a constant, this isn't special and will cause confusions
7973 if we treat it as such. Likewise if it is equivalent to a constant. */
7974 else if (CONSTANT_P (x)
7975 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7978 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7979 will be least confusing to the rest of the compiler. */
7980 else if (mode == BImode)
7982 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7986 /* If X is known to be either 0 or -1, those are the true and
7987 false values when testing X. */
7988 else if (x == constm1_rtx || x == const0_rtx
7989 || (mode != VOIDmode
7990 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7992 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7996 /* Likewise for 0 or a single bit. */
7997 else if (SCALAR_INT_MODE_P (mode)
7998 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7999 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8001 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8005 /* Otherwise fail; show no condition with true and false values the same. */
8006 *ptrue = *pfalse = x;
8010 /* Return the value of expression X given the fact that condition COND
8011 is known to be true when applied to REG as its first operand and VAL
8012 as its second. X is known to not be shared and so can be modified in
8015 We only handle the simplest cases, and specifically those cases that
8016 arise with IF_THEN_ELSE expressions. */
8019 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8021 enum rtx_code code = GET_CODE (x);
8026 if (side_effects_p (x))
8029 /* If either operand of the condition is a floating point value,
8030 then we have to avoid collapsing an EQ comparison. */
8032 && rtx_equal_p (x, reg)
8033 && ! FLOAT_MODE_P (GET_MODE (x))
8034 && ! FLOAT_MODE_P (GET_MODE (val)))
8037 if (cond == UNEQ && rtx_equal_p (x, reg))
8040 /* If X is (abs REG) and we know something about REG's relationship
8041 with zero, we may be able to simplify this. */
8043 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8046 case GE: case GT: case EQ:
8049 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8051 GET_MODE (XEXP (x, 0)));
8056 /* The only other cases we handle are MIN, MAX, and comparisons if the
8057 operands are the same as REG and VAL. */
8059 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8061 if (rtx_equal_p (XEXP (x, 0), val))
8062 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8064 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8066 if (COMPARISON_P (x))
8068 if (comparison_dominates_p (cond, code))
8069 return const_true_rtx;
8071 code = reversed_comparison_code (x, NULL);
8073 && comparison_dominates_p (cond, code))
8078 else if (code == SMAX || code == SMIN
8079 || code == UMIN || code == UMAX)
8081 int unsignedp = (code == UMIN || code == UMAX);
8083 /* Do not reverse the condition when it is NE or EQ.
8084 This is because we cannot conclude anything about
8085 the value of 'SMAX (x, y)' when x is not equal to y,
8086 but we can when x equals y. */
8087 if ((code == SMAX || code == UMAX)
8088 && ! (cond == EQ || cond == NE))
8089 cond = reverse_condition (cond);
8094 return unsignedp ? x : XEXP (x, 1);
8096 return unsignedp ? x : XEXP (x, 0);
8098 return unsignedp ? XEXP (x, 1) : x;
8100 return unsignedp ? XEXP (x, 0) : x;
8107 else if (code == SUBREG)
8109 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8110 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8112 if (SUBREG_REG (x) != r)
8114 /* We must simplify subreg here, before we lose track of the
8115 original inner_mode. */
8116 new_rtx = simplify_subreg (GET_MODE (x), r,
8117 inner_mode, SUBREG_BYTE (x));
8121 SUBST (SUBREG_REG (x), r);
8126 /* We don't have to handle SIGN_EXTEND here, because even in the
8127 case of replacing something with a modeless CONST_INT, a
8128 CONST_INT is already (supposed to be) a valid sign extension for
8129 its narrower mode, which implies it's already properly
8130 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8131 story is different. */
8132 else if (code == ZERO_EXTEND)
8134 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8135 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8137 if (XEXP (x, 0) != r)
8139 /* We must simplify the zero_extend here, before we lose
8140 track of the original inner_mode. */
8141 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8146 SUBST (XEXP (x, 0), r);
8152 fmt = GET_RTX_FORMAT (code);
8153 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8156 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8157 else if (fmt[i] == 'E')
8158 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8159 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8166 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8167 assignment as a field assignment. */
8170 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8172 if (x == y || rtx_equal_p (x, y))
8175 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8178 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8179 Note that all SUBREGs of MEM are paradoxical; otherwise they
8180 would have been rewritten. */
8181 if (MEM_P (x) && GET_CODE (y) == SUBREG
8182 && MEM_P (SUBREG_REG (y))
8183 && rtx_equal_p (SUBREG_REG (y),
8184 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8187 if (MEM_P (y) && GET_CODE (x) == SUBREG
8188 && MEM_P (SUBREG_REG (x))
8189 && rtx_equal_p (SUBREG_REG (x),
8190 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8193 /* We used to see if get_last_value of X and Y were the same but that's
8194 not correct. In one direction, we'll cause the assignment to have
8195 the wrong destination and in the case, we'll import a register into this
8196 insn that might have already have been dead. So fail if none of the
8197 above cases are true. */
8201 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8202 Return that assignment if so.
8204 We only handle the most common cases. */
8207 make_field_assignment (rtx x)
8209 rtx dest = SET_DEST (x);
8210 rtx src = SET_SRC (x);
8215 unsigned HOST_WIDE_INT len;
8217 enum machine_mode mode;
8219 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8220 a clear of a one-bit field. We will have changed it to
8221 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8224 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8225 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8226 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8227 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8229 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8232 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8236 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8237 && subreg_lowpart_p (XEXP (src, 0))
8238 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8239 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8240 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8241 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8242 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8243 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8245 assign = make_extraction (VOIDmode, dest, 0,
8246 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8249 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8253 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8255 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8256 && XEXP (XEXP (src, 0), 0) == const1_rtx
8257 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8259 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8262 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8266 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8267 SRC is an AND with all bits of that field set, then we can discard
8269 if (GET_CODE (dest) == ZERO_EXTRACT
8270 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8271 && GET_CODE (src) == AND
8272 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8274 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8275 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8276 unsigned HOST_WIDE_INT ze_mask;
8278 if (width >= HOST_BITS_PER_WIDE_INT)
8281 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8283 /* Complete overlap. We can remove the source AND. */
8284 if ((and_mask & ze_mask) == ze_mask)
8285 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8287 /* Partial overlap. We can reduce the source AND. */
8288 if ((and_mask & ze_mask) != and_mask)
8290 mode = GET_MODE (src);
8291 src = gen_rtx_AND (mode, XEXP (src, 0),
8292 gen_int_mode (and_mask & ze_mask, mode));
8293 return gen_rtx_SET (VOIDmode, dest, src);
8297 /* The other case we handle is assignments into a constant-position
8298 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8299 a mask that has all one bits except for a group of zero bits and
8300 OTHER is known to have zeros where C1 has ones, this is such an
8301 assignment. Compute the position and length from C1. Shift OTHER
8302 to the appropriate position, force it to the required mode, and
8303 make the extraction. Check for the AND in both operands. */
8305 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8308 rhs = expand_compound_operation (XEXP (src, 0));
8309 lhs = expand_compound_operation (XEXP (src, 1));
8311 if (GET_CODE (rhs) == AND
8312 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8313 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8314 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8315 else if (GET_CODE (lhs) == AND
8316 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8317 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8318 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8322 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8323 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8324 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8325 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8328 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8332 /* The mode to use for the source is the mode of the assignment, or of
8333 what is inside a possible STRICT_LOW_PART. */
8334 mode = (GET_CODE (assign) == STRICT_LOW_PART
8335 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8337 /* Shift OTHER right POS places and make it the source, restricting it
8338 to the proper length and mode. */
8340 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8344 src = force_to_mode (src, mode,
8345 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8346 ? ~(unsigned HOST_WIDE_INT) 0
8347 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8350 /* If SRC is masked by an AND that does not make a difference in
8351 the value being stored, strip it. */
8352 if (GET_CODE (assign) == ZERO_EXTRACT
8353 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8354 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8355 && GET_CODE (src) == AND
8356 && GET_CODE (XEXP (src, 1)) == CONST_INT
8357 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8358 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8359 src = XEXP (src, 0);
8361 return gen_rtx_SET (VOIDmode, assign, src);
8364 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8368 apply_distributive_law (rtx x)
8370 enum rtx_code code = GET_CODE (x);
8371 enum rtx_code inner_code;
8372 rtx lhs, rhs, other;
8375 /* Distributivity is not true for floating point as it can change the
8376 value. So we don't do it unless -funsafe-math-optimizations. */
8377 if (FLOAT_MODE_P (GET_MODE (x))
8378 && ! flag_unsafe_math_optimizations)
8381 /* The outer operation can only be one of the following: */
8382 if (code != IOR && code != AND && code != XOR
8383 && code != PLUS && code != MINUS)
8389 /* If either operand is a primitive we can't do anything, so get out
8391 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8394 lhs = expand_compound_operation (lhs);
8395 rhs = expand_compound_operation (rhs);
8396 inner_code = GET_CODE (lhs);
8397 if (inner_code != GET_CODE (rhs))
8400 /* See if the inner and outer operations distribute. */
8407 /* These all distribute except over PLUS. */
8408 if (code == PLUS || code == MINUS)
8413 if (code != PLUS && code != MINUS)
8418 /* This is also a multiply, so it distributes over everything. */
8422 /* Non-paradoxical SUBREGs distributes over all operations,
8423 provided the inner modes and byte offsets are the same, this
8424 is an extraction of a low-order part, we don't convert an fp
8425 operation to int or vice versa, this is not a vector mode,
8426 and we would not be converting a single-word operation into a
8427 multi-word operation. The latter test is not required, but
8428 it prevents generating unneeded multi-word operations. Some
8429 of the previous tests are redundant given the latter test,
8430 but are retained because they are required for correctness.
8432 We produce the result slightly differently in this case. */
8434 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8435 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8436 || ! subreg_lowpart_p (lhs)
8437 || (GET_MODE_CLASS (GET_MODE (lhs))
8438 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8439 || (GET_MODE_SIZE (GET_MODE (lhs))
8440 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8441 || VECTOR_MODE_P (GET_MODE (lhs))
8442 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8443 /* Result might need to be truncated. Don't change mode if
8444 explicit truncation is needed. */
8445 || !TRULY_NOOP_TRUNCATION
8446 (GET_MODE_BITSIZE (GET_MODE (x)),
8447 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8450 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8451 SUBREG_REG (lhs), SUBREG_REG (rhs));
8452 return gen_lowpart (GET_MODE (x), tem);
8458 /* Set LHS and RHS to the inner operands (A and B in the example
8459 above) and set OTHER to the common operand (C in the example).
8460 There is only one way to do this unless the inner operation is
8462 if (COMMUTATIVE_ARITH_P (lhs)
8463 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8464 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8465 else if (COMMUTATIVE_ARITH_P (lhs)
8466 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8467 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8468 else if (COMMUTATIVE_ARITH_P (lhs)
8469 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8470 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8471 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8472 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8476 /* Form the new inner operation, seeing if it simplifies first. */
8477 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8479 /* There is one exception to the general way of distributing:
8480 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8481 if (code == XOR && inner_code == IOR)
8484 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8487 /* We may be able to continuing distributing the result, so call
8488 ourselves recursively on the inner operation before forming the
8489 outer operation, which we return. */
8490 return simplify_gen_binary (inner_code, GET_MODE (x),
8491 apply_distributive_law (tem), other);
8494 /* See if X is of the form (* (+ A B) C), and if so convert to
8495 (+ (* A C) (* B C)) and try to simplify.
8497 Most of the time, this results in no change. However, if some of
8498 the operands are the same or inverses of each other, simplifications
8501 For example, (and (ior A B) (not B)) can occur as the result of
8502 expanding a bit field assignment. When we apply the distributive
8503 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8504 which then simplifies to (and (A (not B))).
8506 Note that no checks happen on the validity of applying the inverse
8507 distributive law. This is pointless since we can do it in the
8508 few places where this routine is called.
8510 N is the index of the term that is decomposed (the arithmetic operation,
8511 i.e. (+ A B) in the first example above). !N is the index of the term that
8512 is distributed, i.e. of C in the first example above. */
8514 distribute_and_simplify_rtx (rtx x, int n)
8516 enum machine_mode mode;
8517 enum rtx_code outer_code, inner_code;
8518 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8520 /* Distributivity is not true for floating point as it can change the
8521 value. So we don't do it unless -funsafe-math-optimizations. */
8522 if (FLOAT_MODE_P (GET_MODE (x))
8523 && ! flag_unsafe_math_optimizations)
8526 decomposed = XEXP (x, n);
8527 if (!ARITHMETIC_P (decomposed))
8530 mode = GET_MODE (x);
8531 outer_code = GET_CODE (x);
8532 distributed = XEXP (x, !n);
8534 inner_code = GET_CODE (decomposed);
8535 inner_op0 = XEXP (decomposed, 0);
8536 inner_op1 = XEXP (decomposed, 1);
8538 /* Special case (and (xor B C) (not A)), which is equivalent to
8539 (xor (ior A B) (ior A C)) */
8540 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8542 distributed = XEXP (distributed, 0);
8548 /* Distribute the second term. */
8549 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8550 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8554 /* Distribute the first term. */
8555 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8556 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8559 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8561 if (GET_CODE (tmp) != outer_code
8562 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8563 < rtx_cost (x, SET, optimize_this_for_speed_p))
8569 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8570 in MODE. Return an equivalent form, if different from (and VAROP
8571 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8574 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8575 unsigned HOST_WIDE_INT constop)
8577 unsigned HOST_WIDE_INT nonzero;
8578 unsigned HOST_WIDE_INT orig_constop;
8583 orig_constop = constop;
8584 if (GET_CODE (varop) == CLOBBER)
8587 /* Simplify VAROP knowing that we will be only looking at some of the
8590 Note by passing in CONSTOP, we guarantee that the bits not set in
8591 CONSTOP are not significant and will never be examined. We must
8592 ensure that is the case by explicitly masking out those bits
8593 before returning. */
8594 varop = force_to_mode (varop, mode, constop, 0);
8596 /* If VAROP is a CLOBBER, we will fail so return it. */
8597 if (GET_CODE (varop) == CLOBBER)
8600 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8601 to VAROP and return the new constant. */
8602 if (GET_CODE (varop) == CONST_INT)
8603 return gen_int_mode (INTVAL (varop) & constop, mode);
8605 /* See what bits may be nonzero in VAROP. Unlike the general case of
8606 a call to nonzero_bits, here we don't care about bits outside
8609 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8611 /* Turn off all bits in the constant that are known to already be zero.
8612 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8613 which is tested below. */
8617 /* If we don't have any bits left, return zero. */
8621 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8622 a power of two, we can replace this with an ASHIFT. */
8623 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8624 && (i = exact_log2 (constop)) >= 0)
8625 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8627 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8628 or XOR, then try to apply the distributive law. This may eliminate
8629 operations if either branch can be simplified because of the AND.
8630 It may also make some cases more complex, but those cases probably
8631 won't match a pattern either with or without this. */
8633 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8637 apply_distributive_law
8638 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8639 simplify_and_const_int (NULL_RTX,
8643 simplify_and_const_int (NULL_RTX,
8648 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8649 the AND and see if one of the operands simplifies to zero. If so, we
8650 may eliminate it. */
8652 if (GET_CODE (varop) == PLUS
8653 && exact_log2 (constop + 1) >= 0)
8657 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8658 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8659 if (o0 == const0_rtx)
8661 if (o1 == const0_rtx)
8665 /* Make a SUBREG if necessary. If we can't make it, fail. */
8666 varop = gen_lowpart (mode, varop);
8667 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8670 /* If we are only masking insignificant bits, return VAROP. */
8671 if (constop == nonzero)
8674 if (varop == orig_varop && constop == orig_constop)
8677 /* Otherwise, return an AND. */
8678 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8682 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8685 Return an equivalent form, if different from X. Otherwise, return X. If
8686 X is zero, we are to always construct the equivalent form. */
8689 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8690 unsigned HOST_WIDE_INT constop)
8692 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8697 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8698 gen_int_mode (constop, mode));
8699 if (GET_MODE (x) != mode)
8700 x = gen_lowpart (mode, x);
8704 /* Given a REG, X, compute which bits in X can be nonzero.
8705 We don't care about bits outside of those defined in MODE.
8707 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8708 a shift, AND, or zero_extract, we can do better. */
8711 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8712 const_rtx known_x ATTRIBUTE_UNUSED,
8713 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8714 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8715 unsigned HOST_WIDE_INT *nonzero)
8720 /* If X is a register whose nonzero bits value is current, use it.
8721 Otherwise, if X is a register whose value we can find, use that
8722 value. Otherwise, use the previously-computed global nonzero bits
8723 for this register. */
8725 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8726 if (rsp->last_set_value != 0
8727 && (rsp->last_set_mode == mode
8728 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8729 && GET_MODE_CLASS (mode) == MODE_INT))
8730 && ((rsp->last_set_label >= label_tick_ebb_start
8731 && rsp->last_set_label < label_tick)
8732 || (rsp->last_set_label == label_tick
8733 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8734 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8735 && REG_N_SETS (REGNO (x)) == 1
8737 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8739 *nonzero &= rsp->last_set_nonzero_bits;
8743 tem = get_last_value (x);
8747 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8748 /* If X is narrower than MODE and TEM is a non-negative
8749 constant that would appear negative in the mode of X,
8750 sign-extend it for use in reg_nonzero_bits because some
8751 machines (maybe most) will actually do the sign-extension
8752 and this is the conservative approach.
8754 ??? For 2.5, try to tighten up the MD files in this regard
8755 instead of this kludge. */
8757 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8758 && GET_CODE (tem) == CONST_INT
8760 && 0 != (INTVAL (tem)
8761 & ((HOST_WIDE_INT) 1
8762 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8763 tem = GEN_INT (INTVAL (tem)
8764 | ((HOST_WIDE_INT) (-1)
8765 << GET_MODE_BITSIZE (GET_MODE (x))));
8769 else if (nonzero_sign_valid && rsp->nonzero_bits)
8771 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8773 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8774 /* We don't know anything about the upper bits. */
8775 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8782 /* Return the number of bits at the high-order end of X that are known to
8783 be equal to the sign bit. X will be used in mode MODE; if MODE is
8784 VOIDmode, X will be used in its own mode. The returned value will always
8785 be between 1 and the number of bits in MODE. */
8788 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8789 const_rtx known_x ATTRIBUTE_UNUSED,
8790 enum machine_mode known_mode
8792 unsigned int known_ret ATTRIBUTE_UNUSED,
8793 unsigned int *result)
8798 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8799 if (rsp->last_set_value != 0
8800 && rsp->last_set_mode == mode
8801 && ((rsp->last_set_label >= label_tick_ebb_start
8802 && rsp->last_set_label < label_tick)
8803 || (rsp->last_set_label == label_tick
8804 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8805 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8806 && REG_N_SETS (REGNO (x)) == 1
8808 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8810 *result = rsp->last_set_sign_bit_copies;
8814 tem = get_last_value (x);
8818 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8819 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8820 *result = rsp->sign_bit_copies;
8825 /* Return the number of "extended" bits there are in X, when interpreted
8826 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8827 unsigned quantities, this is the number of high-order zero bits.
8828 For signed quantities, this is the number of copies of the sign bit
8829 minus 1. In both case, this function returns the number of "spare"
8830 bits. For example, if two quantities for which this function returns
8831 at least 1 are added, the addition is known not to overflow.
8833 This function will always return 0 unless called during combine, which
8834 implies that it must be called from a define_split. */
8837 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8839 if (nonzero_sign_valid == 0)
8843 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8844 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8845 - floor_log2 (nonzero_bits (x, mode)))
8847 : num_sign_bit_copies (x, mode) - 1);
8850 /* This function is called from `simplify_shift_const' to merge two
8851 outer operations. Specifically, we have already found that we need
8852 to perform operation *POP0 with constant *PCONST0 at the outermost
8853 position. We would now like to also perform OP1 with constant CONST1
8854 (with *POP0 being done last).
8856 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8857 the resulting operation. *PCOMP_P is set to 1 if we would need to
8858 complement the innermost operand, otherwise it is unchanged.
8860 MODE is the mode in which the operation will be done. No bits outside
8861 the width of this mode matter. It is assumed that the width of this mode
8862 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8864 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8865 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8866 result is simply *PCONST0.
8868 If the resulting operation cannot be expressed as one operation, we
8869 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8872 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8874 enum rtx_code op0 = *pop0;
8875 HOST_WIDE_INT const0 = *pconst0;
8877 const0 &= GET_MODE_MASK (mode);
8878 const1 &= GET_MODE_MASK (mode);
8880 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8884 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8887 if (op1 == UNKNOWN || op0 == SET)
8890 else if (op0 == UNKNOWN)
8891 op0 = op1, const0 = const1;
8893 else if (op0 == op1)
8917 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8918 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8921 /* If the two constants aren't the same, we can't do anything. The
8922 remaining six cases can all be done. */
8923 else if (const0 != const1)
8931 /* (a & b) | b == b */
8933 else /* op1 == XOR */
8934 /* (a ^ b) | b == a | b */
8940 /* (a & b) ^ b == (~a) & b */
8941 op0 = AND, *pcomp_p = 1;
8942 else /* op1 == IOR */
8943 /* (a | b) ^ b == a & ~b */
8944 op0 = AND, const0 = ~const0;
8949 /* (a | b) & b == b */
8951 else /* op1 == XOR */
8952 /* (a ^ b) & b) == (~a) & b */
8959 /* Check for NO-OP cases. */
8960 const0 &= GET_MODE_MASK (mode);
8962 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8964 else if (const0 == 0 && op0 == AND)
8966 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8972 /* ??? Slightly redundant with the above mask, but not entirely.
8973 Moving this above means we'd have to sign-extend the mode mask
8974 for the final test. */
8975 if (op0 != UNKNOWN && op0 != NEG)
8976 *pconst0 = trunc_int_for_mode (const0, mode);
8981 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8982 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8983 simplify it. Otherwise, return a simplified value.
8985 The shift is normally computed in the widest mode we find in VAROP, as
8986 long as it isn't a different number of words than RESULT_MODE. Exceptions
8987 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8990 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8991 rtx varop, int orig_count)
8993 enum rtx_code orig_code = code;
8994 rtx orig_varop = varop;
8996 enum machine_mode mode = result_mode;
8997 enum machine_mode shift_mode, tmode;
8998 unsigned int mode_words
8999 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9000 /* We form (outer_op (code varop count) (outer_const)). */
9001 enum rtx_code outer_op = UNKNOWN;
9002 HOST_WIDE_INT outer_const = 0;
9003 int complement_p = 0;
9006 /* Make sure and truncate the "natural" shift on the way in. We don't
9007 want to do this inside the loop as it makes it more difficult to
9009 if (SHIFT_COUNT_TRUNCATED)
9010 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9012 /* If we were given an invalid count, don't do anything except exactly
9013 what was requested. */
9015 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9020 /* Unless one of the branches of the `if' in this loop does a `continue',
9021 we will `break' the loop after the `if'. */
9025 /* If we have an operand of (clobber (const_int 0)), fail. */
9026 if (GET_CODE (varop) == CLOBBER)
9029 /* Convert ROTATERT to ROTATE. */
9030 if (code == ROTATERT)
9032 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9034 if (VECTOR_MODE_P (result_mode))
9035 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9037 count = bitsize - count;
9040 /* We need to determine what mode we will do the shift in. If the
9041 shift is a right shift or a ROTATE, we must always do it in the mode
9042 it was originally done in. Otherwise, we can do it in MODE, the
9043 widest mode encountered. */
9045 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9046 ? result_mode : mode);
9048 /* Handle cases where the count is greater than the size of the mode
9049 minus 1. For ASHIFT, use the size minus one as the count (this can
9050 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9051 take the count modulo the size. For other shifts, the result is
9054 Since these shifts are being produced by the compiler by combining
9055 multiple operations, each of which are defined, we know what the
9056 result is supposed to be. */
9058 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9060 if (code == ASHIFTRT)
9061 count = GET_MODE_BITSIZE (shift_mode) - 1;
9062 else if (code == ROTATE || code == ROTATERT)
9063 count %= GET_MODE_BITSIZE (shift_mode);
9066 /* We can't simply return zero because there may be an
9074 /* If we discovered we had to complement VAROP, leave. Making a NOT
9075 here would cause an infinite loop. */
9079 /* An arithmetic right shift of a quantity known to be -1 or 0
9081 if (code == ASHIFTRT
9082 && (num_sign_bit_copies (varop, shift_mode)
9083 == GET_MODE_BITSIZE (shift_mode)))
9089 /* If we are doing an arithmetic right shift and discarding all but
9090 the sign bit copies, this is equivalent to doing a shift by the
9091 bitsize minus one. Convert it into that shift because it will often
9092 allow other simplifications. */
9094 if (code == ASHIFTRT
9095 && (count + num_sign_bit_copies (varop, shift_mode)
9096 >= GET_MODE_BITSIZE (shift_mode)))
9097 count = GET_MODE_BITSIZE (shift_mode) - 1;
9099 /* We simplify the tests below and elsewhere by converting
9100 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9101 `make_compound_operation' will convert it to an ASHIFTRT for
9102 those machines (such as VAX) that don't have an LSHIFTRT. */
9103 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9105 && ((nonzero_bits (varop, shift_mode)
9106 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9110 if (((code == LSHIFTRT
9111 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9112 && !(nonzero_bits (varop, shift_mode) >> count))
9114 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9115 && !((nonzero_bits (varop, shift_mode) << count)
9116 & GET_MODE_MASK (shift_mode))))
9117 && !side_effects_p (varop))
9120 switch (GET_CODE (varop))
9126 new_rtx = expand_compound_operation (varop);
9127 if (new_rtx != varop)
9135 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9136 minus the width of a smaller mode, we can do this with a
9137 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9138 if ((code == ASHIFTRT || code == LSHIFTRT)
9139 && ! mode_dependent_address_p (XEXP (varop, 0))
9140 && ! MEM_VOLATILE_P (varop)
9141 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9142 MODE_INT, 1)) != BLKmode)
9144 new_rtx = adjust_address_nv (varop, tmode,
9145 BYTES_BIG_ENDIAN ? 0
9146 : count / BITS_PER_UNIT);
9148 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9149 : ZERO_EXTEND, mode, new_rtx);
9156 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9157 the same number of words as what we've seen so far. Then store
9158 the widest mode in MODE. */
9159 if (subreg_lowpart_p (varop)
9160 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9161 > GET_MODE_SIZE (GET_MODE (varop)))
9162 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9163 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9166 varop = SUBREG_REG (varop);
9167 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9168 mode = GET_MODE (varop);
9174 /* Some machines use MULT instead of ASHIFT because MULT
9175 is cheaper. But it is still better on those machines to
9176 merge two shifts into one. */
9177 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9178 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9181 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9183 GEN_INT (exact_log2 (
9184 INTVAL (XEXP (varop, 1)))));
9190 /* Similar, for when divides are cheaper. */
9191 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9192 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9195 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9197 GEN_INT (exact_log2 (
9198 INTVAL (XEXP (varop, 1)))));
9204 /* If we are extracting just the sign bit of an arithmetic
9205 right shift, that shift is not needed. However, the sign
9206 bit of a wider mode may be different from what would be
9207 interpreted as the sign bit in a narrower mode, so, if
9208 the result is narrower, don't discard the shift. */
9209 if (code == LSHIFTRT
9210 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9211 && (GET_MODE_BITSIZE (result_mode)
9212 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9214 varop = XEXP (varop, 0);
9218 /* ... fall through ... */
9223 /* Here we have two nested shifts. The result is usually the
9224 AND of a new shift with a mask. We compute the result below. */
9225 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9226 && INTVAL (XEXP (varop, 1)) >= 0
9227 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9228 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9229 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9230 && !VECTOR_MODE_P (result_mode))
9232 enum rtx_code first_code = GET_CODE (varop);
9233 unsigned int first_count = INTVAL (XEXP (varop, 1));
9234 unsigned HOST_WIDE_INT mask;
9237 /* We have one common special case. We can't do any merging if
9238 the inner code is an ASHIFTRT of a smaller mode. However, if
9239 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9240 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9241 we can convert it to
9242 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9243 This simplifies certain SIGN_EXTEND operations. */
9244 if (code == ASHIFT && first_code == ASHIFTRT
9245 && count == (GET_MODE_BITSIZE (result_mode)
9246 - GET_MODE_BITSIZE (GET_MODE (varop))))
9248 /* C3 has the low-order C1 bits zero. */
9250 mask = (GET_MODE_MASK (mode)
9251 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9253 varop = simplify_and_const_int (NULL_RTX, result_mode,
9254 XEXP (varop, 0), mask);
9255 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9257 count = first_count;
9262 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9263 than C1 high-order bits equal to the sign bit, we can convert
9264 this to either an ASHIFT or an ASHIFTRT depending on the
9267 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9269 if (code == ASHIFTRT && first_code == ASHIFT
9270 && GET_MODE (varop) == shift_mode
9271 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9274 varop = XEXP (varop, 0);
9275 count -= first_count;
9285 /* There are some cases we can't do. If CODE is ASHIFTRT,
9286 we can only do this if FIRST_CODE is also ASHIFTRT.
9288 We can't do the case when CODE is ROTATE and FIRST_CODE is
9291 If the mode of this shift is not the mode of the outer shift,
9292 we can't do this if either shift is a right shift or ROTATE.
9294 Finally, we can't do any of these if the mode is too wide
9295 unless the codes are the same.
9297 Handle the case where the shift codes are the same
9300 if (code == first_code)
9302 if (GET_MODE (varop) != result_mode
9303 && (code == ASHIFTRT || code == LSHIFTRT
9307 count += first_count;
9308 varop = XEXP (varop, 0);
9312 if (code == ASHIFTRT
9313 || (code == ROTATE && first_code == ASHIFTRT)
9314 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9315 || (GET_MODE (varop) != result_mode
9316 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9317 || first_code == ROTATE
9318 || code == ROTATE)))
9321 /* To compute the mask to apply after the shift, shift the
9322 nonzero bits of the inner shift the same way the
9323 outer shift will. */
9325 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9328 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9331 /* Give up if we can't compute an outer operation to use. */
9333 || GET_CODE (mask_rtx) != CONST_INT
9334 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9336 result_mode, &complement_p))
9339 /* If the shifts are in the same direction, we add the
9340 counts. Otherwise, we subtract them. */
9341 if ((code == ASHIFTRT || code == LSHIFTRT)
9342 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9343 count += first_count;
9345 count -= first_count;
9347 /* If COUNT is positive, the new shift is usually CODE,
9348 except for the two exceptions below, in which case it is
9349 FIRST_CODE. If the count is negative, FIRST_CODE should
9352 && ((first_code == ROTATE && code == ASHIFT)
9353 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9356 code = first_code, count = -count;
9358 varop = XEXP (varop, 0);
9362 /* If we have (A << B << C) for any shift, we can convert this to
9363 (A << C << B). This wins if A is a constant. Only try this if
9364 B is not a constant. */
9366 else if (GET_CODE (varop) == code
9367 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9368 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9370 rtx new_rtx = simplify_const_binary_operation (code, mode,
9373 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9380 if (VECTOR_MODE_P (mode))
9383 /* Make this fit the case below. */
9384 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9385 GEN_INT (GET_MODE_MASK (mode)));
9391 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9392 with C the size of VAROP - 1 and the shift is logical if
9393 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9394 we have an (le X 0) operation. If we have an arithmetic shift
9395 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9396 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9398 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9399 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9400 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9401 && (code == LSHIFTRT || code == ASHIFTRT)
9402 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9403 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9406 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9409 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9410 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9415 /* If we have (shift (logical)), move the logical to the outside
9416 to allow it to possibly combine with another logical and the
9417 shift to combine with another shift. This also canonicalizes to
9418 what a ZERO_EXTRACT looks like. Also, some machines have
9419 (and (shift)) insns. */
9421 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9422 /* We can't do this if we have (ashiftrt (xor)) and the
9423 constant has its sign bit set in shift_mode. */
9424 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9425 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9427 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9429 GEN_INT (count))) != 0
9430 && GET_CODE (new_rtx) == CONST_INT
9431 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9432 INTVAL (new_rtx), result_mode, &complement_p))
9434 varop = XEXP (varop, 0);
9438 /* If we can't do that, try to simplify the shift in each arm of the
9439 logical expression, make a new logical expression, and apply
9440 the inverse distributive law. This also can't be done
9441 for some (ashiftrt (xor)). */
9442 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9443 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9444 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9447 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9448 XEXP (varop, 0), count);
9449 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9450 XEXP (varop, 1), count);
9452 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9454 varop = apply_distributive_law (varop);
9462 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9463 says that the sign bit can be tested, FOO has mode MODE, C is
9464 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9465 that may be nonzero. */
9466 if (code == LSHIFTRT
9467 && XEXP (varop, 1) == const0_rtx
9468 && GET_MODE (XEXP (varop, 0)) == result_mode
9469 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9470 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9471 && STORE_FLAG_VALUE == -1
9472 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9473 && merge_outer_ops (&outer_op, &outer_const, XOR,
9474 (HOST_WIDE_INT) 1, result_mode,
9477 varop = XEXP (varop, 0);
9484 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9485 than the number of bits in the mode is equivalent to A. */
9486 if (code == LSHIFTRT
9487 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9488 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9490 varop = XEXP (varop, 0);
9495 /* NEG commutes with ASHIFT since it is multiplication. Move the
9496 NEG outside to allow shifts to combine. */
9498 && merge_outer_ops (&outer_op, &outer_const, NEG,
9499 (HOST_WIDE_INT) 0, result_mode,
9502 varop = XEXP (varop, 0);
9508 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9509 is one less than the number of bits in the mode is
9510 equivalent to (xor A 1). */
9511 if (code == LSHIFTRT
9512 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9513 && XEXP (varop, 1) == constm1_rtx
9514 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9515 && merge_outer_ops (&outer_op, &outer_const, XOR,
9516 (HOST_WIDE_INT) 1, result_mode,
9520 varop = XEXP (varop, 0);
9524 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9525 that might be nonzero in BAR are those being shifted out and those
9526 bits are known zero in FOO, we can replace the PLUS with FOO.
9527 Similarly in the other operand order. This code occurs when
9528 we are computing the size of a variable-size array. */
9530 if ((code == ASHIFTRT || code == LSHIFTRT)
9531 && count < HOST_BITS_PER_WIDE_INT
9532 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9533 && (nonzero_bits (XEXP (varop, 1), result_mode)
9534 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9536 varop = XEXP (varop, 0);
9539 else if ((code == ASHIFTRT || code == LSHIFTRT)
9540 && count < HOST_BITS_PER_WIDE_INT
9541 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9542 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9544 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9545 & nonzero_bits (XEXP (varop, 1),
9548 varop = XEXP (varop, 1);
9552 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9554 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9555 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9557 GEN_INT (count))) != 0
9558 && GET_CODE (new_rtx) == CONST_INT
9559 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9560 INTVAL (new_rtx), result_mode, &complement_p))
9562 varop = XEXP (varop, 0);
9566 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9567 signbit', and attempt to change the PLUS to an XOR and move it to
9568 the outer operation as is done above in the AND/IOR/XOR case
9569 leg for shift(logical). See details in logical handling above
9570 for reasoning in doing so. */
9571 if (code == LSHIFTRT
9572 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9573 && mode_signbit_p (result_mode, XEXP (varop, 1))
9574 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9576 GEN_INT (count))) != 0
9577 && GET_CODE (new_rtx) == CONST_INT
9578 && merge_outer_ops (&outer_op, &outer_const, XOR,
9579 INTVAL (new_rtx), result_mode, &complement_p))
9581 varop = XEXP (varop, 0);
9588 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9589 with C the size of VAROP - 1 and the shift is logical if
9590 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9591 we have a (gt X 0) operation. If the shift is arithmetic with
9592 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9593 we have a (neg (gt X 0)) operation. */
9595 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9596 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9597 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9598 && (code == LSHIFTRT || code == ASHIFTRT)
9599 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9600 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9601 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9604 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9607 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9608 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9615 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9616 if the truncate does not affect the value. */
9617 if (code == LSHIFTRT
9618 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9619 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9620 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9621 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9622 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9624 rtx varop_inner = XEXP (varop, 0);
9627 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9628 XEXP (varop_inner, 0),
9630 (count + INTVAL (XEXP (varop_inner, 1))));
9631 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9644 /* We need to determine what mode to do the shift in. If the shift is
9645 a right shift or ROTATE, we must always do it in the mode it was
9646 originally done in. Otherwise, we can do it in MODE, the widest mode
9647 encountered. The code we care about is that of the shift that will
9648 actually be done, not the shift that was originally requested. */
9650 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9651 ? result_mode : mode);
9653 /* We have now finished analyzing the shift. The result should be
9654 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9655 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9656 to the result of the shift. OUTER_CONST is the relevant constant,
9657 but we must turn off all bits turned off in the shift. */
9659 if (outer_op == UNKNOWN
9660 && orig_code == code && orig_count == count
9661 && varop == orig_varop
9662 && shift_mode == GET_MODE (varop))
9665 /* Make a SUBREG if necessary. If we can't make it, fail. */
9666 varop = gen_lowpart (shift_mode, varop);
9667 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9670 /* If we have an outer operation and we just made a shift, it is
9671 possible that we could have simplified the shift were it not
9672 for the outer operation. So try to do the simplification
9675 if (outer_op != UNKNOWN)
9676 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9681 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9683 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9684 turn off all the bits that the shift would have turned off. */
9685 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9686 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9687 GET_MODE_MASK (result_mode) >> orig_count);
9689 /* Do the remainder of the processing in RESULT_MODE. */
9690 x = gen_lowpart_or_truncate (result_mode, x);
9692 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9695 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9697 if (outer_op != UNKNOWN)
9699 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
9700 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9701 outer_const = trunc_int_for_mode (outer_const, result_mode);
9703 if (outer_op == AND)
9704 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9705 else if (outer_op == SET)
9707 /* This means that we have determined that the result is
9708 equivalent to a constant. This should be rare. */
9709 if (!side_effects_p (x))
9710 x = GEN_INT (outer_const);
9712 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9713 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9715 x = simplify_gen_binary (outer_op, result_mode, x,
9716 GEN_INT (outer_const));
9722 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9723 The result of the shift is RESULT_MODE. If we cannot simplify it,
9724 return X or, if it is NULL, synthesize the expression with
9725 simplify_gen_binary. Otherwise, return a simplified value.
9727 The shift is normally computed in the widest mode we find in VAROP, as
9728 long as it isn't a different number of words than RESULT_MODE. Exceptions
9729 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9732 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9733 rtx varop, int count)
9735 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9740 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9741 if (GET_MODE (x) != result_mode)
9742 x = gen_lowpart (result_mode, x);
9747 /* Like recog, but we receive the address of a pointer to a new pattern.
9748 We try to match the rtx that the pointer points to.
9749 If that fails, we may try to modify or replace the pattern,
9750 storing the replacement into the same pointer object.
9752 Modifications include deletion or addition of CLOBBERs.
9754 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9755 the CLOBBERs are placed.
9757 The value is the final insn code from the pattern ultimately matched,
9761 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9764 int insn_code_number;
9765 int num_clobbers_to_add = 0;
9768 rtx old_notes, old_pat;
9770 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9771 we use to indicate that something didn't match. If we find such a
9772 thing, force rejection. */
9773 if (GET_CODE (pat) == PARALLEL)
9774 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9775 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9776 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9779 old_pat = PATTERN (insn);
9780 old_notes = REG_NOTES (insn);
9781 PATTERN (insn) = pat;
9782 REG_NOTES (insn) = 0;
9784 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9785 if (dump_file && (dump_flags & TDF_DETAILS))
9787 if (insn_code_number < 0)
9788 fputs ("Failed to match this instruction:\n", dump_file);
9790 fputs ("Successfully matched this instruction:\n", dump_file);
9791 print_rtl_single (dump_file, pat);
9794 /* If it isn't, there is the possibility that we previously had an insn
9795 that clobbered some register as a side effect, but the combined
9796 insn doesn't need to do that. So try once more without the clobbers
9797 unless this represents an ASM insn. */
9799 if (insn_code_number < 0 && ! check_asm_operands (pat)
9800 && GET_CODE (pat) == PARALLEL)
9804 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9805 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9808 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9812 SUBST_INT (XVECLEN (pat, 0), pos);
9815 pat = XVECEXP (pat, 0, 0);
9817 PATTERN (insn) = pat;
9818 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9819 if (dump_file && (dump_flags & TDF_DETAILS))
9821 if (insn_code_number < 0)
9822 fputs ("Failed to match this instruction:\n", dump_file);
9824 fputs ("Successfully matched this instruction:\n", dump_file);
9825 print_rtl_single (dump_file, pat);
9828 PATTERN (insn) = old_pat;
9829 REG_NOTES (insn) = old_notes;
9831 /* Recognize all noop sets, these will be killed by followup pass. */
9832 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9833 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9835 /* If we had any clobbers to add, make a new pattern than contains
9836 them. Then check to make sure that all of them are dead. */
9837 if (num_clobbers_to_add)
9839 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9840 rtvec_alloc (GET_CODE (pat) == PARALLEL
9842 + num_clobbers_to_add)
9843 : num_clobbers_to_add + 1));
9845 if (GET_CODE (pat) == PARALLEL)
9846 for (i = 0; i < XVECLEN (pat, 0); i++)
9847 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9849 XVECEXP (newpat, 0, 0) = pat;
9851 add_clobbers (newpat, insn_code_number);
9853 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9854 i < XVECLEN (newpat, 0); i++)
9856 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9857 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9859 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9861 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9862 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9863 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9872 return insn_code_number;
9875 /* Like gen_lowpart_general but for use by combine. In combine it
9876 is not possible to create any new pseudoregs. However, it is
9877 safe to create invalid memory addresses, because combine will
9878 try to recognize them and all they will do is make the combine
9881 If for some reason this cannot do its job, an rtx
9882 (clobber (const_int 0)) is returned.
9883 An insn containing that will not be recognized. */
9886 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9888 enum machine_mode imode = GET_MODE (x);
9889 unsigned int osize = GET_MODE_SIZE (omode);
9890 unsigned int isize = GET_MODE_SIZE (imode);
9896 /* Return identity if this is a CONST or symbolic reference. */
9898 && (GET_CODE (x) == CONST
9899 || GET_CODE (x) == SYMBOL_REF
9900 || GET_CODE (x) == LABEL_REF))
9903 /* We can only support MODE being wider than a word if X is a
9904 constant integer or has a mode the same size. */
9905 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9906 && ! ((imode == VOIDmode
9907 && (GET_CODE (x) == CONST_INT
9908 || GET_CODE (x) == CONST_DOUBLE))
9912 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9913 won't know what to do. So we will strip off the SUBREG here and
9914 process normally. */
9915 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9919 /* For use in case we fall down into the address adjustments
9920 further below, we need to adjust the known mode and size of
9921 x; imode and isize, since we just adjusted x. */
9922 imode = GET_MODE (x);
9927 isize = GET_MODE_SIZE (imode);
9930 result = gen_lowpart_common (omode, x);
9939 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9941 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9944 /* If we want to refer to something bigger than the original memref,
9945 generate a paradoxical subreg instead. That will force a reload
9946 of the original memref X. */
9948 return gen_rtx_SUBREG (omode, x, 0);
9950 if (WORDS_BIG_ENDIAN)
9951 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9953 /* Adjust the address so that the address-after-the-data is
9955 if (BYTES_BIG_ENDIAN)
9956 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9958 return adjust_address_nv (x, omode, offset);
9961 /* If X is a comparison operator, rewrite it in a new mode. This
9962 probably won't match, but may allow further simplifications. */
9963 else if (COMPARISON_P (x))
9964 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9966 /* If we couldn't simplify X any other way, just enclose it in a
9967 SUBREG. Normally, this SUBREG won't match, but some patterns may
9968 include an explicit SUBREG or we may simplify it further in combine. */
9974 offset = subreg_lowpart_offset (omode, imode);
9975 if (imode == VOIDmode)
9977 imode = int_mode_for_mode (omode);
9978 x = gen_lowpart_common (imode, x);
9982 res = simplify_gen_subreg (omode, x, imode, offset);
9988 return gen_rtx_CLOBBER (omode, const0_rtx);
9991 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9992 comparison code that will be tested.
9994 The result is a possibly different comparison code to use. *POP0 and
9995 *POP1 may be updated.
9997 It is possible that we might detect that a comparison is either always
9998 true or always false. However, we do not perform general constant
9999 folding in combine, so this knowledge isn't useful. Such tautologies
10000 should have been detected earlier. Hence we ignore all such cases. */
10002 static enum rtx_code
10003 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10009 enum machine_mode mode, tmode;
10011 /* Try a few ways of applying the same transformation to both operands. */
10014 #ifndef WORD_REGISTER_OPERATIONS
10015 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10016 so check specially. */
10017 if (code != GTU && code != GEU && code != LTU && code != LEU
10018 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10019 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10020 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10021 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10022 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10023 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10024 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10025 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10026 && XEXP (op0, 1) == XEXP (op1, 1)
10027 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10028 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10029 && (INTVAL (XEXP (op0, 1))
10030 == (GET_MODE_BITSIZE (GET_MODE (op0))
10031 - (GET_MODE_BITSIZE
10032 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10034 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10035 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10039 /* If both operands are the same constant shift, see if we can ignore the
10040 shift. We can if the shift is a rotate or if the bits shifted out of
10041 this shift are known to be zero for both inputs and if the type of
10042 comparison is compatible with the shift. */
10043 if (GET_CODE (op0) == GET_CODE (op1)
10044 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10045 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10046 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10047 && (code != GT && code != LT && code != GE && code != LE))
10048 || (GET_CODE (op0) == ASHIFTRT
10049 && (code != GTU && code != LTU
10050 && code != GEU && code != LEU)))
10051 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10052 && INTVAL (XEXP (op0, 1)) >= 0
10053 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10054 && XEXP (op0, 1) == XEXP (op1, 1))
10056 enum machine_mode mode = GET_MODE (op0);
10057 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10058 int shift_count = INTVAL (XEXP (op0, 1));
10060 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10061 mask &= (mask >> shift_count) << shift_count;
10062 else if (GET_CODE (op0) == ASHIFT)
10063 mask = (mask & (mask << shift_count)) >> shift_count;
10065 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10066 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10067 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10072 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10073 SUBREGs are of the same mode, and, in both cases, the AND would
10074 be redundant if the comparison was done in the narrower mode,
10075 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10076 and the operand's possibly nonzero bits are 0xffffff01; in that case
10077 if we only care about QImode, we don't need the AND). This case
10078 occurs if the output mode of an scc insn is not SImode and
10079 STORE_FLAG_VALUE == 1 (e.g., the 386).
10081 Similarly, check for a case where the AND's are ZERO_EXTEND
10082 operations from some narrower mode even though a SUBREG is not
10085 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10086 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10087 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10089 rtx inner_op0 = XEXP (op0, 0);
10090 rtx inner_op1 = XEXP (op1, 0);
10091 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10092 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10095 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10096 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10097 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10098 && (GET_MODE (SUBREG_REG (inner_op0))
10099 == GET_MODE (SUBREG_REG (inner_op1)))
10100 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10101 <= HOST_BITS_PER_WIDE_INT)
10102 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10103 GET_MODE (SUBREG_REG (inner_op0)))))
10104 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10105 GET_MODE (SUBREG_REG (inner_op1))))))
10107 op0 = SUBREG_REG (inner_op0);
10108 op1 = SUBREG_REG (inner_op1);
10110 /* The resulting comparison is always unsigned since we masked
10111 off the original sign bit. */
10112 code = unsigned_condition (code);
10118 for (tmode = GET_CLASS_NARROWEST_MODE
10119 (GET_MODE_CLASS (GET_MODE (op0)));
10120 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10121 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10123 op0 = gen_lowpart (tmode, inner_op0);
10124 op1 = gen_lowpart (tmode, inner_op1);
10125 code = unsigned_condition (code);
10134 /* If both operands are NOT, we can strip off the outer operation
10135 and adjust the comparison code for swapped operands; similarly for
10136 NEG, except that this must be an equality comparison. */
10137 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10138 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10139 && (code == EQ || code == NE)))
10140 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10146 /* If the first operand is a constant, swap the operands and adjust the
10147 comparison code appropriately, but don't do this if the second operand
10148 is already a constant integer. */
10149 if (swap_commutative_operands_p (op0, op1))
10151 tem = op0, op0 = op1, op1 = tem;
10152 code = swap_condition (code);
10155 /* We now enter a loop during which we will try to simplify the comparison.
10156 For the most part, we only are concerned with comparisons with zero,
10157 but some things may really be comparisons with zero but not start
10158 out looking that way. */
10160 while (GET_CODE (op1) == CONST_INT)
10162 enum machine_mode mode = GET_MODE (op0);
10163 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10164 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10165 int equality_comparison_p;
10166 int sign_bit_comparison_p;
10167 int unsigned_comparison_p;
10168 HOST_WIDE_INT const_op;
10170 /* We only want to handle integral modes. This catches VOIDmode,
10171 CCmode, and the floating-point modes. An exception is that we
10172 can handle VOIDmode if OP0 is a COMPARE or a comparison
10175 if (GET_MODE_CLASS (mode) != MODE_INT
10176 && ! (mode == VOIDmode
10177 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10180 /* Get the constant we are comparing against and turn off all bits
10181 not on in our mode. */
10182 const_op = INTVAL (op1);
10183 if (mode != VOIDmode)
10184 const_op = trunc_int_for_mode (const_op, mode);
10185 op1 = GEN_INT (const_op);
10187 /* If we are comparing against a constant power of two and the value
10188 being compared can only have that single bit nonzero (e.g., it was
10189 `and'ed with that bit), we can replace this with a comparison
10192 && (code == EQ || code == NE || code == GE || code == GEU
10193 || code == LT || code == LTU)
10194 && mode_width <= HOST_BITS_PER_WIDE_INT
10195 && exact_log2 (const_op) >= 0
10196 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10198 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10199 op1 = const0_rtx, const_op = 0;
10202 /* Similarly, if we are comparing a value known to be either -1 or
10203 0 with -1, change it to the opposite comparison against zero. */
10206 && (code == EQ || code == NE || code == GT || code == LE
10207 || code == GEU || code == LTU)
10208 && num_sign_bit_copies (op0, mode) == mode_width)
10210 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10211 op1 = const0_rtx, const_op = 0;
10214 /* Do some canonicalizations based on the comparison code. We prefer
10215 comparisons against zero and then prefer equality comparisons.
10216 If we can reduce the size of a constant, we will do that too. */
10221 /* < C is equivalent to <= (C - 1) */
10225 op1 = GEN_INT (const_op);
10227 /* ... fall through to LE case below. */
10233 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10237 op1 = GEN_INT (const_op);
10241 /* If we are doing a <= 0 comparison on a value known to have
10242 a zero sign bit, we can replace this with == 0. */
10243 else if (const_op == 0
10244 && mode_width <= HOST_BITS_PER_WIDE_INT
10245 && (nonzero_bits (op0, mode)
10246 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10251 /* >= C is equivalent to > (C - 1). */
10255 op1 = GEN_INT (const_op);
10257 /* ... fall through to GT below. */
10263 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10267 op1 = GEN_INT (const_op);
10271 /* If we are doing a > 0 comparison on a value known to have
10272 a zero sign bit, we can replace this with != 0. */
10273 else if (const_op == 0
10274 && mode_width <= HOST_BITS_PER_WIDE_INT
10275 && (nonzero_bits (op0, mode)
10276 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10281 /* < C is equivalent to <= (C - 1). */
10285 op1 = GEN_INT (const_op);
10287 /* ... fall through ... */
10290 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10291 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10292 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10294 const_op = 0, op1 = const0_rtx;
10302 /* unsigned <= 0 is equivalent to == 0 */
10306 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10307 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10308 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10310 const_op = 0, op1 = const0_rtx;
10316 /* >= C is equivalent to > (C - 1). */
10320 op1 = GEN_INT (const_op);
10322 /* ... fall through ... */
10325 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10326 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10327 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10329 const_op = 0, op1 = const0_rtx;
10337 /* unsigned > 0 is equivalent to != 0 */
10341 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10342 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10343 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10345 const_op = 0, op1 = const0_rtx;
10354 /* Compute some predicates to simplify code below. */
10356 equality_comparison_p = (code == EQ || code == NE);
10357 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10358 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10361 /* If this is a sign bit comparison and we can do arithmetic in
10362 MODE, say that we will only be needing the sign bit of OP0. */
10363 if (sign_bit_comparison_p
10364 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10365 op0 = force_to_mode (op0, mode,
10367 << (GET_MODE_BITSIZE (mode) - 1)),
10370 /* Now try cases based on the opcode of OP0. If none of the cases
10371 does a "continue", we exit this loop immediately after the
10374 switch (GET_CODE (op0))
10377 /* If we are extracting a single bit from a variable position in
10378 a constant that has only a single bit set and are comparing it
10379 with zero, we can convert this into an equality comparison
10380 between the position and the location of the single bit. */
10381 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10382 have already reduced the shift count modulo the word size. */
10383 if (!SHIFT_COUNT_TRUNCATED
10384 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10385 && XEXP (op0, 1) == const1_rtx
10386 && equality_comparison_p && const_op == 0
10387 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10389 if (BITS_BIG_ENDIAN)
10391 enum machine_mode new_mode
10392 = mode_for_extraction (EP_extzv, 1);
10393 if (new_mode == MAX_MACHINE_MODE)
10394 i = BITS_PER_WORD - 1 - i;
10398 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10402 op0 = XEXP (op0, 2);
10406 /* Result is nonzero iff shift count is equal to I. */
10407 code = reverse_condition (code);
10411 /* ... fall through ... */
10414 tem = expand_compound_operation (op0);
10423 /* If testing for equality, we can take the NOT of the constant. */
10424 if (equality_comparison_p
10425 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10427 op0 = XEXP (op0, 0);
10432 /* If just looking at the sign bit, reverse the sense of the
10434 if (sign_bit_comparison_p)
10436 op0 = XEXP (op0, 0);
10437 code = (code == GE ? LT : GE);
10443 /* If testing for equality, we can take the NEG of the constant. */
10444 if (equality_comparison_p
10445 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10447 op0 = XEXP (op0, 0);
10452 /* The remaining cases only apply to comparisons with zero. */
10456 /* When X is ABS or is known positive,
10457 (neg X) is < 0 if and only if X != 0. */
10459 if (sign_bit_comparison_p
10460 && (GET_CODE (XEXP (op0, 0)) == ABS
10461 || (mode_width <= HOST_BITS_PER_WIDE_INT
10462 && (nonzero_bits (XEXP (op0, 0), mode)
10463 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10465 op0 = XEXP (op0, 0);
10466 code = (code == LT ? NE : EQ);
10470 /* If we have NEG of something whose two high-order bits are the
10471 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10472 if (num_sign_bit_copies (op0, mode) >= 2)
10474 op0 = XEXP (op0, 0);
10475 code = swap_condition (code);
10481 /* If we are testing equality and our count is a constant, we
10482 can perform the inverse operation on our RHS. */
10483 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10484 && (tem = simplify_binary_operation (ROTATERT, mode,
10485 op1, XEXP (op0, 1))) != 0)
10487 op0 = XEXP (op0, 0);
10492 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10493 a particular bit. Convert it to an AND of a constant of that
10494 bit. This will be converted into a ZERO_EXTRACT. */
10495 if (const_op == 0 && sign_bit_comparison_p
10496 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10497 && mode_width <= HOST_BITS_PER_WIDE_INT)
10499 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10502 - INTVAL (XEXP (op0, 1)))));
10503 code = (code == LT ? NE : EQ);
10507 /* Fall through. */
10510 /* ABS is ignorable inside an equality comparison with zero. */
10511 if (const_op == 0 && equality_comparison_p)
10513 op0 = XEXP (op0, 0);
10519 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10520 (compare FOO CONST) if CONST fits in FOO's mode and we
10521 are either testing inequality or have an unsigned
10522 comparison with ZERO_EXTEND or a signed comparison with
10523 SIGN_EXTEND. But don't do it if we don't have a compare
10524 insn of the given mode, since we'd have to revert it
10525 later on, and then we wouldn't know whether to sign- or
10527 mode = GET_MODE (XEXP (op0, 0));
10528 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10529 && ! unsigned_comparison_p
10530 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10531 && ((unsigned HOST_WIDE_INT) const_op
10532 < (((unsigned HOST_WIDE_INT) 1
10533 << (GET_MODE_BITSIZE (mode) - 1))))
10534 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10536 op0 = XEXP (op0, 0);
10542 /* Check for the case where we are comparing A - C1 with C2, that is
10544 (subreg:MODE (plus (A) (-C1))) op (C2)
10546 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10547 comparison in the wider mode. One of the following two conditions
10548 must be true in order for this to be valid:
10550 1. The mode extension results in the same bit pattern being added
10551 on both sides and the comparison is equality or unsigned. As
10552 C2 has been truncated to fit in MODE, the pattern can only be
10555 2. The mode extension results in the sign bit being copied on
10558 The difficulty here is that we have predicates for A but not for
10559 (A - C1) so we need to check that C1 is within proper bounds so
10560 as to perturbate A as little as possible. */
10562 if (mode_width <= HOST_BITS_PER_WIDE_INT
10563 && subreg_lowpart_p (op0)
10564 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10565 && GET_CODE (SUBREG_REG (op0)) == PLUS
10566 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10568 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10569 rtx a = XEXP (SUBREG_REG (op0), 0);
10570 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10573 && (unsigned HOST_WIDE_INT) c1
10574 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10575 && (equality_comparison_p || unsigned_comparison_p)
10576 /* (A - C1) zero-extends if it is positive and sign-extends
10577 if it is negative, C2 both zero- and sign-extends. */
10578 && ((0 == (nonzero_bits (a, inner_mode)
10579 & ~GET_MODE_MASK (mode))
10581 /* (A - C1) sign-extends if it is positive and 1-extends
10582 if it is negative, C2 both sign- and 1-extends. */
10583 || (num_sign_bit_copies (a, inner_mode)
10584 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10587 || ((unsigned HOST_WIDE_INT) c1
10588 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10589 /* (A - C1) always sign-extends, like C2. */
10590 && num_sign_bit_copies (a, inner_mode)
10591 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10592 - (mode_width - 1))))
10594 op0 = SUBREG_REG (op0);
10599 /* If the inner mode is narrower and we are extracting the low part,
10600 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10601 if (subreg_lowpart_p (op0)
10602 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10603 /* Fall through */ ;
10607 /* ... fall through ... */
10610 mode = GET_MODE (XEXP (op0, 0));
10611 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10612 && (unsigned_comparison_p || equality_comparison_p)
10613 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10614 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10615 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10617 op0 = XEXP (op0, 0);
10623 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10624 this for equality comparisons due to pathological cases involving
10626 if (equality_comparison_p
10627 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10628 op1, XEXP (op0, 1))))
10630 op0 = XEXP (op0, 0);
10635 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10636 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10637 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10639 op0 = XEXP (XEXP (op0, 0), 0);
10640 code = (code == LT ? EQ : NE);
10646 /* We used to optimize signed comparisons against zero, but that
10647 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10648 arrive here as equality comparisons, or (GEU, LTU) are
10649 optimized away. No need to special-case them. */
10651 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10652 (eq B (minus A C)), whichever simplifies. We can only do
10653 this for equality comparisons due to pathological cases involving
10655 if (equality_comparison_p
10656 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10657 XEXP (op0, 1), op1)))
10659 op0 = XEXP (op0, 0);
10664 if (equality_comparison_p
10665 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10666 XEXP (op0, 0), op1)))
10668 op0 = XEXP (op0, 1);
10673 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10674 of bits in X minus 1, is one iff X > 0. */
10675 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10676 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10677 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10679 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10681 op0 = XEXP (op0, 1);
10682 code = (code == GE ? LE : GT);
10688 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10689 if C is zero or B is a constant. */
10690 if (equality_comparison_p
10691 && 0 != (tem = simplify_binary_operation (XOR, mode,
10692 XEXP (op0, 1), op1)))
10694 op0 = XEXP (op0, 0);
10701 case UNEQ: case LTGT:
10702 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10703 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10704 case UNORDERED: case ORDERED:
10705 /* We can't do anything if OP0 is a condition code value, rather
10706 than an actual data value. */
10708 || CC0_P (XEXP (op0, 0))
10709 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10712 /* Get the two operands being compared. */
10713 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10714 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10716 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10718 /* Check for the cases where we simply want the result of the
10719 earlier test or the opposite of that result. */
10720 if (code == NE || code == EQ
10721 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10722 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10723 && (STORE_FLAG_VALUE
10724 & (((HOST_WIDE_INT) 1
10725 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10726 && (code == LT || code == GE)))
10728 enum rtx_code new_code;
10729 if (code == LT || code == NE)
10730 new_code = GET_CODE (op0);
10732 new_code = reversed_comparison_code (op0, NULL);
10734 if (new_code != UNKNOWN)
10745 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10747 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10748 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10749 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10751 op0 = XEXP (op0, 1);
10752 code = (code == GE ? GT : LE);
10758 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10759 will be converted to a ZERO_EXTRACT later. */
10760 if (const_op == 0 && equality_comparison_p
10761 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10762 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10764 op0 = simplify_and_const_int
10765 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10767 XEXP (XEXP (op0, 0), 1)),
10768 (HOST_WIDE_INT) 1);
10772 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10773 zero and X is a comparison and C1 and C2 describe only bits set
10774 in STORE_FLAG_VALUE, we can compare with X. */
10775 if (const_op == 0 && equality_comparison_p
10776 && mode_width <= HOST_BITS_PER_WIDE_INT
10777 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10778 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10779 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10780 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10781 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10783 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10784 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10785 if ((~STORE_FLAG_VALUE & mask) == 0
10786 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10787 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10788 && COMPARISON_P (tem))))
10790 op0 = XEXP (XEXP (op0, 0), 0);
10795 /* If we are doing an equality comparison of an AND of a bit equal
10796 to the sign bit, replace this with a LT or GE comparison of
10797 the underlying value. */
10798 if (equality_comparison_p
10800 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10801 && mode_width <= HOST_BITS_PER_WIDE_INT
10802 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10803 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10805 op0 = XEXP (op0, 0);
10806 code = (code == EQ ? GE : LT);
10810 /* If this AND operation is really a ZERO_EXTEND from a narrower
10811 mode, the constant fits within that mode, and this is either an
10812 equality or unsigned comparison, try to do this comparison in
10817 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10818 -> (ne:DI (reg:SI 4) (const_int 0))
10820 unless TRULY_NOOP_TRUNCATION allows it or the register is
10821 known to hold a value of the required mode the
10822 transformation is invalid. */
10823 if ((equality_comparison_p || unsigned_comparison_p)
10824 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10825 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10826 & GET_MODE_MASK (mode))
10828 && const_op >> i == 0
10829 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10830 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10831 GET_MODE_BITSIZE (GET_MODE (op0)))
10832 || (REG_P (XEXP (op0, 0))
10833 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10835 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10839 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10840 fits in both M1 and M2 and the SUBREG is either paradoxical
10841 or represents the low part, permute the SUBREG and the AND
10843 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10845 unsigned HOST_WIDE_INT c1;
10846 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10847 /* Require an integral mode, to avoid creating something like
10849 if (SCALAR_INT_MODE_P (tmode)
10850 /* It is unsafe to commute the AND into the SUBREG if the
10851 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10852 not defined. As originally written the upper bits
10853 have a defined value due to the AND operation.
10854 However, if we commute the AND inside the SUBREG then
10855 they no longer have defined values and the meaning of
10856 the code has been changed. */
10858 #ifdef WORD_REGISTER_OPERATIONS
10859 || (mode_width > GET_MODE_BITSIZE (tmode)
10860 && mode_width <= BITS_PER_WORD)
10862 || (mode_width <= GET_MODE_BITSIZE (tmode)
10863 && subreg_lowpart_p (XEXP (op0, 0))))
10864 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10865 && mode_width <= HOST_BITS_PER_WIDE_INT
10866 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10867 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10868 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10870 && c1 != GET_MODE_MASK (tmode))
10872 op0 = simplify_gen_binary (AND, tmode,
10873 SUBREG_REG (XEXP (op0, 0)),
10874 gen_int_mode (c1, tmode));
10875 op0 = gen_lowpart (mode, op0);
10880 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10881 if (const_op == 0 && equality_comparison_p
10882 && XEXP (op0, 1) == const1_rtx
10883 && GET_CODE (XEXP (op0, 0)) == NOT)
10885 op0 = simplify_and_const_int
10886 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10887 code = (code == NE ? EQ : NE);
10891 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10892 (eq (and (lshiftrt X) 1) 0).
10893 Also handle the case where (not X) is expressed using xor. */
10894 if (const_op == 0 && equality_comparison_p
10895 && XEXP (op0, 1) == const1_rtx
10896 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10898 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10899 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10901 if (GET_CODE (shift_op) == NOT
10902 || (GET_CODE (shift_op) == XOR
10903 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10904 && GET_CODE (shift_count) == CONST_INT
10905 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10906 && (INTVAL (XEXP (shift_op, 1))
10907 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10909 op0 = simplify_and_const_int
10911 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10912 (HOST_WIDE_INT) 1);
10913 code = (code == NE ? EQ : NE);
10920 /* If we have (compare (ashift FOO N) (const_int C)) and
10921 the high order N bits of FOO (N+1 if an inequality comparison)
10922 are known to be zero, we can do this by comparing FOO with C
10923 shifted right N bits so long as the low-order N bits of C are
10925 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10926 && INTVAL (XEXP (op0, 1)) >= 0
10927 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10928 < HOST_BITS_PER_WIDE_INT)
10930 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10931 && mode_width <= HOST_BITS_PER_WIDE_INT
10932 && (nonzero_bits (XEXP (op0, 0), mode)
10933 & ~(mask >> (INTVAL (XEXP (op0, 1))
10934 + ! equality_comparison_p))) == 0)
10936 /* We must perform a logical shift, not an arithmetic one,
10937 as we want the top N bits of C to be zero. */
10938 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10940 temp >>= INTVAL (XEXP (op0, 1));
10941 op1 = gen_int_mode (temp, mode);
10942 op0 = XEXP (op0, 0);
10946 /* If we are doing a sign bit comparison, it means we are testing
10947 a particular bit. Convert it to the appropriate AND. */
10948 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10949 && mode_width <= HOST_BITS_PER_WIDE_INT)
10951 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10954 - INTVAL (XEXP (op0, 1)))));
10955 code = (code == LT ? NE : EQ);
10959 /* If this an equality comparison with zero and we are shifting
10960 the low bit to the sign bit, we can convert this to an AND of the
10962 if (const_op == 0 && equality_comparison_p
10963 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10964 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10967 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10968 (HOST_WIDE_INT) 1);
10974 /* If this is an equality comparison with zero, we can do this
10975 as a logical shift, which might be much simpler. */
10976 if (equality_comparison_p && const_op == 0
10977 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10979 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10981 INTVAL (XEXP (op0, 1)));
10985 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10986 do the comparison in a narrower mode. */
10987 if (! unsigned_comparison_p
10988 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10989 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10990 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10991 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10992 MODE_INT, 1)) != BLKmode
10993 && (((unsigned HOST_WIDE_INT) const_op
10994 + (GET_MODE_MASK (tmode) >> 1) + 1)
10995 <= GET_MODE_MASK (tmode)))
10997 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11001 /* Likewise if OP0 is a PLUS of a sign extension with a
11002 constant, which is usually represented with the PLUS
11003 between the shifts. */
11004 if (! unsigned_comparison_p
11005 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11006 && GET_CODE (XEXP (op0, 0)) == PLUS
11007 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11008 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11009 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11010 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11011 MODE_INT, 1)) != BLKmode
11012 && (((unsigned HOST_WIDE_INT) const_op
11013 + (GET_MODE_MASK (tmode) >> 1) + 1)
11014 <= GET_MODE_MASK (tmode)))
11016 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11017 rtx add_const = XEXP (XEXP (op0, 0), 1);
11018 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11019 add_const, XEXP (op0, 1));
11021 op0 = simplify_gen_binary (PLUS, tmode,
11022 gen_lowpart (tmode, inner),
11027 /* ... fall through ... */
11029 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11030 the low order N bits of FOO are known to be zero, we can do this
11031 by comparing FOO with C shifted left N bits so long as no
11032 overflow occurs. */
11033 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11034 && INTVAL (XEXP (op0, 1)) >= 0
11035 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11036 && mode_width <= HOST_BITS_PER_WIDE_INT
11037 && (nonzero_bits (XEXP (op0, 0), mode)
11038 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11039 && (((unsigned HOST_WIDE_INT) const_op
11040 + (GET_CODE (op0) != LSHIFTRT
11041 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11044 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11046 /* If the shift was logical, then we must make the condition
11048 if (GET_CODE (op0) == LSHIFTRT)
11049 code = unsigned_condition (code);
11051 const_op <<= INTVAL (XEXP (op0, 1));
11052 op1 = GEN_INT (const_op);
11053 op0 = XEXP (op0, 0);
11057 /* If we are using this shift to extract just the sign bit, we
11058 can replace this with an LT or GE comparison. */
11060 && (equality_comparison_p || sign_bit_comparison_p)
11061 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11062 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11065 op0 = XEXP (op0, 0);
11066 code = (code == NE || code == GT ? LT : GE);
11078 /* Now make any compound operations involved in this comparison. Then,
11079 check for an outmost SUBREG on OP0 that is not doing anything or is
11080 paradoxical. The latter transformation must only be performed when
11081 it is known that the "extra" bits will be the same in op0 and op1 or
11082 that they don't matter. There are three cases to consider:
11084 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11085 care bits and we can assume they have any convenient value. So
11086 making the transformation is safe.
11088 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11089 In this case the upper bits of op0 are undefined. We should not make
11090 the simplification in that case as we do not know the contents of
11093 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11094 UNKNOWN. In that case we know those bits are zeros or ones. We must
11095 also be sure that they are the same as the upper bits of op1.
11097 We can never remove a SUBREG for a non-equality comparison because
11098 the sign bit is in a different place in the underlying object. */
11100 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11101 op1 = make_compound_operation (op1, SET);
11103 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11104 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11105 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11106 && (code == NE || code == EQ))
11108 if (GET_MODE_SIZE (GET_MODE (op0))
11109 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11111 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11113 if (REG_P (SUBREG_REG (op0)))
11115 op0 = SUBREG_REG (op0);
11116 op1 = gen_lowpart (GET_MODE (op0), op1);
11119 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11120 <= HOST_BITS_PER_WIDE_INT)
11121 && (nonzero_bits (SUBREG_REG (op0),
11122 GET_MODE (SUBREG_REG (op0)))
11123 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11125 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11127 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11128 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11129 op0 = SUBREG_REG (op0), op1 = tem;
11133 /* We now do the opposite procedure: Some machines don't have compare
11134 insns in all modes. If OP0's mode is an integer mode smaller than a
11135 word and we can't do a compare in that mode, see if there is a larger
11136 mode for which we can do the compare. There are a number of cases in
11137 which we can use the wider mode. */
11139 mode = GET_MODE (op0);
11140 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11141 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11142 && ! have_insn_for (COMPARE, mode))
11143 for (tmode = GET_MODE_WIDER_MODE (mode);
11145 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11146 tmode = GET_MODE_WIDER_MODE (tmode))
11147 if (have_insn_for (COMPARE, tmode))
11151 /* If the only nonzero bits in OP0 and OP1 are those in the
11152 narrower mode and this is an equality or unsigned comparison,
11153 we can use the wider mode. Similarly for sign-extended
11154 values, in which case it is true for all comparisons. */
11155 zero_extended = ((code == EQ || code == NE
11156 || code == GEU || code == GTU
11157 || code == LEU || code == LTU)
11158 && (nonzero_bits (op0, tmode)
11159 & ~GET_MODE_MASK (mode)) == 0
11160 && ((GET_CODE (op1) == CONST_INT
11161 || (nonzero_bits (op1, tmode)
11162 & ~GET_MODE_MASK (mode)) == 0)));
11165 || ((num_sign_bit_copies (op0, tmode)
11166 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11167 - GET_MODE_BITSIZE (mode)))
11168 && (num_sign_bit_copies (op1, tmode)
11169 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11170 - GET_MODE_BITSIZE (mode)))))
11172 /* If OP0 is an AND and we don't have an AND in MODE either,
11173 make a new AND in the proper mode. */
11174 if (GET_CODE (op0) == AND
11175 && !have_insn_for (AND, mode))
11176 op0 = simplify_gen_binary (AND, tmode,
11177 gen_lowpart (tmode,
11179 gen_lowpart (tmode,
11182 op0 = gen_lowpart (tmode, op0);
11183 if (zero_extended && GET_CODE (op1) == CONST_INT)
11184 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11185 op1 = gen_lowpart (tmode, op1);
11189 /* If this is a test for negative, we can make an explicit
11190 test of the sign bit. */
11192 if (op1 == const0_rtx && (code == LT || code == GE)
11193 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11195 op0 = simplify_gen_binary (AND, tmode,
11196 gen_lowpart (tmode, op0),
11197 GEN_INT ((HOST_WIDE_INT) 1
11198 << (GET_MODE_BITSIZE (mode)
11200 code = (code == LT) ? NE : EQ;
11205 #ifdef CANONICALIZE_COMPARISON
11206 /* If this machine only supports a subset of valid comparisons, see if we
11207 can convert an unsupported one into a supported one. */
11208 CANONICALIZE_COMPARISON (code, op0, op1);
11217 /* Utility function for record_value_for_reg. Count number of
11222 enum rtx_code code = GET_CODE (x);
11226 if (GET_RTX_CLASS (code) == '2'
11227 || GET_RTX_CLASS (code) == 'c')
11229 rtx x0 = XEXP (x, 0);
11230 rtx x1 = XEXP (x, 1);
11233 return 1 + 2 * count_rtxs (x0);
11235 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11236 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11237 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11238 return 2 + 2 * count_rtxs (x0)
11239 + count_rtxs (x == XEXP (x1, 0)
11240 ? XEXP (x1, 1) : XEXP (x1, 0));
11242 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11243 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11244 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11245 return 2 + 2 * count_rtxs (x1)
11246 + count_rtxs (x == XEXP (x0, 0)
11247 ? XEXP (x0, 1) : XEXP (x0, 0));
11250 fmt = GET_RTX_FORMAT (code);
11251 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11253 ret += count_rtxs (XEXP (x, i));
11254 else if (fmt[i] == 'E')
11255 for (j = 0; j < XVECLEN (x, i); j++)
11256 ret += count_rtxs (XVECEXP (x, i, j));
11261 /* Utility function for following routine. Called when X is part of a value
11262 being stored into last_set_value. Sets last_set_table_tick
11263 for each register mentioned. Similar to mention_regs in cse.c */
11266 update_table_tick (rtx x)
11268 enum rtx_code code = GET_CODE (x);
11269 const char *fmt = GET_RTX_FORMAT (code);
11274 unsigned int regno = REGNO (x);
11275 unsigned int endregno = END_REGNO (x);
11278 for (r = regno; r < endregno; r++)
11280 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11281 rsp->last_set_table_tick = label_tick;
11287 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11290 /* Check for identical subexpressions. If x contains
11291 identical subexpression we only have to traverse one of
11293 if (i == 0 && ARITHMETIC_P (x))
11295 /* Note that at this point x1 has already been
11297 rtx x0 = XEXP (x, 0);
11298 rtx x1 = XEXP (x, 1);
11300 /* If x0 and x1 are identical then there is no need to
11305 /* If x0 is identical to a subexpression of x1 then while
11306 processing x1, x0 has already been processed. Thus we
11307 are done with x. */
11308 if (ARITHMETIC_P (x1)
11309 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11312 /* If x1 is identical to a subexpression of x0 then we
11313 still have to process the rest of x0. */
11314 if (ARITHMETIC_P (x0)
11315 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11317 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11322 update_table_tick (XEXP (x, i));
11324 else if (fmt[i] == 'E')
11325 for (j = 0; j < XVECLEN (x, i); j++)
11326 update_table_tick (XVECEXP (x, i, j));
11329 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11330 are saying that the register is clobbered and we no longer know its
11331 value. If INSN is zero, don't update reg_stat[].last_set; this is
11332 only permitted with VALUE also zero and is used to invalidate the
11336 record_value_for_reg (rtx reg, rtx insn, rtx value)
11338 unsigned int regno = REGNO (reg);
11339 unsigned int endregno = END_REGNO (reg);
11341 reg_stat_type *rsp;
11343 /* If VALUE contains REG and we have a previous value for REG, substitute
11344 the previous value. */
11345 if (value && insn && reg_overlap_mentioned_p (reg, value))
11349 /* Set things up so get_last_value is allowed to see anything set up to
11351 subst_low_luid = DF_INSN_LUID (insn);
11352 tem = get_last_value (reg);
11354 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11355 it isn't going to be useful and will take a lot of time to process,
11356 so just use the CLOBBER. */
11360 if (ARITHMETIC_P (tem)
11361 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11362 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11363 tem = XEXP (tem, 0);
11364 else if (count_occurrences (value, reg, 1) >= 2)
11366 /* If there are two or more occurrences of REG in VALUE,
11367 prevent the value from growing too much. */
11368 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11369 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11372 value = replace_rtx (copy_rtx (value), reg, tem);
11376 /* For each register modified, show we don't know its value, that
11377 we don't know about its bitwise content, that its value has been
11378 updated, and that we don't know the location of the death of the
11380 for (i = regno; i < endregno; i++)
11382 rsp = VEC_index (reg_stat_type, reg_stat, i);
11385 rsp->last_set = insn;
11387 rsp->last_set_value = 0;
11388 rsp->last_set_mode = 0;
11389 rsp->last_set_nonzero_bits = 0;
11390 rsp->last_set_sign_bit_copies = 0;
11391 rsp->last_death = 0;
11392 rsp->truncated_to_mode = 0;
11395 /* Mark registers that are being referenced in this value. */
11397 update_table_tick (value);
11399 /* Now update the status of each register being set.
11400 If someone is using this register in this block, set this register
11401 to invalid since we will get confused between the two lives in this
11402 basic block. This makes using this register always invalid. In cse, we
11403 scan the table to invalidate all entries using this register, but this
11404 is too much work for us. */
11406 for (i = regno; i < endregno; i++)
11408 rsp = VEC_index (reg_stat_type, reg_stat, i);
11409 rsp->last_set_label = label_tick;
11411 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11412 rsp->last_set_invalid = 1;
11414 rsp->last_set_invalid = 0;
11417 /* The value being assigned might refer to X (like in "x++;"). In that
11418 case, we must replace it with (clobber (const_int 0)) to prevent
11420 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11421 if (value && ! get_last_value_validate (&value, insn,
11422 rsp->last_set_label, 0))
11424 value = copy_rtx (value);
11425 if (! get_last_value_validate (&value, insn,
11426 rsp->last_set_label, 1))
11430 /* For the main register being modified, update the value, the mode, the
11431 nonzero bits, and the number of sign bit copies. */
11433 rsp->last_set_value = value;
11437 enum machine_mode mode = GET_MODE (reg);
11438 subst_low_luid = DF_INSN_LUID (insn);
11439 rsp->last_set_mode = mode;
11440 if (GET_MODE_CLASS (mode) == MODE_INT
11441 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11442 mode = nonzero_bits_mode;
11443 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11444 rsp->last_set_sign_bit_copies
11445 = num_sign_bit_copies (value, GET_MODE (reg));
11449 /* Called via note_stores from record_dead_and_set_regs to handle one
11450 SET or CLOBBER in an insn. DATA is the instruction in which the
11451 set is occurring. */
11454 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11456 rtx record_dead_insn = (rtx) data;
11458 if (GET_CODE (dest) == SUBREG)
11459 dest = SUBREG_REG (dest);
11461 if (!record_dead_insn)
11464 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11470 /* If we are setting the whole register, we know its value. Otherwise
11471 show that we don't know the value. We can handle SUBREG in
11473 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11474 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11475 else if (GET_CODE (setter) == SET
11476 && GET_CODE (SET_DEST (setter)) == SUBREG
11477 && SUBREG_REG (SET_DEST (setter)) == dest
11478 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11479 && subreg_lowpart_p (SET_DEST (setter)))
11480 record_value_for_reg (dest, record_dead_insn,
11481 gen_lowpart (GET_MODE (dest),
11482 SET_SRC (setter)));
11484 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11486 else if (MEM_P (dest)
11487 /* Ignore pushes, they clobber nothing. */
11488 && ! push_operand (dest, GET_MODE (dest)))
11489 mem_last_set = DF_INSN_LUID (record_dead_insn);
11492 /* Update the records of when each REG was most recently set or killed
11493 for the things done by INSN. This is the last thing done in processing
11494 INSN in the combiner loop.
11496 We update reg_stat[], in particular fields last_set, last_set_value,
11497 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11498 last_death, and also the similar information mem_last_set (which insn
11499 most recently modified memory) and last_call_luid (which insn was the
11500 most recent subroutine call). */
11503 record_dead_and_set_regs (rtx insn)
11508 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11510 if (REG_NOTE_KIND (link) == REG_DEAD
11511 && REG_P (XEXP (link, 0)))
11513 unsigned int regno = REGNO (XEXP (link, 0));
11514 unsigned int endregno = END_REGNO (XEXP (link, 0));
11516 for (i = regno; i < endregno; i++)
11518 reg_stat_type *rsp;
11520 rsp = VEC_index (reg_stat_type, reg_stat, i);
11521 rsp->last_death = insn;
11524 else if (REG_NOTE_KIND (link) == REG_INC)
11525 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11530 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11531 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11533 reg_stat_type *rsp;
11535 rsp = VEC_index (reg_stat_type, reg_stat, i);
11536 rsp->last_set_invalid = 1;
11537 rsp->last_set = insn;
11538 rsp->last_set_value = 0;
11539 rsp->last_set_mode = 0;
11540 rsp->last_set_nonzero_bits = 0;
11541 rsp->last_set_sign_bit_copies = 0;
11542 rsp->last_death = 0;
11543 rsp->truncated_to_mode = 0;
11546 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11548 /* We can't combine into a call pattern. Remember, though, that
11549 the return value register is set at this LUID. We could
11550 still replace a register with the return value from the
11551 wrong subroutine call! */
11552 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11555 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11558 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11559 register present in the SUBREG, so for each such SUBREG go back and
11560 adjust nonzero and sign bit information of the registers that are
11561 known to have some zero/sign bits set.
11563 This is needed because when combine blows the SUBREGs away, the
11564 information on zero/sign bits is lost and further combines can be
11565 missed because of that. */
11568 record_promoted_value (rtx insn, rtx subreg)
11571 unsigned int regno = REGNO (SUBREG_REG (subreg));
11572 enum machine_mode mode = GET_MODE (subreg);
11574 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11577 for (links = LOG_LINKS (insn); links;)
11579 reg_stat_type *rsp;
11581 insn = XEXP (links, 0);
11582 set = single_set (insn);
11584 if (! set || !REG_P (SET_DEST (set))
11585 || REGNO (SET_DEST (set)) != regno
11586 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11588 links = XEXP (links, 1);
11592 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11593 if (rsp->last_set == insn)
11595 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11596 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11599 if (REG_P (SET_SRC (set)))
11601 regno = REGNO (SET_SRC (set));
11602 links = LOG_LINKS (insn);
11609 /* Check if X, a register, is known to contain a value already
11610 truncated to MODE. In this case we can use a subreg to refer to
11611 the truncated value even though in the generic case we would need
11612 an explicit truncation. */
11615 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11617 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11618 enum machine_mode truncated = rsp->truncated_to_mode;
11621 || rsp->truncation_label < label_tick_ebb_start)
11623 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11625 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11626 GET_MODE_BITSIZE (truncated)))
11631 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11632 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11633 might be able to turn a truncate into a subreg using this information.
11634 Return -1 if traversing *P is complete or 0 otherwise. */
11637 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11640 enum machine_mode truncated_mode;
11641 reg_stat_type *rsp;
11643 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11645 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11646 truncated_mode = GET_MODE (x);
11648 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11651 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11652 GET_MODE_BITSIZE (original_mode)))
11655 x = SUBREG_REG (x);
11657 /* ??? For hard-regs we now record everything. We might be able to
11658 optimize this using last_set_mode. */
11659 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11660 truncated_mode = GET_MODE (x);
11664 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11665 if (rsp->truncated_to_mode == 0
11666 || rsp->truncation_label < label_tick_ebb_start
11667 || (GET_MODE_SIZE (truncated_mode)
11668 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11670 rsp->truncated_to_mode = truncated_mode;
11671 rsp->truncation_label = label_tick;
11677 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11678 the modes they are used in. This can help truning TRUNCATEs into
11682 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11684 for_each_rtx (x, record_truncated_value, NULL);
11687 /* Scan X for promoted SUBREGs. For each one found,
11688 note what it implies to the registers used in it. */
11691 check_promoted_subreg (rtx insn, rtx x)
11693 if (GET_CODE (x) == SUBREG
11694 && SUBREG_PROMOTED_VAR_P (x)
11695 && REG_P (SUBREG_REG (x)))
11696 record_promoted_value (insn, x);
11699 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11702 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11706 check_promoted_subreg (insn, XEXP (x, i));
11710 if (XVEC (x, i) != 0)
11711 for (j = 0; j < XVECLEN (x, i); j++)
11712 check_promoted_subreg (insn, XVECEXP (x, i, j));
11718 /* Utility routine for the following function. Verify that all the registers
11719 mentioned in *LOC are valid when *LOC was part of a value set when
11720 label_tick == TICK. Return 0 if some are not.
11722 If REPLACE is nonzero, replace the invalid reference with
11723 (clobber (const_int 0)) and return 1. This replacement is useful because
11724 we often can get useful information about the form of a value (e.g., if
11725 it was produced by a shift that always produces -1 or 0) even though
11726 we don't know exactly what registers it was produced from. */
11729 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11732 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11733 int len = GET_RTX_LENGTH (GET_CODE (x));
11738 unsigned int regno = REGNO (x);
11739 unsigned int endregno = END_REGNO (x);
11742 for (j = regno; j < endregno; j++)
11744 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11745 if (rsp->last_set_invalid
11746 /* If this is a pseudo-register that was only set once and not
11747 live at the beginning of the function, it is always valid. */
11748 || (! (regno >= FIRST_PSEUDO_REGISTER
11749 && REG_N_SETS (regno) == 1
11750 && (!REGNO_REG_SET_P
11751 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11752 && rsp->last_set_label > tick))
11755 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11762 /* If this is a memory reference, make sure that there were
11763 no stores after it that might have clobbered the value. We don't
11764 have alias info, so we assume any store invalidates it. */
11765 else if (MEM_P (x) && !MEM_READONLY_P (x)
11766 && DF_INSN_LUID (insn) <= mem_last_set)
11769 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11773 for (i = 0; i < len; i++)
11777 /* Check for identical subexpressions. If x contains
11778 identical subexpression we only have to traverse one of
11780 if (i == 1 && ARITHMETIC_P (x))
11782 /* Note that at this point x0 has already been checked
11783 and found valid. */
11784 rtx x0 = XEXP (x, 0);
11785 rtx x1 = XEXP (x, 1);
11787 /* If x0 and x1 are identical then x is also valid. */
11791 /* If x1 is identical to a subexpression of x0 then
11792 while checking x0, x1 has already been checked. Thus
11793 it is valid and so as x. */
11794 if (ARITHMETIC_P (x0)
11795 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11798 /* If x0 is identical to a subexpression of x1 then x is
11799 valid iff the rest of x1 is valid. */
11800 if (ARITHMETIC_P (x1)
11801 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11803 get_last_value_validate (&XEXP (x1,
11804 x0 == XEXP (x1, 0) ? 1 : 0),
11805 insn, tick, replace);
11808 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11812 else if (fmt[i] == 'E')
11813 for (j = 0; j < XVECLEN (x, i); j++)
11814 if (get_last_value_validate (&XVECEXP (x, i, j),
11815 insn, tick, replace) == 0)
11819 /* If we haven't found a reason for it to be invalid, it is valid. */
11823 /* Get the last value assigned to X, if known. Some registers
11824 in the value may be replaced with (clobber (const_int 0)) if their value
11825 is known longer known reliably. */
11828 get_last_value (const_rtx x)
11830 unsigned int regno;
11832 reg_stat_type *rsp;
11834 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11835 then convert it to the desired mode. If this is a paradoxical SUBREG,
11836 we cannot predict what values the "extra" bits might have. */
11837 if (GET_CODE (x) == SUBREG
11838 && subreg_lowpart_p (x)
11839 && (GET_MODE_SIZE (GET_MODE (x))
11840 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11841 && (value = get_last_value (SUBREG_REG (x))) != 0)
11842 return gen_lowpart (GET_MODE (x), value);
11848 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11849 value = rsp->last_set_value;
11851 /* If we don't have a value, or if it isn't for this basic block and
11852 it's either a hard register, set more than once, or it's a live
11853 at the beginning of the function, return 0.
11855 Because if it's not live at the beginning of the function then the reg
11856 is always set before being used (is never used without being set).
11857 And, if it's set only once, and it's always set before use, then all
11858 uses must have the same last value, even if it's not from this basic
11862 || (rsp->last_set_label < label_tick_ebb_start
11863 && (regno < FIRST_PSEUDO_REGISTER
11864 || REG_N_SETS (regno) != 1
11866 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11869 /* If the value was set in a later insn than the ones we are processing,
11870 we can't use it even if the register was only set once. */
11871 if (rsp->last_set_label == label_tick
11872 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11875 /* If the value has all its registers valid, return it. */
11876 if (get_last_value_validate (&value, rsp->last_set,
11877 rsp->last_set_label, 0))
11880 /* Otherwise, make a copy and replace any invalid register with
11881 (clobber (const_int 0)). If that fails for some reason, return 0. */
11883 value = copy_rtx (value);
11884 if (get_last_value_validate (&value, rsp->last_set,
11885 rsp->last_set_label, 1))
11891 /* Return nonzero if expression X refers to a REG or to memory
11892 that is set in an instruction more recent than FROM_LUID. */
11895 use_crosses_set_p (const_rtx x, int from_luid)
11899 enum rtx_code code = GET_CODE (x);
11903 unsigned int regno = REGNO (x);
11904 unsigned endreg = END_REGNO (x);
11906 #ifdef PUSH_ROUNDING
11907 /* Don't allow uses of the stack pointer to be moved,
11908 because we don't know whether the move crosses a push insn. */
11909 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11912 for (; regno < endreg; regno++)
11914 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11916 && rsp->last_set_label == label_tick
11917 && DF_INSN_LUID (rsp->last_set) > from_luid)
11923 if (code == MEM && mem_last_set > from_luid)
11926 fmt = GET_RTX_FORMAT (code);
11928 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11933 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11934 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11937 else if (fmt[i] == 'e'
11938 && use_crosses_set_p (XEXP (x, i), from_luid))
11944 /* Define three variables used for communication between the following
11947 static unsigned int reg_dead_regno, reg_dead_endregno;
11948 static int reg_dead_flag;
11950 /* Function called via note_stores from reg_dead_at_p.
11952 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11953 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11956 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11958 unsigned int regno, endregno;
11963 regno = REGNO (dest);
11964 endregno = END_REGNO (dest);
11965 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11966 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11969 /* Return nonzero if REG is known to be dead at INSN.
11971 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11972 referencing REG, it is dead. If we hit a SET referencing REG, it is
11973 live. Otherwise, see if it is live or dead at the start of the basic
11974 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11975 must be assumed to be always live. */
11978 reg_dead_at_p (rtx reg, rtx insn)
11983 /* Set variables for reg_dead_at_p_1. */
11984 reg_dead_regno = REGNO (reg);
11985 reg_dead_endregno = END_REGNO (reg);
11989 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11990 we allow the machine description to decide whether use-and-clobber
11991 patterns are OK. */
11992 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11994 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11995 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11999 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12000 beginning of function. */
12001 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
12002 insn = prev_nonnote_insn (insn))
12004 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12006 return reg_dead_flag == 1 ? 1 : 0;
12008 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12012 /* Get the basic block that we were in. */
12014 block = ENTRY_BLOCK_PTR->next_bb;
12017 FOR_EACH_BB (block)
12018 if (insn == BB_HEAD (block))
12021 if (block == EXIT_BLOCK_PTR)
12025 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12026 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12032 /* Note hard registers in X that are used. */
12035 mark_used_regs_combine (rtx x)
12037 RTX_CODE code = GET_CODE (x);
12038 unsigned int regno;
12051 case ADDR_DIFF_VEC:
12054 /* CC0 must die in the insn after it is set, so we don't need to take
12055 special note of it here. */
12061 /* If we are clobbering a MEM, mark any hard registers inside the
12062 address as used. */
12063 if (MEM_P (XEXP (x, 0)))
12064 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12069 /* A hard reg in a wide mode may really be multiple registers.
12070 If so, mark all of them just like the first. */
12071 if (regno < FIRST_PSEUDO_REGISTER)
12073 /* None of this applies to the stack, frame or arg pointers. */
12074 if (regno == STACK_POINTER_REGNUM
12075 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12076 || regno == HARD_FRAME_POINTER_REGNUM
12078 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12079 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12081 || regno == FRAME_POINTER_REGNUM)
12084 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12090 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12092 rtx testreg = SET_DEST (x);
12094 while (GET_CODE (testreg) == SUBREG
12095 || GET_CODE (testreg) == ZERO_EXTRACT
12096 || GET_CODE (testreg) == STRICT_LOW_PART)
12097 testreg = XEXP (testreg, 0);
12099 if (MEM_P (testreg))
12100 mark_used_regs_combine (XEXP (testreg, 0));
12102 mark_used_regs_combine (SET_SRC (x));
12110 /* Recursively scan the operands of this expression. */
12113 const char *fmt = GET_RTX_FORMAT (code);
12115 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12118 mark_used_regs_combine (XEXP (x, i));
12119 else if (fmt[i] == 'E')
12123 for (j = 0; j < XVECLEN (x, i); j++)
12124 mark_used_regs_combine (XVECEXP (x, i, j));
12130 /* Remove register number REGNO from the dead registers list of INSN.
12132 Return the note used to record the death, if there was one. */
12135 remove_death (unsigned int regno, rtx insn)
12137 rtx note = find_regno_note (insn, REG_DEAD, regno);
12140 remove_note (insn, note);
12145 /* For each register (hardware or pseudo) used within expression X, if its
12146 death is in an instruction with luid between FROM_LUID (inclusive) and
12147 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12148 list headed by PNOTES.
12150 That said, don't move registers killed by maybe_kill_insn.
12152 This is done when X is being merged by combination into TO_INSN. These
12153 notes will then be distributed as needed. */
12156 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12161 enum rtx_code code = GET_CODE (x);
12165 unsigned int regno = REGNO (x);
12166 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12168 /* Don't move the register if it gets killed in between from and to. */
12169 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12170 && ! reg_referenced_p (x, maybe_kill_insn))
12174 && DF_INSN_LUID (where_dead) >= from_luid
12175 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12177 rtx note = remove_death (regno, where_dead);
12179 /* It is possible for the call above to return 0. This can occur
12180 when last_death points to I2 or I1 that we combined with.
12181 In that case make a new note.
12183 We must also check for the case where X is a hard register
12184 and NOTE is a death note for a range of hard registers
12185 including X. In that case, we must put REG_DEAD notes for
12186 the remaining registers in place of NOTE. */
12188 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12189 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12190 > GET_MODE_SIZE (GET_MODE (x))))
12192 unsigned int deadregno = REGNO (XEXP (note, 0));
12193 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12194 unsigned int ourend = END_HARD_REGNO (x);
12197 for (i = deadregno; i < deadend; i++)
12198 if (i < regno || i >= ourend)
12199 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12202 /* If we didn't find any note, or if we found a REG_DEAD note that
12203 covers only part of the given reg, and we have a multi-reg hard
12204 register, then to be safe we must check for REG_DEAD notes
12205 for each register other than the first. They could have
12206 their own REG_DEAD notes lying around. */
12207 else if ((note == 0
12209 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12210 < GET_MODE_SIZE (GET_MODE (x)))))
12211 && regno < FIRST_PSEUDO_REGISTER
12212 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12214 unsigned int ourend = END_HARD_REGNO (x);
12215 unsigned int i, offset;
12219 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12223 for (i = regno + offset; i < ourend; i++)
12224 move_deaths (regno_reg_rtx[i],
12225 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12228 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12230 XEXP (note, 1) = *pnotes;
12234 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12240 else if (GET_CODE (x) == SET)
12242 rtx dest = SET_DEST (x);
12244 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12246 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12247 that accesses one word of a multi-word item, some
12248 piece of everything register in the expression is used by
12249 this insn, so remove any old death. */
12250 /* ??? So why do we test for equality of the sizes? */
12252 if (GET_CODE (dest) == ZERO_EXTRACT
12253 || GET_CODE (dest) == STRICT_LOW_PART
12254 || (GET_CODE (dest) == SUBREG
12255 && (((GET_MODE_SIZE (GET_MODE (dest))
12256 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12257 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12258 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12260 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12264 /* If this is some other SUBREG, we know it replaces the entire
12265 value, so use that as the destination. */
12266 if (GET_CODE (dest) == SUBREG)
12267 dest = SUBREG_REG (dest);
12269 /* If this is a MEM, adjust deaths of anything used in the address.
12270 For a REG (the only other possibility), the entire value is
12271 being replaced so the old value is not used in this insn. */
12274 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12279 else if (GET_CODE (x) == CLOBBER)
12282 len = GET_RTX_LENGTH (code);
12283 fmt = GET_RTX_FORMAT (code);
12285 for (i = 0; i < len; i++)
12290 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12291 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12294 else if (fmt[i] == 'e')
12295 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12299 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12300 pattern of an insn. X must be a REG. */
12303 reg_bitfield_target_p (rtx x, rtx body)
12307 if (GET_CODE (body) == SET)
12309 rtx dest = SET_DEST (body);
12311 unsigned int regno, tregno, endregno, endtregno;
12313 if (GET_CODE (dest) == ZERO_EXTRACT)
12314 target = XEXP (dest, 0);
12315 else if (GET_CODE (dest) == STRICT_LOW_PART)
12316 target = SUBREG_REG (XEXP (dest, 0));
12320 if (GET_CODE (target) == SUBREG)
12321 target = SUBREG_REG (target);
12323 if (!REG_P (target))
12326 tregno = REGNO (target), regno = REGNO (x);
12327 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12328 return target == x;
12330 endtregno = end_hard_regno (GET_MODE (target), tregno);
12331 endregno = end_hard_regno (GET_MODE (x), regno);
12333 return endregno > tregno && regno < endtregno;
12336 else if (GET_CODE (body) == PARALLEL)
12337 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12338 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12344 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12345 as appropriate. I3 and I2 are the insns resulting from the combination
12346 insns including FROM (I2 may be zero).
12348 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12349 not need REG_DEAD notes because they are being substituted for. This
12350 saves searching in the most common cases.
12352 Each note in the list is either ignored or placed on some insns, depending
12353 on the type of note. */
12356 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12359 rtx note, next_note;
12362 for (note = notes; note; note = next_note)
12364 rtx place = 0, place2 = 0;
12366 next_note = XEXP (note, 1);
12367 switch (REG_NOTE_KIND (note))
12371 /* Doesn't matter much where we put this, as long as it's somewhere.
12372 It is preferable to keep these notes on branches, which is most
12373 likely to be i3. */
12377 case REG_VALUE_PROFILE:
12378 /* Just get rid of this note, as it is unused later anyway. */
12381 case REG_NON_LOCAL_GOTO:
12386 gcc_assert (i2 && JUMP_P (i2));
12391 case REG_EH_REGION:
12392 /* These notes must remain with the call or trapping instruction. */
12395 else if (i2 && CALL_P (i2))
12399 gcc_assert (flag_non_call_exceptions);
12400 if (may_trap_p (i3))
12402 else if (i2 && may_trap_p (i2))
12404 /* ??? Otherwise assume we've combined things such that we
12405 can now prove that the instructions can't trap. Drop the
12406 note in this case. */
12412 /* These notes must remain with the call. It should not be
12413 possible for both I2 and I3 to be a call. */
12418 gcc_assert (i2 && CALL_P (i2));
12424 /* Any clobbers for i3 may still exist, and so we must process
12425 REG_UNUSED notes from that insn.
12427 Any clobbers from i2 or i1 can only exist if they were added by
12428 recog_for_combine. In that case, recog_for_combine created the
12429 necessary REG_UNUSED notes. Trying to keep any original
12430 REG_UNUSED notes from these insns can cause incorrect output
12431 if it is for the same register as the original i3 dest.
12432 In that case, we will notice that the register is set in i3,
12433 and then add a REG_UNUSED note for the destination of i3, which
12434 is wrong. However, it is possible to have REG_UNUSED notes from
12435 i2 or i1 for register which were both used and clobbered, so
12436 we keep notes from i2 or i1 if they will turn into REG_DEAD
12439 /* If this register is set or clobbered in I3, put the note there
12440 unless there is one already. */
12441 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12443 if (from_insn != i3)
12446 if (! (REG_P (XEXP (note, 0))
12447 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12448 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12451 /* Otherwise, if this register is used by I3, then this register
12452 now dies here, so we must put a REG_DEAD note here unless there
12454 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12455 && ! (REG_P (XEXP (note, 0))
12456 ? find_regno_note (i3, REG_DEAD,
12457 REGNO (XEXP (note, 0)))
12458 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12460 PUT_REG_NOTE_KIND (note, REG_DEAD);
12468 /* These notes say something about results of an insn. We can
12469 only support them if they used to be on I3 in which case they
12470 remain on I3. Otherwise they are ignored.
12472 If the note refers to an expression that is not a constant, we
12473 must also ignore the note since we cannot tell whether the
12474 equivalence is still true. It might be possible to do
12475 slightly better than this (we only have a problem if I2DEST
12476 or I1DEST is present in the expression), but it doesn't
12477 seem worth the trouble. */
12479 if (from_insn == i3
12480 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12485 /* These notes say something about how a register is used. They must
12486 be present on any use of the register in I2 or I3. */
12487 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12490 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12499 case REG_LABEL_TARGET:
12500 case REG_LABEL_OPERAND:
12501 /* This can show up in several ways -- either directly in the
12502 pattern, or hidden off in the constant pool with (or without?)
12503 a REG_EQUAL note. */
12504 /* ??? Ignore the without-reg_equal-note problem for now. */
12505 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12506 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12507 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12508 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12512 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12513 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12514 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12515 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12523 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12524 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12526 if (place && JUMP_P (place)
12527 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12528 && (JUMP_LABEL (place) == NULL
12529 || JUMP_LABEL (place) == XEXP (note, 0)))
12531 rtx label = JUMP_LABEL (place);
12534 JUMP_LABEL (place) = XEXP (note, 0);
12535 else if (LABEL_P (label))
12536 LABEL_NUSES (label)--;
12539 if (place2 && JUMP_P (place2)
12540 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12541 && (JUMP_LABEL (place2) == NULL
12542 || JUMP_LABEL (place2) == XEXP (note, 0)))
12544 rtx label = JUMP_LABEL (place2);
12547 JUMP_LABEL (place2) = XEXP (note, 0);
12548 else if (LABEL_P (label))
12549 LABEL_NUSES (label)--;
12555 /* This note says something about the value of a register prior
12556 to the execution of an insn. It is too much trouble to see
12557 if the note is still correct in all situations. It is better
12558 to simply delete it. */
12562 /* If we replaced the right hand side of FROM_INSN with a
12563 REG_EQUAL note, the original use of the dying register
12564 will not have been combined into I3 and I2. In such cases,
12565 FROM_INSN is guaranteed to be the first of the combined
12566 instructions, so we simply need to search back before
12567 FROM_INSN for the previous use or set of this register,
12568 then alter the notes there appropriately.
12570 If the register is used as an input in I3, it dies there.
12571 Similarly for I2, if it is nonzero and adjacent to I3.
12573 If the register is not used as an input in either I3 or I2
12574 and it is not one of the registers we were supposed to eliminate,
12575 there are two possibilities. We might have a non-adjacent I2
12576 or we might have somehow eliminated an additional register
12577 from a computation. For example, we might have had A & B where
12578 we discover that B will always be zero. In this case we will
12579 eliminate the reference to A.
12581 In both cases, we must search to see if we can find a previous
12582 use of A and put the death note there. */
12585 && from_insn == i2mod
12586 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12591 && CALL_P (from_insn)
12592 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12594 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12596 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12597 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12599 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12601 && reg_overlap_mentioned_p (XEXP (note, 0),
12603 || rtx_equal_p (XEXP (note, 0), elim_i1))
12610 basic_block bb = this_basic_block;
12612 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12614 if (! INSN_P (tem))
12616 if (tem == BB_HEAD (bb))
12621 /* If the register is being set at TEM, see if that is all
12622 TEM is doing. If so, delete TEM. Otherwise, make this
12623 into a REG_UNUSED note instead. Don't delete sets to
12624 global register vars. */
12625 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12626 || !global_regs[REGNO (XEXP (note, 0))])
12627 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12629 rtx set = single_set (tem);
12630 rtx inner_dest = 0;
12632 rtx cc0_setter = NULL_RTX;
12636 for (inner_dest = SET_DEST (set);
12637 (GET_CODE (inner_dest) == STRICT_LOW_PART
12638 || GET_CODE (inner_dest) == SUBREG
12639 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12640 inner_dest = XEXP (inner_dest, 0))
12643 /* Verify that it was the set, and not a clobber that
12644 modified the register.
12646 CC0 targets must be careful to maintain setter/user
12647 pairs. If we cannot delete the setter due to side
12648 effects, mark the user with an UNUSED note instead
12651 if (set != 0 && ! side_effects_p (SET_SRC (set))
12652 && rtx_equal_p (XEXP (note, 0), inner_dest)
12654 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12655 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12656 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12660 /* Move the notes and links of TEM elsewhere.
12661 This might delete other dead insns recursively.
12662 First set the pattern to something that won't use
12664 rtx old_notes = REG_NOTES (tem);
12666 PATTERN (tem) = pc_rtx;
12667 REG_NOTES (tem) = NULL;
12669 distribute_notes (old_notes, tem, tem, NULL_RTX,
12670 NULL_RTX, NULL_RTX);
12671 distribute_links (LOG_LINKS (tem));
12673 SET_INSN_DELETED (tem);
12678 /* Delete the setter too. */
12681 PATTERN (cc0_setter) = pc_rtx;
12682 old_notes = REG_NOTES (cc0_setter);
12683 REG_NOTES (cc0_setter) = NULL;
12685 distribute_notes (old_notes, cc0_setter,
12686 cc0_setter, NULL_RTX,
12687 NULL_RTX, NULL_RTX);
12688 distribute_links (LOG_LINKS (cc0_setter));
12690 SET_INSN_DELETED (cc0_setter);
12691 if (cc0_setter == i2)
12698 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12700 /* If there isn't already a REG_UNUSED note, put one
12701 here. Do not place a REG_DEAD note, even if
12702 the register is also used here; that would not
12703 match the algorithm used in lifetime analysis
12704 and can cause the consistency check in the
12705 scheduler to fail. */
12706 if (! find_regno_note (tem, REG_UNUSED,
12707 REGNO (XEXP (note, 0))))
12712 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12714 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12718 /* If we are doing a 3->2 combination, and we have a
12719 register which formerly died in i3 and was not used
12720 by i2, which now no longer dies in i3 and is used in
12721 i2 but does not die in i2, and place is between i2
12722 and i3, then we may need to move a link from place to
12724 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12726 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12727 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12729 rtx links = LOG_LINKS (place);
12730 LOG_LINKS (place) = 0;
12731 distribute_links (links);
12736 if (tem == BB_HEAD (bb))
12742 /* If the register is set or already dead at PLACE, we needn't do
12743 anything with this note if it is still a REG_DEAD note.
12744 We check here if it is set at all, not if is it totally replaced,
12745 which is what `dead_or_set_p' checks, so also check for it being
12748 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12750 unsigned int regno = REGNO (XEXP (note, 0));
12751 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12753 if (dead_or_set_p (place, XEXP (note, 0))
12754 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12756 /* Unless the register previously died in PLACE, clear
12757 last_death. [I no longer understand why this is
12759 if (rsp->last_death != place)
12760 rsp->last_death = 0;
12764 rsp->last_death = place;
12766 /* If this is a death note for a hard reg that is occupying
12767 multiple registers, ensure that we are still using all
12768 parts of the object. If we find a piece of the object
12769 that is unused, we must arrange for an appropriate REG_DEAD
12770 note to be added for it. However, we can't just emit a USE
12771 and tag the note to it, since the register might actually
12772 be dead; so we recourse, and the recursive call then finds
12773 the previous insn that used this register. */
12775 if (place && regno < FIRST_PSEUDO_REGISTER
12776 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12778 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12782 for (i = regno; i < endregno; i++)
12783 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12784 && ! find_regno_fusage (place, USE, i))
12785 || dead_or_set_regno_p (place, i))
12790 /* Put only REG_DEAD notes for pieces that are
12791 not already dead or set. */
12793 for (i = regno; i < endregno;
12794 i += hard_regno_nregs[i][reg_raw_mode[i]])
12796 rtx piece = regno_reg_rtx[i];
12797 basic_block bb = this_basic_block;
12799 if (! dead_or_set_p (place, piece)
12800 && ! reg_bitfield_target_p (piece,
12804 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12806 distribute_notes (new_note, place, place,
12807 NULL_RTX, NULL_RTX, NULL_RTX);
12809 else if (! refers_to_regno_p (i, i + 1,
12810 PATTERN (place), 0)
12811 && ! find_regno_fusage (place, USE, i))
12812 for (tem = PREV_INSN (place); ;
12813 tem = PREV_INSN (tem))
12815 if (! INSN_P (tem))
12817 if (tem == BB_HEAD (bb))
12821 if (dead_or_set_p (tem, piece)
12822 || reg_bitfield_target_p (piece,
12825 add_reg_note (tem, REG_UNUSED, piece);
12839 /* Any other notes should not be present at this point in the
12841 gcc_unreachable ();
12846 XEXP (note, 1) = REG_NOTES (place);
12847 REG_NOTES (place) = note;
12852 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12853 XEXP (note, 0), REG_NOTES (place2));
12857 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12858 I3, I2, and I1 to new locations. This is also called to add a link
12859 pointing at I3 when I3's destination is changed. */
12862 distribute_links (rtx links)
12864 rtx link, next_link;
12866 for (link = links; link; link = next_link)
12872 next_link = XEXP (link, 1);
12874 /* If the insn that this link points to is a NOTE or isn't a single
12875 set, ignore it. In the latter case, it isn't clear what we
12876 can do other than ignore the link, since we can't tell which
12877 register it was for. Such links wouldn't be used by combine
12880 It is not possible for the destination of the target of the link to
12881 have been changed by combine. The only potential of this is if we
12882 replace I3, I2, and I1 by I3 and I2. But in that case the
12883 destination of I2 also remains unchanged. */
12885 if (NOTE_P (XEXP (link, 0))
12886 || (set = single_set (XEXP (link, 0))) == 0)
12889 reg = SET_DEST (set);
12890 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12891 || GET_CODE (reg) == STRICT_LOW_PART)
12892 reg = XEXP (reg, 0);
12894 /* A LOG_LINK is defined as being placed on the first insn that uses
12895 a register and points to the insn that sets the register. Start
12896 searching at the next insn after the target of the link and stop
12897 when we reach a set of the register or the end of the basic block.
12899 Note that this correctly handles the link that used to point from
12900 I3 to I2. Also note that not much searching is typically done here
12901 since most links don't point very far away. */
12903 for (insn = NEXT_INSN (XEXP (link, 0));
12904 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12905 || BB_HEAD (this_basic_block->next_bb) != insn));
12906 insn = NEXT_INSN (insn))
12907 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12909 if (reg_referenced_p (reg, PATTERN (insn)))
12913 else if (CALL_P (insn)
12914 && find_reg_fusage (insn, USE, reg))
12919 else if (INSN_P (insn) && reg_set_p (reg, insn))
12922 /* If we found a place to put the link, place it there unless there
12923 is already a link to the same insn as LINK at that point. */
12929 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12930 if (XEXP (link2, 0) == XEXP (link, 0))
12935 XEXP (link, 1) = LOG_LINKS (place);
12936 LOG_LINKS (place) = link;
12938 /* Set added_links_insn to the earliest insn we added a
12940 if (added_links_insn == 0
12941 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12942 added_links_insn = place;
12948 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12949 Check whether the expression pointer to by LOC is a register or
12950 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12951 Otherwise return zero. */
12954 unmentioned_reg_p_1 (rtx *loc, void *expr)
12959 && (REG_P (x) || MEM_P (x))
12960 && ! reg_mentioned_p (x, (rtx) expr))
12965 /* Check for any register or memory mentioned in EQUIV that is not
12966 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12967 of EXPR where some registers may have been replaced by constants. */
12970 unmentioned_reg_p (rtx equiv, rtx expr)
12972 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12976 dump_combine_stats (FILE *file)
12980 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12981 combine_attempts, combine_merges, combine_extras, combine_successes);
12985 dump_combine_total_stats (FILE *file)
12989 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12990 total_attempts, total_merges, total_extras, total_successes);
12994 gate_handle_combine (void)
12996 return (optimize > 0);
12999 /* Try combining insns through substitution. */
13000 static unsigned int
13001 rest_of_handle_combine (void)
13003 int rebuild_jump_labels_after_combine;
13005 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13006 df_note_add_problem ();
13009 regstat_init_n_sets_and_refs ();
13011 rebuild_jump_labels_after_combine
13012 = combine_instructions (get_insns (), max_reg_num ());
13014 /* Combining insns may have turned an indirect jump into a
13015 direct jump. Rebuild the JUMP_LABEL fields of jumping
13017 if (rebuild_jump_labels_after_combine)
13019 timevar_push (TV_JUMP);
13020 rebuild_jump_labels (get_insns ());
13022 timevar_pop (TV_JUMP);
13025 regstat_free_n_sets_and_refs ();
13029 struct rtl_opt_pass pass_combine =
13033 "combine", /* name */
13034 gate_handle_combine, /* gate */
13035 rest_of_handle_combine, /* execute */
13038 0, /* static_pass_number */
13039 TV_COMBINE, /* tv_id */
13040 0, /* properties_required */
13041 0, /* properties_provided */
13042 0, /* properties_destroyed */
13043 0, /* todo_flags_start */
13045 TODO_df_finish | TODO_verify_rtl_sharing |
13046 TODO_ggc_collect, /* todo_flags_finish */
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