sys/dev/disk/mps/mpi/mpi2_ioc.h

   1 /* $FreeBSD: src/sys/dev/mps/mpi/mpi2_ioc.h,v 1.1 2010/09/10 15:03:56 ken Exp $ */
   2 /*
   3  *  Copyright (c) 2000-2009 LSI Corporation.
   4  *
   5  *
   6  *           Name:  mpi2_ioc.h
   7  *          Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   8  *  Creation Date:  October 11, 2006
   9  *
  10  *  mpi2_ioc.h Version:  02.00.13
  11  *
  12  *  Version History
  13  *  ---------------
  14  *
  15  *  Date      Version   Description
  16  *  --------  --------  ------------------------------------------------------
  17  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  18  *  06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  19  *                      MaxTargets.
  20  *                      Added TotalImageSize field to FWDownload Request.
  21  *                      Added reserved words to FWUpload Request.
  22  *  06-26-07  02.00.02  Added IR Configuration Change List Event.
  23  *  08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  24  *                      request and replaced it with
  25  *                      ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  26  *                      Replaced the MinReplyQueueDepth field of the IOCFacts
  27  *                      reply with MaxReplyDescriptorPostQueueDepth.
  28  *                      Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  29  *                      depth for the Reply Descriptor Post Queue.
  30  *                      Added SASAddress field to Initiator Device Table
  31  *                      Overflow Event data.
  32  *  10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  33  *                      for SAS Initiator Device Status Change Event data.
  34  *                      Modified Reason Code defines for SAS Topology Change
  35  *                      List Event data, including adding a bit for PHY Vacant
  36  *                      status, and adding a mask for the Reason Code.
  37  *                      Added define for
  38  *                      MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  39  *                      Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  40  *  12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  41  *                      the IOCFacts Reply.
  42  *                      Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  43  *                      Moved MPI2_VERSION_UNION to mpi2.h.
  44  *                      Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  45  *                      instead of enables, and added SASBroadcastPrimitiveMasks
  46  *                      field.
  47  *                      Added Log Entry Added Event and related structure.
  48  *  02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  49  *                      Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  50  *                      Added MaxVolumes and MaxPersistentEntries fields to
  51  *                      IOCFacts reply.
  52  *                      Added ProtocalFlags and IOCCapabilities fields to
  53  *                      MPI2_FW_IMAGE_HEADER.
  54  *                      Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  55  *  03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  56  *                      a U16 (from a U32).
  57  *                      Removed extra 's' from EventMasks name.
  58  *  06-27-08  02.00.08  Fixed an offset in a comment.
  59  *  10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  60  *                      Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  61  *                      renamed MinReplyFrameSize to ReplyFrameSize.
  62  *                      Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  63  *                      Added two new RAIDOperation values for Integrated RAID
  64  *                      Operations Status Event data.
  65  *                      Added four new IR Configuration Change List Event data
  66  *                      ReasonCode values.
  67  *                      Added two new ReasonCode defines for SAS Device Status
  68  *                      Change Event data.
  69  *                      Added three new DiscoveryStatus bits for the SAS
  70  *                      Discovery event data.
  71  *                      Added Multiplexing Status Change bit to the PhyStatus
  72  *                      field of the SAS Topology Change List event data.
  73  *                      Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  74  *                      BootFlags are now product-specific.
  75  *                      Added defines for the indivdual signature bytes
  76  *                      for MPI2_INIT_IMAGE_FOOTER.
  77  *  01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  78  *                      Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  79  *                      define.
  80  *                      Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  81  *                      define.
  82  *                      Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  83  *  05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  84  *                      Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  85  *                      Added two new reason codes for SAS Device Status Change
  86  *                      Event.
  87  *                      Added new event: SAS PHY Counter.
  88  *  07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  89  *                      Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  90  *                      Added new product id family for 2208.
  91  *  10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  92  *                      Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  93  *                      Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  94  *                      Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  95  *                      Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
  96  *                      Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
  97  *                      Added Host Based Discovery Phy Event data.
  98  *                      Added defines for ProductID Product field
  99  *                      (MPI2_FW_HEADER_PID_).
 100  *                      Modified values for SAS ProductID Family
 101  *                      (MPI2_FW_HEADER_PID_FAMILY_).
 102  *  --------------------------------------------------------------------------
 103  */
 104
 105 #ifndef MPI2_IOC_H
 106 #define MPI2_IOC_H
 107
 108 /*****************************************************************************
 109 *
 110 *               IOC Messages
 111 *
 112 *****************************************************************************/
 113
 114 /****************************************************************************
 115 *  IOCInit message
 116 ****************************************************************************/
 117
 118 /* IOCInit Request message */
 119 typedef struct _MPI2_IOC_INIT_REQUEST
 120 {
 121     U8                      WhoInit;                        /* 0x00 */
 122     U8                      Reserved1;                      /* 0x01 */
 123     U8                      ChainOffset;                    /* 0x02 */
 124     U8                      Function;                       /* 0x03 */
 125     U16                     Reserved2;                      /* 0x04 */
 126     U8                      Reserved3;                      /* 0x06 */
 127     U8                      MsgFlags;                       /* 0x07 */
 128     U8                      VP_ID;                          /* 0x08 */
 129     U8                      VF_ID;                          /* 0x09 */
 130     U16                     Reserved4;                      /* 0x0A */
 131     U16                     MsgVersion;                     /* 0x0C */
 132     U16                     HeaderVersion;                  /* 0x0E */
 133     U32                     Reserved5;                      /* 0x10 */
 134     U16                     Reserved6;                      /* 0x14 */
 135     U8                      Reserved7;                      /* 0x16 */
 136     U8                      HostMSIxVectors;                /* 0x17 */
 137     U16                     Reserved8;                      /* 0x18 */
 138     U16                     SystemRequestFrameSize;         /* 0x1A */
 139     U16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
 140     U16                     ReplyFreeQueueDepth;            /* 0x1E */
 141     U32                     SenseBufferAddressHigh;         /* 0x20 */
 142     U32                     SystemReplyAddressHigh;         /* 0x24 */
 143     U64                     SystemRequestFrameBaseAddress;  /* 0x28 */
 144     U64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
 145     U64                     ReplyFreeQueueAddress;          /* 0x38 */
 146     U64                     TimeStamp;                      /* 0x40 */
 147 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 148   Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 149
 150 /* WhoInit values */
 151 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 152 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 153 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 154 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 155 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 156 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 157
 158 /* MsgVersion */
 159 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 160 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 161 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 162 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 163
 164 /* HeaderVersion */
 165 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 166 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 167 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 168 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 169
 170 /* minimum depth for the Reply Descriptor Post Queue */
 171 #define MPI2_RDPQ_DEPTH_MIN                     (16)
 172
 173
 174 /* IOCInit Reply message */
 175 typedef struct _MPI2_IOC_INIT_REPLY
 176 {
 177     U8                      WhoInit;                        /* 0x00 */
 178     U8                      Reserved1;                      /* 0x01 */
 179     U8                      MsgLength;                      /* 0x02 */
 180     U8                      Function;                       /* 0x03 */
 181     U16                     Reserved2;                      /* 0x04 */
 182     U8                      Reserved3;                      /* 0x06 */
 183     U8                      MsgFlags;                       /* 0x07 */
 184     U8                      VP_ID;                          /* 0x08 */
 185     U8                      VF_ID;                          /* 0x09 */
 186     U16                     Reserved4;                      /* 0x0A */
 187     U16                     Reserved5;                      /* 0x0C */
 188     U16                     IOCStatus;                      /* 0x0E */
 189     U32                     IOCLogInfo;                     /* 0x10 */
 190 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
 191   Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
 192
 193
 194 /****************************************************************************
 195 *  IOCFacts message
 196 ****************************************************************************/
 197
 198 /* IOCFacts Request message */
 199 typedef struct _MPI2_IOC_FACTS_REQUEST
 200 {
 201     U16                     Reserved1;                      /* 0x00 */
 202     U8                      ChainOffset;                    /* 0x02 */
 203     U8                      Function;                       /* 0x03 */
 204     U16                     Reserved2;                      /* 0x04 */
 205     U8                      Reserved3;                      /* 0x06 */
 206     U8                      MsgFlags;                       /* 0x07 */
 207     U8                      VP_ID;                          /* 0x08 */
 208     U8                      VF_ID;                          /* 0x09 */
 209     U16                     Reserved4;                      /* 0x0A */
 210 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
 211   Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
 212
 213
 214 /* IOCFacts Reply message */
 215 typedef struct _MPI2_IOC_FACTS_REPLY
 216 {
 217     U16                     MsgVersion;                     /* 0x00 */
 218     U8                      MsgLength;                      /* 0x02 */
 219     U8                      Function;                       /* 0x03 */
 220     U16                     HeaderVersion;                  /* 0x04 */
 221     U8                      IOCNumber;                      /* 0x06 */
 222     U8                      MsgFlags;                       /* 0x07 */
 223     U8                      VP_ID;                          /* 0x08 */
 224     U8                      VF_ID;                          /* 0x09 */
 225     U16                     Reserved1;                      /* 0x0A */
 226     U16                     IOCExceptions;                  /* 0x0C */
 227     U16                     IOCStatus;                      /* 0x0E */
 228     U32                     IOCLogInfo;                     /* 0x10 */
 229     U8                      MaxChainDepth;                  /* 0x14 */
 230     U8                      WhoInit;                        /* 0x15 */
 231     U8                      NumberOfPorts;                  /* 0x16 */
 232     U8                      MaxMSIxVectors;                 /* 0x17 */
 233     U16                     RequestCredit;                  /* 0x18 */
 234     U16                     ProductID;                      /* 0x1A */
 235     U32                     IOCCapabilities;                /* 0x1C */
 236     MPI2_VERSION_UNION      FWVersion;                      /* 0x20 */
 237     U16                     IOCRequestFrameSize;            /* 0x24 */
 238     U16                     Reserved3;                      /* 0x26 */
 239     U16                     MaxInitiators;                  /* 0x28 */
 240     U16                     MaxTargets;                     /* 0x2A */
 241     U16                     MaxSasExpanders;                /* 0x2C */
 242     U16                     MaxEnclosures;                  /* 0x2E */
 243     U16                     ProtocolFlags;                  /* 0x30 */
 244     U16                     HighPriorityCredit;             /* 0x32 */
 245     U16                     MaxReplyDescriptorPostQueueDepth; /* 0x34 */
 246     U8                      ReplyFrameSize;                 /* 0x36 */
 247     U8                      MaxVolumes;                     /* 0x37 */
 248     U16                     MaxDevHandle;                   /* 0x38 */
 249     U16                     MaxPersistentEntries;           /* 0x3A */
 250     U16                     MinDevHandle;                   /* 0x3C */
 251     U16                     Reserved4;                      /* 0x3E */
 252 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
 253   Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
 254
 255 /* MsgVersion */
 256 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 257 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 258 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 259 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 260
 261 /* HeaderVersion */
 262 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 263 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 264 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 265 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 266
 267 /* IOCExceptions */
 268 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 269
 270 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 271 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 272 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 273 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 274 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 275
 276 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 277 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 278 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 279 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 280 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 281
 282 /* defines for WhoInit field are after the IOCInit Request */
 283
 284 /* ProductID field uses MPI2_FW_HEADER_PID_ */
 285
 286 /* IOCCapabilities */
 287 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 288 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 289 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 290 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 291 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 292 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 293 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 294 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 295 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 296 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 297 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 298 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 299 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 300
 301 /* ProtocolFlags */
 302 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 303 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 304
 305
 306 /****************************************************************************
 307 *  PortFacts message
 308 ****************************************************************************/
 309
 310 /* PortFacts Request message */
 311 typedef struct _MPI2_PORT_FACTS_REQUEST
 312 {
 313     U16                     Reserved1;                      /* 0x00 */
 314     U8                      ChainOffset;                    /* 0x02 */
 315     U8                      Function;                       /* 0x03 */
 316     U16                     Reserved2;                      /* 0x04 */
 317     U8                      PortNumber;                     /* 0x06 */
 318     U8                      MsgFlags;                       /* 0x07 */
 319     U8                      VP_ID;                          /* 0x08 */
 320     U8                      VF_ID;                          /* 0x09 */
 321     U16                     Reserved3;                      /* 0x0A */
 322 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
 323   Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
 324
 325 /* PortFacts Reply message */
 326 typedef struct _MPI2_PORT_FACTS_REPLY
 327 {
 328     U16                     Reserved1;                      /* 0x00 */
 329     U8                      MsgLength;                      /* 0x02 */
 330     U8                      Function;                       /* 0x03 */
 331     U16                     Reserved2;                      /* 0x04 */
 332     U8                      PortNumber;                     /* 0x06 */
 333     U8                      MsgFlags;                       /* 0x07 */
 334     U8                      VP_ID;                          /* 0x08 */
 335     U8                      VF_ID;                          /* 0x09 */
 336     U16                     Reserved3;                      /* 0x0A */
 337     U16                     Reserved4;                      /* 0x0C */
 338     U16                     IOCStatus;                      /* 0x0E */
 339     U32                     IOCLogInfo;                     /* 0x10 */
 340     U8                      Reserved5;                      /* 0x14 */
 341     U8                      PortType;                       /* 0x15 */
 342     U16                     Reserved6;                      /* 0x16 */
 343     U16                     MaxPostedCmdBuffers;            /* 0x18 */
 344     U16                     Reserved7;                      /* 0x1A */
 345 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
 346   Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
 347
 348 /* PortType values */
 349 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 350 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 351 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 352 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 353 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 354
 355
 356 /****************************************************************************
 357 *  PortEnable message
 358 ****************************************************************************/
 359
 360 /* PortEnable Request message */
 361 typedef struct _MPI2_PORT_ENABLE_REQUEST
 362 {
 363     U16                     Reserved1;                      /* 0x00 */
 364     U8                      ChainOffset;                    /* 0x02 */
 365     U8                      Function;                       /* 0x03 */
 366     U8                      Reserved2;                      /* 0x04 */
 367     U8                      PortFlags;                      /* 0x05 */
 368     U8                      Reserved3;                      /* 0x06 */
 369     U8                      MsgFlags;                       /* 0x07 */
 370     U8                      VP_ID;                          /* 0x08 */
 371     U8                      VF_ID;                          /* 0x09 */
 372     U16                     Reserved4;                      /* 0x0A */
 373 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
 374   Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
 375
 376
 377 /* PortEnable Reply message */
 378 typedef struct _MPI2_PORT_ENABLE_REPLY
 379 {
 380     U16                     Reserved1;                      /* 0x00 */
 381     U8                      MsgLength;                      /* 0x02 */
 382     U8                      Function;                       /* 0x03 */
 383     U8                      Reserved2;                      /* 0x04 */
 384     U8                      PortFlags;                      /* 0x05 */
 385     U8                      Reserved3;                      /* 0x06 */
 386     U8                      MsgFlags;                       /* 0x07 */
 387     U8                      VP_ID;                          /* 0x08 */
 388     U8                      VF_ID;                          /* 0x09 */
 389     U16                     Reserved4;                      /* 0x0A */
 390     U16                     Reserved5;                      /* 0x0C */
 391     U16                     IOCStatus;                      /* 0x0E */
 392     U32                     IOCLogInfo;                     /* 0x10 */
 393 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
 394   Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
 395
 396
 397 /****************************************************************************
 398 *  EventNotification message
 399 ****************************************************************************/
 400
 401 /* EventNotification Request message */
 402 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 403
 404 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
 405 {
 406     U16                     Reserved1;                      /* 0x00 */
 407     U8                      ChainOffset;                    /* 0x02 */
 408     U8                      Function;                       /* 0x03 */
 409     U16                     Reserved2;                      /* 0x04 */
 410     U8                      Reserved3;                      /* 0x06 */
 411     U8                      MsgFlags;                       /* 0x07 */
 412     U8                      VP_ID;                          /* 0x08 */
 413     U8                      VF_ID;                          /* 0x09 */
 414     U16                     Reserved4;                      /* 0x0A */
 415     U32                     Reserved5;                      /* 0x0C */
 416     U32                     Reserved6;                      /* 0x10 */
 417     U32                     EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
 418     U16                     SASBroadcastPrimitiveMasks;     /* 0x24 */
 419     U16                     Reserved7;                      /* 0x26 */
 420     U32                     Reserved8;                      /* 0x28 */
 421 } MPI2_EVENT_NOTIFICATION_REQUEST,
 422   MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 423   Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
 424
 425
 426 /* EventNotification Reply message */
 427 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
 428 {
 429     U16                     EventDataLength;                /* 0x00 */
 430     U8                      MsgLength;                      /* 0x02 */
 431     U8                      Function;                       /* 0x03 */
 432     U16                     Reserved1;                      /* 0x04 */
 433     U8                      AckRequired;                    /* 0x06 */
 434     U8                      MsgFlags;                       /* 0x07 */
 435     U8                      VP_ID;                          /* 0x08 */
 436     U8                      VF_ID;                          /* 0x09 */
 437     U16                     Reserved2;                      /* 0x0A */
 438     U16                     Reserved3;                      /* 0x0C */
 439     U16                     IOCStatus;                      /* 0x0E */
 440     U32                     IOCLogInfo;                     /* 0x10 */
 441     U16                     Event;                          /* 0x14 */
 442     U16                     Reserved4;                      /* 0x16 */
 443     U32                     EventContext;                   /* 0x18 */
 444     U32                     EventData[1];                   /* 0x1C */
 445 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 446   Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
 447
 448 /* AckRequired */
 449 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 450 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 451
 452 /* Event */
 453 #define MPI2_EVENT_LOG_DATA                         (0x0001)
 454 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 455 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 456 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 457 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E)
 458 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 459 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 460 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 461 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 462 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 463 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 464 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 465 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 466 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
 467 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 468 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 469 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 470 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 471 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 472 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 473
 474
 475 /* Log Entry Added Event data */
 476
 477 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 478 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 479
 480 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
 481 {
 482     U64         TimeStamp;                          /* 0x00 */
 483     U32         Reserved1;                          /* 0x08 */
 484     U16         LogSequence;                        /* 0x0C */
 485     U16         LogEntryQualifier;                  /* 0x0E */
 486     U8          VP_ID;                              /* 0x10 */
 487     U8          VF_ID;                              /* 0x11 */
 488     U16         Reserved2;                          /* 0x12 */
 489     U8          LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
 490 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 491   MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 492   Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
 493
 494 /* GPIO Interrupt Event data */
 495
 496 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
 497 {
 498     U8          GPIONum;                            /* 0x00 */
 499     U8          Reserved1;                          /* 0x01 */
 500     U16         Reserved2;                          /* 0x02 */
 501 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
 502   MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 503   Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
 504
 505 /* Hard Reset Received Event data */
 506
 507 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
 508 {
 509     U8                      Reserved1;                      /* 0x00 */
 510     U8                      Port;                           /* 0x01 */
 511     U16                     Reserved2;                      /* 0x02 */
 512 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 513   MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 514   Mpi2EventDataHardResetReceived_t,
 515   MPI2_POINTER pMpi2EventDataHardResetReceived_t;
 516
 517 /* Task Set Full Event data */
 518
 519 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
 520 {
 521     U16                     DevHandle;                      /* 0x00 */
 522     U16                     CurrentDepth;                   /* 0x02 */
 523 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 524   Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
 525
 526
 527 /* SAS Device Status Change Event data */
 528
 529 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
 530 {
 531     U16                     TaskTag;                        /* 0x00 */
 532     U8                      ReasonCode;                     /* 0x02 */
 533     U8                      Reserved1;                      /* 0x03 */
 534     U8                      ASC;                            /* 0x04 */
 535     U8                      ASCQ;                           /* 0x05 */
 536     U16                     DevHandle;                      /* 0x06 */
 537     U32                     Reserved2;                      /* 0x08 */
 538     U64                     SASAddress;                     /* 0x0C */
 539     U8                      LUN[8];                         /* 0x14 */
 540 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 541   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 542   Mpi2EventDataSasDeviceStatusChange_t,
 543   MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
 544
 545 /* SAS Device Status Change Event data ReasonCode values */
 546 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 547 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 548 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 549 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 550 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 551 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 552 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 553 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 554 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 555 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 556 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 557 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 558 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 559
 560
 561 /* Integrated RAID Operation Status Event data */
 562
 563 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
 564 {
 565     U16                     VolDevHandle;               /* 0x00 */
 566     U16                     Reserved1;                  /* 0x02 */
 567     U8                      RAIDOperation;              /* 0x04 */
 568     U8                      PercentComplete;            /* 0x05 */
 569     U16                     Reserved2;                  /* 0x06 */
 570     U32                     Resereved3;                 /* 0x08 */
 571 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 572   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 573   Mpi2EventDataIrOperationStatus_t,
 574   MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
 575
 576 /* Integrated RAID Operation Status Event data RAIDOperation values */
 577 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 578 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 579 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 580 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 581 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 582
 583
 584 /* Integrated RAID Volume Event data */
 585
 586 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
 587 {
 588     U16                     VolDevHandle;               /* 0x00 */
 589     U8                      ReasonCode;                 /* 0x02 */
 590     U8                      Reserved1;                  /* 0x03 */
 591     U32                     NewValue;                   /* 0x04 */
 592     U32                     PreviousValue;              /* 0x08 */
 593 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
 594   Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
 595
 596 /* Integrated RAID Volume Event data ReasonCode values */
 597 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 598 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 599 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 600
 601
 602 /* Integrated RAID Physical Disk Event data */
 603
 604 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
 605 {
 606     U16                     Reserved1;                  /* 0x00 */
 607     U8                      ReasonCode;                 /* 0x02 */
 608     U8                      PhysDiskNum;                /* 0x03 */
 609     U16                     PhysDiskDevHandle;          /* 0x04 */
 610     U16                     Reserved2;                  /* 0x06 */
 611     U16                     Slot;                       /* 0x08 */
 612     U16                     EnclosureHandle;            /* 0x0A */
 613     U32                     NewValue;                   /* 0x0C */
 614     U32                     PreviousValue;              /* 0x10 */
 615 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 616   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 617   Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
 618
 619 /* Integrated RAID Physical Disk Event data ReasonCode values */
 620 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 621 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 622 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 623
 624
 625 /* Integrated RAID Configuration Change List Event data */
 626
 627 /*
 628  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 629  * one and check NumElements at runtime.
 630  */
 631 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 632 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 633 #endif
 634
 635 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
 636 {
 637     U16                     ElementFlags;               /* 0x00 */
 638     U16                     VolDevHandle;               /* 0x02 */
 639     U8                      ReasonCode;                 /* 0x04 */
 640     U8                      PhysDiskNum;                /* 0x05 */
 641     U16                     PhysDiskDevHandle;          /* 0x06 */
 642 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 643   Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
 644
 645 /* IR Configuration Change List Event data ElementFlags values */
 646 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 647 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 648 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 649 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 650
 651 /* IR Configuration Change List Event data ReasonCode values */
 652 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 653 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 654 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 655 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 656 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 657 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 658 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 659 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 660 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 661
 662 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
 663 {
 664     U8                              NumElements;        /* 0x00 */
 665     U8                              Reserved1;          /* 0x01 */
 666     U8                              Reserved2;          /* 0x02 */
 667     U8                              ConfigNum;          /* 0x03 */
 668     U32                             Flags;              /* 0x04 */
 669     MPI2_EVENT_IR_CONFIG_ELEMENT    ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];    /* 0x08 */
 670 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 671   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 672   Mpi2EventDataIrConfigChangeList_t,
 673   MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
 674
 675 /* IR Configuration Change List Event data Flags values */
 676 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 677
 678
 679 /* SAS Discovery Event data */
 680
 681 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
 682 {
 683     U8                      Flags;                      /* 0x00 */
 684     U8                      ReasonCode;                 /* 0x01 */
 685     U8                      PhysicalPort;               /* 0x02 */
 686     U8                      Reserved1;                  /* 0x03 */
 687     U32                     DiscoveryStatus;            /* 0x04 */
 688 } MPI2_EVENT_DATA_SAS_DISCOVERY,
 689   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 690   Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
 691
 692 /* SAS Discovery Event data Flags values */
 693 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 694 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 695
 696 /* SAS Discovery Event data ReasonCode values */
 697 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 698 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 699
 700 /* SAS Discovery Event data DiscoveryStatus values */
 701 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 702 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 703 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 704 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 705 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 706 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 707 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 708 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 709 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 710 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 711 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 712 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 713 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 714 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 715 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 716 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 717 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 718 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 719 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 720 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 721
 722
 723 /* SAS Broadcast Primitive Event data */
 724
 725 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
 726 {
 727     U8                      PhyNum;                     /* 0x00 */
 728     U8                      Port;                       /* 0x01 */
 729     U8                      PortWidth;                  /* 0x02 */
 730     U8                      Primitive;                  /* 0x03 */
 731 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 732   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 733   Mpi2EventDataSasBroadcastPrimitive_t,
 734   MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
 735
 736 /* defines for the Primitive field */
 737 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 738 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 739 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 740 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 741 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 742 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 743 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 744 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 745
 746
 747 /* SAS Initiator Device Status Change Event data */
 748
 749 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
 750 {
 751     U8                      ReasonCode;                 /* 0x00 */
 752     U8                      PhysicalPort;               /* 0x01 */
 753     U16                     DevHandle;                  /* 0x02 */
 754     U64                     SASAddress;                 /* 0x04 */
 755 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 756   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 757   Mpi2EventDataSasInitDevStatusChange_t,
 758   MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
 759
 760 /* SAS Initiator Device Status Change event ReasonCode values */
 761 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 762 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 763
 764
 765 /* SAS Initiator Device Table Overflow Event data */
 766
 767 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
 768 {
 769     U16                     MaxInit;                    /* 0x00 */
 770     U16                     CurrentInit;                /* 0x02 */
 771     U64                     SASAddress;                 /* 0x04 */
 772 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 773   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 774   Mpi2EventDataSasInitTableOverflow_t,
 775   MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
 776
 777
 778 /* SAS Topology Change List Event data */
 779
 780 /*
 781  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 782  * one and check NumEntries at runtime.
 783  */
 784 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 785 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 786 #endif
 787
 788 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 789 {
 790     U16                     AttachedDevHandle;          /* 0x00 */
 791     U8                      LinkRate;                   /* 0x02 */
 792     U8                      PhyStatus;                  /* 0x03 */
 793 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 794   Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
 795
 796 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
 797 {
 798     U16                             EnclosureHandle;            /* 0x00 */
 799     U16                             ExpanderDevHandle;          /* 0x02 */
 800     U8                              NumPhys;                    /* 0x04 */
 801     U8                              Reserved1;                  /* 0x05 */
 802     U16                             Reserved2;                  /* 0x06 */
 803     U8                              NumEntries;                 /* 0x08 */
 804     U8                              StartPhyNum;                /* 0x09 */
 805     U8                              ExpStatus;                  /* 0x0A */
 806     U8                              PhysicalPort;               /* 0x0B */
 807     MPI2_EVENT_SAS_TOPO_PHY_ENTRY   PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
 808 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 809   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 810   Mpi2EventDataSasTopologyChangeList_t,
 811   MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
 812
 813 /* values for the ExpStatus field */
 814 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 815 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 816 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 817 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 818 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 819
 820 /* defines for the LinkRate field */
 821 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 822 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 823 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 824 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 825
 826 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 827 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 828 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 829 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 830 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 831 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 832 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 833 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 834 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 835
 836 /* values for the PhyStatus field */
 837 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 838 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 839 /* values for the PhyStatus ReasonCode sub-field */
 840 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 841 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 842 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 843 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 844 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 845 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 846
 847
 848 /* SAS Enclosure Device Status Change Event data */
 849
 850 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
 851 {
 852     U16                     EnclosureHandle;            /* 0x00 */
 853     U8                      ReasonCode;                 /* 0x02 */
 854     U8                      PhysicalPort;               /* 0x03 */
 855     U64                     EnclosureLogicalID;         /* 0x04 */
 856     U16                     NumSlots;                   /* 0x0C */
 857     U16                     StartSlot;                  /* 0x0E */
 858     U32                     PhyBits;                    /* 0x10 */
 859 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 860   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 861   Mpi2EventDataSasEnclDevStatusChange_t,
 862   MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
 863
 864 /* SAS Enclosure Device Status Change event ReasonCode values */
 865 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 866 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 867
 868
 869 /* SAS PHY Counter Event data */
 870
 871 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
 872 {
 873     U64         TimeStamp;          /* 0x00 */
 874     U32         Reserved1;          /* 0x08 */
 875     U8          PhyEventCode;       /* 0x0C */
 876     U8          PhyNum;             /* 0x0D */
 877     U16         Reserved2;          /* 0x0E */
 878     U32         PhyEventInfo;       /* 0x10 */
 879     U8          CounterType;        /* 0x14 */
 880     U8          ThresholdWindow;    /* 0x15 */
 881     U8          TimeUnits;          /* 0x16 */
 882     U8          Reserved3;          /* 0x17 */
 883     U32         EventThreshold;     /* 0x18 */
 884     U16         ThresholdFlags;     /* 0x1C */
 885     U16         Reserved4;          /* 0x1E */
 886 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 887   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 888   Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
 889
 890 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
 891
 892 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
 893
 894 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
 895
 896 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
 897
 898
 899 /* Host Based Discovery Phy Event data */
 900
 901 typedef struct _MPI2_EVENT_HBD_PHY_SAS
 902 {
 903     U8          Flags;                      /* 0x00 */
 904     U8          NegotiatedLinkRate;         /* 0x01 */
 905     U8          PhyNum;                     /* 0x02 */
 906     U8          PhysicalPort;               /* 0x03 */
 907     U32         Reserved1;                  /* 0x04 */
 908     U8          InitialFrame[28];           /* 0x08 */
 909 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
 910   Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
 911
 912 /* values for the Flags field */
 913 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
 914 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
 915
 916 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
 917
 918 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
 919 {
 920     MPI2_EVENT_HBD_PHY_SAS      Sas;
 921 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
 922   Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
 923
 924 typedef struct _MPI2_EVENT_DATA_HBD_PHY
 925 {
 926     U8                          DescriptorType;     /* 0x00 */
 927     U8                          Reserved1;          /* 0x01 */
 928     U16                         Reserved2;          /* 0x02 */
 929     U32                         Reserved3;          /* 0x04 */
 930     MPI2_EVENT_HBD_DESCRIPTOR   Descriptor;         /* 0x08 */
 931 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
 932   Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
 933
 934 /* values for the DescriptorType field */
 935 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
 936
 937
 938
 939 /****************************************************************************
 940 *  EventAck message
 941 ****************************************************************************/
 942
 943 /* EventAck Request message */
 944 typedef struct _MPI2_EVENT_ACK_REQUEST
 945 {
 946     U16                     Reserved1;                      /* 0x00 */
 947     U8                      ChainOffset;                    /* 0x02 */
 948     U8                      Function;                       /* 0x03 */
 949     U16                     Reserved2;                      /* 0x04 */
 950     U8                      Reserved3;                      /* 0x06 */
 951     U8                      MsgFlags;                       /* 0x07 */
 952     U8                      VP_ID;                          /* 0x08 */
 953     U8                      VF_ID;                          /* 0x09 */
 954     U16                     Reserved4;                      /* 0x0A */
 955     U16                     Event;                          /* 0x0C */
 956     U16                     Reserved5;                      /* 0x0E */
 957     U32                     EventContext;                   /* 0x10 */
 958 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
 959   Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
 960
 961
 962 /* EventAck Reply message */
 963 typedef struct _MPI2_EVENT_ACK_REPLY
 964 {
 965     U16                     Reserved1;                      /* 0x00 */
 966     U8                      MsgLength;                      /* 0x02 */
 967     U8                      Function;                       /* 0x03 */
 968     U16                     Reserved2;                      /* 0x04 */
 969     U8                      Reserved3;                      /* 0x06 */
 970     U8                      MsgFlags;                       /* 0x07 */
 971     U8                      VP_ID;                          /* 0x08 */
 972     U8                      VF_ID;                          /* 0x09 */
 973     U16                     Reserved4;                      /* 0x0A */
 974     U16                     Reserved5;                      /* 0x0C */
 975     U16                     IOCStatus;                      /* 0x0E */
 976     U32                     IOCLogInfo;                     /* 0x10 */
 977 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
 978   Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
 979
 980
 981 /****************************************************************************
 982 *  FWDownload message
 983 ****************************************************************************/
 984
 985 /* FWDownload Request message */
 986 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
 987 {
 988     U8                      ImageType;                  /* 0x00 */
 989     U8                      Reserved1;                  /* 0x01 */
 990     U8                      ChainOffset;                /* 0x02 */
 991     U8                      Function;                   /* 0x03 */
 992     U16                     Reserved2;                  /* 0x04 */
 993     U8                      Reserved3;                  /* 0x06 */
 994     U8                      MsgFlags;                   /* 0x07 */
 995     U8                      VP_ID;                      /* 0x08 */
 996     U8                      VF_ID;                      /* 0x09 */
 997     U16                     Reserved4;                  /* 0x0A */
 998     U32                     TotalImageSize;             /* 0x0C */
 999     U32                     Reserved5;                  /* 0x10 */
1000     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1001 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1002   Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1003
1004 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1005
1006 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1007 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1008 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1009 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1010 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1011 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1012 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1013
1014 /* FWDownload TransactionContext Element */
1015 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1016 {
1017     U8                      Reserved1;                  /* 0x00 */
1018     U8                      ContextSize;                /* 0x01 */
1019     U8                      DetailsLength;              /* 0x02 */
1020     U8                      Flags;                      /* 0x03 */
1021     U32                     Reserved2;                  /* 0x04 */
1022     U32                     ImageOffset;                /* 0x08 */
1023     U32                     ImageSize;                  /* 0x0C */
1024 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1025   Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1026
1027 /* FWDownload Reply message */
1028 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1029 {
1030     U8                      ImageType;                  /* 0x00 */
1031     U8                      Reserved1;                  /* 0x01 */
1032     U8                      MsgLength;                  /* 0x02 */
1033     U8                      Function;                   /* 0x03 */
1034     U16                     Reserved2;                  /* 0x04 */
1035     U8                      Reserved3;                  /* 0x06 */
1036     U8                      MsgFlags;                   /* 0x07 */
1037     U8                      VP_ID;                      /* 0x08 */
1038     U8                      VF_ID;                      /* 0x09 */
1039     U16                     Reserved4;                  /* 0x0A */
1040     U16                     Reserved5;                  /* 0x0C */
1041     U16                     IOCStatus;                  /* 0x0E */
1042     U32                     IOCLogInfo;                 /* 0x10 */
1043 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1044   Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1045
1046
1047 /****************************************************************************
1048 *  FWUpload message
1049 ****************************************************************************/
1050
1051 /* FWUpload Request message */
1052 typedef struct _MPI2_FW_UPLOAD_REQUEST
1053 {
1054     U8                      ImageType;                  /* 0x00 */
1055     U8                      Reserved1;                  /* 0x01 */
1056     U8                      ChainOffset;                /* 0x02 */
1057     U8                      Function;                   /* 0x03 */
1058     U16                     Reserved2;                  /* 0x04 */
1059     U8                      Reserved3;                  /* 0x06 */
1060     U8                      MsgFlags;                   /* 0x07 */
1061     U8                      VP_ID;                      /* 0x08 */
1062     U8                      VF_ID;                      /* 0x09 */
1063     U16                     Reserved4;                  /* 0x0A */
1064     U32                     Reserved5;                  /* 0x0C */
1065     U32                     Reserved6;                  /* 0x10 */
1066     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1067 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1068   Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1069
1070 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1071 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1072 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1073 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1074 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1075 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1076 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1077 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1078 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1079 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1080
1081 typedef struct _MPI2_FW_UPLOAD_TCSGE
1082 {
1083     U8                      Reserved1;                  /* 0x00 */
1084     U8                      ContextSize;                /* 0x01 */
1085     U8                      DetailsLength;              /* 0x02 */
1086     U8                      Flags;                      /* 0x03 */
1087     U32                     Reserved2;                  /* 0x04 */
1088     U32                     ImageOffset;                /* 0x08 */
1089     U32                     ImageSize;                  /* 0x0C */
1090 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1091   Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1092
1093 /* FWUpload Reply message */
1094 typedef struct _MPI2_FW_UPLOAD_REPLY
1095 {
1096     U8                      ImageType;                  /* 0x00 */
1097     U8                      Reserved1;                  /* 0x01 */
1098     U8                      MsgLength;                  /* 0x02 */
1099     U8                      Function;                   /* 0x03 */
1100     U16                     Reserved2;                  /* 0x04 */
1101     U8                      Reserved3;                  /* 0x06 */
1102     U8                      MsgFlags;                   /* 0x07 */
1103     U8                      VP_ID;                      /* 0x08 */
1104     U8                      VF_ID;                      /* 0x09 */
1105     U16                     Reserved4;                  /* 0x0A */
1106     U16                     Reserved5;                  /* 0x0C */
1107     U16                     IOCStatus;                  /* 0x0E */
1108     U32                     IOCLogInfo;                 /* 0x10 */
1109     U32                     ActualImageSize;            /* 0x14 */
1110 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1111   Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1112
1113
1114 /* FW Image Header */
1115 typedef struct _MPI2_FW_IMAGE_HEADER
1116 {
1117     U32                     Signature;                  /* 0x00 */
1118     U32                     Signature0;                 /* 0x04 */
1119     U32                     Signature1;                 /* 0x08 */
1120     U32                     Signature2;                 /* 0x0C */
1121     MPI2_VERSION_UNION      MPIVersion;                 /* 0x10 */
1122     MPI2_VERSION_UNION      FWVersion;                  /* 0x14 */
1123     MPI2_VERSION_UNION      NVDATAVersion;              /* 0x18 */
1124     MPI2_VERSION_UNION      PackageVersion;             /* 0x1C */
1125     U16                     VendorID;                   /* 0x20 */
1126     U16                     ProductID;                  /* 0x22 */
1127     U16                     ProtocolFlags;              /* 0x24 */
1128     U16                     Reserved26;                 /* 0x26 */
1129     U32                     IOCCapabilities;            /* 0x28 */
1130     U32                     ImageSize;                  /* 0x2C */
1131     U32                     NextImageHeaderOffset;      /* 0x30 */
1132     U32                     Checksum;                   /* 0x34 */
1133     U32                     Reserved38;                 /* 0x38 */
1134     U32                     Reserved3C;                 /* 0x3C */
1135     U32                     Reserved40;                 /* 0x40 */
1136     U32                     Reserved44;                 /* 0x44 */
1137     U32                     Reserved48;                 /* 0x48 */
1138     U32                     Reserved4C;                 /* 0x4C */
1139     U32                     Reserved50;                 /* 0x50 */
1140     U32                     Reserved54;                 /* 0x54 */
1141     U32                     Reserved58;                 /* 0x58 */
1142     U32                     Reserved5C;                 /* 0x5C */
1143     U32                     Reserved60;                 /* 0x60 */
1144     U32                     FirmwareVersionNameWhat;    /* 0x64 */
1145     U8                      FirmwareVersionName[32];    /* 0x68 */
1146     U32                     VendorNameWhat;             /* 0x88 */
1147     U8                      VendorName[32];             /* 0x8C */
1148     U32                     PackageNameWhat;            /* 0x88 */
1149     U8                      PackageName[32];            /* 0x8C */
1150     U32                     ReservedD0;                 /* 0xD0 */
1151     U32                     ReservedD4;                 /* 0xD4 */
1152     U32                     ReservedD8;                 /* 0xD8 */
1153     U32                     ReservedDC;                 /* 0xDC */
1154     U32                     ReservedE0;                 /* 0xE0 */
1155     U32                     ReservedE4;                 /* 0xE4 */
1156     U32                     ReservedE8;                 /* 0xE8 */
1157     U32                     ReservedEC;                 /* 0xEC */
1158     U32                     ReservedF0;                 /* 0xF0 */
1159     U32                     ReservedF4;                 /* 0xF4 */
1160     U32                     ReservedF8;                 /* 0xF8 */
1161     U32                     ReservedFC;                 /* 0xFC */
1162 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1163   Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1164
1165 /* Signature field */
1166 #define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1167 #define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1168 #define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1169
1170 /* Signature0 field */
1171 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1172 #define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1173
1174 /* Signature1 field */
1175 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1176 #define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1177
1178 /* Signature2 field */
1179 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1180 #define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1181
1182
1183 /* defines for using the ProductID field */
1184 #define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1185 #define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1186
1187 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1188 #define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1189 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1190 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1191 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1192
1193
1194 #define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1195 /* SAS */
1196 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1197 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1198
1199 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1200
1201 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1202
1203
1204 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1205 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1206 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1207
1208 #define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1209
1210 #define MPI2_FW_HEADER_SIZE                     (0x100)
1211
1212
1213 /* Extended Image Header */
1214 typedef struct _MPI2_EXT_IMAGE_HEADER
1215
1216 {
1217     U8                      ImageType;                  /* 0x00 */
1218     U8                      Reserved1;                  /* 0x01 */
1219     U16                     Reserved2;                  /* 0x02 */
1220     U32                     Checksum;                   /* 0x04 */
1221     U32                     ImageSize;                  /* 0x08 */
1222     U32                     NextImageHeaderOffset;      /* 0x0C */
1223     U32                     PackageVersion;             /* 0x10 */
1224     U32                     Reserved3;                  /* 0x14 */
1225     U32                     Reserved4;                  /* 0x18 */
1226     U32                     Reserved5;                  /* 0x1C */
1227     U8                      IdentifyString[32];         /* 0x20 */
1228 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1229   Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1230
1231 /* useful offsets */
1232 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1233 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1234 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1235
1236 #define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1237
1238 /* defines for the ImageType field */
1239 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED         (0x00)
1240 #define MPI2_EXT_IMAGE_TYPE_FW                  (0x01)
1241 #define MPI2_EXT_IMAGE_TYPE_NVDATA              (0x03)
1242 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER          (0x04)
1243 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION      (0x05)
1244 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT        (0x06)
1245 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES   (0x07)
1246 #define MPI2_EXT_IMAGE_TYPE_MEGARAID            (0x08)
1247
1248 #define MPI2_EXT_IMAGE_TYPE_MAX                 (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1249
1250
1251
1252 /* FLASH Layout Extended Image Data */
1253
1254 /*
1255  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1256  * one and check RegionsPerLayout at runtime.
1257  */
1258 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1259 #define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1260 #endif
1261
1262 /*
1263  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1264  * one and check NumberOfLayouts at runtime.
1265  */
1266 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1267 #define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1268 #endif
1269
1270 typedef struct _MPI2_FLASH_REGION
1271 {
1272     U8                      RegionType;                 /* 0x00 */
1273     U8                      Reserved1;                  /* 0x01 */
1274     U16                     Reserved2;                  /* 0x02 */
1275     U32                     RegionOffset;               /* 0x04 */
1276     U32                     RegionSize;                 /* 0x08 */
1277     U32                     Reserved3;                  /* 0x0C */
1278 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1279   Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1280
1281 typedef struct _MPI2_FLASH_LAYOUT
1282 {
1283     U32                     FlashSize;                  /* 0x00 */
1284     U32                     Reserved1;                  /* 0x04 */
1285     U32                     Reserved2;                  /* 0x08 */
1286     U32                     Reserved3;                  /* 0x0C */
1287     MPI2_FLASH_REGION       Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1288 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1289   Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1290
1291 typedef struct _MPI2_FLASH_LAYOUT_DATA
1292 {
1293     U8                      ImageRevision;              /* 0x00 */
1294     U8                      Reserved1;                  /* 0x01 */
1295     U8                      SizeOfRegion;               /* 0x02 */
1296     U8                      Reserved2;                  /* 0x03 */
1297     U16                     NumberOfLayouts;            /* 0x04 */
1298     U16                     RegionsPerLayout;           /* 0x06 */
1299     U16                     MinimumSectorAlignment;     /* 0x08 */
1300     U16                     Reserved3;                  /* 0x0A */
1301     U32                     Reserved4;                  /* 0x0C */
1302     MPI2_FLASH_LAYOUT       Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1303 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1304   Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1305
1306 /* defines for the RegionType field */
1307 #define MPI2_FLASH_REGION_UNUSED                (0x00)
1308 #define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1309 #define MPI2_FLASH_REGION_BIOS                  (0x02)
1310 #define MPI2_FLASH_REGION_NVDATA                (0x03)
1311 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1312 #define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1313 #define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1314 #define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1315 #define MPI2_FLASH_REGION_MEGARAID              (0x09)
1316 #define MPI2_FLASH_REGION_INIT                  (0x0A)
1317
1318 /* ImageRevision */
1319 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1320
1321
1322
1323 /* Supported Devices Extended Image Data */
1324
1325 /*
1326  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1327  * one and check NumberOfDevices at runtime.
1328  */
1329 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1330 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1331 #endif
1332
1333 typedef struct _MPI2_SUPPORTED_DEVICE
1334 {
1335     U16                     DeviceID;                   /* 0x00 */
1336     U16                     VendorID;                   /* 0x02 */
1337     U16                     DeviceIDMask;               /* 0x04 */
1338     U16                     Reserved1;                  /* 0x06 */
1339     U8                      LowPCIRev;                  /* 0x08 */
1340     U8                      HighPCIRev;                 /* 0x09 */
1341     U16                     Reserved2;                  /* 0x0A */
1342     U32                     Reserved3;                  /* 0x0C */
1343 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1344   Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1345
1346 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1347 {
1348     U8                      ImageRevision;              /* 0x00 */
1349     U8                      Reserved1;                  /* 0x01 */
1350     U8                      NumberOfDevices;            /* 0x02 */
1351     U8                      Reserved2;                  /* 0x03 */
1352     U32                     Reserved3;                  /* 0x04 */
1353     MPI2_SUPPORTED_DEVICE   SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1354 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1355   Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1356
1357 /* ImageRevision */
1358 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1359
1360
1361 /* Init Extended Image Data */
1362
1363 typedef struct _MPI2_INIT_IMAGE_FOOTER
1364
1365 {
1366     U32                     BootFlags;                  /* 0x00 */
1367     U32                     ImageSize;                  /* 0x04 */
1368     U32                     Signature0;                 /* 0x08 */
1369     U32                     Signature1;                 /* 0x0C */
1370     U32                     Signature2;                 /* 0x10 */
1371     U32                     ResetVector;                /* 0x14 */
1372 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1373   Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1374
1375 /* defines for the BootFlags field */
1376 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1377
1378 /* defines for the ImageSize field */
1379 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1380
1381 /* defines for the Signature0 field */
1382 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1383 #define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1384
1385 /* defines for the Signature1 field */
1386 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1387 #define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1388
1389 /* defines for the Signature2 field */
1390 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1391 #define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1392
1393 /* Signature fields as individual bytes */
1394 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1395 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1396 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1397 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1398
1399 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1400 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1401 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1402 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1403
1404 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1405 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1406 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1407 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1408
1409 /* defines for the ResetVector field */
1410 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1411
1412
1413 #endif