2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2006 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: ar5211_beacon.c,v 1.4 2008/11/10 04:08:02 sam Exp $
23 #include "ah_internal.h"
25 #include "ar5211/ar5211.h"
26 #include "ar5211/ar5211reg.h"
27 #include "ar5211/ar5211desc.h"
30 * Routines used to initialize and generated beacons for the AR5211/AR5311.
34 * Initialize all of the hardware registers used to send beacons.
37 ar5211SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
40 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
41 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
42 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
43 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
45 * Set the Beacon register after setting all timers.
47 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
51 * Legacy api to initialize all of the beacon registers.
54 ar5211BeaconInit(struct ath_hal *ah,
55 uint32_t next_beacon, uint32_t beacon_period)
59 bt.bt_nexttbtt = next_beacon;
61 * TIMER1: in AP/adhoc mode this controls the DMA beacon
62 * alert timer; otherwise it controls the next wakeup time.
63 * TIMER2: in AP mode, it controls the SBA beacon alert
64 * interrupt; otherwise it sets the start of the next CFP.
66 switch (AH_PRIVATE(ah)->ah_opmode) {
69 bt.bt_nextdba = 0xffff;
70 bt.bt_nextswba = 0x7ffff;
74 bt.bt_nextdba = (next_beacon -
75 ath_hal_dma_beacon_response_time) << 3; /* 1/8 TU */
76 bt.bt_nextswba = (next_beacon -
77 ath_hal_sw_beacon_response_time) << 3; /* 1/8 TU */
82 * Our hardware does not support an ATIM window of 0
83 * (beacons will not work). If the ATIM windows is 0,
86 bt.bt_nextatim = next_beacon + 1;
87 bt.bt_intval = beacon_period &
88 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
89 ar5211SetBeaconTimers(ah, &bt);
93 ar5211ResetStaBeaconTimers(struct ath_hal *ah)
97 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
98 val = OS_REG_READ(ah, AR_STA_ID1);
99 val |= AR_STA_ID1_PWR_SAV; /* XXX */
100 /* tell the h/w that the associated AP is not PCF capable */
101 OS_REG_WRITE(ah, AR_STA_ID1,
102 val & ~(AR_STA_ID1_DEFAULT_ANTENNA | AR_STA_ID1_PCF));
103 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
107 * Set all the beacon related bits on the h/w for stations
108 * i.e. initializes the corresponding h/w timers;
109 * also tells the h/w whether to anticipate PCF beacons
112 ar5211SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
114 struct ath_hal_5211 *ahp = AH5211(ah);
116 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: setting beacon timers\n", __func__);
118 HALASSERT(bs->bs_intval != 0);
119 /* if the AP will do PCF */
120 if (bs->bs_cfpmaxduration != 0) {
121 /* tell the h/w that the associated AP is PCF capable */
122 OS_REG_WRITE(ah, AR_STA_ID1,
123 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
125 /* set CFP_PERIOD(1.024ms) register */
126 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
128 /* set CFP_DUR(1.024ms) register to max cfp duration */
129 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
131 /* set TIMER2(128us) to anticipated time of next CFP */
132 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
134 /* tell the h/w that the associated AP is not PCF capable */
135 OS_REG_WRITE(ah, AR_STA_ID1,
136 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
140 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
142 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
145 * Start the beacon timers by setting the BEACON register
146 * to the beacon interval; also write the tim offset which
147 * we should know by now. The code, in ar5211WriteAssocid,
148 * also sets the tim offset once the AID is known which can
149 * be left as such for now.
151 OS_REG_WRITE(ah, AR_BEACON,
152 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
153 | SM(bs->bs_intval, AR_BEACON_PERIOD)
154 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
158 * Configure the BMISS interrupt. Note that we
159 * assume the caller blocks interrupts while enabling
162 HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
163 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
164 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
165 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
168 * Set the sleep duration in 1/8 TU's.
171 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLDUR,
172 (bs->bs_sleepduration - SLEEP_SLOP) << 3);