2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $Id: ar5212_beacon.c,v 1.6 2008/11/10 04:08:03 sam Exp $
23 #include "ah_internal.h"
25 #include "ar5212/ar5212.h"
26 #include "ar5212/ar5212reg.h"
27 #include "ar5212/ar5212desc.h"
30 * Initialize all of the hardware registers used to
31 * send beacons. Note that for station operation the
32 * driver calls ar5212SetStaBeaconTimers instead.
35 ar5212SetBeaconTimers(struct ath_hal *ah, const HAL_BEACON_TIMERS *bt)
38 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt);
39 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba);
40 OS_REG_WRITE(ah, AR_TIMER2, bt->bt_nextswba);
41 OS_REG_WRITE(ah, AR_TIMER3, bt->bt_nextatim);
43 * Set the Beacon register after setting all timers.
45 if (bt->bt_intval & AR_BEACON_RESET_TSF) {
47 * When resetting the TSF,
48 * write twice to the corresponding register; each
49 * write to the RESET_TSF bit toggles the internal
50 * signal to cause a reset of the TSF - but if the signal
51 * is left high, it will reset the TSF on the next
52 * chip reset also! writing the bit an even number
53 * of times fixes this issue
55 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_RESET_TSF);
57 OS_REG_WRITE(ah, AR_BEACON, bt->bt_intval);
61 * Old api for setting up beacon timer registers when
62 * operating in !station mode. Note the fixed constants
63 * adjusting the DBA and SWBA timers and the fixed ATIM
67 ar5212BeaconInit(struct ath_hal *ah,
68 uint32_t next_beacon, uint32_t beacon_period)
72 bt.bt_nexttbtt = next_beacon;
74 * TIMER1: in AP/adhoc mode this controls the DMA beacon
75 * alert timer; otherwise it controls the next wakeup time.
76 * TIMER2: in AP mode, it controls the SBA beacon alert
77 * interrupt; otherwise it sets the start of the next CFP.
79 switch (AH_PRIVATE(ah)->ah_opmode) {
82 bt.bt_nextdba = 0xffff;
83 bt.bt_nextswba = 0x7ffff;
87 bt.bt_nextdba = (next_beacon -
88 ath_hal_dma_beacon_response_time) << 3; /* 1/8 TU */
89 bt.bt_nextswba = (next_beacon -
90 ath_hal_sw_beacon_response_time) << 3; /* 1/8 TU */
95 * Our hardware does not support an ATIM window of 0
96 * (beacons will not work). If the ATIM windows is 0,
99 bt.bt_nextatim = next_beacon + 1;
100 bt.bt_intval = beacon_period &
101 (AR_BEACON_PERIOD | AR_BEACON_RESET_TSF | AR_BEACON_EN);
102 ar5212SetBeaconTimers(ah, &bt);
106 ar5212ResetStaBeaconTimers(struct ath_hal *ah)
110 OS_REG_WRITE(ah, AR_TIMER0, 0); /* no beacons */
111 val = OS_REG_READ(ah, AR_STA_ID1);
112 val |= AR_STA_ID1_PWR_SAV; /* XXX */
113 /* tell the h/w that the associated AP is not PCF capable */
114 OS_REG_WRITE(ah, AR_STA_ID1,
115 val & ~(AR_STA_ID1_USE_DEFANT | AR_STA_ID1_PCF));
116 OS_REG_WRITE(ah, AR_BEACON, AR_BEACON_PERIOD);
120 * Set all the beacon related bits on the h/w for stations
121 * i.e. initializes the corresponding h/w timers;
122 * also tells the h/w whether to anticipate PCF beacons
125 ar5212SetStaBeaconTimers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
127 struct ath_hal_5212 *ahp = AH5212(ah);
128 uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod;
130 HALASSERT(bs->bs_intval != 0);
131 /* if the AP will do PCF */
132 if (bs->bs_cfpmaxduration != 0) {
133 /* tell the h/w that the associated AP is PCF capable */
134 OS_REG_WRITE(ah, AR_STA_ID1,
135 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PCF);
137 /* set CFP_PERIOD(1.024ms) register */
138 OS_REG_WRITE(ah, AR_CFP_PERIOD, bs->bs_cfpperiod);
140 /* set CFP_DUR(1.024ms) register to max cfp duration */
141 OS_REG_WRITE(ah, AR_CFP_DUR, bs->bs_cfpmaxduration);
143 /* set TIMER2(128us) to anticipated time of next CFP */
144 OS_REG_WRITE(ah, AR_TIMER2, bs->bs_cfpnext << 3);
146 /* tell the h/w that the associated AP is not PCF capable */
147 OS_REG_WRITE(ah, AR_STA_ID1,
148 OS_REG_READ(ah, AR_STA_ID1) &~ AR_STA_ID1_PCF);
152 * Set TIMER0(1.024ms) to the anticipated time of the next beacon.
154 OS_REG_WRITE(ah, AR_TIMER0, bs->bs_nexttbtt);
157 * Start the beacon timers by setting the BEACON register
158 * to the beacon interval; also write the tim offset which
159 * we should know by now. The code, in ar5211WriteAssocid,
160 * also sets the tim offset once the AID is known which can
161 * be left as such for now.
163 OS_REG_WRITE(ah, AR_BEACON,
164 (OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_PERIOD|AR_BEACON_TIM))
165 | SM(bs->bs_intval, AR_BEACON_PERIOD)
166 | SM(bs->bs_timoffset ? bs->bs_timoffset + 4 : 0, AR_BEACON_TIM)
170 * Configure the BMISS interrupt. Note that we
171 * assume the caller blocks interrupts while enabling
174 HALASSERT(bs->bs_bmissthreshold <= MS(0xffffffff, AR_RSSI_THR_BM_THR));
175 ahp->ah_rssiThr = (ahp->ah_rssiThr &~ AR_RSSI_THR_BM_THR)
176 | SM(bs->bs_bmissthreshold, AR_RSSI_THR_BM_THR);
177 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
180 * Program the sleep registers to correlate with the beacon setup.
184 * Oahu beacons timers on the station were used for power
185 * save operation (waking up in anticipation of a beacon)
186 * and any CFP function; Venice does sleep/power-save timers
187 * differently - so this is the right place to set them up;
188 * don't think the beacon timers are used by venice sta hw
189 * for any useful purpose anymore
190 * Setup venice's sleep related timers
191 * Current implementation assumes sw processing of beacons -
192 * assuming an interrupt is generated every beacon which
193 * causes the hardware to become awake until the sw tells
194 * it to go to sleep again; beacon timeout is to allow for
195 * beacon jitter; cab timeout is max time to wait for cab
196 * after seeing the last DTIM or MORE CAB bit
198 #define CAB_TIMEOUT_VAL 10 /* in TU */
199 #define BEACON_TIMEOUT_VAL 10 /* in TU */
200 #define SLEEP_SLOP 3 /* in TU */
203 * For max powersave mode we may want to sleep for longer than a
204 * beacon period and not want to receive all beacons; modify the
205 * timers accordingly; make sure to align the next TIM to the
206 * next DTIM if we decide to wake for DTIMs only
208 beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
209 HALASSERT(beaconintval != 0);
210 if (bs->bs_sleepduration > beaconintval) {
211 HALASSERT(roundup(bs->bs_sleepduration, beaconintval) ==
212 bs->bs_sleepduration);
213 beaconintval = bs->bs_sleepduration;
215 dtimperiod = bs->bs_dtimperiod;
216 if (bs->bs_sleepduration > dtimperiod) {
217 HALASSERT(dtimperiod == 0 ||
218 roundup(bs->bs_sleepduration, dtimperiod) ==
219 bs->bs_sleepduration);
220 dtimperiod = bs->bs_sleepduration;
222 HALASSERT(beaconintval <= dtimperiod);
223 if (beaconintval == dtimperiod)
224 nextTbtt = bs->bs_nextdtim;
226 nextTbtt = bs->bs_nexttbtt;
227 nextdtim = bs->bs_nextdtim;
229 OS_REG_WRITE(ah, AR_SLEEP1,
230 SM((nextdtim - SLEEP_SLOP) << 3, AR_SLEEP1_NEXT_DTIM)
231 | SM(CAB_TIMEOUT_VAL, AR_SLEEP1_CAB_TIMEOUT)
232 | AR_SLEEP1_ASSUME_DTIM
233 | AR_SLEEP1_ENH_SLEEP_ENA
235 OS_REG_WRITE(ah, AR_SLEEP2,
236 SM((nextTbtt - SLEEP_SLOP) << 3, AR_SLEEP2_NEXT_TIM)
237 | SM(BEACON_TIMEOUT_VAL, AR_SLEEP2_BEACON_TIMEOUT)
239 OS_REG_WRITE(ah, AR_SLEEP3,
240 SM(beaconintval, AR_SLEEP3_TIM_PERIOD)
241 | SM(dtimperiod, AR_SLEEP3_DTIM_PERIOD)
243 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next DTIM %d\n",
244 __func__, bs->bs_nextdtim);
245 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: next beacon %d\n",
247 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: beacon period %d\n",
248 __func__, beaconintval);
249 HALDEBUG(ah, HAL_DEBUG_BEACON, "%s: DTIM period %d\n",
250 __func__, dtimperiod);
251 #undef CAB_TIMEOUT_VAL
252 #undef BEACON_TIMEOUT_VAL