sys/dev/netif/ig_hal/e1000_82541.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2009, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD: $*/
  34
  35 /*
  36  * 82541EI Gigabit Ethernet Controller
  37  * 82541ER Gigabit Ethernet Controller
  38  * 82541GI Gigabit Ethernet Controller
  39  * 82541PI Gigabit Ethernet Controller
  40  * 82547EI Gigabit Ethernet Controller
  41  * 82547GI Gigabit Ethernet Controller
  42  */
  43
  44 #include "e1000_api.h"
  45
  46 static s32  e1000_init_phy_params_82541(struct e1000_hw *hw);
  47 static s32  e1000_init_nvm_params_82541(struct e1000_hw *hw);
  48 static s32  e1000_init_mac_params_82541(struct e1000_hw *hw);
  49 static s32  e1000_reset_hw_82541(struct e1000_hw *hw);
  50 static s32  e1000_init_hw_82541(struct e1000_hw *hw);
  51 static s32  e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
  52                                          u16 *duplex);
  53 static s32  e1000_phy_hw_reset_82541(struct e1000_hw *hw);
  54 static s32  e1000_setup_copper_link_82541(struct e1000_hw *hw);
  55 static s32  e1000_check_for_link_82541(struct e1000_hw *hw);
  56 static s32  e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
  57 static s32  e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
  58                                           bool active);
  59 static s32  e1000_setup_led_82541(struct e1000_hw *hw);
  60 static s32  e1000_cleanup_led_82541(struct e1000_hw *hw);
  61 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
  62 static s32  e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
  63                                                      bool link_up);
  64 static s32  e1000_phy_init_script_82541(struct e1000_hw *hw);
  65 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
  66
  67 static const u16 e1000_igp_cable_length_table[] =
  68     { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
  69       5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
  70       25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
  71       40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
  72       60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
  73       90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
  74       100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
  75       110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
  76 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
  77                 (sizeof(e1000_igp_cable_length_table) / \
  78                  sizeof(e1000_igp_cable_length_table[0]))
  79
  80 /**
  81  *  e1000_init_phy_params_82541 - Init PHY func ptrs.
  82  *  @hw: pointer to the HW structure
  83  **/
  84 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
  85 {
  86         struct e1000_phy_info *phy = &hw->phy;
  87         s32 ret_val = E1000_SUCCESS;
  88
  89         DEBUGFUNC("e1000_init_phy_params_82541");
  90
  91         phy->addr                      = 1;
  92         phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  93         phy->reset_delay_us            = 10000;
  94         phy->type                      = e1000_phy_igp;
  95
  96         /* Function Pointers */
  97         phy->ops.check_polarity        = e1000_check_polarity_igp;
  98         phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_igp;
  99         phy->ops.get_cable_length      = e1000_get_cable_length_igp_82541;
 100         phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
 101         phy->ops.get_info              = e1000_get_phy_info_igp;
 102         phy->ops.read_reg              = e1000_read_phy_reg_igp;
 103         phy->ops.reset                 = e1000_phy_hw_reset_82541;
 104         phy->ops.set_d3_lplu_state     = e1000_set_d3_lplu_state_82541;
 105         phy->ops.write_reg             = e1000_write_phy_reg_igp;
 106         phy->ops.power_up              = e1000_power_up_phy_copper;
 107         phy->ops.power_down            = e1000_power_down_phy_copper_82541;
 108
 109         ret_val = e1000_get_phy_id(hw);
 110         if (ret_val)
 111                 goto out;
 112
 113         /* Verify phy id */
 114         if (phy->id != IGP01E1000_I_PHY_ID) {
 115                 ret_val = -E1000_ERR_PHY;
 116                 goto out;
 117         }
 118
 119 out:
 120         return ret_val;
 121 }
 122
 123 /**
 124  *  e1000_init_nvm_params_82541 - Init NVM func ptrs.
 125  *  @hw: pointer to the HW structure
 126  **/
 127 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
 128 {
 129         struct   e1000_nvm_info *nvm = &hw->nvm;
 130         s32  ret_val = E1000_SUCCESS;
 131         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 132         u16 size;
 133
 134         DEBUGFUNC("e1000_init_nvm_params_82541");
 135
 136         switch (nvm->override) {
 137         case e1000_nvm_override_spi_large:
 138                 nvm->type = e1000_nvm_eeprom_spi;
 139                 eecd |= E1000_EECD_ADDR_BITS;
 140                 break;
 141         case e1000_nvm_override_spi_small:
 142                 nvm->type = e1000_nvm_eeprom_spi;
 143                 eecd &= ~E1000_EECD_ADDR_BITS;
 144                 break;
 145         case e1000_nvm_override_microwire_large:
 146                 nvm->type = e1000_nvm_eeprom_microwire;
 147                 eecd |= E1000_EECD_SIZE;
 148                 break;
 149         case e1000_nvm_override_microwire_small:
 150                 nvm->type = e1000_nvm_eeprom_microwire;
 151                 eecd &= ~E1000_EECD_SIZE;
 152                 break;
 153         default:
 154                 nvm->type = eecd & E1000_EECD_TYPE
 155                             ? e1000_nvm_eeprom_spi
 156                             : e1000_nvm_eeprom_microwire;
 157                 break;
 158         }
 159
 160         if (nvm->type == e1000_nvm_eeprom_spi) {
 161                 nvm->address_bits       = (eecd & E1000_EECD_ADDR_BITS)
 162                                           ? 16 : 8;
 163                 nvm->delay_usec         = 1;
 164                 nvm->opcode_bits        = 8;
 165                 nvm->page_size          = (eecd & E1000_EECD_ADDR_BITS)
 166                                           ? 32 : 8;
 167
 168                 /* Function Pointers */
 169                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 170                 nvm->ops.read           = e1000_read_nvm_spi;
 171                 nvm->ops.release        = e1000_release_nvm_generic;
 172                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 173                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 174                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 175                 nvm->ops.write          = e1000_write_nvm_spi;
 176
 177                 /*
 178                  * nvm->word_size must be discovered after the pointers
 179                  * are set so we can verify the size from the nvm image
 180                  * itself.  Temporarily set it to a dummy value so the
 181                  * read will work.
 182                  */
 183                 nvm->word_size = 64;
 184                 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
 185                 if (ret_val)
 186                         goto out;
 187                 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
 188                 /*
 189                  * if size != 0, it can be added to a constant and become
 190                  * the left-shift value to set the word_size.  Otherwise,
 191                  * word_size stays at 64.
 192                  */
 193                 if (size) {
 194                         size += NVM_WORD_SIZE_BASE_SHIFT_82541;
 195                         nvm->word_size = 1 << size;
 196                 }
 197         } else {
 198                 nvm->address_bits       = (eecd & E1000_EECD_ADDR_BITS)
 199                                           ? 8 : 6;
 200                 nvm->delay_usec         = 50;
 201                 nvm->opcode_bits        = 3;
 202                 nvm->word_size          = (eecd & E1000_EECD_ADDR_BITS)
 203                                           ? 256 : 64;
 204
 205                 /* Function Pointers */
 206                 nvm->ops.acquire        = e1000_acquire_nvm_generic;
 207                 nvm->ops.read           = e1000_read_nvm_microwire;
 208                 nvm->ops.release        = e1000_release_nvm_generic;
 209                 nvm->ops.update         = e1000_update_nvm_checksum_generic;
 210                 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
 211                 nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
 212                 nvm->ops.write          = e1000_write_nvm_microwire;
 213         }
 214
 215 out:
 216         return ret_val;
 217 }
 218
 219 /**
 220  *  e1000_init_mac_params_82541 - Init MAC func ptrs.
 221  *  @hw: pointer to the HW structure
 222  **/
 223 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
 224 {
 225         struct e1000_mac_info *mac = &hw->mac;
 226
 227         DEBUGFUNC("e1000_init_mac_params_82541");
 228
 229         /* Set media type */
 230         hw->phy.media_type = e1000_media_type_copper;
 231         /* Set mta register count */
 232         mac->mta_reg_count = 128;
 233         /* Set rar entry count */
 234         mac->rar_entry_count = E1000_RAR_ENTRIES;
 235         /* Set if part includes ASF firmware */
 236         mac->asf_firmware_present = TRUE;
 237
 238         /* Function Pointers */
 239
 240         /* bus type/speed/width */
 241         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
 242         /* function id */
 243         mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 244         /* reset */
 245         mac->ops.reset_hw = e1000_reset_hw_82541;
 246         /* hw initialization */
 247         mac->ops.init_hw = e1000_init_hw_82541;
 248         /* link setup */
 249         mac->ops.setup_link = e1000_setup_link_generic;
 250         /* physical interface link setup */
 251         mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
 252         /* check for link */
 253         mac->ops.check_for_link = e1000_check_for_link_82541;
 254         /* link info */
 255         mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
 256         /* multicast address update */
 257         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 258         /* writing VFTA */
 259         mac->ops.write_vfta = e1000_write_vfta_generic;
 260         /* clearing VFTA */
 261         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 262         /* ID LED init */
 263         mac->ops.id_led_init = e1000_id_led_init_generic;
 264         /* setup LED */
 265         mac->ops.setup_led = e1000_setup_led_82541;
 266         /* cleanup LED */
 267         mac->ops.cleanup_led = e1000_cleanup_led_82541;
 268         /* turn on/off LED */
 269         mac->ops.led_on = e1000_led_on_generic;
 270         mac->ops.led_off = e1000_led_off_generic;
 271         /* clear hardware counters */
 272         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
 273
 274         return E1000_SUCCESS;
 275 }
 276
 277 /**
 278  *  e1000_init_function_pointers_82541 - Init func ptrs.
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  Called to initialize all function pointers and parameters.
 282  **/
 283 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
 284 {
 285         DEBUGFUNC("e1000_init_function_pointers_82541");
 286
 287         hw->mac.ops.init_params = e1000_init_mac_params_82541;
 288         hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
 289         hw->phy.ops.init_params = e1000_init_phy_params_82541;
 290 }
 291
 292 /**
 293  *  e1000_reset_hw_82541 - Reset hardware
 294  *  @hw: pointer to the HW structure
 295  *
 296  *  This resets the hardware into a known state.
 297  **/
 298 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
 299 {
 300         u32 ledctl, ctrl, icr, manc;
 301
 302         DEBUGFUNC("e1000_reset_hw_82541");
 303
 304         DEBUGOUT("Masking off all interrupts\n");
 305         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 306
 307         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 308         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 309         E1000_WRITE_FLUSH(hw);
 310
 311         /*
 312          * Delay to allow any outstanding PCI transactions to complete
 313          * before resetting the device.
 314          */
 315         msec_delay(10);
 316
 317         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 318
 319         /* Must reset the Phy before resetting the MAC */
 320         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 321                 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
 322                 msec_delay(5);
 323         }
 324
 325         DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
 326         switch (hw->mac.type) {
 327         case e1000_82541:
 328         case e1000_82541_rev_2:
 329                 /*
 330                  * These controllers can't ack the 64-bit write when
 331                  * issuing the reset, so we use IO-mapping as a
 332                  * workaround to issue the reset.
 333                  */
 334                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 335                 break;
 336         default:
 337                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 338                 break;
 339         }
 340
 341         /* Wait for NVM reload */
 342         msec_delay(20);
 343
 344         /* Disable HW ARPs on ASF enabled adapters */
 345         manc = E1000_READ_REG(hw, E1000_MANC);
 346         manc &= ~E1000_MANC_ARP_EN;
 347         E1000_WRITE_REG(hw, E1000_MANC, manc);
 348
 349         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 350                 e1000_phy_init_script_82541(hw);
 351
 352                 /* Configure activity LED after Phy reset */
 353                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 354                 ledctl &= IGP_ACTIVITY_LED_MASK;
 355                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 356                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 357         }
 358
 359         /* Once again, mask the interrupts */
 360         DEBUGOUT("Masking off all interrupts\n");
 361         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
 362
 363         /* Clear any pending interrupt events. */
 364         icr = E1000_READ_REG(hw, E1000_ICR);
 365
 366         return E1000_SUCCESS;
 367 }
 368
 369 /**
 370  *  e1000_init_hw_82541 - Initialize hardware
 371  *  @hw: pointer to the HW structure
 372  *
 373  *  This inits the hardware readying it for operation.
 374  **/
 375 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
 376 {
 377         struct e1000_mac_info *mac = &hw->mac;
 378         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 379         u32 i, txdctl;
 380         s32 ret_val;
 381
 382         DEBUGFUNC("e1000_init_hw_82541");
 383
 384         /* Initialize identification LED */
 385         ret_val = mac->ops.id_led_init(hw);
 386         if (ret_val) {
 387                 DEBUGOUT("Error initializing identification LED\n");
 388                 /* This is not fatal and we should not stop init due to this */
 389         }
 390
 391         /* Storing the Speed Power Down  value for later use */
 392         ret_val = hw->phy.ops.read_reg(hw,
 393                                        IGP01E1000_GMII_FIFO,
 394                                        &dev_spec->spd_default);
 395         if (ret_val)
 396                 goto out;
 397
 398         /* Disabling VLAN filtering */
 399         DEBUGOUT("Initializing the IEEE VLAN\n");
 400         mac->ops.clear_vfta(hw);
 401
 402         /* Setup the receive address. */
 403         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 404
 405         /* Zero out the Multicast HASH table */
 406         DEBUGOUT("Zeroing the MTA\n");
 407         for (i = 0; i < mac->mta_reg_count; i++) {
 408                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 409                 /*
 410                  * Avoid back to back register writes by adding the register
 411                  * read (flush).  This is to protect against some strange
 412                  * bridge configurations that may issue Memory Write Block
 413                  * (MWB) to our register space.
 414                  */
 415                 E1000_WRITE_FLUSH(hw);
 416         }
 417
 418         /* Setup link and flow control */
 419         ret_val = mac->ops.setup_link(hw);
 420
 421         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
 422         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
 423                  E1000_TXDCTL_FULL_TX_DESC_WB;
 424         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
 425
 426         /*
 427          * Clear all of the statistics registers (clear on read).  It is
 428          * important that we do this after we have tried to establish link
 429          * because the symbol error count will increment wildly if there
 430          * is no link.
 431          */
 432         e1000_clear_hw_cntrs_82541(hw);
 433
 434 out:
 435         return ret_val;
 436 }
 437
 438 /**
 439  * e1000_get_link_up_info_82541 - Report speed and duplex
 440  * @hw: pointer to the HW structure
 441  * @speed: pointer to speed buffer
 442  * @duplex: pointer to duplex buffer
 443  *
 444  * Retrieve the current speed and duplex configuration.
 445  **/
 446 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
 447                                         u16 *duplex)
 448 {
 449         struct e1000_phy_info *phy = &hw->phy;
 450         s32 ret_val;
 451         u16 data;
 452
 453         DEBUGFUNC("e1000_get_link_up_info_82541");
 454
 455         ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
 456         if (ret_val)
 457                 goto out;
 458
 459         if (!phy->speed_downgraded)
 460                 goto out;
 461
 462         /*
 463          * IGP01 PHY may advertise full duplex operation after speed
 464          * downgrade even if it is operating at half duplex.
 465          * Here we set the duplex settings to match the duplex in the
 466          * link partner's capabilities.
 467          */
 468         ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
 469         if (ret_val)
 470                 goto out;
 471
 472         if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
 473                 *duplex = HALF_DUPLEX;
 474         } else {
 475                 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
 476                 if (ret_val)
 477                         goto out;
 478
 479                 if (*speed == SPEED_100) {
 480                         if (!(data & NWAY_LPAR_100TX_FD_CAPS))
 481                                 *duplex = HALF_DUPLEX;
 482                 } else if (*speed == SPEED_10) {
 483                         if (!(data & NWAY_LPAR_10T_FD_CAPS))
 484                                 *duplex = HALF_DUPLEX;
 485                 }
 486         }
 487
 488 out:
 489         return ret_val;
 490 }
 491
 492 /**
 493  *  e1000_phy_hw_reset_82541 - PHY hardware reset
 494  *  @hw: pointer to the HW structure
 495  *
 496  *  Verify the reset block is not blocking us from resetting.  Acquire
 497  *  semaphore (if necessary) and read/set/write the device control reset
 498  *  bit in the PHY.  Wait the appropriate delay time for the device to
 499  *  reset and release the semaphore (if necessary).
 500  **/
 501 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
 502 {
 503         s32 ret_val;
 504         u32 ledctl;
 505
 506         DEBUGFUNC("e1000_phy_hw_reset_82541");
 507
 508         ret_val = e1000_phy_hw_reset_generic(hw);
 509         if (ret_val)
 510                 goto out;
 511
 512         e1000_phy_init_script_82541(hw);
 513
 514         if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
 515                 /* Configure activity LED after PHY reset */
 516                 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 517                 ledctl &= IGP_ACTIVITY_LED_MASK;
 518                 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 519                 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 520         }
 521
 522 out:
 523         return ret_val;
 524 }
 525
 526 /**
 527  *  e1000_setup_copper_link_82541 - Configure copper link settings
 528  *  @hw: pointer to the HW structure
 529  *
 530  *  Calls the appropriate function to configure the link for auto-neg or forced
 531  *  speed and duplex.  Then we check for link, once link is established calls
 532  *  to configure collision distance and flow control are called.  If link is
 533  *  not established, we return -E1000_ERR_PHY (-2).
 534  **/
 535 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
 536 {
 537         struct e1000_phy_info *phy = &hw->phy;
 538         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 539         s32  ret_val;
 540         u32 ctrl, ledctl;
 541
 542         DEBUGFUNC("e1000_setup_copper_link_82541");
 543
 544         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 545         ctrl |= E1000_CTRL_SLU;
 546         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
 547         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 548
 549         hw->phy.reset_disable = FALSE;
 550
 551         /* Earlier revs of the IGP phy require us to force MDI. */
 552         if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
 553                 dev_spec->dsp_config = e1000_dsp_config_disabled;
 554                 phy->mdix = 1;
 555         } else {
 556                 dev_spec->dsp_config = e1000_dsp_config_enabled;
 557         }
 558
 559         ret_val = e1000_copper_link_setup_igp(hw);
 560         if (ret_val)
 561                 goto out;
 562
 563         if (hw->mac.autoneg) {
 564                 if (dev_spec->ffe_config == e1000_ffe_config_active)
 565                         dev_spec->ffe_config = e1000_ffe_config_enabled;
 566         }
 567
 568         /* Configure activity LED after Phy reset */
 569         ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
 570         ledctl &= IGP_ACTIVITY_LED_MASK;
 571         ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
 572         E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
 573
 574         ret_val = e1000_setup_copper_link_generic(hw);
 575
 576 out:
 577         return ret_val;
 578 }
 579
 580 /**
 581  *  e1000_check_for_link_82541 - Check/Store link connection
 582  *  @hw: pointer to the HW structure
 583  *
 584  *  This checks the link condition of the adapter and stores the
 585  *  results in the hw->mac structure.
 586  **/
 587 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
 588 {
 589         struct e1000_mac_info *mac = &hw->mac;
 590         s32 ret_val;
 591         bool link;
 592
 593         DEBUGFUNC("e1000_check_for_link_82541");
 594
 595         /*
 596          * We only want to go out to the PHY registers to see if Auto-Neg
 597          * has completed and/or if our link status has changed.  The
 598          * get_link_status flag is set upon receiving a Link Status
 599          * Change or Rx Sequence Error interrupt.
 600          */
 601         if (!mac->get_link_status) {
 602                 ret_val = E1000_SUCCESS;
 603                 goto out;
 604         }
 605
 606         /*
 607          * First we want to see if the MII Status Register reports
 608          * link.  If so, then we want to get the current speed/duplex
 609          * of the PHY.
 610          */
 611         ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
 612         if (ret_val)
 613                 goto out;
 614
 615         if (!link) {
 616                 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
 617                 goto out; /* No link detected */
 618         }
 619
 620         mac->get_link_status = FALSE;
 621
 622         /*
 623          * Check if there was DownShift, must be checked
 624          * immediately after link-up
 625          */
 626         e1000_check_downshift_generic(hw);
 627
 628         /*
 629          * If we are forcing speed/duplex, then we simply return since
 630          * we have already determined whether we have link or not.
 631          */
 632         if (!mac->autoneg) {
 633                 ret_val = -E1000_ERR_CONFIG;
 634                 goto out;
 635         }
 636
 637         ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
 638
 639         /*
 640          * Auto-Neg is enabled.  Auto Speed Detection takes care
 641          * of MAC speed/duplex configuration.  So we only need to
 642          * configure Collision Distance in the MAC.
 643          */
 644         e1000_config_collision_dist_generic(hw);
 645
 646         /*
 647          * Configure Flow Control now that Auto-Neg has completed.
 648          * First, we need to restore the desired flow control
 649          * settings because we may have had to re-autoneg with a
 650          * different link partner.
 651          */
 652         ret_val = e1000_config_fc_after_link_up_generic(hw);
 653         if (ret_val) {
 654                 DEBUGOUT("Error configuring flow control\n");
 655         }
 656
 657 out:
 658         return ret_val;
 659 }
 660
 661 /**
 662  *  e1000_config_dsp_after_link_change_82541 - Config DSP after link
 663  *  @hw: pointer to the HW structure
 664  *  @link_up: boolean flag for link up status
 665  *
 666  *  Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
 667  *  at any other case.
 668  *
 669  *  82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
 670  *  gigabit link is achieved to improve link quality.
 671  **/
 672 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
 673                                                     bool link_up)
 674 {
 675         struct e1000_phy_info *phy = &hw->phy;
 676         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
 677         s32 ret_val;
 678         u32 idle_errs = 0;
 679         u16 phy_data, phy_saved_data, speed, duplex, i;
 680         u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
 681         u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
 682                                                    {IGP01E1000_PHY_AGC_PARAM_A,
 683                                                     IGP01E1000_PHY_AGC_PARAM_B,
 684                                                     IGP01E1000_PHY_AGC_PARAM_C,
 685                                                     IGP01E1000_PHY_AGC_PARAM_D};
 686
 687         DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
 688
 689         if (link_up) {
 690                 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 691                 if (ret_val) {
 692                         DEBUGOUT("Error getting link speed and duplex\n");
 693                         goto out;
 694                 }
 695
 696                 if (speed != SPEED_1000) {
 697                         ret_val = E1000_SUCCESS;
 698                         goto out;
 699                 }
 700
 701                 ret_val = phy->ops.get_cable_length(hw);
 702                 if (ret_val)
 703                         goto out;
 704
 705                 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
 706                     phy->min_cable_length >= 50) {
 707
 708                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 709                                 ret_val = phy->ops.read_reg(hw,
 710                                                             dsp_reg_array[i],
 711                                                             &phy_data);
 712                                 if (ret_val)
 713                                         goto out;
 714
 715                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 716
 717                                 ret_val = phy->ops.write_reg(hw,
 718                                                              dsp_reg_array[i],
 719                                                              phy_data);
 720                                 if (ret_val)
 721                                         goto out;
 722                         }
 723                         dev_spec->dsp_config = e1000_dsp_config_activated;
 724                 }
 725
 726                 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
 727                     (phy->min_cable_length >= 50)) {
 728                         ret_val = E1000_SUCCESS;
 729                         goto out;
 730                 }
 731
 732                 /* clear previous idle error counts */
 733                 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
 734                 if (ret_val)
 735                         goto out;
 736
 737                 for (i = 0; i < ffe_idle_err_timeout; i++) {
 738                         usec_delay(1000);
 739                         ret_val = phy->ops.read_reg(hw,
 740                                                     PHY_1000T_STATUS,
 741                                                     &phy_data);
 742                         if (ret_val)
 743                                 goto out;
 744
 745                         idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
 746                         if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
 747                                 dev_spec->ffe_config = e1000_ffe_config_active;
 748
 749                                 ret_val = phy->ops.write_reg(hw,
 750                                                   IGP01E1000_PHY_DSP_FFE,
 751                                                   IGP01E1000_PHY_DSP_FFE_CM_CP);
 752                                 if (ret_val)
 753                                         goto out;
 754                                 break;
 755                         }
 756
 757                         if (idle_errs)
 758                                 ffe_idle_err_timeout =
 759                                                  FFE_IDLE_ERR_COUNT_TIMEOUT_100;
 760                 }
 761         } else {
 762                 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
 763                         /*
 764                          * Save off the current value of register 0x2F5B
 765                          * to be restored at the end of the routines.
 766                          */
 767                         ret_val = phy->ops.read_reg(hw,
 768                                                     0x2F5B,
 769                                                     &phy_saved_data);
 770                         if (ret_val)
 771                                 goto out;
 772
 773                         /* Disable the PHY transmitter */
 774                         ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 775                         if (ret_val)
 776                                 goto out;
 777
 778                         msec_delay_irq(20);
 779
 780                         ret_val = phy->ops.write_reg(hw,
 781                                                      0x0000,
 782                                                      IGP01E1000_IEEE_FORCE_GIG);
 783                         if (ret_val)
 784                                 goto out;
 785                         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 786                                 ret_val = phy->ops.read_reg(hw,
 787                                                             dsp_reg_array[i],
 788                                                             &phy_data);
 789                                 if (ret_val)
 790                                         goto out;
 791
 792                                 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
 793                                 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
 794
 795                                 ret_val = phy->ops.write_reg(hw,
 796                                                              dsp_reg_array[i],
 797                                                              phy_data);
 798                                 if (ret_val)
 799                                         goto out;
 800                         }
 801
 802                         ret_val = phy->ops.write_reg(hw,
 803                                                0x0000,
 804                                                IGP01E1000_IEEE_RESTART_AUTONEG);
 805                         if (ret_val)
 806                                 goto out;
 807
 808                         msec_delay_irq(20);
 809
 810                         /* Now enable the transmitter */
 811                         ret_val = phy->ops.write_reg(hw,
 812                                                      0x2F5B,
 813                                                      phy_saved_data);
 814                         if (ret_val)
 815                                 goto out;
 816
 817                         dev_spec->dsp_config = e1000_dsp_config_enabled;
 818                 }
 819
 820                 if (dev_spec->ffe_config != e1000_ffe_config_active) {
 821                         ret_val = E1000_SUCCESS;
 822                         goto out;
 823                 }
 824
 825                 /*
 826                  * Save off the current value of register 0x2F5B
 827                  * to be restored at the end of the routines.
 828                  */
 829                 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
 830                 if (ret_val)
 831                         goto out;
 832
 833                 /* Disable the PHY transmitter */
 834                 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
 835                 if (ret_val)
 836                         goto out;
 837
 838                 msec_delay_irq(20);
 839
 840                 ret_val = phy->ops.write_reg(hw,
 841                                              0x0000,
 842                                              IGP01E1000_IEEE_FORCE_GIG);
 843                 if (ret_val)
 844                         goto out;
 845
 846                 ret_val = phy->ops.write_reg(hw,
 847                                              IGP01E1000_PHY_DSP_FFE,
 848                                              IGP01E1000_PHY_DSP_FFE_DEFAULT);
 849                 if (ret_val)
 850                         goto out;
 851
 852                 ret_val = phy->ops.write_reg(hw,
 853                                              0x0000,
 854                                              IGP01E1000_IEEE_RESTART_AUTONEG);
 855                 if (ret_val)
 856                         goto out;
 857
 858                 msec_delay_irq(20);
 859
 860                 /* Now enable the transmitter */
 861                 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
 862
 863                 if (ret_val)
 864                         goto out;
 865
 866                 dev_spec->ffe_config = e1000_ffe_config_enabled;
 867         }
 868
 869 out:
 870         return ret_val;
 871 }
 872
 873 /**
 874  *  e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
 875  *  @hw: pointer to the HW structure
 876  *
 877  *  The automatic gain control (agc) normalizes the amplitude of the
 878  *  received signal, adjusting for the attenuation produced by the
 879  *  cable.  By reading the AGC registers, which represent the
 880  *  combination of coarse and fine gain value, the value can be put
 881  *  into a lookup table to obtain the approximate cable length
 882  *  for each channel.
 883  **/
 884 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
 885 {
 886         struct e1000_phy_info *phy = &hw->phy;
 887         s32 ret_val = E1000_SUCCESS;
 888         u16 i, data;
 889         u16 cur_agc_value, agc_value = 0;
 890         u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
 891         u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
 892                                                          {IGP01E1000_PHY_AGC_A,
 893                                                           IGP01E1000_PHY_AGC_B,
 894                                                           IGP01E1000_PHY_AGC_C,
 895                                                           IGP01E1000_PHY_AGC_D};
 896
 897         DEBUGFUNC("e1000_get_cable_length_igp_82541");
 898
 899         /* Read the AGC registers for all channels */
 900         for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
 901                 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
 902                 if (ret_val)
 903                         goto out;
 904
 905                 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
 906
 907                 /* Bounds checking */
 908                 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
 909                     (cur_agc_value == 0)) {
 910                         ret_val = -E1000_ERR_PHY;
 911                         goto out;
 912                 }
 913
 914                 agc_value += cur_agc_value;
 915
 916                 if (min_agc_value > cur_agc_value)
 917                         min_agc_value = cur_agc_value;
 918         }
 919
 920         /* Remove the minimal AGC result for length < 50m */
 921         if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
 922                 agc_value -= min_agc_value;
 923                 /* Average the three remaining channels for the length. */
 924                 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
 925         } else {
 926                 /* Average the channels for the length. */
 927                 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
 928         }
 929
 930         phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
 931                                  IGP01E1000_AGC_RANGE)
 932                                 ? (e1000_igp_cable_length_table[agc_value] -
 933                                    IGP01E1000_AGC_RANGE)
 934                                 : 0;
 935         phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
 936                                 IGP01E1000_AGC_RANGE;
 937
 938         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 939
 940 out:
 941         return ret_val;
 942 }
 943
 944 /**
 945  *  e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
 946  *  @hw: pointer to the HW structure
 947  *  @active: boolean used to enable/disable lplu
 948  *
 949  *  Success returns 0, Failure returns 1
 950  *
 951  *  The low power link up (lplu) state is set to the power management level D3
 952  *  and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
 953  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 954  *  is used during Dx states where the power conservation is most important.
 955  *  During driver activity, SmartSpeed should be enabled so performance is
 956  *  maintained.
 957  **/
 958 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
 959 {
 960         struct e1000_phy_info *phy = &hw->phy;
 961         s32 ret_val;
 962         u16 data;
 963
 964         DEBUGFUNC("e1000_set_d3_lplu_state_82541");
 965
 966         switch (hw->mac.type) {
 967         case e1000_82541_rev_2:
 968         case e1000_82547_rev_2:
 969                 break;
 970         default:
 971                 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
 972                 goto out;
 973                 break;
 974         }
 975
 976         ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
 977         if (ret_val)
 978                 goto out;
 979
 980         if (!active) {
 981                 data &= ~IGP01E1000_GMII_FLEX_SPD;
 982                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
 983                 if (ret_val)
 984                         goto out;
 985
 986                 /*
 987                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 988                  * during Dx states where the power conservation is most
 989                  * important.  During driver activity we should enable
 990                  * SmartSpeed, so performance is maintained.
 991                  */
 992                 if (phy->smart_speed == e1000_smart_speed_on) {
 993                         ret_val = phy->ops.read_reg(hw,
 994                                                     IGP01E1000_PHY_PORT_CONFIG,
 995                                                     &data);
 996                         if (ret_val)
 997                                 goto out;
 998
 999                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1000                         ret_val = phy->ops.write_reg(hw,
1001                                                      IGP01E1000_PHY_PORT_CONFIG,
1002                                                      data);
1003                         if (ret_val)
1004                                 goto out;
1005                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1006                         ret_val = phy->ops.read_reg(hw,
1007                                                     IGP01E1000_PHY_PORT_CONFIG,
1008                                                     &data);
1009                         if (ret_val)
1010                                 goto out;
1011
1012                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1013                         ret_val = phy->ops.write_reg(hw,
1014                                                      IGP01E1000_PHY_PORT_CONFIG,
1015                                                      data);
1016                         if (ret_val)
1017                                 goto out;
1018                 }
1019         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1020                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1021                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1022                 data |= IGP01E1000_GMII_FLEX_SPD;
1023                 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1024                 if (ret_val)
1025                         goto out;
1026
1027                 /* When LPLU is enabled, we should disable SmartSpeed */
1028                 ret_val = phy->ops.read_reg(hw,
1029                                             IGP01E1000_PHY_PORT_CONFIG,
1030                                             &data);
1031                 if (ret_val)
1032                         goto out;
1033
1034                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1035                 ret_val = phy->ops.write_reg(hw,
1036                                              IGP01E1000_PHY_PORT_CONFIG,
1037                                              data);
1038         }
1039
1040 out:
1041         return ret_val;
1042 }
1043
1044 /**
1045  *  e1000_setup_led_82541 - Configures SW controllable LED
1046  *  @hw: pointer to the HW structure
1047  *
1048  *  This prepares the SW controllable LED for use and saves the current state
1049  *  of the LED so it can be later restored.
1050  **/
1051 static s32 e1000_setup_led_82541(struct e1000_hw *hw)
1052 {
1053         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1054         s32 ret_val;
1055
1056         DEBUGFUNC("e1000_setup_led_82541");
1057
1058         ret_val = hw->phy.ops.read_reg(hw,
1059                                        IGP01E1000_GMII_FIFO,
1060                                        &dev_spec->spd_default);
1061         if (ret_val)
1062                 goto out;
1063
1064         ret_val = hw->phy.ops.write_reg(hw,
1065                                         IGP01E1000_GMII_FIFO,
1066                                         (u16)(dev_spec->spd_default &
1067                                                 ~IGP01E1000_GMII_SPD));
1068         if (ret_val)
1069                 goto out;
1070
1071         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1072
1073 out:
1074         return ret_val;
1075 }
1076
1077 /**
1078  *  e1000_cleanup_led_82541 - Set LED config to default operation
1079  *  @hw: pointer to the HW structure
1080  *
1081  *  Remove the current LED configuration and set the LED configuration
1082  *  to the default value, saved from the EEPROM.
1083  **/
1084 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1085 {
1086         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1087         s32 ret_val;
1088
1089         DEBUGFUNC("e1000_cleanup_led_82541");
1090
1091         ret_val = hw->phy.ops.write_reg(hw,
1092                                         IGP01E1000_GMII_FIFO,
1093                                         dev_spec->spd_default);
1094         if (ret_val)
1095                 goto out;
1096
1097         E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1098
1099 out:
1100         return ret_val;
1101 }
1102
1103 /**
1104  *  e1000_phy_init_script_82541 - Initialize GbE PHY
1105  *  @hw: pointer to the HW structure
1106  *
1107  *  Initializes the IGP PHY.
1108  **/
1109 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1110 {
1111         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1112         u32 ret_val;
1113         u16 phy_saved_data;
1114
1115         DEBUGFUNC("e1000_phy_init_script_82541");
1116
1117         if (!dev_spec->phy_init_script) {
1118                 ret_val = E1000_SUCCESS;
1119                 goto out;
1120         }
1121
1122         /* Delay after phy reset to enable NVM configuration to load */
1123         msec_delay(20);
1124
1125         /*
1126          * Save off the current value of register 0x2F5B to be restored at
1127          * the end of this routine.
1128          */
1129         ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1130
1131         /* Disabled the PHY transmitter */
1132         hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1133
1134         msec_delay(20);
1135
1136         hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1137
1138         msec_delay(5);
1139
1140         switch (hw->mac.type) {
1141         case e1000_82541:
1142         case e1000_82547:
1143                 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1144
1145                 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1146
1147                 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1148
1149                 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1150
1151                 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1152
1153                 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1154
1155                 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1156
1157                 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1158
1159                 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1160                 break;
1161         case e1000_82541_rev_2:
1162         case e1000_82547_rev_2:
1163                 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1164                 break;
1165         default:
1166                 break;
1167         }
1168
1169         hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1170
1171         msec_delay(20);
1172
1173         /* Now enable the transmitter */
1174         hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1175
1176         if (hw->mac.type == e1000_82547) {
1177                 u16 fused, fine, coarse;
1178
1179                 /* Move to analog registers page */
1180                 hw->phy.ops.read_reg(hw,
1181                                   IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1182                                   &fused);
1183
1184                 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1185                         hw->phy.ops.read_reg(hw,
1186                                           IGP01E1000_ANALOG_FUSE_STATUS,
1187                                           &fused);
1188
1189                         fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1190                         coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1191
1192                         if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1193                                 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1194                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1195                         } else if (coarse ==
1196                                    IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1197                                 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1198
1199                         fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1200                                 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1201                                 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1202
1203                         hw->phy.ops.write_reg(hw,
1204                                            IGP01E1000_ANALOG_FUSE_CONTROL,
1205                                            fused);
1206                         hw->phy.ops.write_reg(hw,
1207                                       IGP01E1000_ANALOG_FUSE_BYPASS,
1208                                       IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1209                 }
1210         }
1211
1212 out:
1213         return ret_val;
1214 }
1215
1216 /**
1217  *  e1000_init_script_state_82541 - Enable/Disable PHY init script
1218  *  @hw: pointer to the HW structure
1219  *  @state: boolean value used to enable/disable PHY init script
1220  *
1221  *  Allows the driver to enable/disable the PHY init script, if the PHY is an
1222  *  IGP PHY.
1223  **/
1224 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1225 {
1226         struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1227
1228         DEBUGFUNC("e1000_init_script_state_82541");
1229
1230         if (hw->phy.type != e1000_phy_igp) {
1231                 DEBUGOUT("Initialization script not necessary.\n");
1232                 goto out;
1233         }
1234
1235         dev_spec->phy_init_script = state;
1236
1237 out:
1238         return;
1239 }
1240
1241 /**
1242  * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1243  * @hw: pointer to the HW structure
1244  *
1245  * In the case of a PHY power down to save power, or to turn off link during a
1246  * driver unload, or wake on lan is not enabled, remove the link.
1247  **/
1248 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1249 {
1250         /* If the management interface is not enabled, then power down */
1251         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1252                 e1000_power_down_phy_copper(hw);
1253
1254         return;
1255 }
1256
1257 /**
1258  *  e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1259  *  @hw: pointer to the HW structure
1260  *
1261  *  Clears the hardware counters by reading the counter registers.
1262  **/
1263 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1264 {
1265         DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1266
1267         e1000_clear_hw_cntrs_base_generic(hw);
1268
1269         E1000_READ_REG(hw, E1000_PRC64);
1270         E1000_READ_REG(hw, E1000_PRC127);
1271         E1000_READ_REG(hw, E1000_PRC255);
1272         E1000_READ_REG(hw, E1000_PRC511);
1273         E1000_READ_REG(hw, E1000_PRC1023);
1274         E1000_READ_REG(hw, E1000_PRC1522);
1275         E1000_READ_REG(hw, E1000_PTC64);
1276         E1000_READ_REG(hw, E1000_PTC127);
1277         E1000_READ_REG(hw, E1000_PTC255);
1278         E1000_READ_REG(hw, E1000_PTC511);
1279         E1000_READ_REG(hw, E1000_PTC1023);
1280         E1000_READ_REG(hw, E1000_PTC1522);
1281
1282         E1000_READ_REG(hw, E1000_ALGNERRC);
1283         E1000_READ_REG(hw, E1000_RXERRC);
1284         E1000_READ_REG(hw, E1000_TNCRS);
1285         E1000_READ_REG(hw, E1000_CEXTERR);
1286         E1000_READ_REG(hw, E1000_TSCTC);
1287         E1000_READ_REG(hw, E1000_TSCTFC);
1288
1289         E1000_READ_REG(hw, E1000_MGTPRC);
1290         E1000_READ_REG(hw, E1000_MGTPDC);
1291         E1000_READ_REG(hw, E1000_MGTPTC);
1292 }